1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZRegisterInfo.h"
10 #include "SystemZInstrInfo.h"
11 #include "SystemZSubtarget.h"
12 #include "llvm/CodeGen/LiveIntervals.h"
13 #include "llvm/ADT/SmallSet.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/CodeGen/TargetFrameLowering.h"
17 #include "llvm/CodeGen/VirtRegMap.h"
18 
19 using namespace llvm;
20 
21 #define GET_REGINFO_TARGET_DESC
22 #include "SystemZGenRegisterInfo.inc"
23 
24 SystemZRegisterInfo::SystemZRegisterInfo()
25     : SystemZGenRegisterInfo(SystemZ::R14D) {}
26 
27 // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
28 // somehow belongs in it. Otherwise, return GRX32.
29 static const TargetRegisterClass *getRC32(MachineOperand &MO,
30                                           const VirtRegMap *VRM,
31                                           const MachineRegisterInfo *MRI) {
32   const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
33 
34   if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
35       MO.getSubReg() == SystemZ::subreg_l32 ||
36       MO.getSubReg() == SystemZ::subreg_hl32)
37     return &SystemZ::GR32BitRegClass;
38   if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
39       MO.getSubReg() == SystemZ::subreg_h32 ||
40       MO.getSubReg() == SystemZ::subreg_hh32)
41     return &SystemZ::GRH32BitRegClass;
42 
43   if (VRM && VRM->hasPhys(MO.getReg())) {
44     unsigned PhysReg = VRM->getPhys(MO.getReg());
45     if (SystemZ::GR32BitRegClass.contains(PhysReg))
46       return &SystemZ::GR32BitRegClass;
47     assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
48             "Phys reg not in GR32 or GRH32?");
49     return &SystemZ::GRH32BitRegClass;
50   }
51 
52   assert (RC == &SystemZ::GRX32BitRegClass);
53   return RC;
54 }
55 
56 // Pass the registers of RC as hints while making sure that if any of these
57 // registers are copy hints (and therefore already in Hints), hint them
58 // first.
59 static void addHints(ArrayRef<MCPhysReg> Order,
60                      SmallVectorImpl<MCPhysReg> &Hints,
61                      const TargetRegisterClass *RC,
62                      const MachineRegisterInfo *MRI) {
63   SmallSet<unsigned, 4> CopyHints;
64   CopyHints.insert(Hints.begin(), Hints.end());
65   Hints.clear();
66   for (MCPhysReg Reg : Order)
67     if (CopyHints.count(Reg) &&
68         RC->contains(Reg) && !MRI->isReserved(Reg))
69       Hints.push_back(Reg);
70   for (MCPhysReg Reg : Order)
71     if (!CopyHints.count(Reg) &&
72         RC->contains(Reg) && !MRI->isReserved(Reg))
73       Hints.push_back(Reg);
74 }
75 
76 bool
77 SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
78                                            ArrayRef<MCPhysReg> Order,
79                                            SmallVectorImpl<MCPhysReg> &Hints,
80                                            const MachineFunction &MF,
81                                            const VirtRegMap *VRM,
82                                            const LiveRegMatrix *Matrix) const {
83   const MachineRegisterInfo *MRI = &MF.getRegInfo();
84   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
85 
86   bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
87       VirtReg, Order, Hints, MF, VRM, Matrix);
88 
89   if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
90     SmallVector<unsigned, 8> Worklist;
91     SmallSet<unsigned, 4> DoneRegs;
92     Worklist.push_back(VirtReg);
93     while (Worklist.size()) {
94       unsigned Reg = Worklist.pop_back_val();
95       if (!DoneRegs.insert(Reg).second)
96         continue;
97 
98       for (auto &Use : MRI->use_instructions(Reg)) {
99         // For LOCRMux, see if the other operand is already a high or low
100         // register, and in that case give the correpsonding hints for
101         // VirtReg. LOCR instructions need both operands in either high or
102         // low parts.
103         if (Use.getOpcode() == SystemZ::LOCRMux) {
104           MachineOperand &TrueMO = Use.getOperand(1);
105           MachineOperand &FalseMO = Use.getOperand(2);
106           const TargetRegisterClass *RC =
107             TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
108                                    getRC32(TrueMO, VRM, MRI));
109           if (RC && RC != &SystemZ::GRX32BitRegClass) {
110             addHints(Order, Hints, RC, MRI);
111             // Return true to make these hints the only regs available to
112             // RA. This may mean extra spilling but since the alternative is
113             // a jump sequence expansion of the LOCRMux, it is preferred.
114             return true;
115           }
116 
117           // Add the other operand of the LOCRMux to the worklist.
118           unsigned OtherReg =
119             (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
120           if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
121             Worklist.push_back(OtherReg);
122         } // end LOCRMux
123         else if (Use.getOpcode() == SystemZ::CHIMux ||
124                  Use.getOpcode() == SystemZ::CFIMux) {
125           if (Use.getOperand(1).getImm() == 0) {
126             bool OnlyLMuxes = true;
127             for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
128               if (DefMI.getOpcode() != SystemZ::LMux)
129                 OnlyLMuxes = false;
130             if (OnlyLMuxes) {
131               addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
132               // Return false to make these hints preferred but not obligatory.
133               return false;
134             }
135           }
136         } // end CHIMux / CFIMux
137       }
138     }
139   }
140 
141   return BaseImplRetVal;
142 }
143 
144 const MCPhysReg *
145 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
146   const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
147   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
148     return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
149                                 : CSR_SystemZ_AllRegs_SaveList;
150   if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
151       MF->getFunction().getAttributes().hasAttrSomewhere(
152           Attribute::SwiftError))
153     return CSR_SystemZ_SwiftError_SaveList;
154   return CSR_SystemZ_SaveList;
155 }
156 
157 const uint32_t *
158 SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
159                                           CallingConv::ID CC) const {
160   const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
161   if (CC == CallingConv::AnyReg)
162     return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
163                                 : CSR_SystemZ_AllRegs_RegMask;
164   if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
165       MF.getFunction().getAttributes().hasAttrSomewhere(
166           Attribute::SwiftError))
167     return CSR_SystemZ_SwiftError_RegMask;
168   return CSR_SystemZ_RegMask;
169 }
170 
171 BitVector
172 SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
173   BitVector Reserved(getNumRegs());
174   const SystemZFrameLowering *TFI = getFrameLowering(MF);
175 
176   if (TFI->hasFP(MF)) {
177     // R11D is the frame pointer.  Reserve all aliases.
178     Reserved.set(SystemZ::R11D);
179     Reserved.set(SystemZ::R11L);
180     Reserved.set(SystemZ::R11H);
181     Reserved.set(SystemZ::R10Q);
182   }
183 
184   // R15D is the stack pointer.  Reserve all aliases.
185   Reserved.set(SystemZ::R15D);
186   Reserved.set(SystemZ::R15L);
187   Reserved.set(SystemZ::R15H);
188   Reserved.set(SystemZ::R14Q);
189 
190   // A0 and A1 hold the thread pointer.
191   Reserved.set(SystemZ::A0);
192   Reserved.set(SystemZ::A1);
193 
194   return Reserved;
195 }
196 
197 void
198 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
199                                          int SPAdj, unsigned FIOperandNum,
200                                          RegScavenger *RS) const {
201   assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
202 
203   MachineBasicBlock &MBB = *MI->getParent();
204   MachineFunction &MF = *MBB.getParent();
205   auto *TII =
206       static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
207   const SystemZFrameLowering *TFI = getFrameLowering(MF);
208   DebugLoc DL = MI->getDebugLoc();
209 
210   // Decompose the frame index into a base and offset.
211   int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
212   unsigned BasePtr;
213   int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
214                     MI->getOperand(FIOperandNum + 1).getImm());
215 
216   // Special handling of dbg_value instructions.
217   if (MI->isDebugValue()) {
218     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
219     MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
220     return;
221   }
222 
223   // See if the offset is in range, or if an equivalent instruction that
224   // accepts the offset exists.
225   unsigned Opcode = MI->getOpcode();
226   unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
227   if (OpcodeForOffset) {
228     if (OpcodeForOffset == SystemZ::LE &&
229         MF.getSubtarget<SystemZSubtarget>().hasVector()) {
230       // If LE is ok for offset, use LDE instead on z13.
231       OpcodeForOffset = SystemZ::LDE32;
232     }
233     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
234   }
235   else {
236     // Create an anchor point that is in range.  Start at 0xffff so that
237     // can use LLILH to load the immediate.
238     int64_t OldOffset = Offset;
239     int64_t Mask = 0xffff;
240     do {
241       Offset = OldOffset & Mask;
242       OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
243       Mask >>= 1;
244       assert(Mask && "One offset must be OK");
245     } while (!OpcodeForOffset);
246 
247     unsigned ScratchReg =
248       MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
249     int64_t HighOffset = OldOffset - Offset;
250 
251     if (MI->getDesc().TSFlags & SystemZII::HasIndex
252         && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
253       // Load the offset into the scratch register and use it as an index.
254       // The scratch register then dies here.
255       TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
256       MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
257       MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
258                                                         false, false, true);
259     } else {
260       // Load the anchor address into a scratch register.
261       unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
262       if (LAOpcode)
263         BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
264           .addReg(BasePtr).addImm(HighOffset).addReg(0);
265       else {
266         // Load the high offset into the scratch register and use it as
267         // an index.
268         TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
269         BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
270           .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
271       }
272 
273       // Use the scratch register as the base.  It then dies here.
274       MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
275                                                     false, false, true);
276     }
277   }
278   MI->setDesc(TII->get(OpcodeForOffset));
279   MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
280 }
281 
282 bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
283                                   const TargetRegisterClass *SrcRC,
284                                   unsigned SubReg,
285                                   const TargetRegisterClass *DstRC,
286                                   unsigned DstSubReg,
287                                   const TargetRegisterClass *NewRC,
288                                   LiveIntervals &LIS) const {
289   assert (MI->isCopy() && "Only expecting COPY instructions");
290 
291   // Coalesce anything which is not a COPY involving a subreg to/from GR128.
292   if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
293         (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
294     return true;
295 
296   // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
297   // and local to one MBB with not too much interferring registers. Otherwise
298   // regalloc may run out of registers.
299 
300   unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
301   unsigned GR128Reg = MI->getOperand(WideOpNo).getReg();
302   unsigned GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
303   LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
304   LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
305 
306   // Check that the two virtual registers are local to MBB.
307   MachineBasicBlock *MBB = MI->getParent();
308   MachineInstr *FirstMI_GR128 =
309     LIS.getInstructionFromIndex(IntGR128.beginIndex());
310   MachineInstr *FirstMI_GRNar =
311     LIS.getInstructionFromIndex(IntGRNar.beginIndex());
312   MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
313   MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
314   if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
315       (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
316       (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
317       (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
318     return false;
319 
320   MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
321   if (WideOpNo == 1) {
322     MII = FirstMI_GR128;
323     MEE = LastMI_GRNar;
324   } else {
325     MII = FirstMI_GRNar;
326     MEE = LastMI_GR128;
327   }
328 
329   // Check if coalescing seems safe by finding the set of clobbered physreg
330   // pairs in the region.
331   BitVector PhysClobbered(getNumRegs());
332   MEE++;
333   for (; MII != MEE; ++MII) {
334     for (const MachineOperand &MO : MII->operands())
335       if (MO.isReg() && isPhysicalRegister(MO.getReg())) {
336         for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
337              SI.isValid(); ++SI)
338           if (NewRC->contains(*SI)) {
339             PhysClobbered.set(*SI);
340             break;
341           }
342       }
343   }
344 
345   // Demand an arbitrary margin of free regs.
346   unsigned const DemandedFreeGR128 = 3;
347   if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
348     return false;
349 
350   return true;
351 }
352 
353 unsigned
354 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
355   const SystemZFrameLowering *TFI = getFrameLowering(MF);
356   return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
357 }
358 
359 const TargetRegisterClass *
360 SystemZRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
361   if (RC == &SystemZ::CCRRegClass)
362     return &SystemZ::GR32BitRegClass;
363   return RC;
364 }
365 
366