1//===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// Record that INSN performs a 64-bit version of unary operator OPERATOR
11// in which the operand is sign-extended from 32 to 64 bits.
12multiclass SXU<SDPatternOperator operator, Instruction insn> {
13  def : Pat<(operator (sext (i32 GR32:$src))),
14            (insn GR32:$src)>;
15  def : Pat<(operator (sext_inreg GR64:$src, i32)),
16            (insn (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
17}
18
19// Record that INSN performs a 64-bit version of binary operator OPERATOR
20// in which the first operand has class CLS and which the second operand
21// is sign-extended from a 32-bit register.
22multiclass SXB<SDPatternOperator operator, RegisterOperand cls,
23               Instruction insn> {
24  def : Pat<(operator cls:$src1, (sext GR32:$src2)),
25            (insn cls:$src1, GR32:$src2)>;
26  def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
27            (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
28}
29
30// Like SXB, but for zero extension.
31multiclass ZXB<SDPatternOperator operator, RegisterOperand cls,
32               Instruction insn> {
33  def : Pat<(operator cls:$src1, (zext GR32:$src2)),
34            (insn cls:$src1, GR32:$src2)>;
35  def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
36            (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
37}
38
39// Record that INSN performs a binary read-modify-write operation,
40// with LOAD, OPERATOR and STORE being the read, modify and write
41// respectively.  MODE is the addressing mode and IMM is the type
42// of the second operand.
43class RMWI<SDPatternOperator load, SDPatternOperator operator,
44           SDPatternOperator store, AddressingMode mode,
45           PatFrag imm, Instruction insn>
46  : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
47        (insn mode:$addr, (UIMM8 imm:$src))>;
48
49// Record that INSN performs binary operation OPERATION on a byte
50// memory location.  IMM is the type of the second operand.
51multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
52                    Instruction insn> {
53  def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
54  def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
55}
56
57// Record that INSN performs insertion TYPE into a register of class CLS.
58// The inserted operand is loaded using LOAD from an address of mode MODE.
59multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
60                     SDPatternOperator load, AddressingMode mode> {
61  def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
62              cls:$src1, (load mode:$src2)),
63            (insn cls:$src1, mode:$src2)>;
64  def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
65              (load mode:$src2), cls:$src1),
66            (insn cls:$src1, mode:$src2)>;
67}
68
69// Try to use MVC instruction INSN for a load of type LOAD followed by a store
70// of the same size.  VT is the type of the intermediate (legalized) value and
71// LENGTH is the number of bytes loaded by LOAD.
72multiclass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn,
73                        bits<5> length> {
74  def : Pat<(mvc_store (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
75            (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
76}
77
78// Use NC-like instruction INSN for block_op operation OPERATOR.
79// The other operand is a load of type LOAD, which accesses LENGTH bytes.
80// VT is the intermediate legalized type in which the binary operation
81// is actually done.
82multiclass BinaryLoadStore<SDPatternOperator operator, SDPatternOperator load,
83                           ValueType vt, Instruction insn, bits<5> length> {
84  def : Pat<(operator (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
85            (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
86}
87
88// A convenient way of generating all block peepholes for a particular
89// LOAD/VT/LENGTH combination.
90multiclass BlockLoadStore<SDPatternOperator load, ValueType vt,
91                          Instruction mvc, Instruction nc, Instruction oc,
92                          Instruction xc, bits<5> length> {
93  defm : MVCLoadStore<load, vt, mvc, length>;
94  defm : BinaryLoadStore<block_and1, load, vt, nc, length>;
95  defm : BinaryLoadStore<block_and2, load, vt, nc, length>;
96  defm : BinaryLoadStore<block_or1,  load, vt, oc, length>;
97  defm : BinaryLoadStore<block_or2,  load, vt, oc, length>;
98  defm : BinaryLoadStore<block_xor1, load, vt, xc, length>;
99  defm : BinaryLoadStore<block_xor2, load, vt, xc, length>;
100}
101
102// Record that INSN is a LOAD AND TEST that can be used to compare
103// registers in CLS against zero.  The instruction has separate R1 and R2
104// operands, but they must be the same when the instruction is used like this.
105class CompareZeroFP<Instruction insn, RegisterOperand cls>
106  : Pat<(z_fcmp cls:$reg, (fpimm0)), (insn cls:$reg, cls:$reg)>;
107