1//===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Type profiles 12//===----------------------------------------------------------------------===// 13def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>, 14 SDTCisVT<1, i64>]>; 15def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>, 16 SDTCisVT<1, i64>]>; 17def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 18def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 19def SDT_ZICmp : SDTypeProfile<0, 3, 20 [SDTCisSameAs<0, 1>, 21 SDTCisVT<2, i32>]>; 22def SDT_ZBRCCMask : SDTypeProfile<0, 3, 23 [SDTCisVT<0, i32>, 24 SDTCisVT<1, i32>, 25 SDTCisVT<2, OtherVT>]>; 26def SDT_ZSelectCCMask : SDTypeProfile<1, 4, 27 [SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisVT<3, i32>, 30 SDTCisVT<4, i32>]>; 31def SDT_ZWrapPtr : SDTypeProfile<1, 1, 32 [SDTCisSameAs<0, 1>, 33 SDTCisPtrTy<0>]>; 34def SDT_ZWrapOffset : SDTypeProfile<1, 2, 35 [SDTCisSameAs<0, 1>, 36 SDTCisSameAs<0, 2>, 37 SDTCisPtrTy<0>]>; 38def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 39def SDT_ZGR128Binary32 : SDTypeProfile<1, 2, 40 [SDTCisVT<0, untyped>, 41 SDTCisVT<1, untyped>, 42 SDTCisVT<2, i32>]>; 43def SDT_ZGR128Binary64 : SDTypeProfile<1, 2, 44 [SDTCisVT<0, untyped>, 45 SDTCisVT<1, untyped>, 46 SDTCisVT<2, i64>]>; 47def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5, 48 [SDTCisVT<0, i32>, 49 SDTCisPtrTy<1>, 50 SDTCisVT<2, i32>, 51 SDTCisVT<3, i32>, 52 SDTCisVT<4, i32>, 53 SDTCisVT<5, i32>]>; 54def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6, 55 [SDTCisVT<0, i32>, 56 SDTCisPtrTy<1>, 57 SDTCisVT<2, i32>, 58 SDTCisVT<3, i32>, 59 SDTCisVT<4, i32>, 60 SDTCisVT<5, i32>, 61 SDTCisVT<6, i32>]>; 62def SDT_ZMemMemLength : SDTypeProfile<0, 3, 63 [SDTCisPtrTy<0>, 64 SDTCisPtrTy<1>, 65 SDTCisVT<2, i64>]>; 66def SDT_ZMemMemLoop : SDTypeProfile<0, 4, 67 [SDTCisPtrTy<0>, 68 SDTCisPtrTy<1>, 69 SDTCisVT<2, i64>, 70 SDTCisVT<3, i64>]>; 71def SDT_ZString : SDTypeProfile<1, 3, 72 [SDTCisPtrTy<0>, 73 SDTCisPtrTy<1>, 74 SDTCisPtrTy<2>, 75 SDTCisVT<3, i32>]>; 76def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 77def SDT_ZPrefetch : SDTypeProfile<0, 2, 78 [SDTCisVT<0, i32>, 79 SDTCisPtrTy<1>]>; 80def SDT_ZLoadBSwap : SDTypeProfile<1, 2, 81 [SDTCisInt<0>, 82 SDTCisPtrTy<1>, 83 SDTCisVT<2, OtherVT>]>; 84def SDT_ZStoreBSwap : SDTypeProfile<0, 3, 85 [SDTCisInt<0>, 86 SDTCisPtrTy<1>, 87 SDTCisVT<2, OtherVT>]>; 88def SDT_ZTBegin : SDTypeProfile<0, 2, 89 [SDTCisPtrTy<0>, 90 SDTCisVT<1, i32>]>; 91def SDT_ZInsertVectorElt : SDTypeProfile<1, 3, 92 [SDTCisVec<0>, 93 SDTCisSameAs<0, 1>, 94 SDTCisVT<3, i32>]>; 95def SDT_ZExtractVectorElt : SDTypeProfile<1, 2, 96 [SDTCisVec<1>, 97 SDTCisVT<2, i32>]>; 98def SDT_ZReplicate : SDTypeProfile<1, 1, 99 [SDTCisVec<0>]>; 100def SDT_ZVecUnaryConv : SDTypeProfile<1, 1, 101 [SDTCisVec<0>, 102 SDTCisVec<1>]>; 103def SDT_ZVecUnary : SDTypeProfile<1, 1, 104 [SDTCisVec<0>, 105 SDTCisSameAs<0, 1>]>; 106def SDT_ZVecBinary : SDTypeProfile<1, 2, 107 [SDTCisVec<0>, 108 SDTCisSameAs<0, 1>, 109 SDTCisSameAs<0, 2>]>; 110def SDT_ZVecBinaryInt : SDTypeProfile<1, 2, 111 [SDTCisVec<0>, 112 SDTCisSameAs<0, 1>, 113 SDTCisVT<2, i32>]>; 114def SDT_ZVecBinaryConv : SDTypeProfile<1, 2, 115 [SDTCisVec<0>, 116 SDTCisVec<1>, 117 SDTCisSameAs<1, 2>]>; 118def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2, 119 [SDTCisVec<0>, 120 SDTCisVec<1>, 121 SDTCisVT<2, i32>]>; 122def SDT_ZRotateMask : SDTypeProfile<1, 2, 123 [SDTCisVec<0>, 124 SDTCisVT<1, i32>, 125 SDTCisVT<2, i32>]>; 126def SDT_ZJoinDwords : SDTypeProfile<1, 2, 127 [SDTCisVT<0, v2i64>, 128 SDTCisVT<1, i64>, 129 SDTCisVT<2, i64>]>; 130def SDT_ZVecTernary : SDTypeProfile<1, 3, 131 [SDTCisVec<0>, 132 SDTCisSameAs<0, 1>, 133 SDTCisSameAs<0, 2>, 134 SDTCisSameAs<0, 3>]>; 135def SDT_ZVecTernaryInt : SDTypeProfile<1, 3, 136 [SDTCisVec<0>, 137 SDTCisSameAs<0, 1>, 138 SDTCisSameAs<0, 2>, 139 SDTCisVT<3, i32>]>; 140def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4, 141 [SDTCisVec<0>, 142 SDTCisSameAs<0, 1>, 143 SDTCisSameAs<0, 2>, 144 SDTCisSameAs<0, 3>, 145 SDTCisVT<4, i32>]>; 146def SDT_ZTest : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>; 147 148//===----------------------------------------------------------------------===// 149// Node definitions 150//===----------------------------------------------------------------------===// 151 152// These are target-independent nodes, but have target-specific formats. 153def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 154 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 155def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 156 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, 157 SDNPOutGlue]>; 158def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>; 159 160// Nodes for SystemZISD::*. See SystemZISelLowering.h for more details. 161def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 162 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 163def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall, 164 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 165 SDNPVariadic]>; 166def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall, 167 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 168 SDNPVariadic]>; 169def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 171 SDNPVariadic]>; 172def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall, 173 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 174 SDNPVariadic]>; 175def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>; 176def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET", 177 SDT_ZWrapOffset, []>; 178def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>; 179def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>; 180def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>; 181def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>; 182def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask, 183 [SDNPHasChain, SDNPInGlue]>; 184def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask, 185 [SDNPInGlue]>; 186def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>; 187def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>; 188def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>; 189def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>; 190def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>; 191def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>; 192def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>; 193 194def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone, 195 [SDNPHasChain, SDNPMayStore]>; 196def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone, 197 [SDNPHasChain, SDNPSideEffect]>; 198 199def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap, 200 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 201def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap, 202 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 203 204def z_tdc : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>; 205 206// Defined because the index is an i32 rather than a pointer. 207def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 208 SDT_ZInsertVectorElt>; 209def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 210 SDT_ZExtractVectorElt>; 211def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>; 212def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>; 213def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>; 214def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>; 215def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>; 216def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>; 217def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>; 218def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>; 219def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS", 220 SDT_ZVecTernaryInt>; 221def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>; 222def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>; 223def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv, 224 [SDNPOutGlue]>; 225def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv, 226 [SDNPOutGlue]>; 227def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>; 228def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>; 229def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>; 230def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>; 231def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR", 232 SDT_ZVecBinaryInt>; 233def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR", 234 SDT_ZVecBinaryInt>; 235def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR", 236 SDT_ZVecBinaryInt>; 237def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>; 238def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>; 239def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>; 240def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>; 241def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary, 242 [SDNPOutGlue]>; 243def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary, 244 [SDNPOutGlue]>; 245def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary, 246 [SDNPOutGlue]>; 247def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>; 248def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>; 249def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>; 250def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv, 251 [SDNPOutGlue]>; 252def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv, 253 [SDNPOutGlue]>; 254def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv, 255 [SDNPOutGlue]>; 256def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>; 257def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>; 258def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>; 259def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt, 260 [SDNPOutGlue]>; 261def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt, 262 [SDNPOutGlue]>; 263def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary, 264 [SDNPOutGlue]>; 265def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary, 266 [SDNPOutGlue]>; 267def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary, 268 [SDNPOutGlue]>; 269def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary, 270 [SDNPOutGlue]>; 271def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary, 272 [SDNPOutGlue]>; 273def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt, 274 [SDNPOutGlue]>; 275def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC", 276 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>; 277def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt, 278 [SDNPOutGlue]>; 279 280class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW> 281 : SDNode<"SystemZISD::"##name, profile, 282 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 283 284def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">; 285def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">; 286def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">; 287def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">; 288def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">; 289def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">; 290def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">; 291def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">; 292def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">; 293def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">; 294def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">; 295def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>; 296 297def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength, 298 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 299def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop, 300 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 301def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength, 302 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 303def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop, 304 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 305def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength, 306 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 307def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop, 308 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 309def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength, 310 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 311def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop, 312 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 313def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength, 314 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 315def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop, 316 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 317def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString, 318 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 319def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString, 320 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 321def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString, 322 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 323def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic, 324 [SDNPInGlue]>; 325def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch, 326 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 327 SDNPMemOperand]>; 328 329def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, 330 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 331 SDNPSideEffect]>; 332def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, 333 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 334 SDNPSideEffect]>; 335def z_tend : SDNode<"SystemZISD::TEND", SDTNone, 336 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 337 338def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>; 339def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>; 340def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>; 341 342//===----------------------------------------------------------------------===// 343// Pattern fragments 344//===----------------------------------------------------------------------===// 345 346def z_lrvh : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i16)>; 347def z_lrv : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i32)>; 348def z_lrvg : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i64)>; 349 350def z_strvh : PatFrag<(ops node:$src, node:$addr), 351 (z_storebswap node:$src, node:$addr, i16)>; 352def z_strv : PatFrag<(ops node:$src, node:$addr), 353 (z_storebswap node:$src, node:$addr, i32)>; 354def z_strvg : PatFrag<(ops node:$src, node:$addr), 355 (z_storebswap node:$src, node:$addr, i64)>; 356 357// Signed and unsigned comparisons. 358def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 359 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 360 return Type != SystemZICMP::UnsignedOnly; 361}]>; 362def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 363 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 364 return Type != SystemZICMP::SignedOnly; 365}]>; 366 367// Register- and memory-based TEST UNDER MASK. 368def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>; 369def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>; 370 371// Register sign-extend operations. Sub-32-bit values are represented as i32s. 372def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>; 373def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>; 374def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>; 375 376// Match extensions of an i32 to an i64, followed by an in-register sign 377// extension from a sub-i32 value. 378def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>; 379def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>; 380 381// Register zero-extend operations. Sub-32-bit values are represented as i32s. 382def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>; 383def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>; 384def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>; 385 386// Extending loads in which the extension type can be signed. 387def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 388 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 389 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD; 390}]>; 391def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 392 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 393}]>; 394def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 395 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 396}]>; 397def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 398 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 399}]>; 400 401// Extending loads in which the extension type can be unsigned. 402def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 403 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 404 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD; 405}]>; 406def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 407 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 408}]>; 409def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 410 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 411}]>; 412def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 413 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 414}]>; 415 416// Extending loads in which the extension type doesn't matter. 417def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 418 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD; 419}]>; 420def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 421 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 422}]>; 423def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 424 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 425}]>; 426def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 427 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 428}]>; 429 430// Aligned loads. 431class AlignedLoad<SDPatternOperator load> 432 : PatFrag<(ops node:$addr), (load node:$addr), [{ 433 auto *Load = cast<LoadSDNode>(N); 434 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize(); 435}]>; 436def aligned_load : AlignedLoad<load>; 437def aligned_asextloadi16 : AlignedLoad<asextloadi16>; 438def aligned_asextloadi32 : AlignedLoad<asextloadi32>; 439def aligned_azextloadi16 : AlignedLoad<azextloadi16>; 440def aligned_azextloadi32 : AlignedLoad<azextloadi32>; 441 442// Aligned stores. 443class AlignedStore<SDPatternOperator store> 444 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 445 auto *Store = cast<StoreSDNode>(N); 446 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize(); 447}]>; 448def aligned_store : AlignedStore<store>; 449def aligned_truncstorei16 : AlignedStore<truncstorei16>; 450def aligned_truncstorei32 : AlignedStore<truncstorei32>; 451 452// Non-volatile loads. Used for instructions that might access the storage 453// location multiple times. 454class NonvolatileLoad<SDPatternOperator load> 455 : PatFrag<(ops node:$addr), (load node:$addr), [{ 456 auto *Load = cast<LoadSDNode>(N); 457 return !Load->isVolatile(); 458}]>; 459def nonvolatile_load : NonvolatileLoad<load>; 460def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>; 461def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>; 462def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>; 463 464// Non-volatile stores. 465class NonvolatileStore<SDPatternOperator store> 466 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 467 auto *Store = cast<StoreSDNode>(N); 468 return !Store->isVolatile(); 469}]>; 470def nonvolatile_store : NonvolatileStore<store>; 471def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>; 472def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>; 473def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>; 474 475// A store of a load that can be implemented using MVC. 476def mvc_store : PatFrag<(ops node:$value, node:$addr), 477 (unindexedstore node:$value, node:$addr), 478 [{ return storeLoadCanUseMVC(N); }]>; 479 480// Binary read-modify-write operations on memory in which the other 481// operand is also memory and for which block operations like NC can 482// be used. There are two patterns for each operator, depending on 483// which operand contains the "other" load. 484multiclass block_op<SDPatternOperator operator> { 485 def "1" : PatFrag<(ops node:$value, node:$addr), 486 (unindexedstore (operator node:$value, 487 (unindexedload node:$addr)), 488 node:$addr), 489 [{ return storeLoadCanUseBlockBinary(N, 0); }]>; 490 def "2" : PatFrag<(ops node:$value, node:$addr), 491 (unindexedstore (operator (unindexedload node:$addr), 492 node:$value), 493 node:$addr), 494 [{ return storeLoadCanUseBlockBinary(N, 1); }]>; 495} 496defm block_and : block_op<and>; 497defm block_or : block_op<or>; 498defm block_xor : block_op<xor>; 499 500// Insertions. 501def inserti8 : PatFrag<(ops node:$src1, node:$src2), 502 (or (and node:$src1, -256), node:$src2)>; 503def insertll : PatFrag<(ops node:$src1, node:$src2), 504 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>; 505def insertlh : PatFrag<(ops node:$src1, node:$src2), 506 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>; 507def inserthl : PatFrag<(ops node:$src1, node:$src2), 508 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>; 509def inserthh : PatFrag<(ops node:$src1, node:$src2), 510 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>; 511def insertlf : PatFrag<(ops node:$src1, node:$src2), 512 (or (and node:$src1, 0xffffffff00000000), node:$src2)>; 513def inserthf : PatFrag<(ops node:$src1, node:$src2), 514 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>; 515 516// ORs that can be treated as insertions. 517def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2), 518 (or node:$src1, node:$src2), [{ 519 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 520 return CurDAG->MaskedValueIsZero(N->getOperand(0), 521 APInt::getLowBitsSet(BitWidth, 8)); 522}]>; 523 524// ORs that can be treated as reversed insertions. 525def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2), 526 (or node:$src1, node:$src2), [{ 527 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 528 return CurDAG->MaskedValueIsZero(N->getOperand(1), 529 APInt::getLowBitsSet(BitWidth, 8)); 530}]>; 531 532// Negative integer absolute. 533def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>; 534 535// Integer absolute, matching the canonical form generated by DAGCombiner. 536def z_iabs32 : PatFrag<(ops node:$src), 537 (xor (add node:$src, (sra node:$src, (i32 31))), 538 (sra node:$src, (i32 31)))>; 539def z_iabs64 : PatFrag<(ops node:$src), 540 (xor (add node:$src, (sra node:$src, (i32 63))), 541 (sra node:$src, (i32 63)))>; 542def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>; 543def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>; 544 545// Integer multiply-and-add 546def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3), 547 (add (mul node:$src1, node:$src2), node:$src3)>; 548 549// Fused multiply-subtract, using the natural operand order. 550def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 551 (fma node:$src1, node:$src2, (fneg node:$src3))>; 552 553// Fused multiply-add and multiply-subtract, but with the order of the 554// operands matching SystemZ's MA and MS instructions. 555def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), 556 (fma node:$src2, node:$src3, node:$src1)>; 557def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 558 (fma node:$src2, node:$src3, (fneg node:$src1))>; 559 560// Floating-point negative absolute. 561def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>; 562 563// Create a unary operator that loads from memory and then performs 564// the given operation on it. 565class loadu<SDPatternOperator operator, SDPatternOperator load = load> 566 : PatFrag<(ops node:$addr), (operator (load node:$addr))>; 567 568// Create a store operator that performs the given unary operation 569// on the value before storing it. 570class storeu<SDPatternOperator operator, SDPatternOperator store = store> 571 : PatFrag<(ops node:$value, node:$addr), 572 (store (operator node:$value), node:$addr)>; 573 574// Create a store operator that performs the given inherent operation 575// and stores the resulting value. 576class storei<SDPatternOperator operator, SDPatternOperator store = store> 577 : PatFrag<(ops node:$addr), 578 (store (operator), node:$addr)>; 579 580// Vector representation of all-zeros and all-ones. 581def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>; 582def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>; 583 584// Load a scalar and replicate it in all elements of a vector. 585class z_replicate_load<ValueType scalartype, SDPatternOperator load> 586 : PatFrag<(ops node:$addr), 587 (z_replicate (scalartype (load node:$addr)))>; 588def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>; 589def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>; 590def z_replicate_loadi32 : z_replicate_load<i32, load>; 591def z_replicate_loadi64 : z_replicate_load<i64, load>; 592def z_replicate_loadf32 : z_replicate_load<f32, load>; 593def z_replicate_loadf64 : z_replicate_load<f64, load>; 594 595// Load a scalar and insert it into a single element of a vector. 596class z_vle<ValueType scalartype, SDPatternOperator load> 597 : PatFrag<(ops node:$vec, node:$addr, node:$index), 598 (z_vector_insert node:$vec, (scalartype (load node:$addr)), 599 node:$index)>; 600def z_vlei8 : z_vle<i32, anyextloadi8>; 601def z_vlei16 : z_vle<i32, anyextloadi16>; 602def z_vlei32 : z_vle<i32, load>; 603def z_vlei64 : z_vle<i64, load>; 604def z_vlef32 : z_vle<f32, load>; 605def z_vlef64 : z_vle<f64, load>; 606 607// Load a scalar and insert it into the low element of the high i64 of a 608// zeroed vector. 609class z_vllez<ValueType scalartype, SDPatternOperator load, int index> 610 : PatFrag<(ops node:$addr), 611 (z_vector_insert (z_vzero), 612 (scalartype (load node:$addr)), (i32 index))>; 613def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>; 614def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>; 615def z_vllezi32 : z_vllez<i32, load, 1>; 616def z_vllezi64 : PatFrag<(ops node:$addr), 617 (z_join_dwords (i64 (load node:$addr)), (i64 0))>; 618// We use high merges to form a v4f32 from four f32s. Propagating zero 619// into all elements but index 1 gives this expression. 620def z_vllezf32 : PatFrag<(ops node:$addr), 621 (bitconvert 622 (z_merge_high 623 (v2i64 624 (z_unpackl_high 625 (v4i32 626 (bitconvert 627 (v4f32 (scalar_to_vector 628 (f32 (load node:$addr)))))))), 629 (v2i64 (z_vzero))))>; 630def z_vllezf64 : PatFrag<(ops node:$addr), 631 (z_merge_high 632 (scalar_to_vector (f64 (load node:$addr))), 633 (z_vzero))>; 634 635// Store one element of a vector. 636class z_vste<ValueType scalartype, SDPatternOperator store> 637 : PatFrag<(ops node:$vec, node:$addr, node:$index), 638 (store (scalartype (z_vector_extract node:$vec, node:$index)), 639 node:$addr)>; 640def z_vstei8 : z_vste<i32, truncstorei8>; 641def z_vstei16 : z_vste<i32, truncstorei16>; 642def z_vstei32 : z_vste<i32, store>; 643def z_vstei64 : z_vste<i64, store>; 644def z_vstef32 : z_vste<f32, store>; 645def z_vstef64 : z_vste<f64, store>; 646 647// Arithmetic negation on vectors. 648def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>; 649 650// Bitwise negation on vectors. 651def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>; 652 653// Signed "integer greater than zero" on vectors. 654def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>; 655 656// Signed "integer less than zero" on vectors. 657def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>; 658 659// Integer absolute on vectors. 660class z_viabs<int shift> 661 : PatFrag<(ops node:$src), 662 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))), 663 (z_vsra_by_scalar node:$src, (i32 shift)))>; 664def z_viabs8 : z_viabs<7>; 665def z_viabs16 : z_viabs<15>; 666def z_viabs32 : z_viabs<31>; 667def z_viabs64 : z_viabs<63>; 668 669// Sign-extend the i64 elements of a vector. 670class z_vse<int shift> 671 : PatFrag<(ops node:$src), 672 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>; 673def z_vsei8 : z_vse<56>; 674def z_vsei16 : z_vse<48>; 675def z_vsei32 : z_vse<32>; 676 677// ...and again with the extensions being done on individual i64 scalars. 678class z_vse_by_parts<SDPatternOperator operator, int index1, int index2> 679 : PatFrag<(ops node:$src), 680 (z_join_dwords 681 (operator (z_vector_extract node:$src, index1)), 682 (operator (z_vector_extract node:$src, index2)))>; 683def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>; 684def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>; 685def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>; 686