1//===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Type profiles 12//===----------------------------------------------------------------------===// 13def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>, 14 SDTCisVT<1, i64>]>; 15def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>, 16 SDTCisVT<1, i64>]>; 17def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 18def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 19def SDT_ZICmp : SDTypeProfile<0, 3, 20 [SDTCisSameAs<0, 1>, 21 SDTCisVT<2, i32>]>; 22def SDT_ZBRCCMask : SDTypeProfile<0, 3, 23 [SDTCisVT<0, i32>, 24 SDTCisVT<1, i32>, 25 SDTCisVT<2, OtherVT>]>; 26def SDT_ZSelectCCMask : SDTypeProfile<1, 4, 27 [SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisVT<3, i32>, 30 SDTCisVT<4, i32>]>; 31def SDT_ZWrapPtr : SDTypeProfile<1, 1, 32 [SDTCisSameAs<0, 1>, 33 SDTCisPtrTy<0>]>; 34def SDT_ZWrapOffset : SDTypeProfile<1, 2, 35 [SDTCisSameAs<0, 1>, 36 SDTCisSameAs<0, 2>, 37 SDTCisPtrTy<0>]>; 38def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 39def SDT_ZGR128Binary32 : SDTypeProfile<1, 2, 40 [SDTCisVT<0, untyped>, 41 SDTCisVT<1, untyped>, 42 SDTCisVT<2, i32>]>; 43def SDT_ZGR128Binary64 : SDTypeProfile<1, 2, 44 [SDTCisVT<0, untyped>, 45 SDTCisVT<1, untyped>, 46 SDTCisVT<2, i64>]>; 47def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5, 48 [SDTCisVT<0, i32>, 49 SDTCisPtrTy<1>, 50 SDTCisVT<2, i32>, 51 SDTCisVT<3, i32>, 52 SDTCisVT<4, i32>, 53 SDTCisVT<5, i32>]>; 54def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6, 55 [SDTCisVT<0, i32>, 56 SDTCisPtrTy<1>, 57 SDTCisVT<2, i32>, 58 SDTCisVT<3, i32>, 59 SDTCisVT<4, i32>, 60 SDTCisVT<5, i32>, 61 SDTCisVT<6, i32>]>; 62def SDT_ZMemMemLength : SDTypeProfile<0, 3, 63 [SDTCisPtrTy<0>, 64 SDTCisPtrTy<1>, 65 SDTCisVT<2, i64>]>; 66def SDT_ZMemMemLoop : SDTypeProfile<0, 4, 67 [SDTCisPtrTy<0>, 68 SDTCisPtrTy<1>, 69 SDTCisVT<2, i64>, 70 SDTCisVT<3, i64>]>; 71def SDT_ZString : SDTypeProfile<1, 3, 72 [SDTCisPtrTy<0>, 73 SDTCisPtrTy<1>, 74 SDTCisPtrTy<2>, 75 SDTCisVT<3, i32>]>; 76def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 77def SDT_ZPrefetch : SDTypeProfile<0, 2, 78 [SDTCisVT<0, i32>, 79 SDTCisPtrTy<1>]>; 80def SDT_ZLoadBSwap : SDTypeProfile<1, 2, 81 [SDTCisInt<0>, 82 SDTCisPtrTy<1>, 83 SDTCisVT<2, OtherVT>]>; 84def SDT_ZStoreBSwap : SDTypeProfile<0, 3, 85 [SDTCisInt<0>, 86 SDTCisPtrTy<1>, 87 SDTCisVT<2, OtherVT>]>; 88def SDT_ZTBegin : SDTypeProfile<0, 2, 89 [SDTCisPtrTy<0>, 90 SDTCisVT<1, i32>]>; 91def SDT_ZInsertVectorElt : SDTypeProfile<1, 3, 92 [SDTCisVec<0>, 93 SDTCisSameAs<0, 1>, 94 SDTCisVT<3, i32>]>; 95def SDT_ZExtractVectorElt : SDTypeProfile<1, 2, 96 [SDTCisVec<1>, 97 SDTCisVT<2, i32>]>; 98def SDT_ZReplicate : SDTypeProfile<1, 1, 99 [SDTCisVec<0>]>; 100def SDT_ZVecUnaryConv : SDTypeProfile<1, 1, 101 [SDTCisVec<0>, 102 SDTCisVec<1>]>; 103def SDT_ZVecUnary : SDTypeProfile<1, 1, 104 [SDTCisVec<0>, 105 SDTCisSameAs<0, 1>]>; 106def SDT_ZVecBinary : SDTypeProfile<1, 2, 107 [SDTCisVec<0>, 108 SDTCisSameAs<0, 1>, 109 SDTCisSameAs<0, 2>]>; 110def SDT_ZVecBinaryInt : SDTypeProfile<1, 2, 111 [SDTCisVec<0>, 112 SDTCisSameAs<0, 1>, 113 SDTCisVT<2, i32>]>; 114def SDT_ZVecBinaryConv : SDTypeProfile<1, 2, 115 [SDTCisVec<0>, 116 SDTCisVec<1>, 117 SDTCisSameAs<1, 2>]>; 118def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2, 119 [SDTCisVec<0>, 120 SDTCisVec<1>, 121 SDTCisVT<2, i32>]>; 122def SDT_ZRotateMask : SDTypeProfile<1, 2, 123 [SDTCisVec<0>, 124 SDTCisVT<1, i32>, 125 SDTCisVT<2, i32>]>; 126def SDT_ZJoinDwords : SDTypeProfile<1, 2, 127 [SDTCisVT<0, v2i64>, 128 SDTCisVT<1, i64>, 129 SDTCisVT<2, i64>]>; 130def SDT_ZVecTernary : SDTypeProfile<1, 3, 131 [SDTCisVec<0>, 132 SDTCisSameAs<0, 1>, 133 SDTCisSameAs<0, 2>, 134 SDTCisSameAs<0, 3>]>; 135def SDT_ZVecTernaryInt : SDTypeProfile<1, 3, 136 [SDTCisVec<0>, 137 SDTCisSameAs<0, 1>, 138 SDTCisSameAs<0, 2>, 139 SDTCisVT<3, i32>]>; 140def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4, 141 [SDTCisVec<0>, 142 SDTCisSameAs<0, 1>, 143 SDTCisSameAs<0, 2>, 144 SDTCisSameAs<0, 3>, 145 SDTCisVT<4, i32>]>; 146def SDT_ZTest : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>; 147 148//===----------------------------------------------------------------------===// 149// Node definitions 150//===----------------------------------------------------------------------===// 151 152// These are target-independent nodes, but have target-specific formats. 153def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 154 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 155def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 156 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, 157 SDNPOutGlue]>; 158def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>; 159 160// Nodes for SystemZISD::*. See SystemZISelLowering.h for more details. 161def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 162 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 163def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall, 164 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 165 SDNPVariadic]>; 166def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall, 167 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 168 SDNPVariadic]>; 169def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 171 SDNPVariadic]>; 172def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall, 173 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 174 SDNPVariadic]>; 175def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>; 176def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET", 177 SDT_ZWrapOffset, []>; 178def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>; 179def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>; 180def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>; 181def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>; 182def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask, 183 [SDNPHasChain, SDNPInGlue]>; 184def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask, 185 [SDNPInGlue]>; 186def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>; 187def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>; 188def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>; 189def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>; 190def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>; 191def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>; 192def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>; 193 194def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone, 195 [SDNPHasChain, SDNPSideEffect]>; 196 197def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap, 198 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 199def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap, 200 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 201 202def z_tdc : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>; 203 204// Defined because the index is an i32 rather than a pointer. 205def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 206 SDT_ZInsertVectorElt>; 207def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 208 SDT_ZExtractVectorElt>; 209def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>; 210def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>; 211def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>; 212def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>; 213def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>; 214def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>; 215def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>; 216def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>; 217def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS", 218 SDT_ZVecTernaryInt>; 219def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>; 220def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>; 221def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv, 222 [SDNPOutGlue]>; 223def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv, 224 [SDNPOutGlue]>; 225def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>; 226def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>; 227def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>; 228def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>; 229def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR", 230 SDT_ZVecBinaryInt>; 231def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR", 232 SDT_ZVecBinaryInt>; 233def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR", 234 SDT_ZVecBinaryInt>; 235def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>; 236def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>; 237def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>; 238def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>; 239def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary, 240 [SDNPOutGlue]>; 241def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary, 242 [SDNPOutGlue]>; 243def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary, 244 [SDNPOutGlue]>; 245def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>; 246def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>; 247def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>; 248def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv, 249 [SDNPOutGlue]>; 250def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv, 251 [SDNPOutGlue]>; 252def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv, 253 [SDNPOutGlue]>; 254def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>; 255def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>; 256def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>; 257def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt, 258 [SDNPOutGlue]>; 259def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt, 260 [SDNPOutGlue]>; 261def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary, 262 [SDNPOutGlue]>; 263def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary, 264 [SDNPOutGlue]>; 265def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary, 266 [SDNPOutGlue]>; 267def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary, 268 [SDNPOutGlue]>; 269def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary, 270 [SDNPOutGlue]>; 271def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt, 272 [SDNPOutGlue]>; 273def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC", 274 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>; 275def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt, 276 [SDNPOutGlue]>; 277 278class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW> 279 : SDNode<"SystemZISD::"##name, profile, 280 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 281 282def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">; 283def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">; 284def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">; 285def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">; 286def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">; 287def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">; 288def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">; 289def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">; 290def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">; 291def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">; 292def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">; 293def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>; 294 295def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength, 296 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 297def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop, 298 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 299def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength, 300 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 301def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop, 302 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 303def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength, 304 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 305def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop, 306 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 307def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength, 308 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 309def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop, 310 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 311def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength, 312 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 313def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop, 314 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 315def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString, 316 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 317def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString, 318 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 319def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString, 320 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 321def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic, 322 [SDNPInGlue]>; 323def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch, 324 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 325 SDNPMemOperand]>; 326 327def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, 328 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 329 SDNPSideEffect]>; 330def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, 331 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 332 SDNPSideEffect]>; 333def z_tend : SDNode<"SystemZISD::TEND", SDTNone, 334 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 335 336def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>; 337def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>; 338def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>; 339 340//===----------------------------------------------------------------------===// 341// Pattern fragments 342//===----------------------------------------------------------------------===// 343 344def z_lrvh : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i16)>; 345def z_lrv : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i32)>; 346def z_lrvg : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i64)>; 347 348def z_strvh : PatFrag<(ops node:$src, node:$addr), 349 (z_storebswap node:$src, node:$addr, i16)>; 350def z_strv : PatFrag<(ops node:$src, node:$addr), 351 (z_storebswap node:$src, node:$addr, i32)>; 352def z_strvg : PatFrag<(ops node:$src, node:$addr), 353 (z_storebswap node:$src, node:$addr, i64)>; 354 355// Signed and unsigned comparisons. 356def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 357 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 358 return Type != SystemZICMP::UnsignedOnly; 359}]>; 360def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 361 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 362 return Type != SystemZICMP::SignedOnly; 363}]>; 364 365// Register- and memory-based TEST UNDER MASK. 366def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>; 367def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>; 368 369// Register sign-extend operations. Sub-32-bit values are represented as i32s. 370def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>; 371def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>; 372def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>; 373 374// Match extensions of an i32 to an i64, followed by an in-register sign 375// extension from a sub-i32 value. 376def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>; 377def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>; 378 379// Register zero-extend operations. Sub-32-bit values are represented as i32s. 380def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>; 381def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>; 382def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>; 383 384// Extending loads in which the extension type can be signed. 385def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 386 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 387 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD; 388}]>; 389def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 390 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 391}]>; 392def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 393 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 394}]>; 395def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 396 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 397}]>; 398 399// Extending loads in which the extension type can be unsigned. 400def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 401 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 402 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD; 403}]>; 404def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 405 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 406}]>; 407def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 408 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 409}]>; 410def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 411 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 412}]>; 413 414// Extending loads in which the extension type doesn't matter. 415def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 416 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD; 417}]>; 418def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 419 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 420}]>; 421def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 422 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 423}]>; 424def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 425 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 426}]>; 427 428// Aligned loads. 429class AlignedLoad<SDPatternOperator load> 430 : PatFrag<(ops node:$addr), (load node:$addr), [{ 431 auto *Load = cast<LoadSDNode>(N); 432 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize(); 433}]>; 434def aligned_load : AlignedLoad<load>; 435def aligned_asextloadi16 : AlignedLoad<asextloadi16>; 436def aligned_asextloadi32 : AlignedLoad<asextloadi32>; 437def aligned_azextloadi16 : AlignedLoad<azextloadi16>; 438def aligned_azextloadi32 : AlignedLoad<azextloadi32>; 439 440// Aligned stores. 441class AlignedStore<SDPatternOperator store> 442 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 443 auto *Store = cast<StoreSDNode>(N); 444 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize(); 445}]>; 446def aligned_store : AlignedStore<store>; 447def aligned_truncstorei16 : AlignedStore<truncstorei16>; 448def aligned_truncstorei32 : AlignedStore<truncstorei32>; 449 450// Non-volatile loads. Used for instructions that might access the storage 451// location multiple times. 452class NonvolatileLoad<SDPatternOperator load> 453 : PatFrag<(ops node:$addr), (load node:$addr), [{ 454 auto *Load = cast<LoadSDNode>(N); 455 return !Load->isVolatile(); 456}]>; 457def nonvolatile_load : NonvolatileLoad<load>; 458def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>; 459def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>; 460def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>; 461 462// Non-volatile stores. 463class NonvolatileStore<SDPatternOperator store> 464 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 465 auto *Store = cast<StoreSDNode>(N); 466 return !Store->isVolatile(); 467}]>; 468def nonvolatile_store : NonvolatileStore<store>; 469def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>; 470def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>; 471def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>; 472 473// A store of a load that can be implemented using MVC. 474def mvc_store : PatFrag<(ops node:$value, node:$addr), 475 (unindexedstore node:$value, node:$addr), 476 [{ return storeLoadCanUseMVC(N); }]>; 477 478// Binary read-modify-write operations on memory in which the other 479// operand is also memory and for which block operations like NC can 480// be used. There are two patterns for each operator, depending on 481// which operand contains the "other" load. 482multiclass block_op<SDPatternOperator operator> { 483 def "1" : PatFrag<(ops node:$value, node:$addr), 484 (unindexedstore (operator node:$value, 485 (unindexedload node:$addr)), 486 node:$addr), 487 [{ return storeLoadCanUseBlockBinary(N, 0); }]>; 488 def "2" : PatFrag<(ops node:$value, node:$addr), 489 (unindexedstore (operator (unindexedload node:$addr), 490 node:$value), 491 node:$addr), 492 [{ return storeLoadCanUseBlockBinary(N, 1); }]>; 493} 494defm block_and : block_op<and>; 495defm block_or : block_op<or>; 496defm block_xor : block_op<xor>; 497 498// Insertions. 499def inserti8 : PatFrag<(ops node:$src1, node:$src2), 500 (or (and node:$src1, -256), node:$src2)>; 501def insertll : PatFrag<(ops node:$src1, node:$src2), 502 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>; 503def insertlh : PatFrag<(ops node:$src1, node:$src2), 504 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>; 505def inserthl : PatFrag<(ops node:$src1, node:$src2), 506 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>; 507def inserthh : PatFrag<(ops node:$src1, node:$src2), 508 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>; 509def insertlf : PatFrag<(ops node:$src1, node:$src2), 510 (or (and node:$src1, 0xffffffff00000000), node:$src2)>; 511def inserthf : PatFrag<(ops node:$src1, node:$src2), 512 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>; 513 514// ORs that can be treated as insertions. 515def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2), 516 (or node:$src1, node:$src2), [{ 517 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 518 return CurDAG->MaskedValueIsZero(N->getOperand(0), 519 APInt::getLowBitsSet(BitWidth, 8)); 520}]>; 521 522// ORs that can be treated as reversed insertions. 523def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2), 524 (or node:$src1, node:$src2), [{ 525 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 526 return CurDAG->MaskedValueIsZero(N->getOperand(1), 527 APInt::getLowBitsSet(BitWidth, 8)); 528}]>; 529 530// Negative integer absolute. 531def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>; 532 533// Integer absolute, matching the canonical form generated by DAGCombiner. 534def z_iabs32 : PatFrag<(ops node:$src), 535 (xor (add node:$src, (sra node:$src, (i32 31))), 536 (sra node:$src, (i32 31)))>; 537def z_iabs64 : PatFrag<(ops node:$src), 538 (xor (add node:$src, (sra node:$src, (i32 63))), 539 (sra node:$src, (i32 63)))>; 540def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>; 541def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>; 542 543// Integer multiply-and-add 544def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3), 545 (add (mul node:$src1, node:$src2), node:$src3)>; 546 547// Fused multiply-subtract, using the natural operand order. 548def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 549 (fma node:$src1, node:$src2, (fneg node:$src3))>; 550 551// Fused multiply-add and multiply-subtract, but with the order of the 552// operands matching SystemZ's MA and MS instructions. 553def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), 554 (fma node:$src2, node:$src3, node:$src1)>; 555def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 556 (fma node:$src2, node:$src3, (fneg node:$src1))>; 557 558// Floating-point negative absolute. 559def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>; 560 561// Create a unary operator that loads from memory and then performs 562// the given operation on it. 563class loadu<SDPatternOperator operator, SDPatternOperator load = load> 564 : PatFrag<(ops node:$addr), (operator (load node:$addr))>; 565 566// Create a store operator that performs the given unary operation 567// on the value before storing it. 568class storeu<SDPatternOperator operator, SDPatternOperator store = store> 569 : PatFrag<(ops node:$value, node:$addr), 570 (store (operator node:$value), node:$addr)>; 571 572// Create a store operator that performs the given inherent operation 573// and stores the resulting value. 574class storei<SDPatternOperator operator, SDPatternOperator store = store> 575 : PatFrag<(ops node:$addr), 576 (store (operator), node:$addr)>; 577 578// Vector representation of all-zeros and all-ones. 579def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>; 580def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>; 581 582// Load a scalar and replicate it in all elements of a vector. 583class z_replicate_load<ValueType scalartype, SDPatternOperator load> 584 : PatFrag<(ops node:$addr), 585 (z_replicate (scalartype (load node:$addr)))>; 586def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>; 587def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>; 588def z_replicate_loadi32 : z_replicate_load<i32, load>; 589def z_replicate_loadi64 : z_replicate_load<i64, load>; 590def z_replicate_loadf32 : z_replicate_load<f32, load>; 591def z_replicate_loadf64 : z_replicate_load<f64, load>; 592 593// Load a scalar and insert it into a single element of a vector. 594class z_vle<ValueType scalartype, SDPatternOperator load> 595 : PatFrag<(ops node:$vec, node:$addr, node:$index), 596 (z_vector_insert node:$vec, (scalartype (load node:$addr)), 597 node:$index)>; 598def z_vlei8 : z_vle<i32, anyextloadi8>; 599def z_vlei16 : z_vle<i32, anyextloadi16>; 600def z_vlei32 : z_vle<i32, load>; 601def z_vlei64 : z_vle<i64, load>; 602def z_vlef32 : z_vle<f32, load>; 603def z_vlef64 : z_vle<f64, load>; 604 605// Load a scalar and insert it into the low element of the high i64 of a 606// zeroed vector. 607class z_vllez<ValueType scalartype, SDPatternOperator load, int index> 608 : PatFrag<(ops node:$addr), 609 (z_vector_insert (z_vzero), 610 (scalartype (load node:$addr)), (i32 index))>; 611def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>; 612def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>; 613def z_vllezi32 : z_vllez<i32, load, 1>; 614def z_vllezi64 : PatFrag<(ops node:$addr), 615 (z_join_dwords (i64 (load node:$addr)), (i64 0))>; 616// We use high merges to form a v4f32 from four f32s. Propagating zero 617// into all elements but index 1 gives this expression. 618def z_vllezf32 : PatFrag<(ops node:$addr), 619 (bitconvert 620 (z_merge_high 621 (v2i64 622 (z_unpackl_high 623 (v4i32 624 (bitconvert 625 (v4f32 (scalar_to_vector 626 (f32 (load node:$addr)))))))), 627 (v2i64 (z_vzero))))>; 628def z_vllezf64 : PatFrag<(ops node:$addr), 629 (z_merge_high 630 (scalar_to_vector (f64 (load node:$addr))), 631 (z_vzero))>; 632 633// Store one element of a vector. 634class z_vste<ValueType scalartype, SDPatternOperator store> 635 : PatFrag<(ops node:$vec, node:$addr, node:$index), 636 (store (scalartype (z_vector_extract node:$vec, node:$index)), 637 node:$addr)>; 638def z_vstei8 : z_vste<i32, truncstorei8>; 639def z_vstei16 : z_vste<i32, truncstorei16>; 640def z_vstei32 : z_vste<i32, store>; 641def z_vstei64 : z_vste<i64, store>; 642def z_vstef32 : z_vste<f32, store>; 643def z_vstef64 : z_vste<f64, store>; 644 645// Arithmetic negation on vectors. 646def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>; 647 648// Bitwise negation on vectors. 649def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>; 650 651// Signed "integer greater than zero" on vectors. 652def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>; 653 654// Signed "integer less than zero" on vectors. 655def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>; 656 657// Integer absolute on vectors. 658class z_viabs<int shift> 659 : PatFrag<(ops node:$src), 660 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))), 661 (z_vsra_by_scalar node:$src, (i32 shift)))>; 662def z_viabs8 : z_viabs<7>; 663def z_viabs16 : z_viabs<15>; 664def z_viabs32 : z_viabs<31>; 665def z_viabs64 : z_viabs<63>; 666 667// Sign-extend the i64 elements of a vector. 668class z_vse<int shift> 669 : PatFrag<(ops node:$src), 670 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>; 671def z_vsei8 : z_vse<56>; 672def z_vsei16 : z_vse<48>; 673def z_vsei32 : z_vse<32>; 674 675// ...and again with the extensions being done on individual i64 scalars. 676class z_vse_by_parts<SDPatternOperator operator, int index1, int index2> 677 : PatFrag<(ops node:$src), 678 (z_join_dwords 679 (operator (z_vector_extract node:$src, index1)), 680 (operator (z_vector_extract node:$src, index2)))>; 681def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>; 682def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>; 683def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>; 684