1//===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Type profiles 12//===----------------------------------------------------------------------===// 13def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>; 14def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>, 15 SDTCisVT<1, i64>]>; 16def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 17def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 18def SDT_ZICmp : SDTypeProfile<0, 3, 19 [SDTCisSameAs<0, 1>, 20 SDTCisVT<2, i32>]>; 21def SDT_ZBRCCMask : SDTypeProfile<0, 3, 22 [SDTCisVT<0, i32>, 23 SDTCisVT<1, i32>, 24 SDTCisVT<2, OtherVT>]>; 25def SDT_ZSelectCCMask : SDTypeProfile<1, 4, 26 [SDTCisSameAs<0, 1>, 27 SDTCisSameAs<1, 2>, 28 SDTCisVT<3, i32>, 29 SDTCisVT<4, i32>]>; 30def SDT_ZWrapPtr : SDTypeProfile<1, 1, 31 [SDTCisSameAs<0, 1>, 32 SDTCisPtrTy<0>]>; 33def SDT_ZWrapOffset : SDTypeProfile<1, 2, 34 [SDTCisSameAs<0, 1>, 35 SDTCisSameAs<0, 2>, 36 SDTCisPtrTy<0>]>; 37def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 38def SDT_ZExtractAccess : SDTypeProfile<1, 1, 39 [SDTCisVT<0, i32>, 40 SDTCisVT<1, i32>]>; 41def SDT_ZGR128Binary32 : SDTypeProfile<1, 2, 42 [SDTCisVT<0, untyped>, 43 SDTCisVT<1, untyped>, 44 SDTCisVT<2, i32>]>; 45def SDT_ZGR128Binary64 : SDTypeProfile<1, 2, 46 [SDTCisVT<0, untyped>, 47 SDTCisVT<1, untyped>, 48 SDTCisVT<2, i64>]>; 49def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5, 50 [SDTCisVT<0, i32>, 51 SDTCisPtrTy<1>, 52 SDTCisVT<2, i32>, 53 SDTCisVT<3, i32>, 54 SDTCisVT<4, i32>, 55 SDTCisVT<5, i32>]>; 56def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6, 57 [SDTCisVT<0, i32>, 58 SDTCisPtrTy<1>, 59 SDTCisVT<2, i32>, 60 SDTCisVT<3, i32>, 61 SDTCisVT<4, i32>, 62 SDTCisVT<5, i32>, 63 SDTCisVT<6, i32>]>; 64def SDT_ZMemMemLength : SDTypeProfile<0, 3, 65 [SDTCisPtrTy<0>, 66 SDTCisPtrTy<1>, 67 SDTCisVT<2, i64>]>; 68def SDT_ZMemMemLoop : SDTypeProfile<0, 4, 69 [SDTCisPtrTy<0>, 70 SDTCisPtrTy<1>, 71 SDTCisVT<2, i64>, 72 SDTCisVT<3, i64>]>; 73def SDT_ZString : SDTypeProfile<1, 3, 74 [SDTCisPtrTy<0>, 75 SDTCisPtrTy<1>, 76 SDTCisPtrTy<2>, 77 SDTCisVT<3, i32>]>; 78def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 79def SDT_ZPrefetch : SDTypeProfile<0, 2, 80 [SDTCisVT<0, i32>, 81 SDTCisPtrTy<1>]>; 82def SDT_ZLoadBSwap : SDTypeProfile<1, 2, 83 [SDTCisInt<0>, 84 SDTCisPtrTy<1>, 85 SDTCisVT<2, OtherVT>]>; 86def SDT_ZStoreBSwap : SDTypeProfile<0, 3, 87 [SDTCisInt<0>, 88 SDTCisPtrTy<1>, 89 SDTCisVT<2, OtherVT>]>; 90def SDT_ZTBegin : SDTypeProfile<0, 2, 91 [SDTCisPtrTy<0>, 92 SDTCisVT<1, i32>]>; 93def SDT_ZInsertVectorElt : SDTypeProfile<1, 3, 94 [SDTCisVec<0>, 95 SDTCisSameAs<0, 1>, 96 SDTCisVT<3, i32>]>; 97def SDT_ZExtractVectorElt : SDTypeProfile<1, 2, 98 [SDTCisVec<1>, 99 SDTCisVT<2, i32>]>; 100def SDT_ZReplicate : SDTypeProfile<1, 1, 101 [SDTCisVec<0>]>; 102def SDT_ZVecUnaryConv : SDTypeProfile<1, 1, 103 [SDTCisVec<0>, 104 SDTCisVec<1>]>; 105def SDT_ZVecUnary : SDTypeProfile<1, 1, 106 [SDTCisVec<0>, 107 SDTCisSameAs<0, 1>]>; 108def SDT_ZVecBinary : SDTypeProfile<1, 2, 109 [SDTCisVec<0>, 110 SDTCisSameAs<0, 1>, 111 SDTCisSameAs<0, 2>]>; 112def SDT_ZVecBinaryInt : SDTypeProfile<1, 2, 113 [SDTCisVec<0>, 114 SDTCisSameAs<0, 1>, 115 SDTCisVT<2, i32>]>; 116def SDT_ZVecBinaryConv : SDTypeProfile<1, 2, 117 [SDTCisVec<0>, 118 SDTCisVec<1>, 119 SDTCisSameAs<1, 2>]>; 120def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2, 121 [SDTCisVec<0>, 122 SDTCisVec<1>, 123 SDTCisVT<2, i32>]>; 124def SDT_ZRotateMask : SDTypeProfile<1, 2, 125 [SDTCisVec<0>, 126 SDTCisVT<1, i32>, 127 SDTCisVT<2, i32>]>; 128def SDT_ZJoinDwords : SDTypeProfile<1, 2, 129 [SDTCisVT<0, v2i64>, 130 SDTCisVT<1, i64>, 131 SDTCisVT<2, i64>]>; 132def SDT_ZVecTernary : SDTypeProfile<1, 3, 133 [SDTCisVec<0>, 134 SDTCisSameAs<0, 1>, 135 SDTCisSameAs<0, 2>, 136 SDTCisSameAs<0, 3>]>; 137def SDT_ZVecTernaryInt : SDTypeProfile<1, 3, 138 [SDTCisVec<0>, 139 SDTCisSameAs<0, 1>, 140 SDTCisSameAs<0, 2>, 141 SDTCisVT<3, i32>]>; 142def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4, 143 [SDTCisVec<0>, 144 SDTCisSameAs<0, 1>, 145 SDTCisSameAs<0, 2>, 146 SDTCisSameAs<0, 3>, 147 SDTCisVT<4, i32>]>; 148 149//===----------------------------------------------------------------------===// 150// Node definitions 151//===----------------------------------------------------------------------===// 152 153// These are target-independent nodes, but have target-specific formats. 154def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 155 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 156def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 157 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, 158 SDNPOutGlue]>; 159def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>; 160 161// Nodes for SystemZISD::*. See SystemZISelLowering.h for more details. 162def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 163 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 164def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall, 165 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 166 SDNPVariadic]>; 167def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall, 168 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 169 SDNPVariadic]>; 170def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall, 171 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 172 SDNPVariadic]>; 173def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall, 174 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 175 SDNPVariadic]>; 176def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>; 177def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET", 178 SDT_ZWrapOffset, []>; 179def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>; 180def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>; 181def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>; 182def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>; 183def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask, 184 [SDNPHasChain, SDNPInGlue]>; 185def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask, 186 [SDNPInGlue]>; 187def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>; 188def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS", 189 SDT_ZExtractAccess>; 190def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>; 191def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>; 192def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>; 193def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>; 194def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>; 195def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>; 196 197def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone, 198 [SDNPHasChain, SDNPMayStore]>; 199def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone, 200 [SDNPHasChain, SDNPSideEffect]>; 201 202def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap, 203 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 204def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap, 205 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 206 207// Defined because the index is an i32 rather than a pointer. 208def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 209 SDT_ZInsertVectorElt>; 210def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 211 SDT_ZExtractVectorElt>; 212def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>; 213def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>; 214def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>; 215def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>; 216def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>; 217def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>; 218def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>; 219def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>; 220def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS", 221 SDT_ZVecTernaryInt>; 222def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>; 223def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>; 224def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv, 225 [SDNPOutGlue]>; 226def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv, 227 [SDNPOutGlue]>; 228def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>; 229def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>; 230def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>; 231def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>; 232def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR", 233 SDT_ZVecBinaryInt>; 234def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR", 235 SDT_ZVecBinaryInt>; 236def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR", 237 SDT_ZVecBinaryInt>; 238def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>; 239def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>; 240def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>; 241def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>; 242def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary, 243 [SDNPOutGlue]>; 244def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary, 245 [SDNPOutGlue]>; 246def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary, 247 [SDNPOutGlue]>; 248def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>; 249def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>; 250def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>; 251def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv, 252 [SDNPOutGlue]>; 253def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv, 254 [SDNPOutGlue]>; 255def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv, 256 [SDNPOutGlue]>; 257def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>; 258def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>; 259def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>; 260def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt, 261 [SDNPOutGlue]>; 262def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt, 263 [SDNPOutGlue]>; 264def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary, 265 [SDNPOutGlue]>; 266def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary, 267 [SDNPOutGlue]>; 268def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary, 269 [SDNPOutGlue]>; 270def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary, 271 [SDNPOutGlue]>; 272def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary, 273 [SDNPOutGlue]>; 274def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt, 275 [SDNPOutGlue]>; 276def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC", 277 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>; 278def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt, 279 [SDNPOutGlue]>; 280 281class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW> 282 : SDNode<"SystemZISD::"##name, profile, 283 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 284 285def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">; 286def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">; 287def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">; 288def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">; 289def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">; 290def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">; 291def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">; 292def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">; 293def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">; 294def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">; 295def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">; 296def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>; 297 298def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength, 299 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 300def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop, 301 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 302def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength, 303 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 304def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop, 305 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 306def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength, 307 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 308def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop, 309 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 310def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength, 311 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 312def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop, 313 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 314def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength, 315 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 316def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop, 317 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 318def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString, 319 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 320def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString, 321 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 322def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString, 323 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 324def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic, 325 [SDNPInGlue]>; 326def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch, 327 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 328 SDNPMemOperand]>; 329 330def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, 331 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 332 SDNPSideEffect]>; 333def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, 334 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 335 SDNPSideEffect]>; 336def z_tend : SDNode<"SystemZISD::TEND", SDTNone, 337 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 338 339def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>; 340def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>; 341def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>; 342 343//===----------------------------------------------------------------------===// 344// Pattern fragments 345//===----------------------------------------------------------------------===// 346 347def z_lrvh : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i16)>; 348def z_lrv : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i32)>; 349def z_lrvg : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i64)>; 350 351def z_strvh : PatFrag<(ops node:$src, node:$addr), 352 (z_storebswap node:$src, node:$addr, i16)>; 353def z_strv : PatFrag<(ops node:$src, node:$addr), 354 (z_storebswap node:$src, node:$addr, i32)>; 355def z_strvg : PatFrag<(ops node:$src, node:$addr), 356 (z_storebswap node:$src, node:$addr, i64)>; 357 358// Signed and unsigned comparisons. 359def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 360 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 361 return Type != SystemZICMP::UnsignedOnly; 362}]>; 363def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 364 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 365 return Type != SystemZICMP::SignedOnly; 366}]>; 367 368// Register- and memory-based TEST UNDER MASK. 369def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>; 370def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>; 371 372// Register sign-extend operations. Sub-32-bit values are represented as i32s. 373def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>; 374def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>; 375def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>; 376 377// Match extensions of an i32 to an i64, followed by an in-register sign 378// extension from a sub-i32 value. 379def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>; 380def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>; 381 382// Register zero-extend operations. Sub-32-bit values are represented as i32s. 383def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>; 384def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>; 385def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>; 386 387// Match extensions of an i32 to an i64, followed by an AND of the low 388// i8 or i16 part. 389def zext8dbl : PatFrag<(ops node:$src), (zext8 (anyext node:$src))>; 390def zext16dbl : PatFrag<(ops node:$src), (zext16 (anyext node:$src))>; 391 392// Typed floating-point loads. 393def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>; 394def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>; 395 396// Extending loads in which the extension type can be signed. 397def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 398 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 399 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD; 400}]>; 401def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 402 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 403}]>; 404def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 405 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 406}]>; 407def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 408 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 409}]>; 410 411// Extending loads in which the extension type can be unsigned. 412def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 413 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 414 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD; 415}]>; 416def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 417 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 418}]>; 419def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 420 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 421}]>; 422def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 423 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 424}]>; 425 426// Extending loads in which the extension type doesn't matter. 427def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 428 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD; 429}]>; 430def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 431 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 432}]>; 433def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 434 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 435}]>; 436def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 437 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 438}]>; 439 440// Aligned loads. 441class AlignedLoad<SDPatternOperator load> 442 : PatFrag<(ops node:$addr), (load node:$addr), [{ 443 auto *Load = cast<LoadSDNode>(N); 444 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize(); 445}]>; 446def aligned_load : AlignedLoad<load>; 447def aligned_asextloadi16 : AlignedLoad<asextloadi16>; 448def aligned_asextloadi32 : AlignedLoad<asextloadi32>; 449def aligned_azextloadi16 : AlignedLoad<azextloadi16>; 450def aligned_azextloadi32 : AlignedLoad<azextloadi32>; 451 452// Aligned stores. 453class AlignedStore<SDPatternOperator store> 454 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 455 auto *Store = cast<StoreSDNode>(N); 456 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize(); 457}]>; 458def aligned_store : AlignedStore<store>; 459def aligned_truncstorei16 : AlignedStore<truncstorei16>; 460def aligned_truncstorei32 : AlignedStore<truncstorei32>; 461 462// Non-volatile loads. Used for instructions that might access the storage 463// location multiple times. 464class NonvolatileLoad<SDPatternOperator load> 465 : PatFrag<(ops node:$addr), (load node:$addr), [{ 466 auto *Load = cast<LoadSDNode>(N); 467 return !Load->isVolatile(); 468}]>; 469def nonvolatile_load : NonvolatileLoad<load>; 470def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>; 471def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>; 472def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>; 473 474// Non-volatile stores. 475class NonvolatileStore<SDPatternOperator store> 476 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 477 auto *Store = cast<StoreSDNode>(N); 478 return !Store->isVolatile(); 479}]>; 480def nonvolatile_store : NonvolatileStore<store>; 481def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>; 482def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>; 483def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>; 484 485// A store of a load that can be implemented using MVC. 486def mvc_store : PatFrag<(ops node:$value, node:$addr), 487 (unindexedstore node:$value, node:$addr), 488 [{ return storeLoadCanUseMVC(N); }]>; 489 490// Binary read-modify-write operations on memory in which the other 491// operand is also memory and for which block operations like NC can 492// be used. There are two patterns for each operator, depending on 493// which operand contains the "other" load. 494multiclass block_op<SDPatternOperator operator> { 495 def "1" : PatFrag<(ops node:$value, node:$addr), 496 (unindexedstore (operator node:$value, 497 (unindexedload node:$addr)), 498 node:$addr), 499 [{ return storeLoadCanUseBlockBinary(N, 0); }]>; 500 def "2" : PatFrag<(ops node:$value, node:$addr), 501 (unindexedstore (operator (unindexedload node:$addr), 502 node:$value), 503 node:$addr), 504 [{ return storeLoadCanUseBlockBinary(N, 1); }]>; 505} 506defm block_and : block_op<and>; 507defm block_or : block_op<or>; 508defm block_xor : block_op<xor>; 509 510// Insertions. 511def inserti8 : PatFrag<(ops node:$src1, node:$src2), 512 (or (and node:$src1, -256), node:$src2)>; 513def insertll : PatFrag<(ops node:$src1, node:$src2), 514 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>; 515def insertlh : PatFrag<(ops node:$src1, node:$src2), 516 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>; 517def inserthl : PatFrag<(ops node:$src1, node:$src2), 518 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>; 519def inserthh : PatFrag<(ops node:$src1, node:$src2), 520 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>; 521def insertlf : PatFrag<(ops node:$src1, node:$src2), 522 (or (and node:$src1, 0xffffffff00000000), node:$src2)>; 523def inserthf : PatFrag<(ops node:$src1, node:$src2), 524 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>; 525 526// ORs that can be treated as insertions. 527def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2), 528 (or node:$src1, node:$src2), [{ 529 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 530 return CurDAG->MaskedValueIsZero(N->getOperand(0), 531 APInt::getLowBitsSet(BitWidth, 8)); 532}]>; 533 534// ORs that can be treated as reversed insertions. 535def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2), 536 (or node:$src1, node:$src2), [{ 537 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); 538 return CurDAG->MaskedValueIsZero(N->getOperand(1), 539 APInt::getLowBitsSet(BitWidth, 8)); 540}]>; 541 542// Negative integer absolute. 543def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>; 544 545// Integer absolute, matching the canonical form generated by DAGCombiner. 546def z_iabs32 : PatFrag<(ops node:$src), 547 (xor (add node:$src, (sra node:$src, (i32 31))), 548 (sra node:$src, (i32 31)))>; 549def z_iabs64 : PatFrag<(ops node:$src), 550 (xor (add node:$src, (sra node:$src, (i32 63))), 551 (sra node:$src, (i32 63)))>; 552def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>; 553def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>; 554 555// Integer multiply-and-add 556def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3), 557 (add (mul node:$src1, node:$src2), node:$src3)>; 558 559// Fused multiply-subtract, using the natural operand order. 560def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 561 (fma node:$src1, node:$src2, (fneg node:$src3))>; 562 563// Fused multiply-add and multiply-subtract, but with the order of the 564// operands matching SystemZ's MA and MS instructions. 565def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), 566 (fma node:$src2, node:$src3, node:$src1)>; 567def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 568 (fma node:$src2, node:$src3, (fneg node:$src1))>; 569 570// Floating-point negative absolute. 571def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>; 572 573// Create a unary operator that loads from memory and then performs 574// the given operation on it. 575class loadu<SDPatternOperator operator, SDPatternOperator load = load> 576 : PatFrag<(ops node:$addr), (operator (load node:$addr))>; 577 578// Create a store operator that performs the given unary operation 579// on the value before storing it. 580class storeu<SDPatternOperator operator, SDPatternOperator store = store> 581 : PatFrag<(ops node:$value, node:$addr), 582 (store (operator node:$value), node:$addr)>; 583 584// Vector representation of all-zeros and all-ones. 585def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>; 586def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>; 587 588// Load a scalar and replicate it in all elements of a vector. 589class z_replicate_load<ValueType scalartype, SDPatternOperator load> 590 : PatFrag<(ops node:$addr), 591 (z_replicate (scalartype (load node:$addr)))>; 592def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>; 593def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>; 594def z_replicate_loadi32 : z_replicate_load<i32, load>; 595def z_replicate_loadi64 : z_replicate_load<i64, load>; 596def z_replicate_loadf32 : z_replicate_load<f32, load>; 597def z_replicate_loadf64 : z_replicate_load<f64, load>; 598 599// Load a scalar and insert it into a single element of a vector. 600class z_vle<ValueType scalartype, SDPatternOperator load> 601 : PatFrag<(ops node:$vec, node:$addr, node:$index), 602 (z_vector_insert node:$vec, (scalartype (load node:$addr)), 603 node:$index)>; 604def z_vlei8 : z_vle<i32, anyextloadi8>; 605def z_vlei16 : z_vle<i32, anyextloadi16>; 606def z_vlei32 : z_vle<i32, load>; 607def z_vlei64 : z_vle<i64, load>; 608def z_vlef32 : z_vle<f32, load>; 609def z_vlef64 : z_vle<f64, load>; 610 611// Load a scalar and insert it into the low element of the high i64 of a 612// zeroed vector. 613class z_vllez<ValueType scalartype, SDPatternOperator load, int index> 614 : PatFrag<(ops node:$addr), 615 (z_vector_insert (z_vzero), 616 (scalartype (load node:$addr)), (i32 index))>; 617def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>; 618def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>; 619def z_vllezi32 : z_vllez<i32, load, 1>; 620def z_vllezi64 : PatFrag<(ops node:$addr), 621 (z_join_dwords (i64 (load node:$addr)), (i64 0))>; 622// We use high merges to form a v4f32 from four f32s. Propagating zero 623// into all elements but index 1 gives this expression. 624def z_vllezf32 : PatFrag<(ops node:$addr), 625 (bitconvert 626 (z_merge_high 627 (v2i64 628 (z_unpackl_high 629 (v4i32 630 (bitconvert 631 (v4f32 (scalar_to_vector 632 (f32 (load node:$addr)))))))), 633 (v2i64 (z_vzero))))>; 634def z_vllezf64 : PatFrag<(ops node:$addr), 635 (z_merge_high 636 (scalar_to_vector (f64 (load node:$addr))), 637 (z_vzero))>; 638 639// Store one element of a vector. 640class z_vste<ValueType scalartype, SDPatternOperator store> 641 : PatFrag<(ops node:$vec, node:$addr, node:$index), 642 (store (scalartype (z_vector_extract node:$vec, node:$index)), 643 node:$addr)>; 644def z_vstei8 : z_vste<i32, truncstorei8>; 645def z_vstei16 : z_vste<i32, truncstorei16>; 646def z_vstei32 : z_vste<i32, store>; 647def z_vstei64 : z_vste<i64, store>; 648def z_vstef32 : z_vste<f32, store>; 649def z_vstef64 : z_vste<f64, store>; 650 651// Arithmetic negation on vectors. 652def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>; 653 654// Bitwise negation on vectors. 655def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>; 656 657// Signed "integer greater than zero" on vectors. 658def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>; 659 660// Signed "integer less than zero" on vectors. 661def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>; 662 663// Integer absolute on vectors. 664class z_viabs<int shift> 665 : PatFrag<(ops node:$src), 666 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))), 667 (z_vsra_by_scalar node:$src, (i32 shift)))>; 668def z_viabs8 : z_viabs<7>; 669def z_viabs16 : z_viabs<15>; 670def z_viabs32 : z_viabs<31>; 671def z_viabs64 : z_viabs<63>; 672 673// Sign-extend the i64 elements of a vector. 674class z_vse<int shift> 675 : PatFrag<(ops node:$src), 676 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>; 677def z_vsei8 : z_vse<56>; 678def z_vsei16 : z_vse<48>; 679def z_vsei32 : z_vse<32>; 680 681// ...and again with the extensions being done on individual i64 scalars. 682class z_vse_by_parts<SDPatternOperator operator, int index1, int index2> 683 : PatFrag<(ops node:$src), 684 (z_join_dwords 685 (operator (z_vector_extract node:$src, index1)), 686 (operator (z_vector_extract node:$src, index2)))>; 687def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>; 688def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>; 689def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>; 690