1//===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Type profiles 12//===----------------------------------------------------------------------===// 13def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>; 14def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>, 15 SDTCisVT<1, i64>]>; 16def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 17def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 18def SDT_ZICmp : SDTypeProfile<0, 3, 19 [SDTCisSameAs<0, 1>, 20 SDTCisVT<2, i32>]>; 21def SDT_ZBRCCMask : SDTypeProfile<0, 3, 22 [SDTCisVT<0, i32>, 23 SDTCisVT<1, i32>, 24 SDTCisVT<2, OtherVT>]>; 25def SDT_ZSelectCCMask : SDTypeProfile<1, 4, 26 [SDTCisSameAs<0, 1>, 27 SDTCisSameAs<1, 2>, 28 SDTCisVT<3, i32>, 29 SDTCisVT<4, i32>]>; 30def SDT_ZWrapPtr : SDTypeProfile<1, 1, 31 [SDTCisSameAs<0, 1>, 32 SDTCisPtrTy<0>]>; 33def SDT_ZWrapOffset : SDTypeProfile<1, 2, 34 [SDTCisSameAs<0, 1>, 35 SDTCisSameAs<0, 2>, 36 SDTCisPtrTy<0>]>; 37def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 38def SDT_ZGR128Binary32 : SDTypeProfile<1, 2, 39 [SDTCisVT<0, untyped>, 40 SDTCisVT<1, untyped>, 41 SDTCisVT<2, i32>]>; 42def SDT_ZGR128Binary64 : SDTypeProfile<1, 2, 43 [SDTCisVT<0, untyped>, 44 SDTCisVT<1, untyped>, 45 SDTCisVT<2, i64>]>; 46def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5, 47 [SDTCisVT<0, i32>, 48 SDTCisPtrTy<1>, 49 SDTCisVT<2, i32>, 50 SDTCisVT<3, i32>, 51 SDTCisVT<4, i32>, 52 SDTCisVT<5, i32>]>; 53def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6, 54 [SDTCisVT<0, i32>, 55 SDTCisPtrTy<1>, 56 SDTCisVT<2, i32>, 57 SDTCisVT<3, i32>, 58 SDTCisVT<4, i32>, 59 SDTCisVT<5, i32>, 60 SDTCisVT<6, i32>]>; 61def SDT_ZMemMemLength : SDTypeProfile<0, 3, 62 [SDTCisPtrTy<0>, 63 SDTCisPtrTy<1>, 64 SDTCisVT<2, i64>]>; 65def SDT_ZMemMemLoop : SDTypeProfile<0, 4, 66 [SDTCisPtrTy<0>, 67 SDTCisPtrTy<1>, 68 SDTCisVT<2, i64>, 69 SDTCisVT<3, i64>]>; 70def SDT_ZString : SDTypeProfile<1, 3, 71 [SDTCisPtrTy<0>, 72 SDTCisPtrTy<1>, 73 SDTCisPtrTy<2>, 74 SDTCisVT<3, i32>]>; 75def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 76def SDT_ZPrefetch : SDTypeProfile<0, 2, 77 [SDTCisVT<0, i32>, 78 SDTCisPtrTy<1>]>; 79def SDT_ZLoadBSwap : SDTypeProfile<1, 2, 80 [SDTCisInt<0>, 81 SDTCisPtrTy<1>, 82 SDTCisVT<2, OtherVT>]>; 83def SDT_ZStoreBSwap : SDTypeProfile<0, 3, 84 [SDTCisInt<0>, 85 SDTCisPtrTy<1>, 86 SDTCisVT<2, OtherVT>]>; 87def SDT_ZTBegin : SDTypeProfile<0, 2, 88 [SDTCisPtrTy<0>, 89 SDTCisVT<1, i32>]>; 90def SDT_ZInsertVectorElt : SDTypeProfile<1, 3, 91 [SDTCisVec<0>, 92 SDTCisSameAs<0, 1>, 93 SDTCisVT<3, i32>]>; 94def SDT_ZExtractVectorElt : SDTypeProfile<1, 2, 95 [SDTCisVec<1>, 96 SDTCisVT<2, i32>]>; 97def SDT_ZReplicate : SDTypeProfile<1, 1, 98 [SDTCisVec<0>]>; 99def SDT_ZVecUnaryConv : SDTypeProfile<1, 1, 100 [SDTCisVec<0>, 101 SDTCisVec<1>]>; 102def SDT_ZVecUnary : SDTypeProfile<1, 1, 103 [SDTCisVec<0>, 104 SDTCisSameAs<0, 1>]>; 105def SDT_ZVecBinary : SDTypeProfile<1, 2, 106 [SDTCisVec<0>, 107 SDTCisSameAs<0, 1>, 108 SDTCisSameAs<0, 2>]>; 109def SDT_ZVecBinaryInt : SDTypeProfile<1, 2, 110 [SDTCisVec<0>, 111 SDTCisSameAs<0, 1>, 112 SDTCisVT<2, i32>]>; 113def SDT_ZVecBinaryConv : SDTypeProfile<1, 2, 114 [SDTCisVec<0>, 115 SDTCisVec<1>, 116 SDTCisSameAs<1, 2>]>; 117def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2, 118 [SDTCisVec<0>, 119 SDTCisVec<1>, 120 SDTCisVT<2, i32>]>; 121def SDT_ZRotateMask : SDTypeProfile<1, 2, 122 [SDTCisVec<0>, 123 SDTCisVT<1, i32>, 124 SDTCisVT<2, i32>]>; 125def SDT_ZJoinDwords : SDTypeProfile<1, 2, 126 [SDTCisVT<0, v2i64>, 127 SDTCisVT<1, i64>, 128 SDTCisVT<2, i64>]>; 129def SDT_ZVecTernary : SDTypeProfile<1, 3, 130 [SDTCisVec<0>, 131 SDTCisSameAs<0, 1>, 132 SDTCisSameAs<0, 2>, 133 SDTCisSameAs<0, 3>]>; 134def SDT_ZVecTernaryInt : SDTypeProfile<1, 3, 135 [SDTCisVec<0>, 136 SDTCisSameAs<0, 1>, 137 SDTCisSameAs<0, 2>, 138 SDTCisVT<3, i32>]>; 139def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4, 140 [SDTCisVec<0>, 141 SDTCisSameAs<0, 1>, 142 SDTCisSameAs<0, 2>, 143 SDTCisSameAs<0, 3>, 144 SDTCisVT<4, i32>]>; 145def SDT_ZTest : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>; 146 147//===----------------------------------------------------------------------===// 148// Node definitions 149//===----------------------------------------------------------------------===// 150 151// These are target-independent nodes, but have target-specific formats. 152def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 153 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 154def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 155 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, 156 SDNPOutGlue]>; 157def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>; 158 159// Nodes for SystemZISD::*. See SystemZISelLowering.h for more details. 160def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 161 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 162def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall, 163 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 164 SDNPVariadic]>; 165def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall, 166 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 167 SDNPVariadic]>; 168def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall, 169 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 170 SDNPVariadic]>; 171def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall, 172 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 173 SDNPVariadic]>; 174def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>; 175def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET", 176 SDT_ZWrapOffset, []>; 177def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>; 178def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>; 179def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>; 180def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>; 181def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask, 182 [SDNPHasChain, SDNPInGlue]>; 183def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask, 184 [SDNPInGlue]>; 185def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>; 186def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>; 187def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>; 188def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>; 189def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>; 190def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>; 191def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>; 192 193def z_serialize : SDNode<"SystemZISD::SERIALIZE", SDTNone, 194 [SDNPHasChain, SDNPMayStore]>; 195def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone, 196 [SDNPHasChain, SDNPSideEffect]>; 197 198def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap, 199 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 200def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap, 201 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 202 203def z_tdc : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>; 204 205// Defined because the index is an i32 rather than a pointer. 206def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 207 SDT_ZInsertVectorElt>; 208def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 209 SDT_ZExtractVectorElt>; 210def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>; 211def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>; 212def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>; 213def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>; 214def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>; 215def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>; 216def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>; 217def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>; 218def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS", 219 SDT_ZVecTernaryInt>; 220def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>; 221def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>; 222def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv, 223 [SDNPOutGlue]>; 224def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv, 225 [SDNPOutGlue]>; 226def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>; 227def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>; 228def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>; 229def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>; 230def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR", 231 SDT_ZVecBinaryInt>; 232def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR", 233 SDT_ZVecBinaryInt>; 234def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR", 235 SDT_ZVecBinaryInt>; 236def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>; 237def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>; 238def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>; 239def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>; 240def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary, 241 [SDNPOutGlue]>; 242def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary, 243 [SDNPOutGlue]>; 244def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary, 245 [SDNPOutGlue]>; 246def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>; 247def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>; 248def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>; 249def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv, 250 [SDNPOutGlue]>; 251def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv, 252 [SDNPOutGlue]>; 253def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv, 254 [SDNPOutGlue]>; 255def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>; 256def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>; 257def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>; 258def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt, 259 [SDNPOutGlue]>; 260def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt, 261 [SDNPOutGlue]>; 262def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary, 263 [SDNPOutGlue]>; 264def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary, 265 [SDNPOutGlue]>; 266def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary, 267 [SDNPOutGlue]>; 268def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary, 269 [SDNPOutGlue]>; 270def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary, 271 [SDNPOutGlue]>; 272def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt, 273 [SDNPOutGlue]>; 274def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC", 275 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>; 276def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt, 277 [SDNPOutGlue]>; 278 279class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW> 280 : SDNode<"SystemZISD::"##name, profile, 281 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 282 283def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">; 284def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">; 285def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">; 286def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">; 287def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">; 288def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">; 289def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">; 290def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">; 291def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">; 292def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">; 293def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">; 294def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>; 295 296def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength, 297 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 298def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop, 299 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 300def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength, 301 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 302def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop, 303 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 304def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength, 305 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 306def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop, 307 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 308def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength, 309 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 310def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop, 311 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 312def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength, 313 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 314def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop, 315 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 316def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString, 317 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 318def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString, 319 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 320def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString, 321 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 322def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic, 323 [SDNPInGlue]>; 324def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch, 325 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 326 SDNPMemOperand]>; 327 328def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, 329 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 330 SDNPSideEffect]>; 331def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, 332 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 333 SDNPSideEffect]>; 334def z_tend : SDNode<"SystemZISD::TEND", SDTNone, 335 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 336 337def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>; 338def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>; 339def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>; 340 341//===----------------------------------------------------------------------===// 342// Pattern fragments 343//===----------------------------------------------------------------------===// 344 345def z_lrvh : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i16)>; 346def z_lrv : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i32)>; 347def z_lrvg : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i64)>; 348 349def z_strvh : PatFrag<(ops node:$src, node:$addr), 350 (z_storebswap node:$src, node:$addr, i16)>; 351def z_strv : PatFrag<(ops node:$src, node:$addr), 352 (z_storebswap node:$src, node:$addr, i32)>; 353def z_strvg : PatFrag<(ops node:$src, node:$addr), 354 (z_storebswap node:$src, node:$addr, i64)>; 355 356// Signed and unsigned comparisons. 357def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 358 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 359 return Type != SystemZICMP::UnsignedOnly; 360}]>; 361def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 362 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 363 return Type != SystemZICMP::SignedOnly; 364}]>; 365 366// Register- and memory-based TEST UNDER MASK. 367def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>; 368def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>; 369 370// Register sign-extend operations. Sub-32-bit values are represented as i32s. 371def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>; 372def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>; 373def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>; 374 375// Match extensions of an i32 to an i64, followed by an in-register sign 376// extension from a sub-i32 value. 377def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>; 378def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>; 379 380// Register zero-extend operations. Sub-32-bit values are represented as i32s. 381def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>; 382def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>; 383def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>; 384 385// Extending loads in which the extension type can be signed. 386def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 387 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 388 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD; 389}]>; 390def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 391 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 392}]>; 393def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 394 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 395}]>; 396def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 397 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 398}]>; 399 400// Extending loads in which the extension type can be unsigned. 401def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 402 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 403 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD; 404}]>; 405def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 406 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 407}]>; 408def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 409 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 410}]>; 411def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 412 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 413}]>; 414 415// Extending loads in which the extension type doesn't matter. 416def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 417 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD; 418}]>; 419def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 420 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 421}]>; 422def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 423 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 424}]>; 425def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 426 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 427}]>; 428 429// Aligned loads. 430class AlignedLoad<SDPatternOperator load> 431 : PatFrag<(ops node:$addr), (load node:$addr), [{ 432 auto *Load = cast<LoadSDNode>(N); 433 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize(); 434}]>; 435def aligned_load : AlignedLoad<load>; 436def aligned_asextloadi16 : AlignedLoad<asextloadi16>; 437def aligned_asextloadi32 : AlignedLoad<asextloadi32>; 438def aligned_azextloadi16 : AlignedLoad<azextloadi16>; 439def aligned_azextloadi32 : AlignedLoad<azextloadi32>; 440 441// Aligned stores. 442class AlignedStore<SDPatternOperator store> 443 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 444 auto *Store = cast<StoreSDNode>(N); 445 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize(); 446}]>; 447def aligned_store : AlignedStore<store>; 448def aligned_truncstorei16 : AlignedStore<truncstorei16>; 449def aligned_truncstorei32 : AlignedStore<truncstorei32>; 450 451// Non-volatile loads. Used for instructions that might access the storage 452// location multiple times. 453class NonvolatileLoad<SDPatternOperator load> 454 : PatFrag<(ops node:$addr), (load node:$addr), [{ 455 auto *Load = cast<LoadSDNode>(N); 456 return !Load->isVolatile(); 457}]>; 458def nonvolatile_load : NonvolatileLoad<load>; 459def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>; 460def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>; 461def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>; 462 463// Non-volatile stores. 464class NonvolatileStore<SDPatternOperator store> 465 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 466 auto *Store = cast<StoreSDNode>(N); 467 return !Store->isVolatile(); 468}]>; 469def nonvolatile_store : NonvolatileStore<store>; 470def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>; 471def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>; 472def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>; 473 474// A store of a load that can be implemented using MVC. 475def mvc_store : PatFrag<(ops node:$value, node:$addr), 476 (unindexedstore node:$value, node:$addr), 477 [{ return storeLoadCanUseMVC(N); }]>; 478 479// Binary read-modify-write operations on memory in which the other 480// operand is also memory and for which block operations like NC can 481// be used. There are two patterns for each operator, depending on 482// which operand contains the "other" load. 483multiclass block_op<SDPatternOperator operator> { 484 def "1" : PatFrag<(ops node:$value, node:$addr), 485 (unindexedstore (operator node:$value, 486 (unindexedload node:$addr)), 487 node:$addr), 488 [{ return storeLoadCanUseBlockBinary(N, 0); }]>; 489 def "2" : PatFrag<(ops node:$value, node:$addr), 490 (unindexedstore (operator (unindexedload node:$addr), 491 node:$value), 492 node:$addr), 493 [{ return storeLoadCanUseBlockBinary(N, 1); }]>; 494} 495defm block_and : block_op<and>; 496defm block_or : block_op<or>; 497defm block_xor : block_op<xor>; 498 499// Insertions. 500def inserti8 : PatFrag<(ops node:$src1, node:$src2), 501 (or (and node:$src1, -256), node:$src2)>; 502def insertll : PatFrag<(ops node:$src1, node:$src2), 503 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>; 504def insertlh : PatFrag<(ops node:$src1, node:$src2), 505 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>; 506def inserthl : PatFrag<(ops node:$src1, node:$src2), 507 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>; 508def inserthh : PatFrag<(ops node:$src1, node:$src2), 509 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>; 510def insertlf : PatFrag<(ops node:$src1, node:$src2), 511 (or (and node:$src1, 0xffffffff00000000), node:$src2)>; 512def inserthf : PatFrag<(ops node:$src1, node:$src2), 513 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>; 514 515// ORs that can be treated as insertions. 516def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2), 517 (or node:$src1, node:$src2), [{ 518 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 519 return CurDAG->MaskedValueIsZero(N->getOperand(0), 520 APInt::getLowBitsSet(BitWidth, 8)); 521}]>; 522 523// ORs that can be treated as reversed insertions. 524def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2), 525 (or node:$src1, node:$src2), [{ 526 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 527 return CurDAG->MaskedValueIsZero(N->getOperand(1), 528 APInt::getLowBitsSet(BitWidth, 8)); 529}]>; 530 531// Negative integer absolute. 532def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>; 533 534// Integer absolute, matching the canonical form generated by DAGCombiner. 535def z_iabs32 : PatFrag<(ops node:$src), 536 (xor (add node:$src, (sra node:$src, (i32 31))), 537 (sra node:$src, (i32 31)))>; 538def z_iabs64 : PatFrag<(ops node:$src), 539 (xor (add node:$src, (sra node:$src, (i32 63))), 540 (sra node:$src, (i32 63)))>; 541def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>; 542def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>; 543 544// Integer multiply-and-add 545def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3), 546 (add (mul node:$src1, node:$src2), node:$src3)>; 547 548// Fused multiply-subtract, using the natural operand order. 549def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 550 (fma node:$src1, node:$src2, (fneg node:$src3))>; 551 552// Fused multiply-add and multiply-subtract, but with the order of the 553// operands matching SystemZ's MA and MS instructions. 554def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), 555 (fma node:$src2, node:$src3, node:$src1)>; 556def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 557 (fma node:$src2, node:$src3, (fneg node:$src1))>; 558 559// Floating-point negative absolute. 560def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>; 561 562// Create a unary operator that loads from memory and then performs 563// the given operation on it. 564class loadu<SDPatternOperator operator, SDPatternOperator load = load> 565 : PatFrag<(ops node:$addr), (operator (load node:$addr))>; 566 567// Create a store operator that performs the given unary operation 568// on the value before storing it. 569class storeu<SDPatternOperator operator, SDPatternOperator store = store> 570 : PatFrag<(ops node:$value, node:$addr), 571 (store (operator node:$value), node:$addr)>; 572 573// Create a store operator that performs the given inherent operation 574// and stores the resulting value. 575class storei<SDPatternOperator operator, SDPatternOperator store = store> 576 : PatFrag<(ops node:$addr), 577 (store (operator), node:$addr)>; 578 579// Vector representation of all-zeros and all-ones. 580def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>; 581def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>; 582 583// Load a scalar and replicate it in all elements of a vector. 584class z_replicate_load<ValueType scalartype, SDPatternOperator load> 585 : PatFrag<(ops node:$addr), 586 (z_replicate (scalartype (load node:$addr)))>; 587def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>; 588def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>; 589def z_replicate_loadi32 : z_replicate_load<i32, load>; 590def z_replicate_loadi64 : z_replicate_load<i64, load>; 591def z_replicate_loadf32 : z_replicate_load<f32, load>; 592def z_replicate_loadf64 : z_replicate_load<f64, load>; 593 594// Load a scalar and insert it into a single element of a vector. 595class z_vle<ValueType scalartype, SDPatternOperator load> 596 : PatFrag<(ops node:$vec, node:$addr, node:$index), 597 (z_vector_insert node:$vec, (scalartype (load node:$addr)), 598 node:$index)>; 599def z_vlei8 : z_vle<i32, anyextloadi8>; 600def z_vlei16 : z_vle<i32, anyextloadi16>; 601def z_vlei32 : z_vle<i32, load>; 602def z_vlei64 : z_vle<i64, load>; 603def z_vlef32 : z_vle<f32, load>; 604def z_vlef64 : z_vle<f64, load>; 605 606// Load a scalar and insert it into the low element of the high i64 of a 607// zeroed vector. 608class z_vllez<ValueType scalartype, SDPatternOperator load, int index> 609 : PatFrag<(ops node:$addr), 610 (z_vector_insert (z_vzero), 611 (scalartype (load node:$addr)), (i32 index))>; 612def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>; 613def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>; 614def z_vllezi32 : z_vllez<i32, load, 1>; 615def z_vllezi64 : PatFrag<(ops node:$addr), 616 (z_join_dwords (i64 (load node:$addr)), (i64 0))>; 617// We use high merges to form a v4f32 from four f32s. Propagating zero 618// into all elements but index 1 gives this expression. 619def z_vllezf32 : PatFrag<(ops node:$addr), 620 (bitconvert 621 (z_merge_high 622 (v2i64 623 (z_unpackl_high 624 (v4i32 625 (bitconvert 626 (v4f32 (scalar_to_vector 627 (f32 (load node:$addr)))))))), 628 (v2i64 (z_vzero))))>; 629def z_vllezf64 : PatFrag<(ops node:$addr), 630 (z_merge_high 631 (scalar_to_vector (f64 (load node:$addr))), 632 (z_vzero))>; 633 634// Store one element of a vector. 635class z_vste<ValueType scalartype, SDPatternOperator store> 636 : PatFrag<(ops node:$vec, node:$addr, node:$index), 637 (store (scalartype (z_vector_extract node:$vec, node:$index)), 638 node:$addr)>; 639def z_vstei8 : z_vste<i32, truncstorei8>; 640def z_vstei16 : z_vste<i32, truncstorei16>; 641def z_vstei32 : z_vste<i32, store>; 642def z_vstei64 : z_vste<i64, store>; 643def z_vstef32 : z_vste<f32, store>; 644def z_vstef64 : z_vste<f64, store>; 645 646// Arithmetic negation on vectors. 647def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>; 648 649// Bitwise negation on vectors. 650def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>; 651 652// Signed "integer greater than zero" on vectors. 653def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>; 654 655// Signed "integer less than zero" on vectors. 656def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>; 657 658// Integer absolute on vectors. 659class z_viabs<int shift> 660 : PatFrag<(ops node:$src), 661 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))), 662 (z_vsra_by_scalar node:$src, (i32 shift)))>; 663def z_viabs8 : z_viabs<7>; 664def z_viabs16 : z_viabs<15>; 665def z_viabs32 : z_viabs<31>; 666def z_viabs64 : z_viabs<63>; 667 668// Sign-extend the i64 elements of a vector. 669class z_vse<int shift> 670 : PatFrag<(ops node:$src), 671 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>; 672def z_vsei8 : z_vse<56>; 673def z_vsei16 : z_vse<48>; 674def z_vsei32 : z_vse<32>; 675 676// ...and again with the extensions being done on individual i64 scalars. 677class z_vse_by_parts<SDPatternOperator operator, int index1, int index2> 678 : PatFrag<(ops node:$src), 679 (z_join_dwords 680 (operator (z_vector_extract node:$src, index1)), 681 (operator (z_vector_extract node:$src, index2)))>; 682def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>; 683def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>; 684def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>; 685