1//===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Type profiles 12//===----------------------------------------------------------------------===// 13def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>, 14 SDTCisVT<1, i64>]>; 15def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>, 16 SDTCisVT<1, i64>]>; 17def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 18def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 19def SDT_ZICmp : SDTypeProfile<0, 3, 20 [SDTCisSameAs<0, 1>, 21 SDTCisVT<2, i32>]>; 22def SDT_ZBRCCMask : SDTypeProfile<0, 3, 23 [SDTCisVT<0, i32>, 24 SDTCisVT<1, i32>, 25 SDTCisVT<2, OtherVT>]>; 26def SDT_ZSelectCCMask : SDTypeProfile<1, 4, 27 [SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisVT<3, i32>, 30 SDTCisVT<4, i32>]>; 31def SDT_ZWrapPtr : SDTypeProfile<1, 1, 32 [SDTCisSameAs<0, 1>, 33 SDTCisPtrTy<0>]>; 34def SDT_ZWrapOffset : SDTypeProfile<1, 2, 35 [SDTCisSameAs<0, 1>, 36 SDTCisSameAs<0, 2>, 37 SDTCisPtrTy<0>]>; 38def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; 39def SDT_ZGR128Binary : SDTypeProfile<1, 2, 40 [SDTCisVT<0, untyped>, 41 SDTCisInt<1>, 42 SDTCisInt<2>]>; 43def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5, 44 [SDTCisVT<0, i32>, 45 SDTCisPtrTy<1>, 46 SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, 48 SDTCisVT<4, i32>, 49 SDTCisVT<5, i32>]>; 50def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6, 51 [SDTCisVT<0, i32>, 52 SDTCisPtrTy<1>, 53 SDTCisVT<2, i32>, 54 SDTCisVT<3, i32>, 55 SDTCisVT<4, i32>, 56 SDTCisVT<5, i32>, 57 SDTCisVT<6, i32>]>; 58def SDT_ZMemMemLength : SDTypeProfile<0, 3, 59 [SDTCisPtrTy<0>, 60 SDTCisPtrTy<1>, 61 SDTCisVT<2, i64>]>; 62def SDT_ZMemMemLoop : SDTypeProfile<0, 4, 63 [SDTCisPtrTy<0>, 64 SDTCisPtrTy<1>, 65 SDTCisVT<2, i64>, 66 SDTCisVT<3, i64>]>; 67def SDT_ZString : SDTypeProfile<1, 3, 68 [SDTCisPtrTy<0>, 69 SDTCisPtrTy<1>, 70 SDTCisPtrTy<2>, 71 SDTCisVT<3, i32>]>; 72def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>; 73def SDT_ZPrefetch : SDTypeProfile<0, 2, 74 [SDTCisVT<0, i32>, 75 SDTCisPtrTy<1>]>; 76def SDT_ZLoadBSwap : SDTypeProfile<1, 2, 77 [SDTCisInt<0>, 78 SDTCisPtrTy<1>, 79 SDTCisVT<2, OtherVT>]>; 80def SDT_ZStoreBSwap : SDTypeProfile<0, 3, 81 [SDTCisInt<0>, 82 SDTCisPtrTy<1>, 83 SDTCisVT<2, OtherVT>]>; 84def SDT_ZTBegin : SDTypeProfile<0, 2, 85 [SDTCisPtrTy<0>, 86 SDTCisVT<1, i32>]>; 87def SDT_ZInsertVectorElt : SDTypeProfile<1, 3, 88 [SDTCisVec<0>, 89 SDTCisSameAs<0, 1>, 90 SDTCisVT<3, i32>]>; 91def SDT_ZExtractVectorElt : SDTypeProfile<1, 2, 92 [SDTCisVec<1>, 93 SDTCisVT<2, i32>]>; 94def SDT_ZReplicate : SDTypeProfile<1, 1, 95 [SDTCisVec<0>]>; 96def SDT_ZVecUnaryConv : SDTypeProfile<1, 1, 97 [SDTCisVec<0>, 98 SDTCisVec<1>]>; 99def SDT_ZVecUnary : SDTypeProfile<1, 1, 100 [SDTCisVec<0>, 101 SDTCisSameAs<0, 1>]>; 102def SDT_ZVecBinary : SDTypeProfile<1, 2, 103 [SDTCisVec<0>, 104 SDTCisSameAs<0, 1>, 105 SDTCisSameAs<0, 2>]>; 106def SDT_ZVecBinaryInt : SDTypeProfile<1, 2, 107 [SDTCisVec<0>, 108 SDTCisSameAs<0, 1>, 109 SDTCisVT<2, i32>]>; 110def SDT_ZVecBinaryConv : SDTypeProfile<1, 2, 111 [SDTCisVec<0>, 112 SDTCisVec<1>, 113 SDTCisSameAs<1, 2>]>; 114def SDT_ZVecBinaryConvInt : SDTypeProfile<1, 2, 115 [SDTCisVec<0>, 116 SDTCisVec<1>, 117 SDTCisVT<2, i32>]>; 118def SDT_ZRotateMask : SDTypeProfile<1, 2, 119 [SDTCisVec<0>, 120 SDTCisVT<1, i32>, 121 SDTCisVT<2, i32>]>; 122def SDT_ZJoinDwords : SDTypeProfile<1, 2, 123 [SDTCisVT<0, v2i64>, 124 SDTCisVT<1, i64>, 125 SDTCisVT<2, i64>]>; 126def SDT_ZVecTernary : SDTypeProfile<1, 3, 127 [SDTCisVec<0>, 128 SDTCisSameAs<0, 1>, 129 SDTCisSameAs<0, 2>, 130 SDTCisSameAs<0, 3>]>; 131def SDT_ZVecTernaryInt : SDTypeProfile<1, 3, 132 [SDTCisVec<0>, 133 SDTCisSameAs<0, 1>, 134 SDTCisSameAs<0, 2>, 135 SDTCisVT<3, i32>]>; 136def SDT_ZVecQuaternaryInt : SDTypeProfile<1, 4, 137 [SDTCisVec<0>, 138 SDTCisSameAs<0, 1>, 139 SDTCisSameAs<0, 2>, 140 SDTCisSameAs<0, 3>, 141 SDTCisVT<4, i32>]>; 142def SDT_ZTest : SDTypeProfile<0, 2, [SDTCisVT<1, i64>]>; 143 144//===----------------------------------------------------------------------===// 145// Node definitions 146//===----------------------------------------------------------------------===// 147 148// These are target-independent nodes, but have target-specific formats. 149def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart, 150 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 151def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd, 152 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, 153 SDNPOutGlue]>; 154def global_offset_table : SDNode<"ISD::GLOBAL_OFFSET_TABLE", SDTPtrLeaf>; 155 156// Nodes for SystemZISD::*. See SystemZISelLowering.h for more details. 157def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone, 158 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 159def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall, 160 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 161 SDNPVariadic]>; 162def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall, 163 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 164 SDNPVariadic]>; 165def z_tls_gdcall : SDNode<"SystemZISD::TLS_GDCALL", SDT_ZCall, 166 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 167 SDNPVariadic]>; 168def z_tls_ldcall : SDNode<"SystemZISD::TLS_LDCALL", SDT_ZCall, 169 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 170 SDNPVariadic]>; 171def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>; 172def z_pcrel_offset : SDNode<"SystemZISD::PCREL_OFFSET", 173 SDT_ZWrapOffset, []>; 174def z_iabs : SDNode<"SystemZISD::IABS", SDTIntUnaryOp, []>; 175def z_icmp : SDNode<"SystemZISD::ICMP", SDT_ZICmp, [SDNPOutGlue]>; 176def z_fcmp : SDNode<"SystemZISD::FCMP", SDT_ZCmp, [SDNPOutGlue]>; 177def z_tm : SDNode<"SystemZISD::TM", SDT_ZICmp, [SDNPOutGlue]>; 178def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask, 179 [SDNPHasChain, SDNPInGlue]>; 180def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask, 181 [SDNPInGlue]>; 182def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>; 183def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>; 184def z_umul_lohi : SDNode<"SystemZISD::UMUL_LOHI", SDT_ZGR128Binary>; 185def z_sdivrem : SDNode<"SystemZISD::SDIVREM", SDT_ZGR128Binary>; 186def z_udivrem : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>; 187 188def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone, 189 [SDNPHasChain, SDNPSideEffect]>; 190 191def z_loadbswap : SDNode<"SystemZISD::LRV", SDT_ZLoadBSwap, 192 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 193def z_storebswap : SDNode<"SystemZISD::STRV", SDT_ZStoreBSwap, 194 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 195 196def z_tdc : SDNode<"SystemZISD::TDC", SDT_ZTest, [SDNPOutGlue]>; 197 198// Defined because the index is an i32 rather than a pointer. 199def z_vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 200 SDT_ZInsertVectorElt>; 201def z_vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 202 SDT_ZExtractVectorElt>; 203def z_byte_mask : SDNode<"SystemZISD::BYTE_MASK", SDT_ZReplicate>; 204def z_rotate_mask : SDNode<"SystemZISD::ROTATE_MASK", SDT_ZRotateMask>; 205def z_replicate : SDNode<"SystemZISD::REPLICATE", SDT_ZReplicate>; 206def z_join_dwords : SDNode<"SystemZISD::JOIN_DWORDS", SDT_ZJoinDwords>; 207def z_splat : SDNode<"SystemZISD::SPLAT", SDT_ZVecBinaryInt>; 208def z_merge_high : SDNode<"SystemZISD::MERGE_HIGH", SDT_ZVecBinary>; 209def z_merge_low : SDNode<"SystemZISD::MERGE_LOW", SDT_ZVecBinary>; 210def z_shl_double : SDNode<"SystemZISD::SHL_DOUBLE", SDT_ZVecTernaryInt>; 211def z_permute_dwords : SDNode<"SystemZISD::PERMUTE_DWORDS", 212 SDT_ZVecTernaryInt>; 213def z_permute : SDNode<"SystemZISD::PERMUTE", SDT_ZVecTernary>; 214def z_pack : SDNode<"SystemZISD::PACK", SDT_ZVecBinaryConv>; 215def z_packs_cc : SDNode<"SystemZISD::PACKS_CC", SDT_ZVecBinaryConv, 216 [SDNPOutGlue]>; 217def z_packls_cc : SDNode<"SystemZISD::PACKLS_CC", SDT_ZVecBinaryConv, 218 [SDNPOutGlue]>; 219def z_unpack_high : SDNode<"SystemZISD::UNPACK_HIGH", SDT_ZVecUnaryConv>; 220def z_unpackl_high : SDNode<"SystemZISD::UNPACKL_HIGH", SDT_ZVecUnaryConv>; 221def z_unpack_low : SDNode<"SystemZISD::UNPACK_LOW", SDT_ZVecUnaryConv>; 222def z_unpackl_low : SDNode<"SystemZISD::UNPACKL_LOW", SDT_ZVecUnaryConv>; 223def z_vshl_by_scalar : SDNode<"SystemZISD::VSHL_BY_SCALAR", 224 SDT_ZVecBinaryInt>; 225def z_vsrl_by_scalar : SDNode<"SystemZISD::VSRL_BY_SCALAR", 226 SDT_ZVecBinaryInt>; 227def z_vsra_by_scalar : SDNode<"SystemZISD::VSRA_BY_SCALAR", 228 SDT_ZVecBinaryInt>; 229def z_vsum : SDNode<"SystemZISD::VSUM", SDT_ZVecBinaryConv>; 230def z_vicmpe : SDNode<"SystemZISD::VICMPE", SDT_ZVecBinary>; 231def z_vicmph : SDNode<"SystemZISD::VICMPH", SDT_ZVecBinary>; 232def z_vicmphl : SDNode<"SystemZISD::VICMPHL", SDT_ZVecBinary>; 233def z_vicmpes : SDNode<"SystemZISD::VICMPES", SDT_ZVecBinary, 234 [SDNPOutGlue]>; 235def z_vicmphs : SDNode<"SystemZISD::VICMPHS", SDT_ZVecBinary, 236 [SDNPOutGlue]>; 237def z_vicmphls : SDNode<"SystemZISD::VICMPHLS", SDT_ZVecBinary, 238 [SDNPOutGlue]>; 239def z_vfcmpe : SDNode<"SystemZISD::VFCMPE", SDT_ZVecBinaryConv>; 240def z_vfcmph : SDNode<"SystemZISD::VFCMPH", SDT_ZVecBinaryConv>; 241def z_vfcmphe : SDNode<"SystemZISD::VFCMPHE", SDT_ZVecBinaryConv>; 242def z_vfcmpes : SDNode<"SystemZISD::VFCMPES", SDT_ZVecBinaryConv, 243 [SDNPOutGlue]>; 244def z_vfcmphs : SDNode<"SystemZISD::VFCMPHS", SDT_ZVecBinaryConv, 245 [SDNPOutGlue]>; 246def z_vfcmphes : SDNode<"SystemZISD::VFCMPHES", SDT_ZVecBinaryConv, 247 [SDNPOutGlue]>; 248def z_vextend : SDNode<"SystemZISD::VEXTEND", SDT_ZVecUnaryConv>; 249def z_vround : SDNode<"SystemZISD::VROUND", SDT_ZVecUnaryConv>; 250def z_vtm : SDNode<"SystemZISD::VTM", SDT_ZCmp, [SDNPOutGlue]>; 251def z_vfae_cc : SDNode<"SystemZISD::VFAE_CC", SDT_ZVecTernaryInt, 252 [SDNPOutGlue]>; 253def z_vfaez_cc : SDNode<"SystemZISD::VFAEZ_CC", SDT_ZVecTernaryInt, 254 [SDNPOutGlue]>; 255def z_vfee_cc : SDNode<"SystemZISD::VFEE_CC", SDT_ZVecBinary, 256 [SDNPOutGlue]>; 257def z_vfeez_cc : SDNode<"SystemZISD::VFEEZ_CC", SDT_ZVecBinary, 258 [SDNPOutGlue]>; 259def z_vfene_cc : SDNode<"SystemZISD::VFENE_CC", SDT_ZVecBinary, 260 [SDNPOutGlue]>; 261def z_vfenez_cc : SDNode<"SystemZISD::VFENEZ_CC", SDT_ZVecBinary, 262 [SDNPOutGlue]>; 263def z_vistr_cc : SDNode<"SystemZISD::VISTR_CC", SDT_ZVecUnary, 264 [SDNPOutGlue]>; 265def z_vstrc_cc : SDNode<"SystemZISD::VSTRC_CC", SDT_ZVecQuaternaryInt, 266 [SDNPOutGlue]>; 267def z_vstrcz_cc : SDNode<"SystemZISD::VSTRCZ_CC", 268 SDT_ZVecQuaternaryInt, [SDNPOutGlue]>; 269def z_vftci : SDNode<"SystemZISD::VFTCI", SDT_ZVecBinaryConvInt, 270 [SDNPOutGlue]>; 271 272class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW> 273 : SDNode<"SystemZISD::"##name, profile, 274 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 275 276def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">; 277def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">; 278def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">; 279def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">; 280def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">; 281def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">; 282def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">; 283def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">; 284def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">; 285def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">; 286def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">; 287def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>; 288 289def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength, 290 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 291def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop, 292 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 293def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength, 294 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 295def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop, 296 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 297def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength, 298 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 299def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop, 300 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 301def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength, 302 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 303def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop, 304 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 305def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength, 306 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 307def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop, 308 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 309def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString, 310 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 311def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString, 312 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>; 313def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString, 314 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>; 315def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic, 316 [SDNPInGlue]>; 317def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch, 318 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 319 SDNPMemOperand]>; 320 321def z_tbegin : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin, 322 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 323 SDNPSideEffect]>; 324def z_tbegin_nofloat : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin, 325 [SDNPHasChain, SDNPOutGlue, SDNPMayStore, 326 SDNPSideEffect]>; 327def z_tend : SDNode<"SystemZISD::TEND", SDTNone, 328 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 329 330def z_vshl : SDNode<"ISD::SHL", SDT_ZVecBinary>; 331def z_vsra : SDNode<"ISD::SRA", SDT_ZVecBinary>; 332def z_vsrl : SDNode<"ISD::SRL", SDT_ZVecBinary>; 333 334//===----------------------------------------------------------------------===// 335// Pattern fragments 336//===----------------------------------------------------------------------===// 337 338def z_lrvh : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i16)>; 339def z_lrv : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i32)>; 340def z_lrvg : PatFrag<(ops node:$addr), (z_loadbswap node:$addr, i64)>; 341 342def z_strvh : PatFrag<(ops node:$src, node:$addr), 343 (z_storebswap node:$src, node:$addr, i16)>; 344def z_strv : PatFrag<(ops node:$src, node:$addr), 345 (z_storebswap node:$src, node:$addr, i32)>; 346def z_strvg : PatFrag<(ops node:$src, node:$addr), 347 (z_storebswap node:$src, node:$addr, i64)>; 348 349// Signed and unsigned comparisons. 350def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 351 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 352 return Type != SystemZICMP::UnsignedOnly; 353}]>; 354def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{ 355 unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 356 return Type != SystemZICMP::SignedOnly; 357}]>; 358 359// Register- and memory-based TEST UNDER MASK. 360def z_tm_reg : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, imm)>; 361def z_tm_mem : PatFrag<(ops node:$a, node:$b), (z_tm node:$a, node:$b, 0)>; 362 363// Register sign-extend operations. Sub-32-bit values are represented as i32s. 364def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>; 365def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>; 366def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>; 367 368// Match extensions of an i32 to an i64, followed by an in-register sign 369// extension from a sub-i32 value. 370def sext8dbl : PatFrag<(ops node:$src), (sext8 (anyext node:$src))>; 371def sext16dbl : PatFrag<(ops node:$src), (sext16 (anyext node:$src))>; 372 373// Register zero-extend operations. Sub-32-bit values are represented as i32s. 374def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>; 375def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>; 376def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>; 377 378// Extending loads in which the extension type can be signed. 379def asextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 380 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 381 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD; 382}]>; 383def asextloadi8 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 384 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 385}]>; 386def asextloadi16 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 387 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 388}]>; 389def asextloadi32 : PatFrag<(ops node:$ptr), (asextload node:$ptr), [{ 390 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 391}]>; 392 393// Extending loads in which the extension type can be unsigned. 394def azextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 395 unsigned Type = cast<LoadSDNode>(N)->getExtensionType(); 396 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD; 397}]>; 398def azextloadi8 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 399 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 400}]>; 401def azextloadi16 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 402 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 403}]>; 404def azextloadi32 : PatFrag<(ops node:$ptr), (azextload node:$ptr), [{ 405 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 406}]>; 407 408// Extending loads in which the extension type doesn't matter. 409def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 410 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD; 411}]>; 412def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 413 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 414}]>; 415def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 416 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 417}]>; 418def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{ 419 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 420}]>; 421 422// Aligned loads. 423class AlignedLoad<SDPatternOperator load> 424 : PatFrag<(ops node:$addr), (load node:$addr), [{ 425 auto *Load = cast<LoadSDNode>(N); 426 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize(); 427}]>; 428def aligned_load : AlignedLoad<load>; 429def aligned_asextloadi16 : AlignedLoad<asextloadi16>; 430def aligned_asextloadi32 : AlignedLoad<asextloadi32>; 431def aligned_azextloadi16 : AlignedLoad<azextloadi16>; 432def aligned_azextloadi32 : AlignedLoad<azextloadi32>; 433 434// Aligned stores. 435class AlignedStore<SDPatternOperator store> 436 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 437 auto *Store = cast<StoreSDNode>(N); 438 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize(); 439}]>; 440def aligned_store : AlignedStore<store>; 441def aligned_truncstorei16 : AlignedStore<truncstorei16>; 442def aligned_truncstorei32 : AlignedStore<truncstorei32>; 443 444// Non-volatile loads. Used for instructions that might access the storage 445// location multiple times. 446class NonvolatileLoad<SDPatternOperator load> 447 : PatFrag<(ops node:$addr), (load node:$addr), [{ 448 auto *Load = cast<LoadSDNode>(N); 449 return !Load->isVolatile(); 450}]>; 451def nonvolatile_load : NonvolatileLoad<load>; 452def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>; 453def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>; 454def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>; 455 456// Non-volatile stores. 457class NonvolatileStore<SDPatternOperator store> 458 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{ 459 auto *Store = cast<StoreSDNode>(N); 460 return !Store->isVolatile(); 461}]>; 462def nonvolatile_store : NonvolatileStore<store>; 463def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>; 464def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>; 465def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>; 466 467// A store of a load that can be implemented using MVC. 468def mvc_store : PatFrag<(ops node:$value, node:$addr), 469 (unindexedstore node:$value, node:$addr), 470 [{ return storeLoadCanUseMVC(N); }]>; 471 472// Binary read-modify-write operations on memory in which the other 473// operand is also memory and for which block operations like NC can 474// be used. There are two patterns for each operator, depending on 475// which operand contains the "other" load. 476multiclass block_op<SDPatternOperator operator> { 477 def "1" : PatFrag<(ops node:$value, node:$addr), 478 (unindexedstore (operator node:$value, 479 (unindexedload node:$addr)), 480 node:$addr), 481 [{ return storeLoadCanUseBlockBinary(N, 0); }]>; 482 def "2" : PatFrag<(ops node:$value, node:$addr), 483 (unindexedstore (operator (unindexedload node:$addr), 484 node:$value), 485 node:$addr), 486 [{ return storeLoadCanUseBlockBinary(N, 1); }]>; 487} 488defm block_and : block_op<and>; 489defm block_or : block_op<or>; 490defm block_xor : block_op<xor>; 491 492// Insertions. 493def inserti8 : PatFrag<(ops node:$src1, node:$src2), 494 (or (and node:$src1, -256), node:$src2)>; 495def insertll : PatFrag<(ops node:$src1, node:$src2), 496 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>; 497def insertlh : PatFrag<(ops node:$src1, node:$src2), 498 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>; 499def inserthl : PatFrag<(ops node:$src1, node:$src2), 500 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>; 501def inserthh : PatFrag<(ops node:$src1, node:$src2), 502 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>; 503def insertlf : PatFrag<(ops node:$src1, node:$src2), 504 (or (and node:$src1, 0xffffffff00000000), node:$src2)>; 505def inserthf : PatFrag<(ops node:$src1, node:$src2), 506 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>; 507 508// ORs that can be treated as insertions. 509def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2), 510 (or node:$src1, node:$src2), [{ 511 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 512 return CurDAG->MaskedValueIsZero(N->getOperand(0), 513 APInt::getLowBitsSet(BitWidth, 8)); 514}]>; 515 516// ORs that can be treated as reversed insertions. 517def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2), 518 (or node:$src1, node:$src2), [{ 519 unsigned BitWidth = N->getValueType(0).getScalarSizeInBits(); 520 return CurDAG->MaskedValueIsZero(N->getOperand(1), 521 APInt::getLowBitsSet(BitWidth, 8)); 522}]>; 523 524// Negative integer absolute. 525def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>; 526 527// Integer absolute, matching the canonical form generated by DAGCombiner. 528def z_iabs32 : PatFrag<(ops node:$src), 529 (xor (add node:$src, (sra node:$src, (i32 31))), 530 (sra node:$src, (i32 31)))>; 531def z_iabs64 : PatFrag<(ops node:$src), 532 (xor (add node:$src, (sra node:$src, (i32 63))), 533 (sra node:$src, (i32 63)))>; 534def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>; 535def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>; 536 537// Integer multiply-and-add 538def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3), 539 (add (mul node:$src1, node:$src2), node:$src3)>; 540 541// Fused multiply-subtract, using the natural operand order. 542def fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 543 (fma node:$src1, node:$src2, (fneg node:$src3))>; 544 545// Fused multiply-add and multiply-subtract, but with the order of the 546// operands matching SystemZ's MA and MS instructions. 547def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), 548 (fma node:$src2, node:$src3, node:$src1)>; 549def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), 550 (fma node:$src2, node:$src3, (fneg node:$src1))>; 551 552// Floating-point negative absolute. 553def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>; 554 555// Create a unary operator that loads from memory and then performs 556// the given operation on it. 557class loadu<SDPatternOperator operator, SDPatternOperator load = load> 558 : PatFrag<(ops node:$addr), (operator (load node:$addr))>; 559 560// Create a store operator that performs the given unary operation 561// on the value before storing it. 562class storeu<SDPatternOperator operator, SDPatternOperator store = store> 563 : PatFrag<(ops node:$value, node:$addr), 564 (store (operator node:$value), node:$addr)>; 565 566// Create a store operator that performs the given inherent operation 567// and stores the resulting value. 568class storei<SDPatternOperator operator, SDPatternOperator store = store> 569 : PatFrag<(ops node:$addr), 570 (store (operator), node:$addr)>; 571 572// Vector representation of all-zeros and all-ones. 573def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>; 574def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>; 575 576// Load a scalar and replicate it in all elements of a vector. 577class z_replicate_load<ValueType scalartype, SDPatternOperator load> 578 : PatFrag<(ops node:$addr), 579 (z_replicate (scalartype (load node:$addr)))>; 580def z_replicate_loadi8 : z_replicate_load<i32, anyextloadi8>; 581def z_replicate_loadi16 : z_replicate_load<i32, anyextloadi16>; 582def z_replicate_loadi32 : z_replicate_load<i32, load>; 583def z_replicate_loadi64 : z_replicate_load<i64, load>; 584def z_replicate_loadf32 : z_replicate_load<f32, load>; 585def z_replicate_loadf64 : z_replicate_load<f64, load>; 586 587// Load a scalar and insert it into a single element of a vector. 588class z_vle<ValueType scalartype, SDPatternOperator load> 589 : PatFrag<(ops node:$vec, node:$addr, node:$index), 590 (z_vector_insert node:$vec, (scalartype (load node:$addr)), 591 node:$index)>; 592def z_vlei8 : z_vle<i32, anyextloadi8>; 593def z_vlei16 : z_vle<i32, anyextloadi16>; 594def z_vlei32 : z_vle<i32, load>; 595def z_vlei64 : z_vle<i64, load>; 596def z_vlef32 : z_vle<f32, load>; 597def z_vlef64 : z_vle<f64, load>; 598 599// Load a scalar and insert it into the low element of the high i64 of a 600// zeroed vector. 601class z_vllez<ValueType scalartype, SDPatternOperator load, int index> 602 : PatFrag<(ops node:$addr), 603 (z_vector_insert (z_vzero), 604 (scalartype (load node:$addr)), (i32 index))>; 605def z_vllezi8 : z_vllez<i32, anyextloadi8, 7>; 606def z_vllezi16 : z_vllez<i32, anyextloadi16, 3>; 607def z_vllezi32 : z_vllez<i32, load, 1>; 608def z_vllezi64 : PatFrag<(ops node:$addr), 609 (z_join_dwords (i64 (load node:$addr)), (i64 0))>; 610// We use high merges to form a v4f32 from four f32s. Propagating zero 611// into all elements but index 1 gives this expression. 612def z_vllezf32 : PatFrag<(ops node:$addr), 613 (bitconvert 614 (z_merge_high 615 (v2i64 616 (z_unpackl_high 617 (v4i32 618 (bitconvert 619 (v4f32 (scalar_to_vector 620 (f32 (load node:$addr)))))))), 621 (v2i64 (z_vzero))))>; 622def z_vllezf64 : PatFrag<(ops node:$addr), 623 (z_merge_high 624 (scalar_to_vector (f64 (load node:$addr))), 625 (z_vzero))>; 626 627// Store one element of a vector. 628class z_vste<ValueType scalartype, SDPatternOperator store> 629 : PatFrag<(ops node:$vec, node:$addr, node:$index), 630 (store (scalartype (z_vector_extract node:$vec, node:$index)), 631 node:$addr)>; 632def z_vstei8 : z_vste<i32, truncstorei8>; 633def z_vstei16 : z_vste<i32, truncstorei16>; 634def z_vstei32 : z_vste<i32, store>; 635def z_vstei64 : z_vste<i64, store>; 636def z_vstef32 : z_vste<f32, store>; 637def z_vstef64 : z_vste<f64, store>; 638 639// Arithmetic negation on vectors. 640def z_vneg : PatFrag<(ops node:$x), (sub (z_vzero), node:$x)>; 641 642// Bitwise negation on vectors. 643def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (z_vones))>; 644 645// Signed "integer greater than zero" on vectors. 646def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (z_vzero))>; 647 648// Signed "integer less than zero" on vectors. 649def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (z_vzero), node:$x)>; 650 651// Integer absolute on vectors. 652class z_viabs<int shift> 653 : PatFrag<(ops node:$src), 654 (xor (add node:$src, (z_vsra_by_scalar node:$src, (i32 shift))), 655 (z_vsra_by_scalar node:$src, (i32 shift)))>; 656def z_viabs8 : z_viabs<7>; 657def z_viabs16 : z_viabs<15>; 658def z_viabs32 : z_viabs<31>; 659def z_viabs64 : z_viabs<63>; 660 661// Sign-extend the i64 elements of a vector. 662class z_vse<int shift> 663 : PatFrag<(ops node:$src), 664 (z_vsra_by_scalar (z_vshl_by_scalar node:$src, shift), shift)>; 665def z_vsei8 : z_vse<56>; 666def z_vsei16 : z_vse<48>; 667def z_vsei32 : z_vse<32>; 668 669// ...and again with the extensions being done on individual i64 scalars. 670class z_vse_by_parts<SDPatternOperator operator, int index1, int index2> 671 : PatFrag<(ops node:$src), 672 (z_join_dwords 673 (operator (z_vector_extract node:$src, index1)), 674 (operator (z_vector_extract node:$src, index2)))>; 675def z_vsei8_by_parts : z_vse_by_parts<sext8dbl, 7, 15>; 676def z_vsei16_by_parts : z_vse_by_parts<sext16dbl, 3, 7>; 677def z_vsei32_by_parts : z_vse_by_parts<sext32, 1, 3>; 678