1//=====- SystemZOperands.td - SystemZ Operands defs ---------*- tblgen-*-=====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the various SystemZ instruction operands.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Instruction Pattern Stuff.
16//===----------------------------------------------------------------------===//
17
18// SystemZ specific condition code. These correspond to CondCode in
19// SystemZ.h. They must be kept in synch.
20def SYSTEMZ_COND_O   : PatLeaf<(i8 0)>;
21def SYSTEMZ_COND_H   : PatLeaf<(i8 1)>;
22def SYSTEMZ_COND_NLE : PatLeaf<(i8 2)>;
23def SYSTEMZ_COND_L   : PatLeaf<(i8 3)>;
24def SYSTEMZ_COND_NHE : PatLeaf<(i8 4)>;
25def SYSTEMZ_COND_LH  : PatLeaf<(i8 5)>;
26def SYSTEMZ_COND_NE  : PatLeaf<(i8 6)>;
27def SYSTEMZ_COND_E   : PatLeaf<(i8 7)>;
28def SYSTEMZ_COND_NLH : PatLeaf<(i8 8)>;
29def SYSTEMZ_COND_HE  : PatLeaf<(i8 9)>;
30def SYSTEMZ_COND_NL  : PatLeaf<(i8 10)>;
31def SYSTEMZ_COND_LE  : PatLeaf<(i8 11)>;
32def SYSTEMZ_COND_NH  : PatLeaf<(i8 12)>;
33def SYSTEMZ_COND_NO  : PatLeaf<(i8 13)>;
34
35def LO8 : SDNodeXForm<imm, [{
36  // Transformation function: return low 8 bits.
37  return getI8Imm(N->getZExtValue() & 0x00000000000000FFULL);
38}]>;
39
40def LL16 : SDNodeXForm<imm, [{
41  // Transformation function: return low 16 bits.
42  return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
43}]>;
44
45def LH16 : SDNodeXForm<imm, [{
46  // Transformation function: return bits 16-31.
47  return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
48}]>;
49
50def HL16 : SDNodeXForm<imm, [{
51  // Transformation function: return bits 32-47.
52  return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
53}]>;
54
55def HH16 : SDNodeXForm<imm, [{
56  // Transformation function: return bits 48-63.
57  return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
58}]>;
59
60def LO32 : SDNodeXForm<imm, [{
61  // Transformation function: return low 32 bits.
62  return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
63}]>;
64
65def HI32 : SDNodeXForm<imm, [{
66  // Transformation function: return bits 32-63.
67  return getI32Imm(N->getZExtValue() >> 32);
68}]>;
69
70def i32ll16 : PatLeaf<(i32 imm), [{
71  // i32ll16 predicate - true if the 32-bit immediate has only rightmost 16
72  // bits set.
73  return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
74}], LL16>;
75
76def i32lh16 : PatLeaf<(i32 imm), [{
77  // i32lh16 predicate - true if the 32-bit immediate has only bits 16-31 set.
78  return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
79}], LH16>;
80
81def i32ll16c : PatLeaf<(i32 imm), [{
82  // i32ll16c predicate - true if the 32-bit immediate has all bits 16-31 set.
83  return ((N->getZExtValue() | 0x00000000FFFF0000ULL) == N->getZExtValue());
84}], LL16>;
85
86def i32lh16c : PatLeaf<(i32 imm), [{
87  // i32lh16c predicate - true if the 32-bit immediate has all rightmost 16
88  //  bits set.
89  return ((N->getZExtValue() | 0x000000000000FFFFULL) == N->getZExtValue());
90}], LH16>;
91
92def i64ll16 : PatLeaf<(i64 imm), [{
93  // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
94  // bits set.
95  return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
96}], LL16>;
97
98def i64lh16 : PatLeaf<(i64 imm), [{
99  // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
100  return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
101}], LH16>;
102
103def i64hl16 : PatLeaf<(i64 imm), [{
104  // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
105  return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
106}], HL16>;
107
108def i64hh16 : PatLeaf<(i64 imm), [{
109  // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
110  return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
111}], HH16>;
112
113def i64ll16c : PatLeaf<(i64 imm), [{
114  // i64ll16c predicate - true if the 64-bit immediate has only rightmost 16
115  // bits set.
116  return ((N->getZExtValue() | 0xFFFFFFFFFFFF0000ULL) == N->getZExtValue());
117}], LL16>;
118
119def i64lh16c : PatLeaf<(i64 imm), [{
120  // i64lh16c predicate - true if the 64-bit immediate has only bits 16-31 set.
121  return ((N->getZExtValue() | 0xFFFFFFFF0000FFFFULL) == N->getZExtValue());
122}], LH16>;
123
124def i64hl16c : PatLeaf<(i64 imm), [{
125  // i64hl16c predicate - true if the 64-bit immediate has only bits 32-47 set.
126  return ((N->getZExtValue() | 0xFFFF0000FFFFFFFFULL) == N->getZExtValue());
127}], HL16>;
128
129def i64hh16c : PatLeaf<(i64 imm), [{
130  // i64hh16c predicate - true if the 64-bit immediate has only bits 48-63 set.
131  return ((N->getZExtValue() | 0x0000FFFFFFFFFFFFULL) == N->getZExtValue());
132}], HH16>;
133
134def immSExt16 : PatLeaf<(imm), [{
135  // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
136  // field.
137  if (N->getValueType(0) == MVT::i64) {
138    uint64_t val = N->getZExtValue();
139    return ((int64_t)val == (int16_t)val);
140  } else if (N->getValueType(0) == MVT::i32) {
141    uint32_t val = N->getZExtValue();
142    return ((int32_t)val == (int16_t)val);
143  }
144
145  return false;
146}], LL16>;
147
148def immSExt32 : PatLeaf<(i64 imm), [{
149  // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
150  // field.
151  uint64_t val = N->getZExtValue();
152  return ((int64_t)val == (int32_t)val);
153}], LO32>;
154
155def i64lo32 : PatLeaf<(i64 imm), [{
156  // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
157  // bits set.
158  return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
159}], LO32>;
160
161def i64hi32 : PatLeaf<(i64 imm), [{
162  // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
163  return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
164}], HI32>;
165
166def i64lo32c : PatLeaf<(i64 imm), [{
167  // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
168  // bits set.
169  return ((N->getZExtValue() | 0xFFFFFFFF00000000ULL) == N->getZExtValue());
170}], LO32>;
171
172def i64hi32c : PatLeaf<(i64 imm), [{
173  // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
174  return ((N->getZExtValue() | 0x00000000FFFFFFFFULL) == N->getZExtValue());
175}], HI32>;
176
177def i32immSExt8  : PatLeaf<(i32 imm), [{
178  // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
179  // sign extended field.
180  return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
181}], LO8>;
182
183def i32immSExt16 : PatLeaf<(i32 imm), [{
184  // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
185  // sign extended field.
186  return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
187}], LL16>;
188
189def i64immSExt32 : PatLeaf<(i64 imm), [{
190  // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
191  // sign extended field.
192  return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
193}], LO32>;
194
195def i64immZExt32 : PatLeaf<(i64 imm), [{
196  // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
197  // zero extended field.
198  return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
199}], LO32>;
200
201// extloads
202def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8  node:$ptr))>;
203def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
204def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8  node:$ptr))>;
205def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
206def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
207
208def sextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (sextloadi8  node:$ptr))>;
209def sextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
210def sextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (sextloadi8  node:$ptr))>;
211def sextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
212def sextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
213
214def zextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (zextloadi8  node:$ptr))>;
215def zextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
216def zextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (zextloadi8  node:$ptr))>;
217def zextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
218def zextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
219
220// A couple of more descriptive operand definitions.
221// 32-bits but only 8 bits are significant.
222def i32i8imm  : Operand<i32>;
223// 32-bits but only 16 bits are significant.
224def i32i16imm : Operand<i32>;
225// 64-bits but only 32 bits are significant.
226def i64i32imm : Operand<i64>;
227// Branch targets have OtherVT type.
228def brtarget : Operand<OtherVT>;
229
230// Unsigned i12
231def u12imm : Operand<i32> {
232  let PrintMethod = "printU12ImmOperand";
233}
234def u12imm64 : Operand<i64> {
235  let PrintMethod = "printU12ImmOperand";
236}
237
238// Signed i16
239def s16imm : Operand<i32> {
240  let PrintMethod = "printS16ImmOperand";
241}
242def s16imm64 : Operand<i64> {
243  let PrintMethod = "printS16ImmOperand";
244}
245// Signed i20
246def s20imm : Operand<i32> {
247  let PrintMethod = "printS20ImmOperand";
248}
249def s20imm64 : Operand<i64> {
250  let PrintMethod = "printS20ImmOperand";
251}
252// Signed i32
253def s32imm : Operand<i32> {
254  let PrintMethod = "printS32ImmOperand";
255}
256def s32imm64 : Operand<i64> {
257  let PrintMethod = "printS32ImmOperand";
258}
259
260def imm_pcrel : Operand<i64> {
261  let PrintMethod = "printPCRelImmOperand";
262}
263
264//===----------------------------------------------------------------------===//
265// SystemZ Operand Definitions.
266//===----------------------------------------------------------------------===//
267
268// Address operands
269
270// riaddr := reg + imm
271def riaddr32 : Operand<i64>,
272               ComplexPattern<i64, 2, "SelectAddrRI12Only", []> {
273  let PrintMethod = "printRIAddrOperand";
274  let MIOperandInfo = (ops ADDR64:$base, u12imm:$disp);
275}
276
277def riaddr12 : Operand<i64>,
278               ComplexPattern<i64, 2, "SelectAddrRI12", []> {
279  let PrintMethod = "printRIAddrOperand";
280  let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp);
281}
282
283def riaddr : Operand<i64>,
284             ComplexPattern<i64, 2, "SelectAddrRI", []> {
285  let PrintMethod = "printRIAddrOperand";
286  let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp);
287}
288
289//===----------------------------------------------------------------------===//
290
291// rriaddr := reg + reg + imm
292def rriaddr12 : Operand<i64>,
293                ComplexPattern<i64, 3, "SelectAddrRRI12", [], []> {
294  let PrintMethod = "printRRIAddrOperand";
295  let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp, ADDR64:$index);
296}
297def rriaddr : Operand<i64>,
298              ComplexPattern<i64, 3, "SelectAddrRRI20", [], []> {
299  let PrintMethod = "printRRIAddrOperand";
300  let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
301}
302def laaddr : Operand<i64>,
303             ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
304  let PrintMethod = "printRRIAddrOperand";
305  let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
306}
307