1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Move instructions 12//===----------------------------------------------------------------------===// 13 14let Predicates = [FeatureVector] in { 15 // Register move. 16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 17 def VLR32 : UnaryAliasVRR<null_frag, v32eb, v32eb>; 18 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 19 20 // Load GR from VR element. 21 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 22 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 23 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 24 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 25 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 26 27 // Load VR element from GR. 28 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 29 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 30 v128b, v128b, GR32, 0>; 31 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 32 v128h, v128h, GR32, 1>; 33 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 34 v128f, v128f, GR32, 2>; 35 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 36 v128g, v128g, GR64, 3>; 37 38 // Load VR from GRs disjoint. 39 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 40 def VLVGP32 : BinaryAliasVRRf<GR32>; 41} 42 43// Extractions always assign to the full GR64, even if the element would 44// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 45// subreg of the result. 46class VectorExtractSubreg<ValueType type, Instruction insn> 47 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 48 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 49 50def : VectorExtractSubreg<v16i8, VLGVB>; 51def : VectorExtractSubreg<v8i16, VLGVH>; 52def : VectorExtractSubreg<v4i32, VLGVF>; 53 54//===----------------------------------------------------------------------===// 55// Immediate instructions 56//===----------------------------------------------------------------------===// 57 58let Predicates = [FeatureVector] in { 59 // Generate byte mask. 60 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 61 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 62 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; 63 64 // Generate mask. 65 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 66 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 67 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 68 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 69 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 70 71 // Load element immediate. 72 // 73 // We want these instructions to be used ahead of VLVG* where possible. 74 // However, VLVG* takes a variable BD-format index whereas VLEI takes 75 // a plain immediate index. This means that VLVG* has an extra "base" 76 // register operand and is 3 units more complex. Bumping the complexity 77 // of the VLEI* instructions by 4 means that they are strictly better 78 // than VLVG* in cases where both forms match. 79 let AddedComplexity = 4 in { 80 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 81 v128b, v128b, imm32sx16trunc, imm32zx4>; 82 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 83 v128h, v128h, imm32sx16trunc, imm32zx3>; 84 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 85 v128f, v128f, imm32sx16, imm32zx2>; 86 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 87 v128g, v128g, imm64sx16, imm32zx1>; 88 } 89 90 // Replicate immediate. 91 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 92 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; 93 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; 94 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; 95 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; 96} 97 98//===----------------------------------------------------------------------===// 99// Loads 100//===----------------------------------------------------------------------===// 101 102let Predicates = [FeatureVector] in { 103 // Load. 104 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>; 105 106 // Load to block boundary. The number of loaded bytes is only known 107 // at run time. The instruction is really polymorphic, but v128b matches 108 // the return type of the associated intrinsic. 109 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 110 111 // Load count to block boundary. 112 let Defs = [CC] in 113 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 114 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 115 "lcbb\t$R1, $XBD2, $M3", 116 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 117 imm32zx4:$M3))]>; 118 119 // Load with length. The number of loaded bytes is only known at run time. 120 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 121 122 // Load multiple. 123 def VLM : LoadMultipleVRSa<"vlm", 0xE736>; 124 125 // Load and replicate 126 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 127 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 128 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 129 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 130 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 131 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 132 (VLREPF bdxaddr12only:$addr)>; 133 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 134 (VLREPG bdxaddr12only:$addr)>; 135 136 // Use VLREP to load subvectors. These patterns use "12pair" because 137 // LEY and LDY offer full 20-bit displacement fields. It's often better 138 // to use those instructions rather than force a 20-bit displacement 139 // into a GPR temporary. 140 def VL32 : UnaryAliasVRX<load, v32eb, bdxaddr12pair>; 141 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>; 142 143 // Load logical element and zero. 144 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 145 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 146 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 147 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 148 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 149 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)), 150 (VLLEZF bdxaddr12only:$addr)>; 151 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)), 152 (VLLEZG bdxaddr12only:$addr)>; 153 154 // Load element. 155 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 156 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 157 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 158 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 159 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 160 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 161 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 162 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 163 164 // Gather element. 165 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 166 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 167} 168 169// Use replicating loads if we're inserting a single element into an 170// undefined vector. This avoids a false dependency on the previous 171// register contents. 172multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 173 SDPatternOperator load, ValueType scalartype> { 174 def : Pat<(vectype (z_vector_insert 175 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 176 (vlrep bdxaddr12only:$addr)>; 177 def : Pat<(vectype (scalar_to_vector 178 (scalartype (load bdxaddr12only:$addr)))), 179 (vlrep bdxaddr12only:$addr)>; 180} 181defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>; 182defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>; 183defm : ReplicatePeephole<VLREPF, v4i32, load, i32>; 184defm : ReplicatePeephole<VLREPG, v2i64, load, i64>; 185defm : ReplicatePeephole<VLREPF, v4f32, load, f32>; 186defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 187 188//===----------------------------------------------------------------------===// 189// Stores 190//===----------------------------------------------------------------------===// 191 192let Predicates = [FeatureVector] in { 193 // Store. 194 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>; 195 196 // Store with length. The number of stored bytes is only known at run time. 197 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 198 199 // Store multiple. 200 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>; 201 202 // Store element. 203 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 204 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 205 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 206 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 207 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 208 imm32zx2:$index), 209 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 210 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 211 imm32zx1:$index), 212 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 213 214 // Use VSTE to store subvectors. These patterns use "12pair" because 215 // STEY and STDY offer full 20-bit displacement fields. It's often better 216 // to use those instructions rather than force a 20-bit displacement 217 // into a GPR temporary. 218 def VST32 : StoreAliasVRX<store, v32eb, bdxaddr12pair>; 219 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 220 221 // Scatter element. 222 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 223 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 224} 225 226//===----------------------------------------------------------------------===// 227// Selects and permutes 228//===----------------------------------------------------------------------===// 229 230let Predicates = [FeatureVector] in { 231 // Merge high. 232 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 233 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 234 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 235 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 236 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 237 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 238 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 239 240 // Merge low. 241 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 242 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 243 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 244 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 245 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 246 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 247 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 248 249 // Permute. 250 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 251 252 // Permute doubleword immediate. 253 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 254 255 // Replicate. 256 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 257 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 258 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 259 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 260 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 261 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)), 262 (VREPF VR128:$vec, imm32zx16:$index)>; 263 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)), 264 (VREPG VR128:$vec, imm32zx16:$index)>; 265 266 // Select. 267 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 268} 269 270//===----------------------------------------------------------------------===// 271// Widening and narrowing 272//===----------------------------------------------------------------------===// 273 274let Predicates = [FeatureVector] in { 275 // Pack 276 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 277 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 278 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 279 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 280 281 // Pack saturate. 282 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 283 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 284 v128b, v128h, 1>; 285 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 286 v128h, v128f, 2>; 287 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 288 v128f, v128g, 3>; 289 290 // Pack saturate logical. 291 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 292 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 293 v128b, v128h, 1>; 294 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 295 v128h, v128f, 2>; 296 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 297 v128f, v128g, 3>; 298 299 // Sign-extend to doubleword. 300 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 301 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 302 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 303 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 304 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 305 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 306 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 307 308 // Unpack high. 309 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 310 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 311 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 312 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 313 314 // Unpack logical high. 315 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 316 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 317 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 318 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 319 320 // Unpack low. 321 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 322 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 323 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 324 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 325 326 // Unpack logical low. 327 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 328 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 329 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 330 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 331} 332 333//===----------------------------------------------------------------------===// 334// Instantiating generic operations for specific types. 335//===----------------------------------------------------------------------===// 336 337multiclass GenericVectorOps<ValueType type, ValueType inttype> { 338 let Predicates = [FeatureVector] in { 339 def : Pat<(type (load bdxaddr12only:$addr)), 340 (VL bdxaddr12only:$addr)>; 341 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 342 (VST VR128:$src, bdxaddr12only:$addr)>; 343 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 344 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 345 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 346 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 347 } 348} 349 350defm : GenericVectorOps<v16i8, v16i8>; 351defm : GenericVectorOps<v8i16, v8i16>; 352defm : GenericVectorOps<v4i32, v4i32>; 353defm : GenericVectorOps<v2i64, v2i64>; 354defm : GenericVectorOps<v4f32, v4i32>; 355defm : GenericVectorOps<v2f64, v2i64>; 356 357//===----------------------------------------------------------------------===// 358// Integer arithmetic 359//===----------------------------------------------------------------------===// 360 361let Predicates = [FeatureVector] in { 362 // Add. 363 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 364 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 365 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 366 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 367 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 368 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>; 369 370 // Add compute carry. 371 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 372 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>; 373 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>; 374 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>; 375 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>; 376 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>; 377 378 // Add with carry. 379 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 380 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>; 381 382 // Add with carry compute carry. 383 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 384 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>; 385 386 // And. 387 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 388 389 // And with complement. 390 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 391 392 // Average. 393 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 394 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 395 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 396 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 397 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 398 399 // Average logical. 400 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 401 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 402 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 403 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 404 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 405 406 // Checksum. 407 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 408 409 // Count leading zeros. 410 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 411 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 412 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 413 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 414 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 415 416 // Count trailing zeros. 417 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 418 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 419 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 420 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 421 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 422 423 // Exclusive or. 424 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 425 426 // Galois field multiply sum. 427 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 428 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 429 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 430 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 431 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 432 433 // Galois field multiply sum and accumulate. 434 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 435 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 436 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 437 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 438 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 439 440 // Load complement. 441 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 442 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 443 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 444 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 445 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 446 447 // Load positive. 448 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 449 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>; 450 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>; 451 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>; 452 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>; 453 454 // Maximum. 455 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 456 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 457 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 458 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 459 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 460 461 // Maximum logical. 462 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 463 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 464 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 465 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 466 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 467 468 // Minimum. 469 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 470 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 471 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 472 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 473 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 474 475 // Minimum logical. 476 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 477 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 478 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 479 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 480 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 481 482 // Multiply and add low. 483 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 484 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 485 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 486 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 487 488 // Multiply and add high. 489 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 490 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 491 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 492 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 493 494 // Multiply and add logical high. 495 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 496 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 497 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 498 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 499 500 // Multiply and add even. 501 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 502 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 503 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 504 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 505 506 // Multiply and add logical even. 507 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 508 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 509 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 510 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 511 512 // Multiply and add odd. 513 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 514 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 515 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 516 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 517 518 // Multiply and add logical odd. 519 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 520 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 521 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 522 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 523 524 // Multiply high. 525 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 526 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 527 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 528 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 529 530 // Multiply logical high. 531 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 532 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 533 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 534 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 535 536 // Multiply low. 537 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 538 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 539 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 540 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 541 542 // Multiply even. 543 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 544 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 545 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 546 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 547 548 // Multiply logical even. 549 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 550 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 551 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 552 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 553 554 // Multiply odd. 555 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 556 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 557 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 558 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 559 560 // Multiply logical odd. 561 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 562 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 563 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 564 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 565 566 // Nor. 567 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 568 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 569 570 // Or. 571 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 572 573 // Population count. 574 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 575 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 576 577 // Element rotate left logical (with vector shift amount). 578 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 579 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb, 580 v128b, v128b, 0>; 581 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh, 582 v128h, v128h, 1>; 583 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf, 584 v128f, v128f, 2>; 585 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg, 586 v128g, v128g, 3>; 587 588 // Element rotate left logical (with scalar shift amount). 589 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 590 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>; 591 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>; 592 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>; 593 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>; 594 595 // Element rotate and insert under mask. 596 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 597 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 598 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 599 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 600 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 601 602 // Element shift left (with vector shift amount). 603 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 604 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 605 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 606 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 607 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 608 609 // Element shift left (with scalar shift amount). 610 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 611 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 612 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 613 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 614 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 615 616 // Element shift right arithmetic (with vector shift amount). 617 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 618 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 619 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 620 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 621 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 622 623 // Element shift right arithmetic (with scalar shift amount). 624 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 625 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 626 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 627 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 628 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 629 630 // Element shift right logical (with vector shift amount). 631 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 632 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 633 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 634 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 635 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 636 637 // Element shift right logical (with scalar shift amount). 638 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 639 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 640 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 641 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 642 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 643 644 // Shift left. 645 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 646 647 // Shift left by byte. 648 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 649 650 // Shift left double by byte. 651 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 652 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8:$z), 653 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 654 655 // Shift right arithmetic. 656 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 657 658 // Shift right arithmetic by byte. 659 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 660 661 // Shift right logical. 662 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 663 664 // Shift right logical by byte. 665 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 666 667 // Subtract. 668 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 669 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 670 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 671 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 672 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 673 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>; 674 675 // Subtract compute borrow indication. 676 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 677 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>; 678 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>; 679 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>; 680 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>; 681 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>; 682 683 // Subtract with borrow indication. 684 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 685 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>; 686 687 // Subtract with borrow compute borrow indication. 688 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 689 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq, 690 v128q, v128q, 4>; 691 692 // Sum across doubleword. 693 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 694 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 695 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 696 697 // Sum across quadword. 698 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 699 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 700 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 701 702 // Sum across word. 703 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 704 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 705 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 706} 707 708// Instantiate the bitwise ops for type TYPE. 709multiclass BitwiseVectorOps<ValueType type> { 710 let Predicates = [FeatureVector] in { 711 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 712 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))), 713 (VNC VR128:$x, VR128:$y)>; 714 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 715 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 716 def : Pat<(type (or (and VR128:$x, VR128:$z), 717 (and VR128:$y, (z_vnot VR128:$z)))), 718 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 719 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))), 720 (VNO VR128:$x, VR128:$y)>; 721 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; 722 } 723} 724 725defm : BitwiseVectorOps<v16i8>; 726defm : BitwiseVectorOps<v8i16>; 727defm : BitwiseVectorOps<v4i32>; 728defm : BitwiseVectorOps<v2i64>; 729 730// Instantiate additional patterns for absolute-related expressions on 731// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 732// instruction. 733multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 734 Instruction lp, int shift> { 735 let Predicates = [FeatureVector] in { 736 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 737 (z_vneg VR128:$x), VR128:$x)), 738 (lc (lp VR128:$x))>; 739 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 740 VR128:$x, (z_vneg VR128:$x))), 741 (lc (lp VR128:$x))>; 742 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 743 VR128:$x, (z_vneg VR128:$x))), 744 (lc (lp VR128:$x))>; 745 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 746 (z_vneg VR128:$x), VR128:$x)), 747 (lc (lp VR128:$x))>; 748 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 749 (z_vneg VR128:$x)), 750 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 751 VR128:$x))), 752 (lp VR128:$x)>; 753 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 754 VR128:$x), 755 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 756 (z_vneg VR128:$x)))), 757 (lc (lp VR128:$x))>; 758 } 759} 760 761defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 762defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 763defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 764defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 765 766// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 767// signed or unsigned "set if greater than" comparison instruction and 768// MIN and MAX are the associated minimum and maximum instructions. 769multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 770 Instruction min, Instruction max> { 771 let Predicates = [FeatureVector] in { 772 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 773 (max VR128:$x, VR128:$y)>; 774 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 775 (min VR128:$x, VR128:$y)>; 776 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 777 VR128:$x, VR128:$y)), 778 (min VR128:$x, VR128:$y)>; 779 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 780 VR128:$y, VR128:$x)), 781 (max VR128:$x, VR128:$y)>; 782 } 783} 784 785// Signed min/max. 786defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 787defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 788defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 789defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 790 791// Unsigned min/max. 792defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 793defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 794defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 795defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 796 797//===----------------------------------------------------------------------===// 798// Integer comparison 799//===----------------------------------------------------------------------===// 800 801let Predicates = [FeatureVector] in { 802 // Element compare. 803 let Defs = [CC] in { 804 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 805 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 806 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 807 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 808 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 809 } 810 811 // Element compare logical. 812 let Defs = [CC] in { 813 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 814 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 815 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 816 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 817 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 818 } 819 820 // Compare equal. 821 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 822 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 823 v128b, v128b, 0>; 824 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 825 v128h, v128h, 1>; 826 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 827 v128f, v128f, 2>; 828 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 829 v128g, v128g, 3>; 830 831 // Compare high. 832 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 833 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 834 v128b, v128b, 0>; 835 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 836 v128h, v128h, 1>; 837 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 838 v128f, v128f, 2>; 839 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 840 v128g, v128g, 3>; 841 842 // Compare high logical. 843 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 844 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 845 v128b, v128b, 0>; 846 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 847 v128h, v128h, 1>; 848 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 849 v128f, v128f, 2>; 850 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 851 v128g, v128g, 3>; 852 853 // Test under mask. 854 let Defs = [CC] in 855 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 856} 857 858//===----------------------------------------------------------------------===// 859// Floating-point arithmetic 860//===----------------------------------------------------------------------===// 861 862// See comments in SystemZInstrFP.td for the suppression flags and 863// rounding modes. 864multiclass VectorRounding<Instruction insn, TypedReg tr> { 865 def : FPConversion<insn, frint, tr, tr, 0, 0>; 866 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>; 867 def : FPConversion<insn, ffloor, tr, tr, 4, 7>; 868 def : FPConversion<insn, fceil, tr, tr, 4, 6>; 869 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>; 870 def : FPConversion<insn, fround, tr, tr, 4, 1>; 871} 872 873let Predicates = [FeatureVector] in { 874 // Add. 875 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 876 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>; 877 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, fadd, v64db, v64db, 3, 8>; 878 879 // Convert from fixed 64-bit. 880 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 881 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 882 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 883 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>; 884 885 // Convert from logical 64-bit. 886 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 887 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 888 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 889 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>; 890 891 // Convert to fixed 64-bit. 892 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 893 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 894 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 895 // Rounding mode should agree with SystemZInstrFP.td. 896 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>; 897 898 // Convert to logical 64-bit. 899 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 900 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 901 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 902 // Rounding mode should agree with SystemZInstrFP.td. 903 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>; 904 905 // Divide. 906 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 907 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>; 908 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, fdiv, v64db, v64db, 3, 8>; 909 910 // Load FP integer. 911 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 912 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 913 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 914 defm : VectorRounding<VFIDB, v128db>; 915 defm : VectorRounding<WFIDB, v64db>; 916 917 // Load lengthened. 918 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 919 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128eb, 2, 0>; 920 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, fpextend, v64db, v32eb, 2, 8>; 921 922 // Load rounded, 923 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 924 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>; 925 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>; 926 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 927 def : FPConversion<WLEDB, fpround, v32eb, v64db, 0, 0>; 928 929 // Multiply. 930 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 931 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>; 932 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, fmul, v64db, v64db, 3, 8>; 933 934 // Multiply and add. 935 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 936 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>; 937 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, fma, v64db, v64db, 8, 3>; 938 939 // Multiply and subtract. 940 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 941 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>; 942 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>; 943 944 // Perform sign operation. 945 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 946 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 947 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 948 949 // Load complement. 950 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 951 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 952 953 // Load negative. 954 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 955 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 956 957 // Load positive. 958 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 959 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 960 961 // Square root. 962 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 963 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>; 964 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, fsqrt, v64db, v64db, 3, 8>; 965 966 // Subtract. 967 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 968 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>; 969 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, fsub, v64db, v64db, 3, 8>; 970 971 // Test data class immediate. 972 let Defs = [CC] in { 973 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 974 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 975 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 976 } 977} 978 979//===----------------------------------------------------------------------===// 980// Floating-point comparison 981//===----------------------------------------------------------------------===// 982 983let Predicates = [FeatureVector] in { 984 // Compare scalar. 985 let Defs = [CC] in { 986 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 987 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>; 988 } 989 990 // Compare and signal scalar. 991 let Defs = [CC] in { 992 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 993 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>; 994 } 995 996 // Compare equal. 997 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 998 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, z_vfcmpes, 999 v128g, v128db, 3, 0>; 1000 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1001 v64g, v64db, 3, 8>; 1002 1003 // Compare high. 1004 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1005 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs, 1006 v128g, v128db, 3, 0>; 1007 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1008 v64g, v64db, 3, 8>; 1009 1010 // Compare high or equal. 1011 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1012 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1013 v128g, v128db, 3, 0>; 1014 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1015 v64g, v64db, 3, 8>; 1016} 1017 1018//===----------------------------------------------------------------------===// 1019// Conversions 1020//===----------------------------------------------------------------------===// 1021 1022def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 1023def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 1024def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 1025def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 1026def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 1027 1028def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 1029def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 1030def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 1031def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 1032def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 1033 1034def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 1035def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 1036def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 1037def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 1038def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 1039 1040def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 1041def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 1042def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 1043def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 1044def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 1045 1046def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 1047def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 1048def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 1049def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 1050def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 1051 1052def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 1053def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 1054def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 1055def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 1056def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 1057 1058//===----------------------------------------------------------------------===// 1059// Replicating scalars 1060//===----------------------------------------------------------------------===// 1061 1062// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 1063// INDEX is 8 minus the element size in bytes. 1064class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 1065 : Pat<(type (z_replicate GR32:$scalar)), 1066 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 1067 1068def : VectorReplicateScalar<v16i8, VREPB, 7>; 1069def : VectorReplicateScalar<v8i16, VREPH, 3>; 1070def : VectorReplicateScalar<v4i32, VREPF, 1>; 1071 1072// i64 replications are just a single isntruction. 1073def : Pat<(v2i64 (z_replicate GR64:$scalar)), 1074 (VLVGP GR64:$scalar, GR64:$scalar)>; 1075 1076//===----------------------------------------------------------------------===// 1077// Floating-point insertion and extraction 1078//===----------------------------------------------------------------------===// 1079 1080// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 1081// and VLGVF. 1082let Predicates = [FeatureVector] in { 1083 def LEFR : UnaryAliasVRS<VR32, GR32>; 1084 def LFER : UnaryAliasVRS<GR64, VR32>; 1085 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 1086 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 1087 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 1088} 1089 1090// Floating-point values are stored in element 0 of the corresponding 1091// vector register. Scalar to vector conversion is just a subreg and 1092// scalar replication can just replicate element 0 of the vector register. 1093multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 1094 SubRegIndex subreg> { 1095 def : Pat<(vt (scalar_to_vector cls:$scalar)), 1096 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 1097 def : Pat<(vt (z_replicate cls:$scalar)), 1098 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 1099 subreg), 0)>; 1100} 1101defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_r32>; 1102defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>; 1103 1104// Match v2f64 insertions. The AddedComplexity counters the 3 added by 1105// TableGen for the base register operand in VLVG-based integer insertions 1106// and ensures that this version is strictly better. 1107let AddedComplexity = 4 in { 1108 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 1109 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1110 subreg_r64), VR128:$vec, 1)>; 1111 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 1112 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1113 subreg_r64), 0)>; 1114} 1115 1116// We extract floating-point element X by replicating (for elements other 1117// than 0) and then taking a high subreg. The AddedComplexity counters the 1118// 3 added by TableGen for the base register operand in VLGV-based integer 1119// extractions and ensures that this version is strictly better. 1120let AddedComplexity = 4 in { 1121 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 1122 (EXTRACT_SUBREG VR128:$vec, subreg_r32)>; 1123 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 1124 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_r32)>; 1125 1126 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 1127 (EXTRACT_SUBREG VR128:$vec, subreg_r64)>; 1128 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 1129 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>; 1130} 1131 1132//===----------------------------------------------------------------------===// 1133// String instructions 1134//===----------------------------------------------------------------------===// 1135 1136let Predicates = [FeatureVector] in { 1137 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 1138 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 1139 z_vfae_cc, v128b, v128b, 0>; 1140 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 1141 z_vfae_cc, v128h, v128h, 1>; 1142 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 1143 z_vfae_cc, v128f, v128f, 2>; 1144 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 1145 z_vfaez_cc, v128b, v128b, 0, 2>; 1146 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 1147 z_vfaez_cc, v128h, v128h, 1, 2>; 1148 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 1149 z_vfaez_cc, v128f, v128f, 2, 2>; 1150 1151 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 1152 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 1153 z_vfee_cc, v128b, v128b, 0>; 1154 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 1155 z_vfee_cc, v128h, v128h, 1>; 1156 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 1157 z_vfee_cc, v128f, v128f, 2>; 1158 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 1159 z_vfeez_cc, v128b, v128b, 0, 2>; 1160 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 1161 z_vfeez_cc, v128h, v128h, 1, 2>; 1162 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 1163 z_vfeez_cc, v128f, v128f, 2, 2>; 1164 1165 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 1166 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 1167 z_vfene_cc, v128b, v128b, 0>; 1168 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 1169 z_vfene_cc, v128h, v128h, 1>; 1170 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 1171 z_vfene_cc, v128f, v128f, 2>; 1172 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 1173 z_vfenez_cc, v128b, v128b, 0, 2>; 1174 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 1175 z_vfenez_cc, v128h, v128h, 1, 2>; 1176 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 1177 z_vfenez_cc, v128f, v128f, 2, 2>; 1178 1179 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 1180 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 1181 z_vistr_cc, v128b, v128b, 0>; 1182 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 1183 z_vistr_cc, v128h, v128h, 1>; 1184 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 1185 z_vistr_cc, v128f, v128f, 2>; 1186 1187 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 1188 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 1189 z_vstrc_cc, v128b, v128b, 0>; 1190 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 1191 z_vstrc_cc, v128h, v128h, 1>; 1192 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 1193 z_vstrc_cc, v128f, v128f, 2>; 1194 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 1195 z_vstrcz_cc, v128b, v128b, 0, 2>; 1196 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 1197 z_vstrcz_cc, v128h, v128h, 1, 2>; 1198 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 1199 z_vstrcz_cc, v128f, v128f, 2, 2>; 1200} 1201