1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Move instructions 11//===----------------------------------------------------------------------===// 12 13let Predicates = [FeatureVector] in { 14 // Register move. 15 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 16 def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>; 17 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 18 19 // Load GR from VR element. 20 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 21 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 22 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 23 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 24 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 25 26 // Load VR element from GR. 27 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 28 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 29 v128b, v128b, GR32, 0>; 30 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 31 v128h, v128h, GR32, 1>; 32 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 33 v128f, v128f, GR32, 2>; 34 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 35 v128g, v128g, GR64, 3>; 36 37 // Load VR from GRs disjoint. 38 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 39 def VLVGP32 : BinaryAliasVRRf<GR32>; 40} 41 42// Extractions always assign to the full GR64, even if the element would 43// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 44// subreg of the result. 45class VectorExtractSubreg<ValueType type, Instruction insn> 46 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 47 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 48 49def : VectorExtractSubreg<v16i8, VLGVB>; 50def : VectorExtractSubreg<v8i16, VLGVH>; 51def : VectorExtractSubreg<v4i32, VLGVF>; 52 53//===----------------------------------------------------------------------===// 54// Immediate instructions 55//===----------------------------------------------------------------------===// 56 57let Predicates = [FeatureVector] in { 58 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 59 60 // Generate byte mask. 61 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 62 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 63 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16_timm>; 64 65 // Generate mask. 66 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 67 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 68 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 69 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 70 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 71 72 // Replicate immediate. 73 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 74 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16_timm, 0>; 75 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16_timm, 1>; 76 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16_timm, 2>; 77 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16_timm, 3>; 78 } 79 80 // Load element immediate. 81 // 82 // We want these instructions to be used ahead of VLVG* where possible. 83 // However, VLVG* takes a variable BD-format index whereas VLEI takes 84 // a plain immediate index. This means that VLVG* has an extra "base" 85 // register operand and is 3 units more complex. Bumping the complexity 86 // of the VLEI* instructions by 4 means that they are strictly better 87 // than VLVG* in cases where both forms match. 88 let AddedComplexity = 4 in { 89 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 90 v128b, v128b, imm32sx16trunc, imm32zx4>; 91 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 92 v128h, v128h, imm32sx16trunc, imm32zx3>; 93 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 94 v128f, v128f, imm32sx16, imm32zx2>; 95 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 96 v128g, v128g, imm64sx16, imm32zx1>; 97 } 98} 99 100//===----------------------------------------------------------------------===// 101// Loads 102//===----------------------------------------------------------------------===// 103 104let Predicates = [FeatureVector] in { 105 // Load. 106 defm VL : UnaryVRXAlign<"vl", 0xE706>; 107 108 // Load to block boundary. The number of loaded bytes is only known 109 // at run time. The instruction is really polymorphic, but v128b matches 110 // the return type of the associated intrinsic. 111 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 112 113 // Load count to block boundary. 114 let Defs = [CC] in 115 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 116 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 117 "lcbb\t$R1, $XBD2, $M3", 118 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 119 imm32zx4_timm:$M3))]>; 120 121 // Load with length. The number of loaded bytes is only known at run time. 122 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 123 124 // Load multiple. 125 defm VLM : LoadMultipleVRSaAlign<"vlm", 0xE736>; 126 127 // Load and replicate 128 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 129 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 130 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 131 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 132 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 133 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 134 (VLREPF bdxaddr12only:$addr)>; 135 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 136 (VLREPG bdxaddr12only:$addr)>; 137 138 // Use VLREP to load subvectors. These patterns use "12pair" because 139 // LEY and LDY offer full 20-bit displacement fields. It's often better 140 // to use those instructions rather than force a 20-bit displacement 141 // into a GPR temporary. 142 let mayLoad = 1 in { 143 def VL32 : UnaryAliasVRX<load, v32sb, bdxaddr12pair>; 144 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>; 145 } 146 147 // Load logical element and zero. 148 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 149 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 150 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 151 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 152 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 153 def : Pat<(z_vllezf32 bdxaddr12only:$addr), 154 (VLLEZF bdxaddr12only:$addr)>; 155 def : Pat<(z_vllezf64 bdxaddr12only:$addr), 156 (VLLEZG bdxaddr12only:$addr)>; 157 let Predicates = [FeatureVectorEnhancements1] in { 158 def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>; 159 def : Pat<(z_vllezlf32 bdxaddr12only:$addr), 160 (VLLEZLF bdxaddr12only:$addr)>; 161 } 162 163 // Load element. 164 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 165 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 166 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 167 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 168 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 169 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 170 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 171 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 172 173 // Gather element. 174 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 175 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 176} 177 178let Predicates = [FeatureVectorPackedDecimal] in { 179 // Load rightmost with length. The number of loaded bytes is only known 180 // at run time. Note that while the instruction will accept immediate 181 // lengths larger that 15 at runtime, those will always result in a trap, 182 // so we never emit them here. 183 def VLRL : BinaryVSI<"vlrl", 0xE635, null_frag, 0>; 184 def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>; 185 def : Pat<(int_s390_vlrl imm32zx4:$len, bdaddr12only:$addr), 186 (VLRL bdaddr12only:$addr, imm32zx4:$len)>; 187} 188 189// Use replicating loads if we're inserting a single element into an 190// undefined vector. This avoids a false dependency on the previous 191// register contents. 192multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 193 SDPatternOperator load, ValueType scalartype> { 194 def : Pat<(vectype (z_vector_insert 195 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 196 (vlrep bdxaddr12only:$addr)>; 197 def : Pat<(vectype (scalar_to_vector 198 (scalartype (load bdxaddr12only:$addr)))), 199 (vlrep bdxaddr12only:$addr)>; 200} 201defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>; 202defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>; 203defm : ReplicatePeephole<VLREPF, v4i32, load, i32>; 204defm : ReplicatePeephole<VLREPG, v2i64, load, i64>; 205defm : ReplicatePeephole<VLREPF, v4f32, load, f32>; 206defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 207 208//===----------------------------------------------------------------------===// 209// Stores 210//===----------------------------------------------------------------------===// 211 212let Predicates = [FeatureVector] in { 213 // Store. 214 defm VST : StoreVRXAlign<"vst", 0xE70E>; 215 216 // Store with length. The number of stored bytes is only known at run time. 217 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 218 219 // Store multiple. 220 defm VSTM : StoreMultipleVRSaAlign<"vstm", 0xE73E>; 221 222 // Store element. 223 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 224 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 225 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 226 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 227 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 228 imm32zx2:$index), 229 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 230 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 231 imm32zx1:$index), 232 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 233 234 // Use VSTE to store subvectors. These patterns use "12pair" because 235 // STEY and STDY offer full 20-bit displacement fields. It's often better 236 // to use those instructions rather than force a 20-bit displacement 237 // into a GPR temporary. 238 let mayStore = 1 in { 239 def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>; 240 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 241 } 242 243 // Scatter element. 244 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 245 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 246} 247 248let Predicates = [FeatureVectorPackedDecimal] in { 249 // Store rightmost with length. The number of stored bytes is only known 250 // at run time. Note that while the instruction will accept immediate 251 // lengths larger that 15 at runtime, those will always result in a trap, 252 // so we never emit them here. 253 def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, null_frag, 0>; 254 def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>; 255 def : Pat<(int_s390_vstrl VR128:$val, imm32zx4:$len, bdaddr12only:$addr), 256 (VSTRL VR128:$val, bdaddr12only:$addr, imm32zx4:$len)>; 257} 258 259//===----------------------------------------------------------------------===// 260// Byte swaps 261//===----------------------------------------------------------------------===// 262 263let Predicates = [FeatureVectorEnhancements2] in { 264 // Load byte-reversed elements. 265 def VLBR : UnaryVRXGeneric<"vlbr", 0xE606>; 266 def VLBRH : UnaryVRX<"vlbrh", 0xE606, z_loadbswap, v128h, 16, 1>; 267 def VLBRF : UnaryVRX<"vlbrf", 0xE606, z_loadbswap, v128f, 16, 2>; 268 def VLBRG : UnaryVRX<"vlbrg", 0xE606, z_loadbswap, v128g, 16, 3>; 269 def VLBRQ : UnaryVRX<"vlbrq", 0xE606, null_frag, v128q, 16, 4>; 270 271 // Load elements reversed. 272 def VLER : UnaryVRXGeneric<"vler", 0xE607>; 273 def VLERH : UnaryVRX<"vlerh", 0xE607, z_loadeswap, v128h, 16, 1>; 274 def VLERF : UnaryVRX<"vlerf", 0xE607, z_loadeswap, v128f, 16, 2>; 275 def VLERG : UnaryVRX<"vlerg", 0xE607, z_loadeswap, v128g, 16, 3>; 276 def : Pat<(v4f32 (z_loadeswap bdxaddr12only:$addr)), 277 (VLERF bdxaddr12only:$addr)>; 278 def : Pat<(v2f64 (z_loadeswap bdxaddr12only:$addr)), 279 (VLERG bdxaddr12only:$addr)>; 280 def : Pat<(v16i8 (z_loadeswap bdxaddr12only:$addr)), 281 (VLBRQ bdxaddr12only:$addr)>; 282 283 // Load byte-reversed element. 284 def VLEBRH : TernaryVRX<"vlebrh", 0xE601, z_vlebri16, v128h, v128h, 2, imm32zx3>; 285 def VLEBRF : TernaryVRX<"vlebrf", 0xE603, z_vlebri32, v128f, v128f, 4, imm32zx2>; 286 def VLEBRG : TernaryVRX<"vlebrg", 0xE602, z_vlebri64, v128g, v128g, 8, imm32zx1>; 287 288 // Load byte-reversed element and zero. 289 def VLLEBRZ : UnaryVRXGeneric<"vllebrz", 0xE604>; 290 def VLLEBRZH : UnaryVRX<"vllebrzh", 0xE604, z_vllebrzi16, v128h, 2, 1>; 291 def VLLEBRZF : UnaryVRX<"vllebrzf", 0xE604, z_vllebrzi32, v128f, 4, 2>; 292 def VLLEBRZG : UnaryVRX<"vllebrzg", 0xE604, z_vllebrzi64, v128g, 8, 3>; 293 def VLLEBRZE : UnaryVRX<"vllebrze", 0xE604, z_vllebrzli32, v128f, 4, 6>; 294 def : InstAlias<"lerv\t$V1, $XBD2", 295 (VLLEBRZE VR128:$V1, bdxaddr12only:$XBD2), 0>; 296 def : InstAlias<"ldrv\t$V1, $XBD2", 297 (VLLEBRZG VR128:$V1, bdxaddr12only:$XBD2), 0>; 298 299 // Load byte-reversed element and replicate. 300 def VLBRREP : UnaryVRXGeneric<"vlbrrep", 0xE605>; 301 def VLBRREPH : UnaryVRX<"vlbrreph", 0xE605, z_replicate_loadbswapi16, v128h, 2, 1>; 302 def VLBRREPF : UnaryVRX<"vlbrrepf", 0xE605, z_replicate_loadbswapi32, v128f, 4, 2>; 303 def VLBRREPG : UnaryVRX<"vlbrrepg", 0xE605, z_replicate_loadbswapi64, v128g, 8, 3>; 304 305 // Store byte-reversed elements. 306 def VSTBR : StoreVRXGeneric<"vstbr", 0xE60E>; 307 def VSTBRH : StoreVRX<"vstbrh", 0xE60E, z_storebswap, v128h, 16, 1>; 308 def VSTBRF : StoreVRX<"vstbrf", 0xE60E, z_storebswap, v128f, 16, 2>; 309 def VSTBRG : StoreVRX<"vstbrg", 0xE60E, z_storebswap, v128g, 16, 3>; 310 def VSTBRQ : StoreVRX<"vstbrq", 0xE60E, null_frag, v128q, 16, 4>; 311 312 // Store elements reversed. 313 def VSTER : StoreVRXGeneric<"vster", 0xE60F>; 314 def VSTERH : StoreVRX<"vsterh", 0xE60F, z_storeeswap, v128h, 16, 1>; 315 def VSTERF : StoreVRX<"vsterf", 0xE60F, z_storeeswap, v128f, 16, 2>; 316 def VSTERG : StoreVRX<"vsterg", 0xE60F, z_storeeswap, v128g, 16, 3>; 317 def : Pat<(z_storeeswap (v4f32 VR128:$val), bdxaddr12only:$addr), 318 (VSTERF VR128:$val, bdxaddr12only:$addr)>; 319 def : Pat<(z_storeeswap (v2f64 VR128:$val), bdxaddr12only:$addr), 320 (VSTERG VR128:$val, bdxaddr12only:$addr)>; 321 def : Pat<(z_storeeswap (v16i8 VR128:$val), bdxaddr12only:$addr), 322 (VSTBRQ VR128:$val, bdxaddr12only:$addr)>; 323 324 // Store byte-reversed element. 325 def VSTEBRH : StoreBinaryVRX<"vstebrh", 0xE609, z_vstebri16, v128h, 2, imm32zx3>; 326 def VSTEBRF : StoreBinaryVRX<"vstebrf", 0xE60B, z_vstebri32, v128f, 4, imm32zx2>; 327 def VSTEBRG : StoreBinaryVRX<"vstebrg", 0xE60A, z_vstebri64, v128g, 8, imm32zx1>; 328 def : InstAlias<"sterv\t$V1, $XBD2", 329 (VSTEBRF VR128:$V1, bdxaddr12only:$XBD2, 0), 0>; 330 def : InstAlias<"stdrv\t$V1, $XBD2", 331 (VSTEBRG VR128:$V1, bdxaddr12only:$XBD2, 0), 0>; 332} 333 334//===----------------------------------------------------------------------===// 335// Selects and permutes 336//===----------------------------------------------------------------------===// 337 338let Predicates = [FeatureVector] in { 339 // Merge high. 340 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 341 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 342 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 343 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 344 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 345 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 346 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 347 348 // Merge low. 349 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 350 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 351 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 352 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 353 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 354 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 355 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 356 357 // Permute. 358 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 359 360 // Permute doubleword immediate. 361 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 362 363 // Bit Permute. 364 let Predicates = [FeatureVectorEnhancements1] in 365 def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>; 366 367 // Replicate. 368 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 369 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 370 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 371 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 372 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 373 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16_timm:$index)), 374 (VREPF VR128:$vec, imm32zx16:$index)>; 375 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16_timm:$index)), 376 (VREPG VR128:$vec, imm32zx16:$index)>; 377 378 // Select. 379 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 380} 381 382//===----------------------------------------------------------------------===// 383// Widening and narrowing 384//===----------------------------------------------------------------------===// 385 386let Predicates = [FeatureVector] in { 387 // Pack 388 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 389 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 390 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 391 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 392 393 // Pack saturate. 394 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 395 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 396 v128b, v128h, 1>; 397 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 398 v128h, v128f, 2>; 399 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 400 v128f, v128g, 3>; 401 402 // Pack saturate logical. 403 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 404 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 405 v128b, v128h, 1>; 406 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 407 v128h, v128f, 2>; 408 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 409 v128f, v128g, 3>; 410 411 // Sign-extend to doubleword. 412 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 413 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 414 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 415 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 416 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 417 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 418 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 419 420 // Unpack high. 421 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 422 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 423 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 424 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 425 426 // Unpack logical high. 427 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 428 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 429 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 430 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 431 432 // Unpack low. 433 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 434 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 435 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 436 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 437 438 // Unpack logical low. 439 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 440 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 441 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 442 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 443} 444 445//===----------------------------------------------------------------------===// 446// Instantiating generic operations for specific types. 447//===----------------------------------------------------------------------===// 448 449multiclass GenericVectorOps<ValueType type, ValueType inttype> { 450 let Predicates = [FeatureVector] in { 451 def : Pat<(type (load bdxaddr12only:$addr)), 452 (VL bdxaddr12only:$addr)>; 453 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 454 (VST VR128:$src, bdxaddr12only:$addr)>; 455 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 456 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 457 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 458 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 459 } 460} 461 462defm : GenericVectorOps<v16i8, v16i8>; 463defm : GenericVectorOps<v8i16, v8i16>; 464defm : GenericVectorOps<v4i32, v4i32>; 465defm : GenericVectorOps<v2i64, v2i64>; 466defm : GenericVectorOps<v4f32, v4i32>; 467defm : GenericVectorOps<v2f64, v2i64>; 468 469//===----------------------------------------------------------------------===// 470// Integer arithmetic 471//===----------------------------------------------------------------------===// 472 473let Predicates = [FeatureVector] in { 474 let isCommutable = 1 in { 475 // Add. 476 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 477 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 478 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 479 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 480 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 481 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>; 482 } 483 484 let isCommutable = 1 in { 485 // Add compute carry. 486 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 487 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>; 488 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>; 489 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>; 490 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>; 491 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>; 492 493 // Add with carry. 494 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 495 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>; 496 497 // Add with carry compute carry. 498 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 499 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>; 500 } 501 502 // And. 503 let isCommutable = 1 in 504 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 505 506 // And with complement. 507 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 508 509 let isCommutable = 1 in { 510 // Average. 511 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 512 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 513 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 514 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 515 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 516 517 // Average logical. 518 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 519 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 520 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 521 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 522 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 523 } 524 525 // Checksum. 526 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 527 528 // Count leading zeros. 529 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 530 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 531 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 532 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 533 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 534 535 // Count trailing zeros. 536 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 537 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 538 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 539 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 540 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 541 542 let isCommutable = 1 in { 543 // Not exclusive or. 544 let Predicates = [FeatureVectorEnhancements1] in 545 def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>; 546 547 // Exclusive or. 548 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 549 } 550 551 // Galois field multiply sum. 552 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 553 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 554 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 555 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 556 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 557 558 // Galois field multiply sum and accumulate. 559 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 560 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 561 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 562 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 563 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 564 565 // Load complement. 566 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 567 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 568 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 569 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 570 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 571 572 // Load positive. 573 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 574 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>; 575 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>; 576 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>; 577 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>; 578 579 let isCommutable = 1 in { 580 // Maximum. 581 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 582 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 583 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 584 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 585 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 586 587 // Maximum logical. 588 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 589 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 590 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 591 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 592 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 593 } 594 595 let isCommutable = 1 in { 596 // Minimum. 597 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 598 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 599 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 600 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 601 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 602 603 // Minimum logical. 604 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 605 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 606 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 607 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 608 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 609 } 610 611 let isCommutable = 1 in { 612 // Multiply and add low. 613 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 614 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 615 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 616 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 617 618 // Multiply and add high. 619 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 620 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 621 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 622 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 623 624 // Multiply and add logical high. 625 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 626 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 627 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 628 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 629 630 // Multiply and add even. 631 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 632 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 633 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 634 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 635 636 // Multiply and add logical even. 637 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 638 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 639 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 640 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 641 642 // Multiply and add odd. 643 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 644 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 645 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 646 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 647 648 // Multiply and add logical odd. 649 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 650 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 651 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 652 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 653 } 654 655 let isCommutable = 1 in { 656 // Multiply high. 657 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 658 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 659 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 660 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 661 662 // Multiply logical high. 663 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 664 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 665 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 666 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 667 668 // Multiply low. 669 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 670 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 671 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 672 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 673 674 // Multiply even. 675 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 676 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 677 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 678 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 679 680 // Multiply logical even. 681 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 682 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 683 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 684 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 685 686 // Multiply odd. 687 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 688 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 689 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 690 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 691 692 // Multiply logical odd. 693 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 694 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 695 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 696 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 697 } 698 699 // Multiply sum logical. 700 let Predicates = [FeatureVectorEnhancements1], isCommutable = 1 in { 701 def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>; 702 def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg, 703 v128q, v128g, v128g, v128q, 3>; 704 } 705 706 // Nand. 707 let Predicates = [FeatureVectorEnhancements1], isCommutable = 1 in 708 def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>; 709 710 // Nor. 711 let isCommutable = 1 in 712 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 713 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 714 715 // Or. 716 let isCommutable = 1 in 717 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 718 719 // Or with complement. 720 let Predicates = [FeatureVectorEnhancements1] in 721 def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>; 722 723 // Population count. 724 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 725 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 726 let Predicates = [FeatureVectorEnhancements1] in { 727 def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>; 728 def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>; 729 def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>; 730 def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>; 731 } 732 733 // Element rotate left logical (with vector shift amount). 734 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 735 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb, 736 v128b, v128b, 0>; 737 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh, 738 v128h, v128h, 1>; 739 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf, 740 v128f, v128f, 2>; 741 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg, 742 v128g, v128g, 3>; 743 744 // Element rotate left logical (with scalar shift amount). 745 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 746 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>; 747 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>; 748 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>; 749 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>; 750 751 // Element rotate and insert under mask. 752 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 753 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 754 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 755 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 756 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 757 758 // Element shift left (with vector shift amount). 759 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 760 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 761 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 762 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 763 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 764 765 // Element shift left (with scalar shift amount). 766 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 767 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 768 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 769 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 770 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 771 772 // Element shift right arithmetic (with vector shift amount). 773 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 774 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 775 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 776 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 777 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 778 779 // Element shift right arithmetic (with scalar shift amount). 780 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 781 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 782 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 783 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 784 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 785 786 // Element shift right logical (with vector shift amount). 787 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 788 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 789 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 790 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 791 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 792 793 // Element shift right logical (with scalar shift amount). 794 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 795 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 796 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 797 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 798 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 799 800 // Shift left. 801 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 802 803 // Shift left by byte. 804 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 805 806 // Shift left double by byte. 807 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 808 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8_timm:$z), 809 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 810 811 // Shift left double by bit. 812 let Predicates = [FeatureVectorEnhancements2] in 813 def VSLD : TernaryVRId<"vsld", 0xE786, int_s390_vsld, v128b, v128b, 0>; 814 815 // Shift right arithmetic. 816 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 817 818 // Shift right arithmetic by byte. 819 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 820 821 // Shift right logical. 822 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 823 824 // Shift right logical by byte. 825 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 826 827 // Shift right double by bit. 828 let Predicates = [FeatureVectorEnhancements2] in 829 def VSRD : TernaryVRId<"vsrd", 0xE787, int_s390_vsrd, v128b, v128b, 0>; 830 831 // Subtract. 832 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 833 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 834 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 835 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 836 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 837 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>; 838 839 // Subtract compute borrow indication. 840 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 841 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>; 842 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>; 843 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>; 844 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>; 845 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>; 846 847 // Subtract with borrow indication. 848 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 849 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>; 850 851 // Subtract with borrow compute borrow indication. 852 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 853 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq, 854 v128q, v128q, 4>; 855 856 // Sum across doubleword. 857 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 858 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 859 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 860 861 // Sum across quadword. 862 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 863 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 864 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 865 866 // Sum across word. 867 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 868 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 869 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 870} 871 872// Instantiate the bitwise ops for type TYPE. 873multiclass BitwiseVectorOps<ValueType type> { 874 let Predicates = [FeatureVector] in { 875 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 876 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))), 877 (VNC VR128:$x, VR128:$y)>; 878 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 879 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 880 def : Pat<(type (or (and VR128:$x, VR128:$z), 881 (and VR128:$y, (z_vnot VR128:$z)))), 882 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 883 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))), 884 (VNO VR128:$x, VR128:$y)>; 885 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; 886 } 887 let Predicates = [FeatureVectorEnhancements1] in { 888 def : Pat<(type (z_vnot (xor VR128:$x, VR128:$y))), 889 (VNX VR128:$x, VR128:$y)>; 890 def : Pat<(type (z_vnot (and VR128:$x, VR128:$y))), 891 (VNN VR128:$x, VR128:$y)>; 892 def : Pat<(type (or VR128:$x, (z_vnot VR128:$y))), 893 (VOC VR128:$x, VR128:$y)>; 894 } 895} 896 897defm : BitwiseVectorOps<v16i8>; 898defm : BitwiseVectorOps<v8i16>; 899defm : BitwiseVectorOps<v4i32>; 900defm : BitwiseVectorOps<v2i64>; 901 902// Instantiate additional patterns for absolute-related expressions on 903// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 904// instruction. 905multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 906 Instruction lp, int shift> { 907 let Predicates = [FeatureVector] in { 908 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 909 (z_vneg VR128:$x), VR128:$x)), 910 (lc (lp VR128:$x))>; 911 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 912 VR128:$x, (z_vneg VR128:$x))), 913 (lc (lp VR128:$x))>; 914 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 915 VR128:$x, (z_vneg VR128:$x))), 916 (lc (lp VR128:$x))>; 917 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 918 (z_vneg VR128:$x), VR128:$x)), 919 (lc (lp VR128:$x))>; 920 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 921 (z_vneg VR128:$x)), 922 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 923 VR128:$x))), 924 (lp VR128:$x)>; 925 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 926 VR128:$x), 927 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 928 (z_vneg VR128:$x)))), 929 (lc (lp VR128:$x))>; 930 } 931} 932 933defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 934defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 935defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 936defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 937 938// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 939// signed or unsigned "set if greater than" comparison instruction and 940// MIN and MAX are the associated minimum and maximum instructions. 941multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 942 Instruction min, Instruction max> { 943 let Predicates = [FeatureVector] in { 944 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 945 (max VR128:$x, VR128:$y)>; 946 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 947 (min VR128:$x, VR128:$y)>; 948 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 949 VR128:$x, VR128:$y)), 950 (min VR128:$x, VR128:$y)>; 951 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 952 VR128:$y, VR128:$x)), 953 (max VR128:$x, VR128:$y)>; 954 } 955} 956 957// Signed min/max. 958defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 959defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 960defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 961defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 962 963// Unsigned min/max. 964defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 965defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 966defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 967defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 968 969//===----------------------------------------------------------------------===// 970// Integer comparison 971//===----------------------------------------------------------------------===// 972 973let Predicates = [FeatureVector] in { 974 // Element compare. 975 let Defs = [CC] in { 976 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 977 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 978 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 979 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 980 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 981 } 982 983 // Element compare logical. 984 let Defs = [CC] in { 985 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 986 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 987 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 988 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 989 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 990 } 991 992 // Compare equal. 993 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 994 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 995 v128b, v128b, 0>; 996 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 997 v128h, v128h, 1>; 998 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 999 v128f, v128f, 2>; 1000 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 1001 v128g, v128g, 3>; 1002 1003 // Compare high. 1004 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 1005 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 1006 v128b, v128b, 0>; 1007 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 1008 v128h, v128h, 1>; 1009 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 1010 v128f, v128f, 2>; 1011 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 1012 v128g, v128g, 3>; 1013 1014 // Compare high logical. 1015 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 1016 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 1017 v128b, v128b, 0>; 1018 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 1019 v128h, v128h, 1>; 1020 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 1021 v128f, v128f, 2>; 1022 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 1023 v128g, v128g, 3>; 1024 1025 // Test under mask. 1026 let Defs = [CC] in 1027 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 1028} 1029 1030//===----------------------------------------------------------------------===// 1031// Floating-point arithmetic 1032//===----------------------------------------------------------------------===// 1033 1034// See comments in SystemZInstrFP.td for the suppression flags and 1035// rounding modes. 1036multiclass VectorRounding<Instruction insn, TypedReg tr> { 1037 def : FPConversion<insn, any_frint, tr, tr, 0, 0>; 1038 def : FPConversion<insn, any_fnearbyint, tr, tr, 4, 0>; 1039 def : FPConversion<insn, any_ffloor, tr, tr, 4, 7>; 1040 def : FPConversion<insn, any_fceil, tr, tr, 4, 6>; 1041 def : FPConversion<insn, any_ftrunc, tr, tr, 4, 5>; 1042 def : FPConversion<insn, any_fround, tr, tr, 4, 1>; 1043} 1044 1045let Predicates = [FeatureVector] in { 1046 // Add. 1047 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1048 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 1049 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, any_fadd, v128db, v128db, 3, 0>; 1050 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, any_fadd, v64db, v64db, 3, 8>; 1051 let Predicates = [FeatureVectorEnhancements1] in { 1052 def VFASB : BinaryVRRc<"vfasb", 0xE7E3, any_fadd, v128sb, v128sb, 2, 0>; 1053 def WFASB : BinaryVRRc<"wfasb", 0xE7E3, any_fadd, v32sb, v32sb, 2, 8>; 1054 def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, any_fadd, v128xb, v128xb, 4, 8>; 1055 } 1056 } 1057 1058 // Convert from fixed. 1059 let Uses = [FPC], mayRaiseFPException = 1 in { 1060 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 1061 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 1062 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 1063 } 1064 def : FPConversion<VCDGB, any_sint_to_fp, v128db, v128g, 0, 0>; 1065 let Predicates = [FeatureVectorEnhancements2] in { 1066 let Uses = [FPC], mayRaiseFPException = 1 in { 1067 let isAsmParserOnly = 1 in 1068 def VCFPS : TernaryVRRaFloatGeneric<"vcfps", 0xE7C3>; 1069 def VCEFB : TernaryVRRa<"vcefb", 0xE7C3, null_frag, v128sb, v128g, 2, 0>; 1070 def WCEFB : TernaryVRRa<"wcefb", 0xE7C3, null_frag, v32sb, v32f, 2, 8>; 1071 } 1072 def : FPConversion<VCEFB, any_sint_to_fp, v128sb, v128f, 0, 0>; 1073 } 1074 1075 // Convert from logical. 1076 let Uses = [FPC], mayRaiseFPException = 1 in { 1077 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 1078 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 1079 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 1080 } 1081 def : FPConversion<VCDLGB, any_uint_to_fp, v128db, v128g, 0, 0>; 1082 let Predicates = [FeatureVectorEnhancements2] in { 1083 let Uses = [FPC], mayRaiseFPException = 1 in { 1084 let isAsmParserOnly = 1 in 1085 def VCFPL : TernaryVRRaFloatGeneric<"vcfpl", 0xE7C1>; 1086 def VCELFB : TernaryVRRa<"vcelfb", 0xE7C1, null_frag, v128sb, v128g, 2, 0>; 1087 def WCELFB : TernaryVRRa<"wcelfb", 0xE7C1, null_frag, v32sb, v32f, 2, 8>; 1088 } 1089 def : FPConversion<VCELFB, any_uint_to_fp, v128sb, v128f, 0, 0>; 1090 } 1091 1092 // Convert to fixed. 1093 let Uses = [FPC], mayRaiseFPException = 1 in { 1094 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 1095 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 1096 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 1097 } 1098 // Rounding mode should agree with SystemZInstrFP.td. 1099 def : FPConversion<VCGDB, any_fp_to_sint, v128g, v128db, 0, 5>; 1100 let Predicates = [FeatureVectorEnhancements2] in { 1101 let Uses = [FPC], mayRaiseFPException = 1 in { 1102 let isAsmParserOnly = 1 in 1103 def VCSFP : TernaryVRRaFloatGeneric<"vcsfp", 0xE7C2>; 1104 def VCFEB : TernaryVRRa<"vcfeb", 0xE7C2, null_frag, v128sb, v128g, 2, 0>; 1105 def WCFEB : TernaryVRRa<"wcfeb", 0xE7C2, null_frag, v32sb, v32f, 2, 8>; 1106 } 1107 // Rounding mode should agree with SystemZInstrFP.td. 1108 def : FPConversion<VCFEB, any_fp_to_sint, v128f, v128sb, 0, 5>; 1109 } 1110 1111 // Convert to logical. 1112 let Uses = [FPC], mayRaiseFPException = 1 in { 1113 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 1114 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 1115 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 1116 } 1117 // Rounding mode should agree with SystemZInstrFP.td. 1118 def : FPConversion<VCLGDB, any_fp_to_uint, v128g, v128db, 0, 5>; 1119 let Predicates = [FeatureVectorEnhancements2] in { 1120 let Uses = [FPC], mayRaiseFPException = 1 in { 1121 let isAsmParserOnly = 1 in 1122 def VCLFP : TernaryVRRaFloatGeneric<"vclfp", 0xE7C0>; 1123 def VCLFEB : TernaryVRRa<"vclfeb", 0xE7C0, null_frag, v128sb, v128g, 2, 0>; 1124 def WCLFEB : TernaryVRRa<"wclfeb", 0xE7C0, null_frag, v32sb, v32f, 2, 8>; 1125 } 1126 // Rounding mode should agree with SystemZInstrFP.td. 1127 def : FPConversion<VCLFEB, any_fp_to_uint, v128f, v128sb, 0, 5>; 1128 } 1129 1130 // Divide. 1131 let Uses = [FPC], mayRaiseFPException = 1 in { 1132 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 1133 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, any_fdiv, v128db, v128db, 3, 0>; 1134 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, any_fdiv, v64db, v64db, 3, 8>; 1135 let Predicates = [FeatureVectorEnhancements1] in { 1136 def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, any_fdiv, v128sb, v128sb, 2, 0>; 1137 def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, any_fdiv, v32sb, v32sb, 2, 8>; 1138 def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, any_fdiv, v128xb, v128xb, 4, 8>; 1139 } 1140 } 1141 1142 // Load FP integer. 1143 let Uses = [FPC], mayRaiseFPException = 1 in { 1144 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 1145 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 1146 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 1147 } 1148 defm : VectorRounding<VFIDB, v128db>; 1149 defm : VectorRounding<WFIDB, v64db>; 1150 let Predicates = [FeatureVectorEnhancements1] in { 1151 let Uses = [FPC], mayRaiseFPException = 1 in { 1152 def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>; 1153 def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>; 1154 def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>; 1155 } 1156 defm : VectorRounding<VFISB, v128sb>; 1157 defm : VectorRounding<WFISB, v32sb>; 1158 defm : VectorRounding<WFIXB, v128xb>; 1159 } 1160 1161 // Load lengthened. 1162 let Uses = [FPC], mayRaiseFPException = 1 in { 1163 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 1164 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_any_vextend, v128db, v128sb, 2, 0>; 1165 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, any_fpextend, v64db, v32sb, 2, 8>; 1166 } 1167 let Predicates = [FeatureVectorEnhancements1] in { 1168 let Uses = [FPC], mayRaiseFPException = 1 in { 1169 let isAsmParserOnly = 1 in { 1170 def VFLL : UnaryVRRaFloatGeneric<"vfll", 0xE7C4>; 1171 def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>; 1172 def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>; 1173 } 1174 def WFLLD : UnaryVRRa<"wflld", 0xE7C4, any_fpextend, v128xb, v64db, 3, 8>; 1175 } 1176 def : Pat<(f128 (any_fpextend (f32 VR32:$src))), 1177 (WFLLD (WLDEB VR32:$src))>; 1178 } 1179 1180 // Load rounded. 1181 let Uses = [FPC], mayRaiseFPException = 1 in { 1182 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 1183 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1184 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1185 } 1186 def : Pat<(v4f32 (z_any_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 1187 def : FPConversion<WLEDB, any_fpround, v32sb, v64db, 0, 0>; 1188 let Predicates = [FeatureVectorEnhancements1] in { 1189 let Uses = [FPC], mayRaiseFPException = 1 in { 1190 let isAsmParserOnly = 1 in { 1191 def VFLR : TernaryVRRaFloatGeneric<"vflr", 0xE7C5>; 1192 def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1193 def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1194 } 1195 def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>; 1196 } 1197 def : FPConversion<WFLRX, any_fpround, v64db, v128xb, 0, 0>; 1198 def : Pat<(f32 (any_fpround (f128 VR128:$src))), 1199 (WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>; 1200 } 1201 1202 // Maximum. 1203 multiclass VectorMax<Instruction insn, TypedReg tr> { 1204 def : FPMinMax<insn, any_fmaxnum, tr, 4>; 1205 def : FPMinMax<insn, any_fmaximum, tr, 1>; 1206 } 1207 let Predicates = [FeatureVectorEnhancements1] in { 1208 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1209 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; 1210 def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb, 1211 v128db, v128db, 3, 0>; 1212 def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag, 1213 v64db, v64db, 3, 8>; 1214 def VFMAXSB : TernaryVRRcFloat<"vfmaxsb", 0xE7EF, int_s390_vfmaxsb, 1215 v128sb, v128sb, 2, 0>; 1216 def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag, 1217 v32sb, v32sb, 2, 8>; 1218 def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag, 1219 v128xb, v128xb, 4, 8>; 1220 } 1221 defm : VectorMax<VFMAXDB, v128db>; 1222 defm : VectorMax<WFMAXDB, v64db>; 1223 defm : VectorMax<VFMAXSB, v128sb>; 1224 defm : VectorMax<WFMAXSB, v32sb>; 1225 defm : VectorMax<WFMAXXB, v128xb>; 1226 } 1227 1228 // Minimum. 1229 multiclass VectorMin<Instruction insn, TypedReg tr> { 1230 def : FPMinMax<insn, any_fminnum, tr, 4>; 1231 def : FPMinMax<insn, any_fminimum, tr, 1>; 1232 } 1233 let Predicates = [FeatureVectorEnhancements1] in { 1234 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1235 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; 1236 def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb, 1237 v128db, v128db, 3, 0>; 1238 def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag, 1239 v64db, v64db, 3, 8>; 1240 def VFMINSB : TernaryVRRcFloat<"vfminsb", 0xE7EE, int_s390_vfminsb, 1241 v128sb, v128sb, 2, 0>; 1242 def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag, 1243 v32sb, v32sb, 2, 8>; 1244 def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag, 1245 v128xb, v128xb, 4, 8>; 1246 } 1247 defm : VectorMin<VFMINDB, v128db>; 1248 defm : VectorMin<WFMINDB, v64db>; 1249 defm : VectorMin<VFMINSB, v128sb>; 1250 defm : VectorMin<WFMINSB, v32sb>; 1251 defm : VectorMin<WFMINXB, v128xb>; 1252 } 1253 1254 // Multiply. 1255 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1256 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 1257 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, any_fmul, v128db, v128db, 3, 0>; 1258 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, any_fmul, v64db, v64db, 3, 8>; 1259 let Predicates = [FeatureVectorEnhancements1] in { 1260 def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, any_fmul, v128sb, v128sb, 2, 0>; 1261 def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, any_fmul, v32sb, v32sb, 2, 8>; 1262 def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, any_fmul, v128xb, v128xb, 4, 8>; 1263 } 1264 } 1265 1266 // Multiply and add. 1267 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1268 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 1269 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, any_fma, v128db, v128db, 0, 3>; 1270 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, any_fma, v64db, v64db, 8, 3>; 1271 let Predicates = [FeatureVectorEnhancements1] in { 1272 def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, any_fma, v128sb, v128sb, 0, 2>; 1273 def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, any_fma, v32sb, v32sb, 8, 2>; 1274 def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, any_fma, v128xb, v128xb, 8, 4>; 1275 } 1276 } 1277 1278 // Multiply and subtract. 1279 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1 in { 1280 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 1281 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, any_fms, v128db, v128db, 0, 3>; 1282 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, any_fms, v64db, v64db, 8, 3>; 1283 let Predicates = [FeatureVectorEnhancements1] in { 1284 def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, any_fms, v128sb, v128sb, 0, 2>; 1285 def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, any_fms, v32sb, v32sb, 8, 2>; 1286 def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, any_fms, v128xb, v128xb, 8, 4>; 1287 } 1288 } 1289 1290 // Negative multiply and add. 1291 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1, 1292 Predicates = [FeatureVectorEnhancements1] in { 1293 def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>; 1294 def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, any_fnma, v128db, v128db, 0, 3>; 1295 def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, any_fnma, v64db, v64db, 8, 3>; 1296 def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, any_fnma, v128sb, v128sb, 0, 2>; 1297 def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, any_fnma, v32sb, v32sb, 8, 2>; 1298 def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, any_fnma, v128xb, v128xb, 8, 4>; 1299 } 1300 1301 // Negative multiply and subtract. 1302 let Uses = [FPC], mayRaiseFPException = 1, isCommutable = 1, 1303 Predicates = [FeatureVectorEnhancements1] in { 1304 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>; 1305 def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, any_fnms, v128db, v128db, 0, 3>; 1306 def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, any_fnms, v64db, v64db, 8, 3>; 1307 def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, any_fnms, v128sb, v128sb, 0, 2>; 1308 def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, any_fnms, v32sb, v32sb, 8, 2>; 1309 def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, any_fnms, v128xb, v128xb, 8, 4>; 1310 } 1311 1312 // Perform sign operation. 1313 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 1314 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 1315 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 1316 let Predicates = [FeatureVectorEnhancements1] in { 1317 def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>; 1318 def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>; 1319 def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>; 1320 } 1321 1322 // Load complement. 1323 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 1324 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 1325 let Predicates = [FeatureVectorEnhancements1] in { 1326 def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>; 1327 def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>; 1328 def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>; 1329 } 1330 1331 // Load negative. 1332 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 1333 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 1334 let Predicates = [FeatureVectorEnhancements1] in { 1335 def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>; 1336 def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>; 1337 def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>; 1338 } 1339 1340 // Load positive. 1341 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 1342 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 1343 let Predicates = [FeatureVectorEnhancements1] in { 1344 def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>; 1345 def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>; 1346 def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>; 1347 } 1348 1349 // Square root. 1350 let Uses = [FPC], mayRaiseFPException = 1 in { 1351 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 1352 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, any_fsqrt, v128db, v128db, 3, 0>; 1353 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, any_fsqrt, v64db, v64db, 3, 8>; 1354 let Predicates = [FeatureVectorEnhancements1] in { 1355 def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, any_fsqrt, v128sb, v128sb, 2, 0>; 1356 def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, any_fsqrt, v32sb, v32sb, 2, 8>; 1357 def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, any_fsqrt, v128xb, v128xb, 4, 8>; 1358 } 1359 } 1360 1361 // Subtract. 1362 let Uses = [FPC], mayRaiseFPException = 1 in { 1363 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 1364 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, any_fsub, v128db, v128db, 3, 0>; 1365 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, any_fsub, v64db, v64db, 3, 8>; 1366 let Predicates = [FeatureVectorEnhancements1] in { 1367 def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, any_fsub, v128sb, v128sb, 2, 0>; 1368 def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, any_fsub, v32sb, v32sb, 2, 8>; 1369 def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, any_fsub, v128xb, v128xb, 4, 8>; 1370 } 1371 } 1372 1373 // Test data class immediate. 1374 let Defs = [CC] in { 1375 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 1376 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 1377 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 1378 let Predicates = [FeatureVectorEnhancements1] in { 1379 def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>; 1380 def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>; 1381 def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>; 1382 } 1383 } 1384} 1385 1386//===----------------------------------------------------------------------===// 1387// Floating-point comparison 1388//===----------------------------------------------------------------------===// 1389 1390let Predicates = [FeatureVector] in { 1391 // Compare scalar. 1392 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 1393 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 1394 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_any_fcmp, v64db, 3>; 1395 let Predicates = [FeatureVectorEnhancements1] in { 1396 def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_any_fcmp, v32sb, 2>; 1397 def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_any_fcmp, v128xb, 4>; 1398 } 1399 } 1400 1401 // Compare and signal scalar. 1402 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 1403 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 1404 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, z_strict_fcmps, v64db, 3>; 1405 let Predicates = [FeatureVectorEnhancements1] in { 1406 def WFKSB : CompareVRRa<"wfksb", 0xE7CA, z_strict_fcmps, v32sb, 2>; 1407 def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, z_strict_fcmps, v128xb, 4>; 1408 } 1409 } 1410 1411 // Compare equal. 1412 let Uses = [FPC], mayRaiseFPException = 1 in { 1413 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 1414 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_any_vfcmpe, z_vfcmpes, 1415 v128g, v128db, 3, 0>; 1416 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1417 v64g, v64db, 3, 8>; 1418 let Predicates = [FeatureVectorEnhancements1] in { 1419 defm VFCESB : BinaryVRRcSPair<"vfcesb", 0xE7E8, z_any_vfcmpe, z_vfcmpes, 1420 v128f, v128sb, 2, 0>; 1421 defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag, 1422 v32f, v32sb, 2, 8>; 1423 defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag, 1424 v128q, v128xb, 4, 8>; 1425 } 1426 } 1427 1428 // Compare and signal equal. 1429 let Uses = [FPC], mayRaiseFPException = 1, 1430 Predicates = [FeatureVectorEnhancements1] in { 1431 defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, z_strict_vfcmpes, null_frag, 1432 v128g, v128db, 3, 4>; 1433 defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag, 1434 v64g, v64db, 3, 12>; 1435 defm VFKESB : BinaryVRRcSPair<"vfkesb", 0xE7E8, z_strict_vfcmpes, null_frag, 1436 v128f, v128sb, 2, 4>; 1437 defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag, 1438 v32f, v32sb, 2, 12>; 1439 defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag, 1440 v128q, v128xb, 4, 12>; 1441 } 1442 1443 // Compare high. 1444 let Uses = [FPC], mayRaiseFPException = 1 in { 1445 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1446 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_any_vfcmph, z_vfcmphs, 1447 v128g, v128db, 3, 0>; 1448 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1449 v64g, v64db, 3, 8>; 1450 let Predicates = [FeatureVectorEnhancements1] in { 1451 defm VFCHSB : BinaryVRRcSPair<"vfchsb", 0xE7EB, z_any_vfcmph, z_vfcmphs, 1452 v128f, v128sb, 2, 0>; 1453 defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag, 1454 v32f, v32sb, 2, 8>; 1455 defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag, 1456 v128q, v128xb, 4, 8>; 1457 } 1458 } 1459 1460 // Compare and signal high. 1461 let Uses = [FPC], mayRaiseFPException = 1, 1462 Predicates = [FeatureVectorEnhancements1] in { 1463 defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, z_strict_vfcmphs, null_frag, 1464 v128g, v128db, 3, 4>; 1465 defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag, 1466 v64g, v64db, 3, 12>; 1467 defm VFKHSB : BinaryVRRcSPair<"vfkhsb", 0xE7EB, z_strict_vfcmphs, null_frag, 1468 v128f, v128sb, 2, 4>; 1469 defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag, 1470 v32f, v32sb, 2, 12>; 1471 defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag, 1472 v128q, v128xb, 4, 12>; 1473 } 1474 1475 // Compare high or equal. 1476 let Uses = [FPC], mayRaiseFPException = 1 in { 1477 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1478 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_any_vfcmphe, z_vfcmphes, 1479 v128g, v128db, 3, 0>; 1480 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1481 v64g, v64db, 3, 8>; 1482 let Predicates = [FeatureVectorEnhancements1] in { 1483 defm VFCHESB : BinaryVRRcSPair<"vfchesb", 0xE7EA, z_any_vfcmphe, z_vfcmphes, 1484 v128f, v128sb, 2, 0>; 1485 defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag, 1486 v32f, v32sb, 2, 8>; 1487 defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag, 1488 v128q, v128xb, 4, 8>; 1489 } 1490 } 1491 1492 // Compare and signal high or equal. 1493 let Uses = [FPC], mayRaiseFPException = 1, 1494 Predicates = [FeatureVectorEnhancements1] in { 1495 defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, z_strict_vfcmphes, null_frag, 1496 v128g, v128db, 3, 4>; 1497 defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag, 1498 v64g, v64db, 3, 12>; 1499 defm VFKHESB : BinaryVRRcSPair<"vfkhesb", 0xE7EA, z_strict_vfcmphes, null_frag, 1500 v128f, v128sb, 2, 4>; 1501 defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag, 1502 v32f, v32sb, 2, 12>; 1503 defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag, 1504 v128q, v128xb, 4, 12>; 1505 } 1506} 1507 1508//===----------------------------------------------------------------------===// 1509// Conversions 1510//===----------------------------------------------------------------------===// 1511 1512def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 1513def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 1514def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 1515def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 1516def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 1517def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>; 1518 1519def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 1520def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 1521def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 1522def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 1523def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 1524def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>; 1525 1526def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 1527def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 1528def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 1529def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 1530def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 1531def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>; 1532 1533def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 1534def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 1535def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 1536def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 1537def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 1538def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>; 1539 1540def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 1541def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 1542def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 1543def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 1544def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 1545def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>; 1546 1547def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 1548def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 1549def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 1550def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 1551def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 1552def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>; 1553 1554def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>; 1555def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>; 1556def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>; 1557def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>; 1558def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>; 1559def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>; 1560 1561//===----------------------------------------------------------------------===// 1562// Replicating scalars 1563//===----------------------------------------------------------------------===// 1564 1565// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 1566// INDEX is 8 minus the element size in bytes. 1567class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 1568 : Pat<(type (z_replicate GR32:$scalar)), 1569 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 1570 1571def : VectorReplicateScalar<v16i8, VREPB, 7>; 1572def : VectorReplicateScalar<v8i16, VREPH, 3>; 1573def : VectorReplicateScalar<v4i32, VREPF, 1>; 1574 1575// i64 replications are just a single instruction. 1576def : Pat<(v2i64 (z_replicate GR64:$scalar)), 1577 (VLVGP GR64:$scalar, GR64:$scalar)>; 1578 1579//===----------------------------------------------------------------------===// 1580// Floating-point insertion and extraction 1581//===----------------------------------------------------------------------===// 1582 1583// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 1584// and VLGVF. 1585let Predicates = [FeatureVector] in { 1586 def LEFR : UnaryAliasVRS<VR32, GR32>; 1587 def LFER : UnaryAliasVRS<GR64, VR32>; 1588 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 1589 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 1590 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 1591} 1592 1593// Floating-point values are stored in element 0 of the corresponding 1594// vector register. Scalar to vector conversion is just a subreg and 1595// scalar replication can just replicate element 0 of the vector register. 1596multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 1597 SubRegIndex subreg> { 1598 def : Pat<(vt (scalar_to_vector cls:$scalar)), 1599 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 1600 def : Pat<(vt (z_replicate cls:$scalar)), 1601 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 1602 subreg), 0)>; 1603} 1604defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_h32>; 1605defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>; 1606 1607// Match v2f64 insertions. The AddedComplexity counters the 3 added by 1608// TableGen for the base register operand in VLVG-based integer insertions 1609// and ensures that this version is strictly better. 1610let AddedComplexity = 4 in { 1611 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 1612 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1613 subreg_h64), VR128:$vec, 1)>; 1614 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 1615 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1616 subreg_h64), 0)>; 1617} 1618 1619// We extract floating-point element X by replicating (for elements other 1620// than 0) and then taking a high subreg. The AddedComplexity counters the 1621// 3 added by TableGen for the base register operand in VLGV-based integer 1622// extractions and ensures that this version is strictly better. 1623let AddedComplexity = 4 in { 1624 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 1625 (EXTRACT_SUBREG VR128:$vec, subreg_h32)>; 1626 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 1627 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_h32)>; 1628 1629 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 1630 (EXTRACT_SUBREG VR128:$vec, subreg_h64)>; 1631 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 1632 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_h64)>; 1633} 1634 1635//===----------------------------------------------------------------------===// 1636// Support for 128-bit floating-point values in vector registers 1637//===----------------------------------------------------------------------===// 1638 1639let Predicates = [FeatureVectorEnhancements1] in { 1640 def : Pat<(f128 (load bdxaddr12only:$addr)), 1641 (VL bdxaddr12only:$addr)>; 1642 def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr), 1643 (VST VR128:$src, bdxaddr12only:$addr)>; 1644 1645 def : Pat<(f128 fpimm0), (VZERO)>; 1646 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>; 1647} 1648 1649//===----------------------------------------------------------------------===// 1650// String instructions 1651//===----------------------------------------------------------------------===// 1652 1653let Predicates = [FeatureVector] in { 1654 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 1655 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 1656 z_vfae_cc, v128b, v128b, 0>; 1657 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 1658 z_vfae_cc, v128h, v128h, 1>; 1659 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 1660 z_vfae_cc, v128f, v128f, 2>; 1661 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 1662 z_vfaez_cc, v128b, v128b, 0, 2>; 1663 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 1664 z_vfaez_cc, v128h, v128h, 1, 2>; 1665 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 1666 z_vfaez_cc, v128f, v128f, 2, 2>; 1667 1668 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 1669 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 1670 z_vfee_cc, v128b, v128b, 0>; 1671 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 1672 z_vfee_cc, v128h, v128h, 1>; 1673 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 1674 z_vfee_cc, v128f, v128f, 2>; 1675 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 1676 z_vfeez_cc, v128b, v128b, 0, 2>; 1677 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 1678 z_vfeez_cc, v128h, v128h, 1, 2>; 1679 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 1680 z_vfeez_cc, v128f, v128f, 2, 2>; 1681 1682 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 1683 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 1684 z_vfene_cc, v128b, v128b, 0>; 1685 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 1686 z_vfene_cc, v128h, v128h, 1>; 1687 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 1688 z_vfene_cc, v128f, v128f, 2>; 1689 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 1690 z_vfenez_cc, v128b, v128b, 0, 2>; 1691 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 1692 z_vfenez_cc, v128h, v128h, 1, 2>; 1693 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 1694 z_vfenez_cc, v128f, v128f, 2, 2>; 1695 1696 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 1697 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 1698 z_vistr_cc, v128b, v128b, 0>; 1699 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 1700 z_vistr_cc, v128h, v128h, 1>; 1701 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 1702 z_vistr_cc, v128f, v128f, 2>; 1703 1704 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 1705 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 1706 z_vstrc_cc, v128b, v128b, 0>; 1707 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 1708 z_vstrc_cc, v128h, v128h, 1>; 1709 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 1710 z_vstrc_cc, v128f, v128f, 2>; 1711 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 1712 z_vstrcz_cc, v128b, v128b, 0, 2>; 1713 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 1714 z_vstrcz_cc, v128h, v128h, 1, 2>; 1715 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 1716 z_vstrcz_cc, v128f, v128f, 2, 2>; 1717} 1718 1719let Predicates = [FeatureVectorEnhancements2] in { 1720 defm VSTRS : TernaryExtraVRRdGeneric<"vstrs", 0xE78B>; 1721 defm VSTRSB : TernaryExtraVRRd<"vstrsb", 0xE78B, 1722 z_vstrs_cc, v128b, v128b, 0>; 1723 defm VSTRSH : TernaryExtraVRRd<"vstrsh", 0xE78B, 1724 z_vstrs_cc, v128b, v128h, 1>; 1725 defm VSTRSF : TernaryExtraVRRd<"vstrsf", 0xE78B, 1726 z_vstrs_cc, v128b, v128f, 2>; 1727 let Defs = [CC] in { 1728 def VSTRSZB : TernaryVRRd<"vstrszb", 0xE78B, 1729 z_vstrsz_cc, v128b, v128b, 0, 2>; 1730 def VSTRSZH : TernaryVRRd<"vstrszh", 0xE78B, 1731 z_vstrsz_cc, v128b, v128h, 1, 2>; 1732 def VSTRSZF : TernaryVRRd<"vstrszf", 0xE78B, 1733 z_vstrsz_cc, v128b, v128f, 2, 2>; 1734 } 1735} 1736 1737//===----------------------------------------------------------------------===// 1738// Packed-decimal instructions 1739//===----------------------------------------------------------------------===// 1740 1741let Predicates = [FeatureVectorPackedDecimal] in { 1742 def VLIP : BinaryVRIh<"vlip", 0xE649>; 1743 1744 def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>; 1745 def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>; 1746 1747 let Defs = [CC] in { 1748 let Predicates = [FeatureVectorPackedDecimalEnhancement] in { 1749 def VCVBOpt : TernaryVRRi<"vcvb", 0xE650, GR32>; 1750 def VCVBGOpt : TernaryVRRi<"vcvbg", 0xE652, GR64>; 1751 } 1752 def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>; 1753 def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>; 1754 def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>; 1755 def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>; 1756 1757 def VAP : QuaternaryVRIf<"vap", 0xE671>; 1758 def VSP : QuaternaryVRIf<"vsp", 0xE673>; 1759 1760 def VMP : QuaternaryVRIf<"vmp", 0xE678>; 1761 def VMSP : QuaternaryVRIf<"vmsp", 0xE679>; 1762 1763 def VDP : QuaternaryVRIf<"vdp", 0xE67A>; 1764 def VRP : QuaternaryVRIf<"vrp", 0xE67B>; 1765 def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>; 1766 1767 def VSRP : QuaternaryVRIg<"vsrp", 0xE659>; 1768 def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>; 1769 1770 def VTP : TestVRRg<"vtp", 0xE65F>; 1771 def VCP : CompareVRRh<"vcp", 0xE677>; 1772 } 1773} 1774