1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Move instructions 12//===----------------------------------------------------------------------===// 13 14let Predicates = [FeatureVector] in { 15 // Register move. 16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 17 def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>; 18 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 19 20 // Load GR from VR element. 21 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 22 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 23 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 24 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 25 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 26 27 // Load VR element from GR. 28 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 29 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 30 v128b, v128b, GR32, 0>; 31 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 32 v128h, v128h, GR32, 1>; 33 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 34 v128f, v128f, GR32, 2>; 35 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 36 v128g, v128g, GR64, 3>; 37 38 // Load VR from GRs disjoint. 39 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 40 def VLVGP32 : BinaryAliasVRRf<GR32>; 41} 42 43// Extractions always assign to the full GR64, even if the element would 44// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 45// subreg of the result. 46class VectorExtractSubreg<ValueType type, Instruction insn> 47 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 48 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 49 50def : VectorExtractSubreg<v16i8, VLGVB>; 51def : VectorExtractSubreg<v8i16, VLGVH>; 52def : VectorExtractSubreg<v4i32, VLGVF>; 53 54//===----------------------------------------------------------------------===// 55// Immediate instructions 56//===----------------------------------------------------------------------===// 57 58let Predicates = [FeatureVector] in { 59 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 60 isReMaterializable = 1 in { 61 62 // Generate byte mask. 63 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 64 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 65 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; 66 67 // Generate mask. 68 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 69 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 70 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 71 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 72 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 73 74 // Replicate immediate. 75 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 76 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; 77 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; 78 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; 79 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; 80 } 81 82 // Load element immediate. 83 // 84 // We want these instructions to be used ahead of VLVG* where possible. 85 // However, VLVG* takes a variable BD-format index whereas VLEI takes 86 // a plain immediate index. This means that VLVG* has an extra "base" 87 // register operand and is 3 units more complex. Bumping the complexity 88 // of the VLEI* instructions by 4 means that they are strictly better 89 // than VLVG* in cases where both forms match. 90 let AddedComplexity = 4 in { 91 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 92 v128b, v128b, imm32sx16trunc, imm32zx4>; 93 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 94 v128h, v128h, imm32sx16trunc, imm32zx3>; 95 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 96 v128f, v128f, imm32sx16, imm32zx2>; 97 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 98 v128g, v128g, imm64sx16, imm32zx1>; 99 } 100} 101 102//===----------------------------------------------------------------------===// 103// Loads 104//===----------------------------------------------------------------------===// 105 106let Predicates = [FeatureVector] in { 107 // Load. 108 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>; 109 110 // Load to block boundary. The number of loaded bytes is only known 111 // at run time. The instruction is really polymorphic, but v128b matches 112 // the return type of the associated intrinsic. 113 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 114 115 // Load count to block boundary. 116 let Defs = [CC] in 117 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 118 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 119 "lcbb\t$R1, $XBD2, $M3", 120 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 121 imm32zx4:$M3))]>; 122 123 // Load with length. The number of loaded bytes is only known at run time. 124 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 125 126 // Load multiple. 127 def VLM : LoadMultipleVRSa<"vlm", 0xE736>; 128 129 // Load and replicate 130 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 131 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 132 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 133 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 134 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 135 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 136 (VLREPF bdxaddr12only:$addr)>; 137 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 138 (VLREPG bdxaddr12only:$addr)>; 139 140 // Use VLREP to load subvectors. These patterns use "12pair" because 141 // LEY and LDY offer full 20-bit displacement fields. It's often better 142 // to use those instructions rather than force a 20-bit displacement 143 // into a GPR temporary. 144 def VL32 : UnaryAliasVRX<load, v32sb, bdxaddr12pair>; 145 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>; 146 147 // Load logical element and zero. 148 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 149 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 150 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 151 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 152 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 153 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)), 154 (VLLEZF bdxaddr12only:$addr)>; 155 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)), 156 (VLLEZG bdxaddr12only:$addr)>; 157 let Predicates = [FeatureVectorEnhancements1] in { 158 def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>; 159 def : Pat<(v4f32 (z_vllezlf32 bdxaddr12only:$addr)), 160 (VLLEZLF bdxaddr12only:$addr)>; 161 } 162 163 // Load element. 164 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 165 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 166 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 167 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 168 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 169 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 170 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 171 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 172 173 // Gather element. 174 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 175 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 176} 177 178let Predicates = [FeatureVectorPackedDecimal] in { 179 // Load rightmost with length. The number of loaded bytes is only known 180 // at run time. 181 def VLRL : BinaryVSI<"vlrl", 0xE635, int_s390_vlrl, 0>; 182 def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>; 183} 184 185// Use replicating loads if we're inserting a single element into an 186// undefined vector. This avoids a false dependency on the previous 187// register contents. 188multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 189 SDPatternOperator load, ValueType scalartype> { 190 def : Pat<(vectype (z_vector_insert 191 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 192 (vlrep bdxaddr12only:$addr)>; 193 def : Pat<(vectype (scalar_to_vector 194 (scalartype (load bdxaddr12only:$addr)))), 195 (vlrep bdxaddr12only:$addr)>; 196} 197defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>; 198defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>; 199defm : ReplicatePeephole<VLREPF, v4i32, load, i32>; 200defm : ReplicatePeephole<VLREPG, v2i64, load, i64>; 201defm : ReplicatePeephole<VLREPF, v4f32, load, f32>; 202defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 203 204//===----------------------------------------------------------------------===// 205// Stores 206//===----------------------------------------------------------------------===// 207 208let Predicates = [FeatureVector] in { 209 // Store. 210 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>; 211 212 // Store with length. The number of stored bytes is only known at run time. 213 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 214 215 // Store multiple. 216 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>; 217 218 // Store element. 219 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 220 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 221 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 222 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 223 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 224 imm32zx2:$index), 225 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 226 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 227 imm32zx1:$index), 228 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 229 230 // Use VSTE to store subvectors. These patterns use "12pair" because 231 // STEY and STDY offer full 20-bit displacement fields. It's often better 232 // to use those instructions rather than force a 20-bit displacement 233 // into a GPR temporary. 234 def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>; 235 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 236 237 // Scatter element. 238 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 239 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 240} 241 242let Predicates = [FeatureVectorPackedDecimal] in { 243 // Store rightmost with length. The number of stored bytes is only known 244 // at run time. 245 def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, int_s390_vstrl, 0>; 246 def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>; 247} 248 249//===----------------------------------------------------------------------===// 250// Selects and permutes 251//===----------------------------------------------------------------------===// 252 253let Predicates = [FeatureVector] in { 254 // Merge high. 255 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 256 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 257 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 258 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 259 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 260 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 261 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 262 263 // Merge low. 264 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 265 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 266 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 267 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 268 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 269 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 270 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 271 272 // Permute. 273 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 274 275 // Permute doubleword immediate. 276 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 277 278 // Bit Permute. 279 let Predicates = [FeatureVectorEnhancements1] in 280 def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>; 281 282 // Replicate. 283 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 284 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 285 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 286 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 287 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 288 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)), 289 (VREPF VR128:$vec, imm32zx16:$index)>; 290 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)), 291 (VREPG VR128:$vec, imm32zx16:$index)>; 292 293 // Select. 294 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 295} 296 297//===----------------------------------------------------------------------===// 298// Widening and narrowing 299//===----------------------------------------------------------------------===// 300 301let Predicates = [FeatureVector] in { 302 // Pack 303 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 304 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 305 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 306 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 307 308 // Pack saturate. 309 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 310 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 311 v128b, v128h, 1>; 312 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 313 v128h, v128f, 2>; 314 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 315 v128f, v128g, 3>; 316 317 // Pack saturate logical. 318 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 319 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 320 v128b, v128h, 1>; 321 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 322 v128h, v128f, 2>; 323 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 324 v128f, v128g, 3>; 325 326 // Sign-extend to doubleword. 327 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 328 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 329 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 330 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 331 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 332 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 333 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 334 335 // Unpack high. 336 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 337 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 338 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 339 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 340 341 // Unpack logical high. 342 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 343 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 344 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 345 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 346 347 // Unpack low. 348 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 349 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 350 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 351 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 352 353 // Unpack logical low. 354 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 355 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 356 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 357 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 358} 359 360//===----------------------------------------------------------------------===// 361// Instantiating generic operations for specific types. 362//===----------------------------------------------------------------------===// 363 364multiclass GenericVectorOps<ValueType type, ValueType inttype> { 365 let Predicates = [FeatureVector] in { 366 def : Pat<(type (load bdxaddr12only:$addr)), 367 (VL bdxaddr12only:$addr)>; 368 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 369 (VST VR128:$src, bdxaddr12only:$addr)>; 370 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 371 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 372 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 373 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 374 } 375} 376 377defm : GenericVectorOps<v16i8, v16i8>; 378defm : GenericVectorOps<v8i16, v8i16>; 379defm : GenericVectorOps<v4i32, v4i32>; 380defm : GenericVectorOps<v2i64, v2i64>; 381defm : GenericVectorOps<v4f32, v4i32>; 382defm : GenericVectorOps<v2f64, v2i64>; 383 384//===----------------------------------------------------------------------===// 385// Integer arithmetic 386//===----------------------------------------------------------------------===// 387 388let Predicates = [FeatureVector] in { 389 // Add. 390 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 391 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 392 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 393 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 394 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 395 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>; 396 397 // Add compute carry. 398 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 399 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>; 400 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>; 401 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>; 402 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>; 403 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>; 404 405 // Add with carry. 406 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 407 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>; 408 409 // Add with carry compute carry. 410 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 411 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>; 412 413 // And. 414 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 415 416 // And with complement. 417 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 418 419 // Average. 420 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 421 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 422 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 423 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 424 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 425 426 // Average logical. 427 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 428 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 429 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 430 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 431 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 432 433 // Checksum. 434 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 435 436 // Count leading zeros. 437 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 438 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 439 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 440 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 441 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 442 443 // Count trailing zeros. 444 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 445 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 446 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 447 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 448 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 449 450 // Not exclusive or. 451 let Predicates = [FeatureVectorEnhancements1] in 452 def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>; 453 454 // Exclusive or. 455 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 456 457 // Galois field multiply sum. 458 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 459 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 460 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 461 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 462 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 463 464 // Galois field multiply sum and accumulate. 465 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 466 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 467 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 468 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 469 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 470 471 // Load complement. 472 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 473 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 474 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 475 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 476 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 477 478 // Load positive. 479 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 480 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>; 481 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>; 482 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>; 483 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>; 484 485 // Maximum. 486 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 487 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 488 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 489 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 490 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 491 492 // Maximum logical. 493 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 494 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 495 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 496 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 497 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 498 499 // Minimum. 500 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 501 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 502 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 503 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 504 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 505 506 // Minimum logical. 507 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 508 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 509 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 510 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 511 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 512 513 // Multiply and add low. 514 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 515 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 516 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 517 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 518 519 // Multiply and add high. 520 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 521 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 522 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 523 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 524 525 // Multiply and add logical high. 526 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 527 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 528 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 529 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 530 531 // Multiply and add even. 532 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 533 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 534 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 535 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 536 537 // Multiply and add logical even. 538 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 539 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 540 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 541 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 542 543 // Multiply and add odd. 544 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 545 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 546 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 547 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 548 549 // Multiply and add logical odd. 550 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 551 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 552 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 553 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 554 555 // Multiply high. 556 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 557 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 558 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 559 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 560 561 // Multiply logical high. 562 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 563 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 564 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 565 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 566 567 // Multiply low. 568 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 569 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 570 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 571 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 572 573 // Multiply even. 574 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 575 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 576 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 577 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 578 579 // Multiply logical even. 580 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 581 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 582 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 583 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 584 585 // Multiply odd. 586 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 587 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 588 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 589 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 590 591 // Multiply logical odd. 592 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 593 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 594 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 595 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 596 597 // Multiply sum logical. 598 let Predicates = [FeatureVectorEnhancements1] in { 599 def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>; 600 def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg, 601 v128q, v128g, v128g, v128q, 3>; 602 } 603 604 // Nand. 605 let Predicates = [FeatureVectorEnhancements1] in 606 def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>; 607 608 // Nor. 609 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 610 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 611 612 // Or. 613 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 614 615 // Or with complement. 616 let Predicates = [FeatureVectorEnhancements1] in 617 def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>; 618 619 // Population count. 620 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 621 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 622 let Predicates = [FeatureVectorEnhancements1] in { 623 def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>; 624 def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>; 625 def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>; 626 def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>; 627 } 628 629 // Element rotate left logical (with vector shift amount). 630 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 631 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb, 632 v128b, v128b, 0>; 633 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh, 634 v128h, v128h, 1>; 635 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf, 636 v128f, v128f, 2>; 637 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg, 638 v128g, v128g, 3>; 639 640 // Element rotate left logical (with scalar shift amount). 641 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 642 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>; 643 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>; 644 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>; 645 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>; 646 647 // Element rotate and insert under mask. 648 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 649 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 650 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 651 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 652 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 653 654 // Element shift left (with vector shift amount). 655 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 656 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 657 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 658 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 659 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 660 661 // Element shift left (with scalar shift amount). 662 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 663 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 664 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 665 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 666 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 667 668 // Element shift right arithmetic (with vector shift amount). 669 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 670 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 671 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 672 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 673 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 674 675 // Element shift right arithmetic (with scalar shift amount). 676 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 677 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 678 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 679 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 680 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 681 682 // Element shift right logical (with vector shift amount). 683 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 684 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 685 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 686 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 687 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 688 689 // Element shift right logical (with scalar shift amount). 690 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 691 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 692 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 693 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 694 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 695 696 // Shift left. 697 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 698 699 // Shift left by byte. 700 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 701 702 // Shift left double by byte. 703 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 704 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8:$z), 705 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 706 707 // Shift right arithmetic. 708 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 709 710 // Shift right arithmetic by byte. 711 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 712 713 // Shift right logical. 714 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 715 716 // Shift right logical by byte. 717 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 718 719 // Subtract. 720 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 721 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 722 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 723 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 724 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 725 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>; 726 727 // Subtract compute borrow indication. 728 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 729 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>; 730 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>; 731 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>; 732 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>; 733 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>; 734 735 // Subtract with borrow indication. 736 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 737 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>; 738 739 // Subtract with borrow compute borrow indication. 740 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 741 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq, 742 v128q, v128q, 4>; 743 744 // Sum across doubleword. 745 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 746 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 747 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 748 749 // Sum across quadword. 750 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 751 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 752 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 753 754 // Sum across word. 755 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 756 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 757 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 758} 759 760// Instantiate the bitwise ops for type TYPE. 761multiclass BitwiseVectorOps<ValueType type> { 762 let Predicates = [FeatureVector] in { 763 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 764 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))), 765 (VNC VR128:$x, VR128:$y)>; 766 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 767 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 768 def : Pat<(type (or (and VR128:$x, VR128:$z), 769 (and VR128:$y, (z_vnot VR128:$z)))), 770 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 771 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))), 772 (VNO VR128:$x, VR128:$y)>; 773 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; 774 } 775 let Predicates = [FeatureVectorEnhancements1] in { 776 def : Pat<(type (z_vnot (xor VR128:$x, VR128:$y))), 777 (VNX VR128:$x, VR128:$y)>; 778 def : Pat<(type (z_vnot (and VR128:$x, VR128:$y))), 779 (VNN VR128:$x, VR128:$y)>; 780 def : Pat<(type (or VR128:$x, (z_vnot VR128:$y))), 781 (VOC VR128:$x, VR128:$y)>; 782 } 783} 784 785defm : BitwiseVectorOps<v16i8>; 786defm : BitwiseVectorOps<v8i16>; 787defm : BitwiseVectorOps<v4i32>; 788defm : BitwiseVectorOps<v2i64>; 789 790// Instantiate additional patterns for absolute-related expressions on 791// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 792// instruction. 793multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 794 Instruction lp, int shift> { 795 let Predicates = [FeatureVector] in { 796 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 797 (z_vneg VR128:$x), VR128:$x)), 798 (lc (lp VR128:$x))>; 799 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 800 VR128:$x, (z_vneg VR128:$x))), 801 (lc (lp VR128:$x))>; 802 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 803 VR128:$x, (z_vneg VR128:$x))), 804 (lc (lp VR128:$x))>; 805 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 806 (z_vneg VR128:$x), VR128:$x)), 807 (lc (lp VR128:$x))>; 808 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 809 (z_vneg VR128:$x)), 810 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 811 VR128:$x))), 812 (lp VR128:$x)>; 813 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 814 VR128:$x), 815 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 816 (z_vneg VR128:$x)))), 817 (lc (lp VR128:$x))>; 818 } 819} 820 821defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 822defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 823defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 824defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 825 826// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 827// signed or unsigned "set if greater than" comparison instruction and 828// MIN and MAX are the associated minimum and maximum instructions. 829multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 830 Instruction min, Instruction max> { 831 let Predicates = [FeatureVector] in { 832 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 833 (max VR128:$x, VR128:$y)>; 834 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 835 (min VR128:$x, VR128:$y)>; 836 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 837 VR128:$x, VR128:$y)), 838 (min VR128:$x, VR128:$y)>; 839 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 840 VR128:$y, VR128:$x)), 841 (max VR128:$x, VR128:$y)>; 842 } 843} 844 845// Signed min/max. 846defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 847defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 848defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 849defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 850 851// Unsigned min/max. 852defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 853defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 854defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 855defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 856 857//===----------------------------------------------------------------------===// 858// Integer comparison 859//===----------------------------------------------------------------------===// 860 861let Predicates = [FeatureVector] in { 862 // Element compare. 863 let Defs = [CC] in { 864 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 865 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 866 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 867 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 868 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 869 } 870 871 // Element compare logical. 872 let Defs = [CC] in { 873 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 874 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 875 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 876 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 877 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 878 } 879 880 // Compare equal. 881 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 882 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 883 v128b, v128b, 0>; 884 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 885 v128h, v128h, 1>; 886 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 887 v128f, v128f, 2>; 888 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 889 v128g, v128g, 3>; 890 891 // Compare high. 892 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 893 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 894 v128b, v128b, 0>; 895 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 896 v128h, v128h, 1>; 897 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 898 v128f, v128f, 2>; 899 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 900 v128g, v128g, 3>; 901 902 // Compare high logical. 903 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 904 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 905 v128b, v128b, 0>; 906 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 907 v128h, v128h, 1>; 908 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 909 v128f, v128f, 2>; 910 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 911 v128g, v128g, 3>; 912 913 // Test under mask. 914 let Defs = [CC] in 915 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 916} 917 918//===----------------------------------------------------------------------===// 919// Floating-point arithmetic 920//===----------------------------------------------------------------------===// 921 922// See comments in SystemZInstrFP.td for the suppression flags and 923// rounding modes. 924multiclass VectorRounding<Instruction insn, TypedReg tr> { 925 def : FPConversion<insn, frint, tr, tr, 0, 0>; 926 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>; 927 def : FPConversion<insn, ffloor, tr, tr, 4, 7>; 928 def : FPConversion<insn, fceil, tr, tr, 4, 6>; 929 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>; 930 def : FPConversion<insn, fround, tr, tr, 4, 1>; 931} 932 933let Predicates = [FeatureVector] in { 934 // Add. 935 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 936 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>; 937 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, fadd, v64db, v64db, 3, 8>; 938 let Predicates = [FeatureVectorEnhancements1] in { 939 def VFASB : BinaryVRRc<"vfasb", 0xE7E3, fadd, v128sb, v128sb, 2, 0>; 940 def WFASB : BinaryVRRc<"wfasb", 0xE7E3, fadd, v32sb, v32sb, 2, 8>; 941 def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, fadd, v128xb, v128xb, 4, 8>; 942 } 943 944 // Convert from fixed 64-bit. 945 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 946 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 947 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 948 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>; 949 950 // Convert from logical 64-bit. 951 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 952 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 953 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 954 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>; 955 956 // Convert to fixed 64-bit. 957 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 958 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 959 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 960 // Rounding mode should agree with SystemZInstrFP.td. 961 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>; 962 963 // Convert to logical 64-bit. 964 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 965 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 966 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 967 // Rounding mode should agree with SystemZInstrFP.td. 968 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>; 969 970 // Divide. 971 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 972 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>; 973 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, fdiv, v64db, v64db, 3, 8>; 974 let Predicates = [FeatureVectorEnhancements1] in { 975 def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, fdiv, v128sb, v128sb, 2, 0>; 976 def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, fdiv, v32sb, v32sb, 2, 8>; 977 def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, fdiv, v128xb, v128xb, 4, 8>; 978 } 979 980 // Load FP integer. 981 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 982 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 983 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 984 defm : VectorRounding<VFIDB, v128db>; 985 defm : VectorRounding<WFIDB, v64db>; 986 let Predicates = [FeatureVectorEnhancements1] in { 987 def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>; 988 def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>; 989 def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>; 990 defm : VectorRounding<VFISB, v128sb>; 991 defm : VectorRounding<WFISB, v32sb>; 992 defm : VectorRounding<WFIXB, v128xb>; 993 } 994 995 // Load lengthened. 996 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 997 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128sb, 2, 0>; 998 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, fpextend, v64db, v32sb, 2, 8>; 999 let Predicates = [FeatureVectorEnhancements1] in { 1000 let isAsmParserOnly = 1 in { 1001 def VFLL : UnaryVRRaFloatGeneric<"vfll", 0xE7C4>; 1002 def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>; 1003 def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>; 1004 } 1005 def WFLLD : UnaryVRRa<"wflld", 0xE7C4, fpextend, v128xb, v64db, 3, 8>; 1006 def : Pat<(f128 (fpextend (f32 VR32:$src))), 1007 (WFLLD (WLDEB VR32:$src))>; 1008 } 1009 1010 // Load rounded. 1011 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 1012 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1013 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1014 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 1015 def : FPConversion<WLEDB, fpround, v32sb, v64db, 0, 0>; 1016 let Predicates = [FeatureVectorEnhancements1] in { 1017 let isAsmParserOnly = 1 in { 1018 def VFLR : TernaryVRRaFloatGeneric<"vflr", 0xE7C5>; 1019 def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1020 def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1021 } 1022 def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>; 1023 def : FPConversion<WFLRX, fpround, v64db, v128xb, 0, 0>; 1024 def : Pat<(f32 (fpround (f128 VR128:$src))), 1025 (WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>; 1026 } 1027 1028 // Maximum. 1029 multiclass VectorMax<Instruction insn, TypedReg tr> { 1030 def : FPMinMax<insn, fmaxnum, tr, 4>; 1031 def : FPMinMax<insn, fmaxnan, tr, 1>; 1032 } 1033 let Predicates = [FeatureVectorEnhancements1] in { 1034 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; 1035 def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb, 1036 v128db, v128db, 3, 0>; 1037 def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag, 1038 v64db, v64db, 3, 8>; 1039 def VFMAXSB : TernaryVRRcFloat<"vfmaxsb", 0xE7EF, int_s390_vfmaxsb, 1040 v128sb, v128sb, 2, 0>; 1041 def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag, 1042 v32sb, v32sb, 2, 8>; 1043 def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag, 1044 v128xb, v128xb, 4, 8>; 1045 defm : VectorMax<VFMAXDB, v128db>; 1046 defm : VectorMax<WFMAXDB, v64db>; 1047 defm : VectorMax<VFMAXSB, v128sb>; 1048 defm : VectorMax<WFMAXSB, v32sb>; 1049 defm : VectorMax<WFMAXXB, v128xb>; 1050 } 1051 1052 // Minimum. 1053 multiclass VectorMin<Instruction insn, TypedReg tr> { 1054 def : FPMinMax<insn, fminnum, tr, 4>; 1055 def : FPMinMax<insn, fminnan, tr, 1>; 1056 } 1057 let Predicates = [FeatureVectorEnhancements1] in { 1058 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; 1059 def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb, 1060 v128db, v128db, 3, 0>; 1061 def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag, 1062 v64db, v64db, 3, 8>; 1063 def VFMINSB : TernaryVRRcFloat<"vfminsb", 0xE7EE, int_s390_vfminsb, 1064 v128sb, v128sb, 2, 0>; 1065 def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag, 1066 v32sb, v32sb, 2, 8>; 1067 def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag, 1068 v128xb, v128xb, 4, 8>; 1069 defm : VectorMin<VFMINDB, v128db>; 1070 defm : VectorMin<WFMINDB, v64db>; 1071 defm : VectorMin<VFMINSB, v128sb>; 1072 defm : VectorMin<WFMINSB, v32sb>; 1073 defm : VectorMin<WFMINXB, v128xb>; 1074 } 1075 1076 // Multiply. 1077 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 1078 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>; 1079 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, fmul, v64db, v64db, 3, 8>; 1080 let Predicates = [FeatureVectorEnhancements1] in { 1081 def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, fmul, v128sb, v128sb, 2, 0>; 1082 def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, fmul, v32sb, v32sb, 2, 8>; 1083 def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, fmul, v128xb, v128xb, 4, 8>; 1084 } 1085 1086 // Multiply and add. 1087 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 1088 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>; 1089 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, fma, v64db, v64db, 8, 3>; 1090 let Predicates = [FeatureVectorEnhancements1] in { 1091 def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, fma, v128sb, v128sb, 0, 2>; 1092 def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, fma, v32sb, v32sb, 8, 2>; 1093 def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, fma, v128xb, v128xb, 8, 4>; 1094 } 1095 1096 // Multiply and subtract. 1097 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 1098 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>; 1099 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>; 1100 let Predicates = [FeatureVectorEnhancements1] in { 1101 def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, fms, v128sb, v128sb, 0, 2>; 1102 def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, fms, v32sb, v32sb, 8, 2>; 1103 def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, fms, v128xb, v128xb, 8, 4>; 1104 } 1105 1106 // Negative multiply and add. 1107 let Predicates = [FeatureVectorEnhancements1] in { 1108 def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>; 1109 def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, fnma, v128db, v128db, 0, 3>; 1110 def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, fnma, v64db, v64db, 8, 3>; 1111 def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, fnma, v128sb, v128sb, 0, 2>; 1112 def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, fnma, v32sb, v32sb, 8, 2>; 1113 def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, fnma, v128xb, v128xb, 8, 4>; 1114 } 1115 1116 // Negative multiply and subtract. 1117 let Predicates = [FeatureVectorEnhancements1] in { 1118 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>; 1119 def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, fnms, v128db, v128db, 0, 3>; 1120 def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, fnms, v64db, v64db, 8, 3>; 1121 def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, fnms, v128sb, v128sb, 0, 2>; 1122 def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, fnms, v32sb, v32sb, 8, 2>; 1123 def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, fnms, v128xb, v128xb, 8, 4>; 1124 } 1125 1126 // Perform sign operation. 1127 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 1128 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 1129 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 1130 let Predicates = [FeatureVectorEnhancements1] in { 1131 def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>; 1132 def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>; 1133 def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>; 1134 } 1135 1136 // Load complement. 1137 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 1138 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 1139 let Predicates = [FeatureVectorEnhancements1] in { 1140 def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>; 1141 def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>; 1142 def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>; 1143 } 1144 1145 // Load negative. 1146 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 1147 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 1148 let Predicates = [FeatureVectorEnhancements1] in { 1149 def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>; 1150 def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>; 1151 def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>; 1152 } 1153 1154 // Load positive. 1155 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 1156 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 1157 let Predicates = [FeatureVectorEnhancements1] in { 1158 def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>; 1159 def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>; 1160 def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>; 1161 } 1162 1163 // Square root. 1164 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 1165 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>; 1166 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, fsqrt, v64db, v64db, 3, 8>; 1167 let Predicates = [FeatureVectorEnhancements1] in { 1168 def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, fsqrt, v128sb, v128sb, 2, 0>; 1169 def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, fsqrt, v32sb, v32sb, 2, 8>; 1170 def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, fsqrt, v128xb, v128xb, 4, 8>; 1171 } 1172 1173 // Subtract. 1174 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 1175 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>; 1176 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, fsub, v64db, v64db, 3, 8>; 1177 let Predicates = [FeatureVectorEnhancements1] in { 1178 def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, fsub, v128sb, v128sb, 2, 0>; 1179 def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, fsub, v32sb, v32sb, 2, 8>; 1180 def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, fsub, v128xb, v128xb, 4, 8>; 1181 } 1182 1183 // Test data class immediate. 1184 let Defs = [CC] in { 1185 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 1186 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 1187 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 1188 let Predicates = [FeatureVectorEnhancements1] in { 1189 def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>; 1190 def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>; 1191 def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>; 1192 } 1193 } 1194} 1195 1196//===----------------------------------------------------------------------===// 1197// Floating-point comparison 1198//===----------------------------------------------------------------------===// 1199 1200let Predicates = [FeatureVector] in { 1201 // Compare scalar. 1202 let Defs = [CC] in { 1203 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 1204 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>; 1205 let Predicates = [FeatureVectorEnhancements1] in { 1206 def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_fcmp, v32sb, 2>; 1207 def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_fcmp, v128xb, 4>; 1208 } 1209 } 1210 1211 // Compare and signal scalar. 1212 let Defs = [CC] in { 1213 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 1214 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>; 1215 let Predicates = [FeatureVectorEnhancements1] in { 1216 def WFKSB : CompareVRRa<"wfksb", 0xE7CA, null_frag, v32sb, 2>; 1217 def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, null_frag, v128xb, 4>; 1218 } 1219 } 1220 1221 // Compare equal. 1222 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 1223 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1224 v128g, v128db, 3, 0>; 1225 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1226 v64g, v64db, 3, 8>; 1227 let Predicates = [FeatureVectorEnhancements1] in { 1228 defm VFCESB : BinaryVRRcSPair<"vfcesb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1229 v128f, v128sb, 2, 0>; 1230 defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag, 1231 v32f, v32sb, 2, 8>; 1232 defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag, 1233 v128q, v128xb, 4, 8>; 1234 } 1235 1236 // Compare and signal equal. 1237 let Predicates = [FeatureVectorEnhancements1] in { 1238 defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, null_frag, null_frag, 1239 v128g, v128db, 3, 4>; 1240 defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag, 1241 v64g, v64db, 3, 12>; 1242 defm VFKESB : BinaryVRRcSPair<"vfkesb", 0xE7E8, null_frag, null_frag, 1243 v128f, v128sb, 2, 4>; 1244 defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag, 1245 v32f, v32sb, 2, 12>; 1246 defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag, 1247 v128q, v128xb, 4, 12>; 1248 } 1249 1250 // Compare high. 1251 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1252 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs, 1253 v128g, v128db, 3, 0>; 1254 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1255 v64g, v64db, 3, 8>; 1256 let Predicates = [FeatureVectorEnhancements1] in { 1257 defm VFCHSB : BinaryVRRcSPair<"vfchsb", 0xE7EB, z_vfcmph, z_vfcmphs, 1258 v128f, v128sb, 2, 0>; 1259 defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag, 1260 v32f, v32sb, 2, 8>; 1261 defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag, 1262 v128q, v128xb, 4, 8>; 1263 } 1264 1265 // Compare and signal high. 1266 let Predicates = [FeatureVectorEnhancements1] in { 1267 defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, null_frag, null_frag, 1268 v128g, v128db, 3, 4>; 1269 defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag, 1270 v64g, v64db, 3, 12>; 1271 defm VFKHSB : BinaryVRRcSPair<"vfkhsb", 0xE7EB, null_frag, null_frag, 1272 v128f, v128sb, 2, 4>; 1273 defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag, 1274 v32f, v32sb, 2, 12>; 1275 defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag, 1276 v128q, v128xb, 4, 12>; 1277 } 1278 1279 // Compare high or equal. 1280 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1281 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1282 v128g, v128db, 3, 0>; 1283 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1284 v64g, v64db, 3, 8>; 1285 let Predicates = [FeatureVectorEnhancements1] in { 1286 defm VFCHESB : BinaryVRRcSPair<"vfchesb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1287 v128f, v128sb, 2, 0>; 1288 defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag, 1289 v32f, v32sb, 2, 8>; 1290 defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag, 1291 v128q, v128xb, 4, 8>; 1292 } 1293 1294 // Compare and signal high or equal. 1295 let Predicates = [FeatureVectorEnhancements1] in { 1296 defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, null_frag, null_frag, 1297 v128g, v128db, 3, 4>; 1298 defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag, 1299 v64g, v64db, 3, 12>; 1300 defm VFKHESB : BinaryVRRcSPair<"vfkhesb", 0xE7EA, null_frag, null_frag, 1301 v128f, v128sb, 2, 4>; 1302 defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag, 1303 v32f, v32sb, 2, 12>; 1304 defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag, 1305 v128q, v128xb, 4, 12>; 1306 } 1307} 1308 1309//===----------------------------------------------------------------------===// 1310// Conversions 1311//===----------------------------------------------------------------------===// 1312 1313def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 1314def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 1315def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 1316def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 1317def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 1318def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>; 1319 1320def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 1321def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 1322def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 1323def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 1324def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 1325def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>; 1326 1327def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 1328def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 1329def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 1330def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 1331def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 1332def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>; 1333 1334def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 1335def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 1336def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 1337def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 1338def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 1339def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>; 1340 1341def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 1342def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 1343def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 1344def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 1345def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 1346def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>; 1347 1348def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 1349def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 1350def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 1351def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 1352def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 1353def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>; 1354 1355def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>; 1356def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>; 1357def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>; 1358def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>; 1359def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>; 1360def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>; 1361 1362//===----------------------------------------------------------------------===// 1363// Replicating scalars 1364//===----------------------------------------------------------------------===// 1365 1366// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 1367// INDEX is 8 minus the element size in bytes. 1368class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 1369 : Pat<(type (z_replicate GR32:$scalar)), 1370 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 1371 1372def : VectorReplicateScalar<v16i8, VREPB, 7>; 1373def : VectorReplicateScalar<v8i16, VREPH, 3>; 1374def : VectorReplicateScalar<v4i32, VREPF, 1>; 1375 1376// i64 replications are just a single isntruction. 1377def : Pat<(v2i64 (z_replicate GR64:$scalar)), 1378 (VLVGP GR64:$scalar, GR64:$scalar)>; 1379 1380//===----------------------------------------------------------------------===// 1381// Floating-point insertion and extraction 1382//===----------------------------------------------------------------------===// 1383 1384// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 1385// and VLGVF. 1386let Predicates = [FeatureVector] in { 1387 def LEFR : UnaryAliasVRS<VR32, GR32>; 1388 def LFER : UnaryAliasVRS<GR64, VR32>; 1389 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 1390 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 1391 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 1392} 1393 1394// Floating-point values are stored in element 0 of the corresponding 1395// vector register. Scalar to vector conversion is just a subreg and 1396// scalar replication can just replicate element 0 of the vector register. 1397multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 1398 SubRegIndex subreg> { 1399 def : Pat<(vt (scalar_to_vector cls:$scalar)), 1400 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 1401 def : Pat<(vt (z_replicate cls:$scalar)), 1402 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 1403 subreg), 0)>; 1404} 1405defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_r32>; 1406defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>; 1407 1408// Match v2f64 insertions. The AddedComplexity counters the 3 added by 1409// TableGen for the base register operand in VLVG-based integer insertions 1410// and ensures that this version is strictly better. 1411let AddedComplexity = 4 in { 1412 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 1413 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1414 subreg_r64), VR128:$vec, 1)>; 1415 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 1416 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1417 subreg_r64), 0)>; 1418} 1419 1420// We extract floating-point element X by replicating (for elements other 1421// than 0) and then taking a high subreg. The AddedComplexity counters the 1422// 3 added by TableGen for the base register operand in VLGV-based integer 1423// extractions and ensures that this version is strictly better. 1424let AddedComplexity = 4 in { 1425 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 1426 (EXTRACT_SUBREG VR128:$vec, subreg_r32)>; 1427 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 1428 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_r32)>; 1429 1430 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 1431 (EXTRACT_SUBREG VR128:$vec, subreg_r64)>; 1432 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 1433 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>; 1434} 1435 1436//===----------------------------------------------------------------------===// 1437// Support for 128-bit floating-point values in vector registers 1438//===----------------------------------------------------------------------===// 1439 1440let Predicates = [FeatureVectorEnhancements1] in { 1441 def : Pat<(f128 (load bdxaddr12only:$addr)), 1442 (VL bdxaddr12only:$addr)>; 1443 def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr), 1444 (VST VR128:$src, bdxaddr12only:$addr)>; 1445 1446 def : Pat<(f128 fpimm0), (VZERO)>; 1447 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>; 1448} 1449 1450//===----------------------------------------------------------------------===// 1451// String instructions 1452//===----------------------------------------------------------------------===// 1453 1454let Predicates = [FeatureVector] in { 1455 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 1456 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 1457 z_vfae_cc, v128b, v128b, 0>; 1458 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 1459 z_vfae_cc, v128h, v128h, 1>; 1460 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 1461 z_vfae_cc, v128f, v128f, 2>; 1462 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 1463 z_vfaez_cc, v128b, v128b, 0, 2>; 1464 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 1465 z_vfaez_cc, v128h, v128h, 1, 2>; 1466 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 1467 z_vfaez_cc, v128f, v128f, 2, 2>; 1468 1469 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 1470 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 1471 z_vfee_cc, v128b, v128b, 0>; 1472 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 1473 z_vfee_cc, v128h, v128h, 1>; 1474 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 1475 z_vfee_cc, v128f, v128f, 2>; 1476 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 1477 z_vfeez_cc, v128b, v128b, 0, 2>; 1478 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 1479 z_vfeez_cc, v128h, v128h, 1, 2>; 1480 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 1481 z_vfeez_cc, v128f, v128f, 2, 2>; 1482 1483 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 1484 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 1485 z_vfene_cc, v128b, v128b, 0>; 1486 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 1487 z_vfene_cc, v128h, v128h, 1>; 1488 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 1489 z_vfene_cc, v128f, v128f, 2>; 1490 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 1491 z_vfenez_cc, v128b, v128b, 0, 2>; 1492 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 1493 z_vfenez_cc, v128h, v128h, 1, 2>; 1494 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 1495 z_vfenez_cc, v128f, v128f, 2, 2>; 1496 1497 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 1498 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 1499 z_vistr_cc, v128b, v128b, 0>; 1500 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 1501 z_vistr_cc, v128h, v128h, 1>; 1502 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 1503 z_vistr_cc, v128f, v128f, 2>; 1504 1505 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 1506 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 1507 z_vstrc_cc, v128b, v128b, 0>; 1508 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 1509 z_vstrc_cc, v128h, v128h, 1>; 1510 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 1511 z_vstrc_cc, v128f, v128f, 2>; 1512 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 1513 z_vstrcz_cc, v128b, v128b, 0, 2>; 1514 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 1515 z_vstrcz_cc, v128h, v128h, 1, 2>; 1516 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 1517 z_vstrcz_cc, v128f, v128f, 2, 2>; 1518} 1519 1520//===----------------------------------------------------------------------===// 1521// Packed-decimal instructions 1522//===----------------------------------------------------------------------===// 1523 1524let Predicates = [FeatureVectorPackedDecimal] in { 1525 def VLIP : BinaryVRIh<"vlip", 0xE649>; 1526 1527 def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>; 1528 def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>; 1529 1530 let Defs = [CC] in { 1531 def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>; 1532 def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>; 1533 def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>; 1534 def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>; 1535 1536 def VAP : QuaternaryVRIf<"vap", 0xE671>; 1537 def VSP : QuaternaryVRIf<"vsp", 0xE673>; 1538 1539 def VMP : QuaternaryVRIf<"vmp", 0xE678>; 1540 def VMSP : QuaternaryVRIf<"vmsp", 0xE679>; 1541 1542 def VDP : QuaternaryVRIf<"vdp", 0xE67A>; 1543 def VRP : QuaternaryVRIf<"vrp", 0xE67B>; 1544 def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>; 1545 1546 def VSRP : QuaternaryVRIg<"vsrp", 0xE659>; 1547 def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>; 1548 1549 def VTP : TestVRRg<"vtp", 0xE65F>; 1550 def VCP : CompareVRRh<"vcp", 0xE677>; 1551 } 1552} 1553