1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Move instructions 11//===----------------------------------------------------------------------===// 12 13let Predicates = [FeatureVector] in { 14 // Register move. 15 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 16 def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>; 17 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 18 19 // Load GR from VR element. 20 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 21 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 22 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 23 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 24 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 25 26 // Load VR element from GR. 27 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 28 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 29 v128b, v128b, GR32, 0>; 30 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 31 v128h, v128h, GR32, 1>; 32 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 33 v128f, v128f, GR32, 2>; 34 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 35 v128g, v128g, GR64, 3>; 36 37 // Load VR from GRs disjoint. 38 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 39 def VLVGP32 : BinaryAliasVRRf<GR32>; 40} 41 42// Extractions always assign to the full GR64, even if the element would 43// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 44// subreg of the result. 45class VectorExtractSubreg<ValueType type, Instruction insn> 46 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 47 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 48 49def : VectorExtractSubreg<v16i8, VLGVB>; 50def : VectorExtractSubreg<v8i16, VLGVH>; 51def : VectorExtractSubreg<v4i32, VLGVF>; 52 53//===----------------------------------------------------------------------===// 54// Immediate instructions 55//===----------------------------------------------------------------------===// 56 57let Predicates = [FeatureVector] in { 58 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 59 60 // Generate byte mask. 61 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 62 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 63 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; 64 65 // Generate mask. 66 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 67 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 68 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 69 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 70 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 71 72 // Replicate immediate. 73 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 74 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; 75 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; 76 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; 77 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; 78 } 79 80 // Load element immediate. 81 // 82 // We want these instructions to be used ahead of VLVG* where possible. 83 // However, VLVG* takes a variable BD-format index whereas VLEI takes 84 // a plain immediate index. This means that VLVG* has an extra "base" 85 // register operand and is 3 units more complex. Bumping the complexity 86 // of the VLEI* instructions by 4 means that they are strictly better 87 // than VLVG* in cases where both forms match. 88 let AddedComplexity = 4 in { 89 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 90 v128b, v128b, imm32sx16trunc, imm32zx4>; 91 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 92 v128h, v128h, imm32sx16trunc, imm32zx3>; 93 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 94 v128f, v128f, imm32sx16, imm32zx2>; 95 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 96 v128g, v128g, imm64sx16, imm32zx1>; 97 } 98} 99 100//===----------------------------------------------------------------------===// 101// Loads 102//===----------------------------------------------------------------------===// 103 104let Predicates = [FeatureVector] in { 105 // Load. 106 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>; 107 108 // Load to block boundary. The number of loaded bytes is only known 109 // at run time. The instruction is really polymorphic, but v128b matches 110 // the return type of the associated intrinsic. 111 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 112 113 // Load count to block boundary. 114 let Defs = [CC] in 115 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 116 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 117 "lcbb\t$R1, $XBD2, $M3", 118 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 119 imm32zx4:$M3))]>; 120 121 // Load with length. The number of loaded bytes is only known at run time. 122 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 123 124 // Load multiple. 125 def VLM : LoadMultipleVRSa<"vlm", 0xE736>; 126 127 // Load and replicate 128 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 129 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 130 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 131 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 132 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 133 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 134 (VLREPF bdxaddr12only:$addr)>; 135 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 136 (VLREPG bdxaddr12only:$addr)>; 137 138 // Use VLREP to load subvectors. These patterns use "12pair" because 139 // LEY and LDY offer full 20-bit displacement fields. It's often better 140 // to use those instructions rather than force a 20-bit displacement 141 // into a GPR temporary. 142 let mayLoad = 1 in { 143 def VL32 : UnaryAliasVRX<load, v32sb, bdxaddr12pair>; 144 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>; 145 } 146 147 // Load logical element and zero. 148 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 149 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 150 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 151 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 152 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 153 def : Pat<(z_vllezf32 bdxaddr12only:$addr), 154 (VLLEZF bdxaddr12only:$addr)>; 155 def : Pat<(z_vllezf64 bdxaddr12only:$addr), 156 (VLLEZG bdxaddr12only:$addr)>; 157 let Predicates = [FeatureVectorEnhancements1] in { 158 def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>; 159 def : Pat<(z_vllezlf32 bdxaddr12only:$addr), 160 (VLLEZLF bdxaddr12only:$addr)>; 161 } 162 163 // Load element. 164 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 165 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 166 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 167 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 168 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 169 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 170 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 171 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 172 173 // Gather element. 174 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 175 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 176} 177 178let Predicates = [FeatureVectorPackedDecimal] in { 179 // Load rightmost with length. The number of loaded bytes is only known 180 // at run time. 181 def VLRL : BinaryVSI<"vlrl", 0xE635, int_s390_vlrl, 0>; 182 def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>; 183} 184 185// Use replicating loads if we're inserting a single element into an 186// undefined vector. This avoids a false dependency on the previous 187// register contents. 188multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 189 SDPatternOperator load, ValueType scalartype> { 190 def : Pat<(vectype (z_vector_insert 191 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 192 (vlrep bdxaddr12only:$addr)>; 193 def : Pat<(vectype (scalar_to_vector 194 (scalartype (load bdxaddr12only:$addr)))), 195 (vlrep bdxaddr12only:$addr)>; 196} 197defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>; 198defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>; 199defm : ReplicatePeephole<VLREPF, v4i32, load, i32>; 200defm : ReplicatePeephole<VLREPG, v2i64, load, i64>; 201defm : ReplicatePeephole<VLREPF, v4f32, load, f32>; 202defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 203 204//===----------------------------------------------------------------------===// 205// Stores 206//===----------------------------------------------------------------------===// 207 208let Predicates = [FeatureVector] in { 209 // Store. 210 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>; 211 212 // Store with length. The number of stored bytes is only known at run time. 213 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 214 215 // Store multiple. 216 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>; 217 218 // Store element. 219 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 220 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 221 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 222 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 223 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 224 imm32zx2:$index), 225 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 226 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 227 imm32zx1:$index), 228 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 229 230 // Use VSTE to store subvectors. These patterns use "12pair" because 231 // STEY and STDY offer full 20-bit displacement fields. It's often better 232 // to use those instructions rather than force a 20-bit displacement 233 // into a GPR temporary. 234 let mayStore = 1 in { 235 def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>; 236 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 237 } 238 239 // Scatter element. 240 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 241 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 242} 243 244let Predicates = [FeatureVectorPackedDecimal] in { 245 // Store rightmost with length. The number of stored bytes is only known 246 // at run time. 247 def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, int_s390_vstrl, 0>; 248 def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>; 249} 250 251//===----------------------------------------------------------------------===// 252// Selects and permutes 253//===----------------------------------------------------------------------===// 254 255let Predicates = [FeatureVector] in { 256 // Merge high. 257 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 258 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 259 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 260 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 261 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 262 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 263 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 264 265 // Merge low. 266 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 267 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 268 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 269 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 270 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 271 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 272 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 273 274 // Permute. 275 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 276 277 // Permute doubleword immediate. 278 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 279 280 // Bit Permute. 281 let Predicates = [FeatureVectorEnhancements1] in 282 def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>; 283 284 // Replicate. 285 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 286 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 287 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 288 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 289 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 290 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)), 291 (VREPF VR128:$vec, imm32zx16:$index)>; 292 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)), 293 (VREPG VR128:$vec, imm32zx16:$index)>; 294 295 // Select. 296 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 297} 298 299//===----------------------------------------------------------------------===// 300// Widening and narrowing 301//===----------------------------------------------------------------------===// 302 303let Predicates = [FeatureVector] in { 304 // Pack 305 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 306 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 307 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 308 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 309 310 // Pack saturate. 311 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 312 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 313 v128b, v128h, 1>; 314 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 315 v128h, v128f, 2>; 316 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 317 v128f, v128g, 3>; 318 319 // Pack saturate logical. 320 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 321 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 322 v128b, v128h, 1>; 323 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 324 v128h, v128f, 2>; 325 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 326 v128f, v128g, 3>; 327 328 // Sign-extend to doubleword. 329 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 330 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 331 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 332 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 333 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 334 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 335 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 336 337 // Unpack high. 338 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 339 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 340 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 341 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 342 343 // Unpack logical high. 344 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 345 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 346 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 347 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 348 349 // Unpack low. 350 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 351 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 352 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 353 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 354 355 // Unpack logical low. 356 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 357 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 358 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 359 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 360} 361 362//===----------------------------------------------------------------------===// 363// Instantiating generic operations for specific types. 364//===----------------------------------------------------------------------===// 365 366multiclass GenericVectorOps<ValueType type, ValueType inttype> { 367 let Predicates = [FeatureVector] in { 368 def : Pat<(type (load bdxaddr12only:$addr)), 369 (VL bdxaddr12only:$addr)>; 370 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 371 (VST VR128:$src, bdxaddr12only:$addr)>; 372 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 373 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 374 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 375 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 376 } 377} 378 379defm : GenericVectorOps<v16i8, v16i8>; 380defm : GenericVectorOps<v8i16, v8i16>; 381defm : GenericVectorOps<v4i32, v4i32>; 382defm : GenericVectorOps<v2i64, v2i64>; 383defm : GenericVectorOps<v4f32, v4i32>; 384defm : GenericVectorOps<v2f64, v2i64>; 385 386//===----------------------------------------------------------------------===// 387// Integer arithmetic 388//===----------------------------------------------------------------------===// 389 390let Predicates = [FeatureVector] in { 391 // Add. 392 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 393 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 394 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 395 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 396 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 397 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>; 398 399 // Add compute carry. 400 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 401 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>; 402 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>; 403 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>; 404 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>; 405 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>; 406 407 // Add with carry. 408 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 409 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>; 410 411 // Add with carry compute carry. 412 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 413 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>; 414 415 // And. 416 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 417 418 // And with complement. 419 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 420 421 // Average. 422 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 423 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 424 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 425 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 426 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 427 428 // Average logical. 429 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 430 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 431 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 432 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 433 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 434 435 // Checksum. 436 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 437 438 // Count leading zeros. 439 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 440 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 441 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 442 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 443 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 444 445 // Count trailing zeros. 446 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 447 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 448 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 449 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 450 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 451 452 // Not exclusive or. 453 let Predicates = [FeatureVectorEnhancements1] in 454 def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>; 455 456 // Exclusive or. 457 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 458 459 // Galois field multiply sum. 460 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 461 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 462 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 463 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 464 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 465 466 // Galois field multiply sum and accumulate. 467 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 468 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 469 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 470 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 471 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 472 473 // Load complement. 474 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 475 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 476 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 477 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 478 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 479 480 // Load positive. 481 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 482 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>; 483 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>; 484 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>; 485 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>; 486 487 // Maximum. 488 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 489 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 490 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 491 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 492 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 493 494 // Maximum logical. 495 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 496 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 497 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 498 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 499 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 500 501 // Minimum. 502 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 503 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 504 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 505 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 506 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 507 508 // Minimum logical. 509 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 510 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 511 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 512 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 513 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 514 515 // Multiply and add low. 516 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 517 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 518 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 519 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 520 521 // Multiply and add high. 522 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 523 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 524 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 525 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 526 527 // Multiply and add logical high. 528 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 529 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 530 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 531 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 532 533 // Multiply and add even. 534 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 535 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 536 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 537 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 538 539 // Multiply and add logical even. 540 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 541 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 542 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 543 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 544 545 // Multiply and add odd. 546 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 547 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 548 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 549 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 550 551 // Multiply and add logical odd. 552 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 553 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 554 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 555 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 556 557 // Multiply high. 558 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 559 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 560 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 561 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 562 563 // Multiply logical high. 564 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 565 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 566 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 567 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 568 569 // Multiply low. 570 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 571 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 572 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 573 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 574 575 // Multiply even. 576 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 577 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 578 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 579 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 580 581 // Multiply logical even. 582 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 583 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 584 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 585 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 586 587 // Multiply odd. 588 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 589 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 590 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 591 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 592 593 // Multiply logical odd. 594 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 595 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 596 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 597 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 598 599 // Multiply sum logical. 600 let Predicates = [FeatureVectorEnhancements1] in { 601 def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>; 602 def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg, 603 v128q, v128g, v128g, v128q, 3>; 604 } 605 606 // Nand. 607 let Predicates = [FeatureVectorEnhancements1] in 608 def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>; 609 610 // Nor. 611 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 612 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 613 614 // Or. 615 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 616 617 // Or with complement. 618 let Predicates = [FeatureVectorEnhancements1] in 619 def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>; 620 621 // Population count. 622 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 623 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 624 let Predicates = [FeatureVectorEnhancements1] in { 625 def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>; 626 def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>; 627 def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>; 628 def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>; 629 } 630 631 // Element rotate left logical (with vector shift amount). 632 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 633 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb, 634 v128b, v128b, 0>; 635 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh, 636 v128h, v128h, 1>; 637 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf, 638 v128f, v128f, 2>; 639 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg, 640 v128g, v128g, 3>; 641 642 // Element rotate left logical (with scalar shift amount). 643 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 644 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>; 645 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>; 646 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>; 647 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>; 648 649 // Element rotate and insert under mask. 650 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 651 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 652 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 653 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 654 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 655 656 // Element shift left (with vector shift amount). 657 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 658 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 659 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 660 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 661 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 662 663 // Element shift left (with scalar shift amount). 664 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 665 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 666 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 667 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 668 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 669 670 // Element shift right arithmetic (with vector shift amount). 671 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 672 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 673 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 674 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 675 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 676 677 // Element shift right arithmetic (with scalar shift amount). 678 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 679 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 680 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 681 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 682 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 683 684 // Element shift right logical (with vector shift amount). 685 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 686 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 687 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 688 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 689 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 690 691 // Element shift right logical (with scalar shift amount). 692 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 693 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 694 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 695 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 696 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 697 698 // Shift left. 699 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 700 701 // Shift left by byte. 702 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 703 704 // Shift left double by byte. 705 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 706 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8:$z), 707 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 708 709 // Shift right arithmetic. 710 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 711 712 // Shift right arithmetic by byte. 713 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 714 715 // Shift right logical. 716 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 717 718 // Shift right logical by byte. 719 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 720 721 // Subtract. 722 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 723 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 724 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 725 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 726 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 727 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>; 728 729 // Subtract compute borrow indication. 730 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 731 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>; 732 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>; 733 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>; 734 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>; 735 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>; 736 737 // Subtract with borrow indication. 738 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 739 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>; 740 741 // Subtract with borrow compute borrow indication. 742 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 743 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq, 744 v128q, v128q, 4>; 745 746 // Sum across doubleword. 747 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 748 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 749 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 750 751 // Sum across quadword. 752 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 753 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 754 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 755 756 // Sum across word. 757 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 758 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 759 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 760} 761 762// Instantiate the bitwise ops for type TYPE. 763multiclass BitwiseVectorOps<ValueType type> { 764 let Predicates = [FeatureVector] in { 765 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 766 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))), 767 (VNC VR128:$x, VR128:$y)>; 768 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 769 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 770 def : Pat<(type (or (and VR128:$x, VR128:$z), 771 (and VR128:$y, (z_vnot VR128:$z)))), 772 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 773 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))), 774 (VNO VR128:$x, VR128:$y)>; 775 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; 776 } 777 let Predicates = [FeatureVectorEnhancements1] in { 778 def : Pat<(type (z_vnot (xor VR128:$x, VR128:$y))), 779 (VNX VR128:$x, VR128:$y)>; 780 def : Pat<(type (z_vnot (and VR128:$x, VR128:$y))), 781 (VNN VR128:$x, VR128:$y)>; 782 def : Pat<(type (or VR128:$x, (z_vnot VR128:$y))), 783 (VOC VR128:$x, VR128:$y)>; 784 } 785} 786 787defm : BitwiseVectorOps<v16i8>; 788defm : BitwiseVectorOps<v8i16>; 789defm : BitwiseVectorOps<v4i32>; 790defm : BitwiseVectorOps<v2i64>; 791 792// Instantiate additional patterns for absolute-related expressions on 793// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 794// instruction. 795multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 796 Instruction lp, int shift> { 797 let Predicates = [FeatureVector] in { 798 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 799 (z_vneg VR128:$x), VR128:$x)), 800 (lc (lp VR128:$x))>; 801 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 802 VR128:$x, (z_vneg VR128:$x))), 803 (lc (lp VR128:$x))>; 804 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 805 VR128:$x, (z_vneg VR128:$x))), 806 (lc (lp VR128:$x))>; 807 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 808 (z_vneg VR128:$x), VR128:$x)), 809 (lc (lp VR128:$x))>; 810 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 811 (z_vneg VR128:$x)), 812 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 813 VR128:$x))), 814 (lp VR128:$x)>; 815 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 816 VR128:$x), 817 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 818 (z_vneg VR128:$x)))), 819 (lc (lp VR128:$x))>; 820 } 821} 822 823defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 824defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 825defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 826defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 827 828// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 829// signed or unsigned "set if greater than" comparison instruction and 830// MIN and MAX are the associated minimum and maximum instructions. 831multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 832 Instruction min, Instruction max> { 833 let Predicates = [FeatureVector] in { 834 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 835 (max VR128:$x, VR128:$y)>; 836 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 837 (min VR128:$x, VR128:$y)>; 838 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 839 VR128:$x, VR128:$y)), 840 (min VR128:$x, VR128:$y)>; 841 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 842 VR128:$y, VR128:$x)), 843 (max VR128:$x, VR128:$y)>; 844 } 845} 846 847// Signed min/max. 848defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 849defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 850defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 851defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 852 853// Unsigned min/max. 854defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 855defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 856defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 857defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 858 859//===----------------------------------------------------------------------===// 860// Integer comparison 861//===----------------------------------------------------------------------===// 862 863let Predicates = [FeatureVector] in { 864 // Element compare. 865 let Defs = [CC] in { 866 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 867 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 868 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 869 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 870 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 871 } 872 873 // Element compare logical. 874 let Defs = [CC] in { 875 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 876 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 877 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 878 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 879 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 880 } 881 882 // Compare equal. 883 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 884 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 885 v128b, v128b, 0>; 886 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 887 v128h, v128h, 1>; 888 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 889 v128f, v128f, 2>; 890 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 891 v128g, v128g, 3>; 892 893 // Compare high. 894 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 895 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 896 v128b, v128b, 0>; 897 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 898 v128h, v128h, 1>; 899 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 900 v128f, v128f, 2>; 901 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 902 v128g, v128g, 3>; 903 904 // Compare high logical. 905 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 906 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 907 v128b, v128b, 0>; 908 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 909 v128h, v128h, 1>; 910 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 911 v128f, v128f, 2>; 912 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 913 v128g, v128g, 3>; 914 915 // Test under mask. 916 let Defs = [CC] in 917 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 918} 919 920//===----------------------------------------------------------------------===// 921// Floating-point arithmetic 922//===----------------------------------------------------------------------===// 923 924// See comments in SystemZInstrFP.td for the suppression flags and 925// rounding modes. 926multiclass VectorRounding<Instruction insn, TypedReg tr> { 927 def : FPConversion<insn, frint, tr, tr, 0, 0>; 928 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>; 929 def : FPConversion<insn, ffloor, tr, tr, 4, 7>; 930 def : FPConversion<insn, fceil, tr, tr, 4, 6>; 931 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>; 932 def : FPConversion<insn, fround, tr, tr, 4, 1>; 933} 934 935let Predicates = [FeatureVector] in { 936 // Add. 937 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 938 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>; 939 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, fadd, v64db, v64db, 3, 8>; 940 let Predicates = [FeatureVectorEnhancements1] in { 941 def VFASB : BinaryVRRc<"vfasb", 0xE7E3, fadd, v128sb, v128sb, 2, 0>; 942 def WFASB : BinaryVRRc<"wfasb", 0xE7E3, fadd, v32sb, v32sb, 2, 8>; 943 def WFAXB : BinaryVRRc<"wfaxb", 0xE7E3, fadd, v128xb, v128xb, 4, 8>; 944 } 945 946 // Convert from fixed 64-bit. 947 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 948 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 949 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 950 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>; 951 952 // Convert from logical 64-bit. 953 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 954 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 955 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 956 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>; 957 958 // Convert to fixed 64-bit. 959 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 960 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 961 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 962 // Rounding mode should agree with SystemZInstrFP.td. 963 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>; 964 965 // Convert to logical 64-bit. 966 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 967 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 968 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 969 // Rounding mode should agree with SystemZInstrFP.td. 970 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>; 971 972 // Divide. 973 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 974 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>; 975 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, fdiv, v64db, v64db, 3, 8>; 976 let Predicates = [FeatureVectorEnhancements1] in { 977 def VFDSB : BinaryVRRc<"vfdsb", 0xE7E5, fdiv, v128sb, v128sb, 2, 0>; 978 def WFDSB : BinaryVRRc<"wfdsb", 0xE7E5, fdiv, v32sb, v32sb, 2, 8>; 979 def WFDXB : BinaryVRRc<"wfdxb", 0xE7E5, fdiv, v128xb, v128xb, 4, 8>; 980 } 981 982 // Load FP integer. 983 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 984 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 985 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 986 defm : VectorRounding<VFIDB, v128db>; 987 defm : VectorRounding<WFIDB, v64db>; 988 let Predicates = [FeatureVectorEnhancements1] in { 989 def VFISB : TernaryVRRa<"vfisb", 0xE7C7, int_s390_vfisb, v128sb, v128sb, 2, 0>; 990 def WFISB : TernaryVRRa<"wfisb", 0xE7C7, null_frag, v32sb, v32sb, 2, 8>; 991 def WFIXB : TernaryVRRa<"wfixb", 0xE7C7, null_frag, v128xb, v128xb, 4, 8>; 992 defm : VectorRounding<VFISB, v128sb>; 993 defm : VectorRounding<WFISB, v32sb>; 994 defm : VectorRounding<WFIXB, v128xb>; 995 } 996 997 // Load lengthened. 998 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 999 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128sb, 2, 0>; 1000 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, fpextend, v64db, v32sb, 2, 8>; 1001 let Predicates = [FeatureVectorEnhancements1] in { 1002 let isAsmParserOnly = 1 in { 1003 def VFLL : UnaryVRRaFloatGeneric<"vfll", 0xE7C4>; 1004 def VFLLS : UnaryVRRa<"vflls", 0xE7C4, null_frag, v128db, v128sb, 2, 0>; 1005 def WFLLS : UnaryVRRa<"wflls", 0xE7C4, null_frag, v64db, v32sb, 2, 8>; 1006 } 1007 def WFLLD : UnaryVRRa<"wflld", 0xE7C4, fpextend, v128xb, v64db, 3, 8>; 1008 def : Pat<(f128 (fpextend (f32 VR32:$src))), 1009 (WFLLD (WLDEB VR32:$src))>; 1010 } 1011 1012 // Load rounded. 1013 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 1014 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1015 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1016 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 1017 def : FPConversion<WLEDB, fpround, v32sb, v64db, 0, 0>; 1018 let Predicates = [FeatureVectorEnhancements1] in { 1019 let isAsmParserOnly = 1 in { 1020 def VFLR : TernaryVRRaFloatGeneric<"vflr", 0xE7C5>; 1021 def VFLRD : TernaryVRRa<"vflrd", 0xE7C5, null_frag, v128sb, v128db, 3, 0>; 1022 def WFLRD : TernaryVRRa<"wflrd", 0xE7C5, null_frag, v32sb, v64db, 3, 8>; 1023 } 1024 def WFLRX : TernaryVRRa<"wflrx", 0xE7C5, null_frag, v64db, v128xb, 4, 8>; 1025 def : FPConversion<WFLRX, fpround, v64db, v128xb, 0, 0>; 1026 def : Pat<(f32 (fpround (f128 VR128:$src))), 1027 (WLEDB (WFLRX VR128:$src, 0, 3), 0, 0)>; 1028 } 1029 1030 // Maximum. 1031 multiclass VectorMax<Instruction insn, TypedReg tr> { 1032 def : FPMinMax<insn, fmaxnum, tr, 4>; 1033 def : FPMinMax<insn, fmaximum, tr, 1>; 1034 } 1035 let Predicates = [FeatureVectorEnhancements1] in { 1036 def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; 1037 def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb, 1038 v128db, v128db, 3, 0>; 1039 def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag, 1040 v64db, v64db, 3, 8>; 1041 def VFMAXSB : TernaryVRRcFloat<"vfmaxsb", 0xE7EF, int_s390_vfmaxsb, 1042 v128sb, v128sb, 2, 0>; 1043 def WFMAXSB : TernaryVRRcFloat<"wfmaxsb", 0xE7EF, null_frag, 1044 v32sb, v32sb, 2, 8>; 1045 def WFMAXXB : TernaryVRRcFloat<"wfmaxxb", 0xE7EF, null_frag, 1046 v128xb, v128xb, 4, 8>; 1047 defm : VectorMax<VFMAXDB, v128db>; 1048 defm : VectorMax<WFMAXDB, v64db>; 1049 defm : VectorMax<VFMAXSB, v128sb>; 1050 defm : VectorMax<WFMAXSB, v32sb>; 1051 defm : VectorMax<WFMAXXB, v128xb>; 1052 } 1053 1054 // Minimum. 1055 multiclass VectorMin<Instruction insn, TypedReg tr> { 1056 def : FPMinMax<insn, fminnum, tr, 4>; 1057 def : FPMinMax<insn, fminimum, tr, 1>; 1058 } 1059 let Predicates = [FeatureVectorEnhancements1] in { 1060 def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; 1061 def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb, 1062 v128db, v128db, 3, 0>; 1063 def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag, 1064 v64db, v64db, 3, 8>; 1065 def VFMINSB : TernaryVRRcFloat<"vfminsb", 0xE7EE, int_s390_vfminsb, 1066 v128sb, v128sb, 2, 0>; 1067 def WFMINSB : TernaryVRRcFloat<"wfminsb", 0xE7EE, null_frag, 1068 v32sb, v32sb, 2, 8>; 1069 def WFMINXB : TernaryVRRcFloat<"wfminxb", 0xE7EE, null_frag, 1070 v128xb, v128xb, 4, 8>; 1071 defm : VectorMin<VFMINDB, v128db>; 1072 defm : VectorMin<WFMINDB, v64db>; 1073 defm : VectorMin<VFMINSB, v128sb>; 1074 defm : VectorMin<WFMINSB, v32sb>; 1075 defm : VectorMin<WFMINXB, v128xb>; 1076 } 1077 1078 // Multiply. 1079 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 1080 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>; 1081 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, fmul, v64db, v64db, 3, 8>; 1082 let Predicates = [FeatureVectorEnhancements1] in { 1083 def VFMSB : BinaryVRRc<"vfmsb", 0xE7E7, fmul, v128sb, v128sb, 2, 0>; 1084 def WFMSB : BinaryVRRc<"wfmsb", 0xE7E7, fmul, v32sb, v32sb, 2, 8>; 1085 def WFMXB : BinaryVRRc<"wfmxb", 0xE7E7, fmul, v128xb, v128xb, 4, 8>; 1086 } 1087 1088 // Multiply and add. 1089 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 1090 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>; 1091 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, fma, v64db, v64db, 8, 3>; 1092 let Predicates = [FeatureVectorEnhancements1] in { 1093 def VFMASB : TernaryVRRe<"vfmasb", 0xE78F, fma, v128sb, v128sb, 0, 2>; 1094 def WFMASB : TernaryVRRe<"wfmasb", 0xE78F, fma, v32sb, v32sb, 8, 2>; 1095 def WFMAXB : TernaryVRRe<"wfmaxb", 0xE78F, fma, v128xb, v128xb, 8, 4>; 1096 } 1097 1098 // Multiply and subtract. 1099 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 1100 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>; 1101 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>; 1102 let Predicates = [FeatureVectorEnhancements1] in { 1103 def VFMSSB : TernaryVRRe<"vfmssb", 0xE78E, fms, v128sb, v128sb, 0, 2>; 1104 def WFMSSB : TernaryVRRe<"wfmssb", 0xE78E, fms, v32sb, v32sb, 8, 2>; 1105 def WFMSXB : TernaryVRRe<"wfmsxb", 0xE78E, fms, v128xb, v128xb, 8, 4>; 1106 } 1107 1108 // Negative multiply and add. 1109 let Predicates = [FeatureVectorEnhancements1] in { 1110 def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>; 1111 def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, fnma, v128db, v128db, 0, 3>; 1112 def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, fnma, v64db, v64db, 8, 3>; 1113 def VFNMASB : TernaryVRRe<"vfnmasb", 0xE79F, fnma, v128sb, v128sb, 0, 2>; 1114 def WFNMASB : TernaryVRRe<"wfnmasb", 0xE79F, fnma, v32sb, v32sb, 8, 2>; 1115 def WFNMAXB : TernaryVRRe<"wfnmaxb", 0xE79F, fnma, v128xb, v128xb, 8, 4>; 1116 } 1117 1118 // Negative multiply and subtract. 1119 let Predicates = [FeatureVectorEnhancements1] in { 1120 def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>; 1121 def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, fnms, v128db, v128db, 0, 3>; 1122 def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, fnms, v64db, v64db, 8, 3>; 1123 def VFNMSSB : TernaryVRRe<"vfnmssb", 0xE79E, fnms, v128sb, v128sb, 0, 2>; 1124 def WFNMSSB : TernaryVRRe<"wfnmssb", 0xE79E, fnms, v32sb, v32sb, 8, 2>; 1125 def WFNMSXB : TernaryVRRe<"wfnmsxb", 0xE79E, fnms, v128xb, v128xb, 8, 4>; 1126 } 1127 1128 // Perform sign operation. 1129 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 1130 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 1131 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 1132 let Predicates = [FeatureVectorEnhancements1] in { 1133 def VFPSOSB : BinaryVRRa<"vfpsosb", 0xE7CC, null_frag, v128sb, v128sb, 2, 0>; 1134 def WFPSOSB : BinaryVRRa<"wfpsosb", 0xE7CC, null_frag, v32sb, v32sb, 2, 8>; 1135 def WFPSOXB : BinaryVRRa<"wfpsoxb", 0xE7CC, null_frag, v128xb, v128xb, 4, 8>; 1136 } 1137 1138 // Load complement. 1139 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 1140 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 1141 let Predicates = [FeatureVectorEnhancements1] in { 1142 def VFLCSB : UnaryVRRa<"vflcsb", 0xE7CC, fneg, v128sb, v128sb, 2, 0, 0>; 1143 def WFLCSB : UnaryVRRa<"wflcsb", 0xE7CC, fneg, v32sb, v32sb, 2, 8, 0>; 1144 def WFLCXB : UnaryVRRa<"wflcxb", 0xE7CC, fneg, v128xb, v128xb, 4, 8, 0>; 1145 } 1146 1147 // Load negative. 1148 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 1149 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 1150 let Predicates = [FeatureVectorEnhancements1] in { 1151 def VFLNSB : UnaryVRRa<"vflnsb", 0xE7CC, fnabs, v128sb, v128sb, 2, 0, 1>; 1152 def WFLNSB : UnaryVRRa<"wflnsb", 0xE7CC, fnabs, v32sb, v32sb, 2, 8, 1>; 1153 def WFLNXB : UnaryVRRa<"wflnxb", 0xE7CC, fnabs, v128xb, v128xb, 4, 8, 1>; 1154 } 1155 1156 // Load positive. 1157 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 1158 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 1159 let Predicates = [FeatureVectorEnhancements1] in { 1160 def VFLPSB : UnaryVRRa<"vflpsb", 0xE7CC, fabs, v128sb, v128sb, 2, 0, 2>; 1161 def WFLPSB : UnaryVRRa<"wflpsb", 0xE7CC, fabs, v32sb, v32sb, 2, 8, 2>; 1162 def WFLPXB : UnaryVRRa<"wflpxb", 0xE7CC, fabs, v128xb, v128xb, 4, 8, 2>; 1163 } 1164 1165 // Square root. 1166 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 1167 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>; 1168 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, fsqrt, v64db, v64db, 3, 8>; 1169 let Predicates = [FeatureVectorEnhancements1] in { 1170 def VFSQSB : UnaryVRRa<"vfsqsb", 0xE7CE, fsqrt, v128sb, v128sb, 2, 0>; 1171 def WFSQSB : UnaryVRRa<"wfsqsb", 0xE7CE, fsqrt, v32sb, v32sb, 2, 8>; 1172 def WFSQXB : UnaryVRRa<"wfsqxb", 0xE7CE, fsqrt, v128xb, v128xb, 4, 8>; 1173 } 1174 1175 // Subtract. 1176 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 1177 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>; 1178 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, fsub, v64db, v64db, 3, 8>; 1179 let Predicates = [FeatureVectorEnhancements1] in { 1180 def VFSSB : BinaryVRRc<"vfssb", 0xE7E2, fsub, v128sb, v128sb, 2, 0>; 1181 def WFSSB : BinaryVRRc<"wfssb", 0xE7E2, fsub, v32sb, v32sb, 2, 8>; 1182 def WFSXB : BinaryVRRc<"wfsxb", 0xE7E2, fsub, v128xb, v128xb, 4, 8>; 1183 } 1184 1185 // Test data class immediate. 1186 let Defs = [CC] in { 1187 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 1188 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 1189 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 1190 let Predicates = [FeatureVectorEnhancements1] in { 1191 def VFTCISB : BinaryVRIe<"vftcisb", 0xE74A, z_vftci, v128f, v128sb, 2, 0>; 1192 def WFTCISB : BinaryVRIe<"wftcisb", 0xE74A, null_frag, v32f, v32sb, 2, 8>; 1193 def WFTCIXB : BinaryVRIe<"wftcixb", 0xE74A, null_frag, v128q, v128xb, 4, 8>; 1194 } 1195 } 1196} 1197 1198//===----------------------------------------------------------------------===// 1199// Floating-point comparison 1200//===----------------------------------------------------------------------===// 1201 1202let Predicates = [FeatureVector] in { 1203 // Compare scalar. 1204 let Defs = [CC] in { 1205 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 1206 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>; 1207 let Predicates = [FeatureVectorEnhancements1] in { 1208 def WFCSB : CompareVRRa<"wfcsb", 0xE7CB, z_fcmp, v32sb, 2>; 1209 def WFCXB : CompareVRRa<"wfcxb", 0xE7CB, z_fcmp, v128xb, 4>; 1210 } 1211 } 1212 1213 // Compare and signal scalar. 1214 let Defs = [CC] in { 1215 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 1216 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>; 1217 let Predicates = [FeatureVectorEnhancements1] in { 1218 def WFKSB : CompareVRRa<"wfksb", 0xE7CA, null_frag, v32sb, 2>; 1219 def WFKXB : CompareVRRa<"wfkxb", 0xE7CA, null_frag, v128xb, 4>; 1220 } 1221 } 1222 1223 // Compare equal. 1224 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 1225 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1226 v128g, v128db, 3, 0>; 1227 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1228 v64g, v64db, 3, 8>; 1229 let Predicates = [FeatureVectorEnhancements1] in { 1230 defm VFCESB : BinaryVRRcSPair<"vfcesb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1231 v128f, v128sb, 2, 0>; 1232 defm WFCESB : BinaryVRRcSPair<"wfcesb", 0xE7E8, null_frag, null_frag, 1233 v32f, v32sb, 2, 8>; 1234 defm WFCEXB : BinaryVRRcSPair<"wfcexb", 0xE7E8, null_frag, null_frag, 1235 v128q, v128xb, 4, 8>; 1236 } 1237 1238 // Compare and signal equal. 1239 let Predicates = [FeatureVectorEnhancements1] in { 1240 defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, null_frag, null_frag, 1241 v128g, v128db, 3, 4>; 1242 defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag, 1243 v64g, v64db, 3, 12>; 1244 defm VFKESB : BinaryVRRcSPair<"vfkesb", 0xE7E8, null_frag, null_frag, 1245 v128f, v128sb, 2, 4>; 1246 defm WFKESB : BinaryVRRcSPair<"wfkesb", 0xE7E8, null_frag, null_frag, 1247 v32f, v32sb, 2, 12>; 1248 defm WFKEXB : BinaryVRRcSPair<"wfkexb", 0xE7E8, null_frag, null_frag, 1249 v128q, v128xb, 4, 12>; 1250 } 1251 1252 // Compare high. 1253 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1254 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs, 1255 v128g, v128db, 3, 0>; 1256 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1257 v64g, v64db, 3, 8>; 1258 let Predicates = [FeatureVectorEnhancements1] in { 1259 defm VFCHSB : BinaryVRRcSPair<"vfchsb", 0xE7EB, z_vfcmph, z_vfcmphs, 1260 v128f, v128sb, 2, 0>; 1261 defm WFCHSB : BinaryVRRcSPair<"wfchsb", 0xE7EB, null_frag, null_frag, 1262 v32f, v32sb, 2, 8>; 1263 defm WFCHXB : BinaryVRRcSPair<"wfchxb", 0xE7EB, null_frag, null_frag, 1264 v128q, v128xb, 4, 8>; 1265 } 1266 1267 // Compare and signal high. 1268 let Predicates = [FeatureVectorEnhancements1] in { 1269 defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, null_frag, null_frag, 1270 v128g, v128db, 3, 4>; 1271 defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag, 1272 v64g, v64db, 3, 12>; 1273 defm VFKHSB : BinaryVRRcSPair<"vfkhsb", 0xE7EB, null_frag, null_frag, 1274 v128f, v128sb, 2, 4>; 1275 defm WFKHSB : BinaryVRRcSPair<"wfkhsb", 0xE7EB, null_frag, null_frag, 1276 v32f, v32sb, 2, 12>; 1277 defm WFKHXB : BinaryVRRcSPair<"wfkhxb", 0xE7EB, null_frag, null_frag, 1278 v128q, v128xb, 4, 12>; 1279 } 1280 1281 // Compare high or equal. 1282 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1283 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1284 v128g, v128db, 3, 0>; 1285 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1286 v64g, v64db, 3, 8>; 1287 let Predicates = [FeatureVectorEnhancements1] in { 1288 defm VFCHESB : BinaryVRRcSPair<"vfchesb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1289 v128f, v128sb, 2, 0>; 1290 defm WFCHESB : BinaryVRRcSPair<"wfchesb", 0xE7EA, null_frag, null_frag, 1291 v32f, v32sb, 2, 8>; 1292 defm WFCHEXB : BinaryVRRcSPair<"wfchexb", 0xE7EA, null_frag, null_frag, 1293 v128q, v128xb, 4, 8>; 1294 } 1295 1296 // Compare and signal high or equal. 1297 let Predicates = [FeatureVectorEnhancements1] in { 1298 defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, null_frag, null_frag, 1299 v128g, v128db, 3, 4>; 1300 defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag, 1301 v64g, v64db, 3, 12>; 1302 defm VFKHESB : BinaryVRRcSPair<"vfkhesb", 0xE7EA, null_frag, null_frag, 1303 v128f, v128sb, 2, 4>; 1304 defm WFKHESB : BinaryVRRcSPair<"wfkhesb", 0xE7EA, null_frag, null_frag, 1305 v32f, v32sb, 2, 12>; 1306 defm WFKHEXB : BinaryVRRcSPair<"wfkhexb", 0xE7EA, null_frag, null_frag, 1307 v128q, v128xb, 4, 12>; 1308 } 1309} 1310 1311//===----------------------------------------------------------------------===// 1312// Conversions 1313//===----------------------------------------------------------------------===// 1314 1315def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 1316def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 1317def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 1318def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 1319def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 1320def : Pat<(v16i8 (bitconvert (f128 VR128:$src))), (v16i8 VR128:$src)>; 1321 1322def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 1323def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 1324def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 1325def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 1326def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 1327def : Pat<(v8i16 (bitconvert (f128 VR128:$src))), (v8i16 VR128:$src)>; 1328 1329def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 1330def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 1331def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 1332def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 1333def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 1334def : Pat<(v4i32 (bitconvert (f128 VR128:$src))), (v4i32 VR128:$src)>; 1335 1336def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 1337def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 1338def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 1339def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 1340def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 1341def : Pat<(v2i64 (bitconvert (f128 VR128:$src))), (v2i64 VR128:$src)>; 1342 1343def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 1344def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 1345def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 1346def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 1347def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 1348def : Pat<(v4f32 (bitconvert (f128 VR128:$src))), (v4f32 VR128:$src)>; 1349 1350def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 1351def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 1352def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 1353def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 1354def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 1355def : Pat<(v2f64 (bitconvert (f128 VR128:$src))), (v2f64 VR128:$src)>; 1356 1357def : Pat<(f128 (bitconvert (v16i8 VR128:$src))), (f128 VR128:$src)>; 1358def : Pat<(f128 (bitconvert (v8i16 VR128:$src))), (f128 VR128:$src)>; 1359def : Pat<(f128 (bitconvert (v4i32 VR128:$src))), (f128 VR128:$src)>; 1360def : Pat<(f128 (bitconvert (v2i64 VR128:$src))), (f128 VR128:$src)>; 1361def : Pat<(f128 (bitconvert (v4f32 VR128:$src))), (f128 VR128:$src)>; 1362def : Pat<(f128 (bitconvert (v2f64 VR128:$src))), (f128 VR128:$src)>; 1363 1364//===----------------------------------------------------------------------===// 1365// Replicating scalars 1366//===----------------------------------------------------------------------===// 1367 1368// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 1369// INDEX is 8 minus the element size in bytes. 1370class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 1371 : Pat<(type (z_replicate GR32:$scalar)), 1372 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 1373 1374def : VectorReplicateScalar<v16i8, VREPB, 7>; 1375def : VectorReplicateScalar<v8i16, VREPH, 3>; 1376def : VectorReplicateScalar<v4i32, VREPF, 1>; 1377 1378// i64 replications are just a single isntruction. 1379def : Pat<(v2i64 (z_replicate GR64:$scalar)), 1380 (VLVGP GR64:$scalar, GR64:$scalar)>; 1381 1382//===----------------------------------------------------------------------===// 1383// Floating-point insertion and extraction 1384//===----------------------------------------------------------------------===// 1385 1386// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 1387// and VLGVF. 1388let Predicates = [FeatureVector] in { 1389 def LEFR : UnaryAliasVRS<VR32, GR32>; 1390 def LFER : UnaryAliasVRS<GR64, VR32>; 1391 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 1392 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 1393 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 1394} 1395 1396// Floating-point values are stored in element 0 of the corresponding 1397// vector register. Scalar to vector conversion is just a subreg and 1398// scalar replication can just replicate element 0 of the vector register. 1399multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 1400 SubRegIndex subreg> { 1401 def : Pat<(vt (scalar_to_vector cls:$scalar)), 1402 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 1403 def : Pat<(vt (z_replicate cls:$scalar)), 1404 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 1405 subreg), 0)>; 1406} 1407defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_h32>; 1408defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>; 1409 1410// Match v2f64 insertions. The AddedComplexity counters the 3 added by 1411// TableGen for the base register operand in VLVG-based integer insertions 1412// and ensures that this version is strictly better. 1413let AddedComplexity = 4 in { 1414 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 1415 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1416 subreg_h64), VR128:$vec, 1)>; 1417 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 1418 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1419 subreg_h64), 0)>; 1420} 1421 1422// We extract floating-point element X by replicating (for elements other 1423// than 0) and then taking a high subreg. The AddedComplexity counters the 1424// 3 added by TableGen for the base register operand in VLGV-based integer 1425// extractions and ensures that this version is strictly better. 1426let AddedComplexity = 4 in { 1427 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 1428 (EXTRACT_SUBREG VR128:$vec, subreg_h32)>; 1429 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 1430 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_h32)>; 1431 1432 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 1433 (EXTRACT_SUBREG VR128:$vec, subreg_h64)>; 1434 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 1435 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_h64)>; 1436} 1437 1438//===----------------------------------------------------------------------===// 1439// Support for 128-bit floating-point values in vector registers 1440//===----------------------------------------------------------------------===// 1441 1442let Predicates = [FeatureVectorEnhancements1] in { 1443 def : Pat<(f128 (load bdxaddr12only:$addr)), 1444 (VL bdxaddr12only:$addr)>; 1445 def : Pat<(store (f128 VR128:$src), bdxaddr12only:$addr), 1446 (VST VR128:$src, bdxaddr12only:$addr)>; 1447 1448 def : Pat<(f128 fpimm0), (VZERO)>; 1449 def : Pat<(f128 fpimmneg0), (WFLNXB (VZERO))>; 1450} 1451 1452//===----------------------------------------------------------------------===// 1453// String instructions 1454//===----------------------------------------------------------------------===// 1455 1456let Predicates = [FeatureVector] in { 1457 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 1458 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 1459 z_vfae_cc, v128b, v128b, 0>; 1460 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 1461 z_vfae_cc, v128h, v128h, 1>; 1462 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 1463 z_vfae_cc, v128f, v128f, 2>; 1464 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 1465 z_vfaez_cc, v128b, v128b, 0, 2>; 1466 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 1467 z_vfaez_cc, v128h, v128h, 1, 2>; 1468 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 1469 z_vfaez_cc, v128f, v128f, 2, 2>; 1470 1471 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 1472 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 1473 z_vfee_cc, v128b, v128b, 0>; 1474 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 1475 z_vfee_cc, v128h, v128h, 1>; 1476 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 1477 z_vfee_cc, v128f, v128f, 2>; 1478 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 1479 z_vfeez_cc, v128b, v128b, 0, 2>; 1480 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 1481 z_vfeez_cc, v128h, v128h, 1, 2>; 1482 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 1483 z_vfeez_cc, v128f, v128f, 2, 2>; 1484 1485 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 1486 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 1487 z_vfene_cc, v128b, v128b, 0>; 1488 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 1489 z_vfene_cc, v128h, v128h, 1>; 1490 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 1491 z_vfene_cc, v128f, v128f, 2>; 1492 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 1493 z_vfenez_cc, v128b, v128b, 0, 2>; 1494 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 1495 z_vfenez_cc, v128h, v128h, 1, 2>; 1496 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 1497 z_vfenez_cc, v128f, v128f, 2, 2>; 1498 1499 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 1500 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 1501 z_vistr_cc, v128b, v128b, 0>; 1502 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 1503 z_vistr_cc, v128h, v128h, 1>; 1504 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 1505 z_vistr_cc, v128f, v128f, 2>; 1506 1507 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 1508 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 1509 z_vstrc_cc, v128b, v128b, 0>; 1510 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 1511 z_vstrc_cc, v128h, v128h, 1>; 1512 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 1513 z_vstrc_cc, v128f, v128f, 2>; 1514 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 1515 z_vstrcz_cc, v128b, v128b, 0, 2>; 1516 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 1517 z_vstrcz_cc, v128h, v128h, 1, 2>; 1518 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 1519 z_vstrcz_cc, v128f, v128f, 2, 2>; 1520} 1521 1522//===----------------------------------------------------------------------===// 1523// Packed-decimal instructions 1524//===----------------------------------------------------------------------===// 1525 1526let Predicates = [FeatureVectorPackedDecimal] in { 1527 def VLIP : BinaryVRIh<"vlip", 0xE649>; 1528 1529 def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>; 1530 def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>; 1531 1532 let Defs = [CC] in { 1533 def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>; 1534 def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>; 1535 def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>; 1536 def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>; 1537 1538 def VAP : QuaternaryVRIf<"vap", 0xE671>; 1539 def VSP : QuaternaryVRIf<"vsp", 0xE673>; 1540 1541 def VMP : QuaternaryVRIf<"vmp", 0xE678>; 1542 def VMSP : QuaternaryVRIf<"vmsp", 0xE679>; 1543 1544 def VDP : QuaternaryVRIf<"vdp", 0xE67A>; 1545 def VRP : QuaternaryVRIf<"vrp", 0xE67B>; 1546 def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>; 1547 1548 def VSRP : QuaternaryVRIg<"vsrp", 0xE659>; 1549 def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>; 1550 1551 def VTP : TestVRRg<"vtp", 0xE65F>; 1552 def VCP : CompareVRRh<"vcp", 0xE677>; 1553 } 1554} 1555