1//==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Move instructions 12//===----------------------------------------------------------------------===// 13 14let Predicates = [FeatureVector] in { 15 // Register move. 16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>; 17 def VLR32 : UnaryAliasVRR<null_frag, v32eb, v32eb>; 18 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>; 19 20 // Load GR from VR element. 21 def VLGV : BinaryVRScGeneric<"vlgv", 0xE721>; 22 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>; 23 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>; 24 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>; 25 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>; 26 27 // Load VR element from GR. 28 def VLVG : TernaryVRSbGeneric<"vlvg", 0xE722>; 29 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert, 30 v128b, v128b, GR32, 0>; 31 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert, 32 v128h, v128h, GR32, 1>; 33 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert, 34 v128f, v128f, GR32, 2>; 35 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert, 36 v128g, v128g, GR64, 3>; 37 38 // Load VR from GRs disjoint. 39 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>; 40 def VLVGP32 : BinaryAliasVRRf<GR32>; 41} 42 43// Extractions always assign to the full GR64, even if the element would 44// fit in the lower 32 bits. Sub-i64 extracts therefore need to take a 45// subreg of the result. 46class VectorExtractSubreg<ValueType type, Instruction insn> 47 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)), 48 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>; 49 50def : VectorExtractSubreg<v16i8, VLGVB>; 51def : VectorExtractSubreg<v8i16, VLGVH>; 52def : VectorExtractSubreg<v4i32, VLGVF>; 53 54//===----------------------------------------------------------------------===// 55// Immediate instructions 56//===----------------------------------------------------------------------===// 57 58let Predicates = [FeatureVector] in { 59 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 60 isReMaterializable = 1 in { 61 62 // Generate byte mask. 63 def VZERO : InherentVRIa<"vzero", 0xE744, 0>; 64 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; 65 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; 66 67 // Generate mask. 68 def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; 69 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; 70 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; 71 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; 72 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; 73 74 // Replicate immediate. 75 def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; 76 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; 77 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; 78 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; 79 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; 80 } 81 82 // Load element immediate. 83 // 84 // We want these instructions to be used ahead of VLVG* where possible. 85 // However, VLVG* takes a variable BD-format index whereas VLEI takes 86 // a plain immediate index. This means that VLVG* has an extra "base" 87 // register operand and is 3 units more complex. Bumping the complexity 88 // of the VLEI* instructions by 4 means that they are strictly better 89 // than VLVG* in cases where both forms match. 90 let AddedComplexity = 4 in { 91 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert, 92 v128b, v128b, imm32sx16trunc, imm32zx4>; 93 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert, 94 v128h, v128h, imm32sx16trunc, imm32zx3>; 95 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert, 96 v128f, v128f, imm32sx16, imm32zx2>; 97 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, 98 v128g, v128g, imm64sx16, imm32zx1>; 99 } 100} 101 102//===----------------------------------------------------------------------===// 103// Loads 104//===----------------------------------------------------------------------===// 105 106let Predicates = [FeatureVector] in { 107 // Load. 108 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>; 109 110 // Load to block boundary. The number of loaded bytes is only known 111 // at run time. The instruction is really polymorphic, but v128b matches 112 // the return type of the associated intrinsic. 113 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>; 114 115 // Load count to block boundary. 116 let Defs = [CC] in 117 def LCBB : InstRXE<0xE727, (outs GR32:$R1), 118 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 119 "lcbb\t$R1, $XBD2, $M3", 120 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2, 121 imm32zx4:$M3))]>; 122 123 // Load with length. The number of loaded bytes is only known at run time. 124 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>; 125 126 // Load multiple. 127 def VLM : LoadMultipleVRSa<"vlm", 0xE736>; 128 129 // Load and replicate 130 def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>; 131 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>; 132 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>; 133 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>; 134 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>; 135 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)), 136 (VLREPF bdxaddr12only:$addr)>; 137 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)), 138 (VLREPG bdxaddr12only:$addr)>; 139 140 // Use VLREP to load subvectors. These patterns use "12pair" because 141 // LEY and LDY offer full 20-bit displacement fields. It's often better 142 // to use those instructions rather than force a 20-bit displacement 143 // into a GPR temporary. 144 def VL32 : UnaryAliasVRX<load, v32eb, bdxaddr12pair>; 145 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>; 146 147 // Load logical element and zero. 148 def VLLEZ : UnaryVRXGeneric<"vllez", 0xE704>; 149 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>; 150 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>; 151 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>; 152 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>; 153 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)), 154 (VLLEZF bdxaddr12only:$addr)>; 155 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)), 156 (VLLEZG bdxaddr12only:$addr)>; 157 158 // Load element. 159 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; 160 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>; 161 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>; 162 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>; 163 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index), 164 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 165 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index), 166 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 167 168 // Gather element. 169 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>; 170 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; 171} 172 173// Use replicating loads if we're inserting a single element into an 174// undefined vector. This avoids a false dependency on the previous 175// register contents. 176multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype, 177 SDPatternOperator load, ValueType scalartype> { 178 def : Pat<(vectype (z_vector_insert 179 (undef), (scalartype (load bdxaddr12only:$addr)), 0)), 180 (vlrep bdxaddr12only:$addr)>; 181 def : Pat<(vectype (scalar_to_vector 182 (scalartype (load bdxaddr12only:$addr)))), 183 (vlrep bdxaddr12only:$addr)>; 184} 185defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>; 186defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>; 187defm : ReplicatePeephole<VLREPF, v4i32, load, i32>; 188defm : ReplicatePeephole<VLREPG, v2i64, load, i64>; 189defm : ReplicatePeephole<VLREPF, v4f32, load, f32>; 190defm : ReplicatePeephole<VLREPG, v2f64, load, f64>; 191 192//===----------------------------------------------------------------------===// 193// Stores 194//===----------------------------------------------------------------------===// 195 196let Predicates = [FeatureVector] in { 197 // Store. 198 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>; 199 200 // Store with length. The number of stored bytes is only known at run time. 201 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>; 202 203 // Store multiple. 204 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>; 205 206 // Store element. 207 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>; 208 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>; 209 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>; 210 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>; 211 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr, 212 imm32zx2:$index), 213 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>; 214 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr, 215 imm32zx1:$index), 216 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>; 217 218 // Use VSTE to store subvectors. These patterns use "12pair" because 219 // STEY and STDY offer full 20-bit displacement fields. It's often better 220 // to use those instructions rather than force a 20-bit displacement 221 // into a GPR temporary. 222 def VST32 : StoreAliasVRX<store, v32eb, bdxaddr12pair>; 223 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>; 224 225 // Scatter element. 226 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>; 227 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; 228} 229 230//===----------------------------------------------------------------------===// 231// Selects and permutes 232//===----------------------------------------------------------------------===// 233 234let Predicates = [FeatureVector] in { 235 // Merge high. 236 def VMRH: BinaryVRRcGeneric<"vmrh", 0xE761>; 237 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>; 238 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>; 239 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>; 240 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>; 241 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>; 242 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>; 243 244 // Merge low. 245 def VMRL: BinaryVRRcGeneric<"vmrl", 0xE760>; 246 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>; 247 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>; 248 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>; 249 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>; 250 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>; 251 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>; 252 253 // Permute. 254 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>; 255 256 // Permute doubleword immediate. 257 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; 258 259 // Replicate. 260 def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; 261 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; 262 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>; 263 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>; 264 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>; 265 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)), 266 (VREPF VR128:$vec, imm32zx16:$index)>; 267 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)), 268 (VREPG VR128:$vec, imm32zx16:$index)>; 269 270 // Select. 271 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>; 272} 273 274//===----------------------------------------------------------------------===// 275// Widening and narrowing 276//===----------------------------------------------------------------------===// 277 278let Predicates = [FeatureVector] in { 279 // Pack 280 def VPK : BinaryVRRcGeneric<"vpk", 0xE794>; 281 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>; 282 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>; 283 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>; 284 285 // Pack saturate. 286 def VPKS : BinaryVRRbSPairGeneric<"vpks", 0xE797>; 287 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc, 288 v128b, v128h, 1>; 289 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc, 290 v128h, v128f, 2>; 291 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc, 292 v128f, v128g, 3>; 293 294 // Pack saturate logical. 295 def VPKLS : BinaryVRRbSPairGeneric<"vpkls", 0xE795>; 296 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc, 297 v128b, v128h, 1>; 298 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc, 299 v128h, v128f, 2>; 300 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc, 301 v128f, v128g, 3>; 302 303 // Sign-extend to doubleword. 304 def VSEG : UnaryVRRaGeneric<"vseg", 0xE75F>; 305 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>; 306 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>; 307 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>; 308 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>; 309 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>; 310 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>; 311 312 // Unpack high. 313 def VUPH : UnaryVRRaGeneric<"vuph", 0xE7D7>; 314 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>; 315 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>; 316 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>; 317 318 // Unpack logical high. 319 def VUPLH : UnaryVRRaGeneric<"vuplh", 0xE7D5>; 320 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>; 321 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>; 322 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>; 323 324 // Unpack low. 325 def VUPL : UnaryVRRaGeneric<"vupl", 0xE7D6>; 326 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>; 327 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>; 328 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>; 329 330 // Unpack logical low. 331 def VUPLL : UnaryVRRaGeneric<"vupll", 0xE7D4>; 332 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>; 333 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>; 334 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>; 335} 336 337//===----------------------------------------------------------------------===// 338// Instantiating generic operations for specific types. 339//===----------------------------------------------------------------------===// 340 341multiclass GenericVectorOps<ValueType type, ValueType inttype> { 342 let Predicates = [FeatureVector] in { 343 def : Pat<(type (load bdxaddr12only:$addr)), 344 (VL bdxaddr12only:$addr)>; 345 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr), 346 (VST VR128:$src, bdxaddr12only:$addr)>; 347 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)), 348 (VSEL VR128:$y, VR128:$z, VR128:$x)>; 349 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)), 350 (VSEL VR128:$z, VR128:$y, VR128:$x)>; 351 } 352} 353 354defm : GenericVectorOps<v16i8, v16i8>; 355defm : GenericVectorOps<v8i16, v8i16>; 356defm : GenericVectorOps<v4i32, v4i32>; 357defm : GenericVectorOps<v2i64, v2i64>; 358defm : GenericVectorOps<v4f32, v4i32>; 359defm : GenericVectorOps<v2f64, v2i64>; 360 361//===----------------------------------------------------------------------===// 362// Integer arithmetic 363//===----------------------------------------------------------------------===// 364 365let Predicates = [FeatureVector] in { 366 // Add. 367 def VA : BinaryVRRcGeneric<"va", 0xE7F3>; 368 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>; 369 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>; 370 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>; 371 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>; 372 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>; 373 374 // Add compute carry. 375 def VACC : BinaryVRRcGeneric<"vacc", 0xE7F1>; 376 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>; 377 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>; 378 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>; 379 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>; 380 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>; 381 382 // Add with carry. 383 def VAC : TernaryVRRdGeneric<"vac", 0xE7BB>; 384 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>; 385 386 // Add with carry compute carry. 387 def VACCC : TernaryVRRdGeneric<"vaccc", 0xE7B9>; 388 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>; 389 390 // And. 391 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>; 392 393 // And with complement. 394 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>; 395 396 // Average. 397 def VAVG : BinaryVRRcGeneric<"vavg", 0xE7F2>; 398 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>; 399 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>; 400 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>; 401 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>; 402 403 // Average logical. 404 def VAVGL : BinaryVRRcGeneric<"vavgl", 0xE7F0>; 405 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>; 406 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>; 407 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>; 408 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>; 409 410 // Checksum. 411 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>; 412 413 // Count leading zeros. 414 def VCLZ : UnaryVRRaGeneric<"vclz", 0xE753>; 415 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>; 416 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>; 417 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>; 418 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>; 419 420 // Count trailing zeros. 421 def VCTZ : UnaryVRRaGeneric<"vctz", 0xE752>; 422 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>; 423 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>; 424 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; 425 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; 426 427 // Exclusive or. 428 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; 429 430 // Galois field multiply sum. 431 def VGFM : BinaryVRRcGeneric<"vgfm", 0xE7B4>; 432 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>; 433 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>; 434 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>; 435 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>; 436 437 // Galois field multiply sum and accumulate. 438 def VGFMA : TernaryVRRdGeneric<"vgfma", 0xE7BC>; 439 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>; 440 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>; 441 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>; 442 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>; 443 444 // Load complement. 445 def VLC : UnaryVRRaGeneric<"vlc", 0xE7DE>; 446 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>; 447 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>; 448 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>; 449 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>; 450 451 // Load positive. 452 def VLP : UnaryVRRaGeneric<"vlp", 0xE7DF>; 453 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>; 454 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>; 455 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>; 456 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>; 457 458 // Maximum. 459 def VMX : BinaryVRRcGeneric<"vmx", 0xE7FF>; 460 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>; 461 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>; 462 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>; 463 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>; 464 465 // Maximum logical. 466 def VMXL : BinaryVRRcGeneric<"vmxl", 0xE7FD>; 467 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>; 468 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>; 469 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>; 470 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>; 471 472 // Minimum. 473 def VMN : BinaryVRRcGeneric<"vmn", 0xE7FE>; 474 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>; 475 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>; 476 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>; 477 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>; 478 479 // Minimum logical. 480 def VMNL : BinaryVRRcGeneric<"vmnl", 0xE7FC>; 481 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>; 482 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>; 483 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>; 484 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>; 485 486 // Multiply and add low. 487 def VMAL : TernaryVRRdGeneric<"vmal", 0xE7AA>; 488 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>; 489 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>; 490 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>; 491 492 // Multiply and add high. 493 def VMAH : TernaryVRRdGeneric<"vmah", 0xE7AB>; 494 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>; 495 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>; 496 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>; 497 498 // Multiply and add logical high. 499 def VMALH : TernaryVRRdGeneric<"vmalh", 0xE7A9>; 500 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>; 501 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>; 502 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>; 503 504 // Multiply and add even. 505 def VMAE : TernaryVRRdGeneric<"vmae", 0xE7AE>; 506 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>; 507 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>; 508 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>; 509 510 // Multiply and add logical even. 511 def VMALE : TernaryVRRdGeneric<"vmale", 0xE7AC>; 512 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>; 513 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>; 514 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>; 515 516 // Multiply and add odd. 517 def VMAO : TernaryVRRdGeneric<"vmao", 0xE7AF>; 518 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>; 519 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>; 520 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>; 521 522 // Multiply and add logical odd. 523 def VMALO : TernaryVRRdGeneric<"vmalo", 0xE7AD>; 524 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>; 525 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>; 526 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>; 527 528 // Multiply high. 529 def VMH : BinaryVRRcGeneric<"vmh", 0xE7A3>; 530 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>; 531 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>; 532 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>; 533 534 // Multiply logical high. 535 def VMLH : BinaryVRRcGeneric<"vmlh", 0xE7A1>; 536 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>; 537 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>; 538 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>; 539 540 // Multiply low. 541 def VML : BinaryVRRcGeneric<"vml", 0xE7A2>; 542 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>; 543 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>; 544 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>; 545 546 // Multiply even. 547 def VME : BinaryVRRcGeneric<"vme", 0xE7A6>; 548 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>; 549 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>; 550 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>; 551 552 // Multiply logical even. 553 def VMLE : BinaryVRRcGeneric<"vmle", 0xE7A4>; 554 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>; 555 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>; 556 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>; 557 558 // Multiply odd. 559 def VMO : BinaryVRRcGeneric<"vmo", 0xE7A7>; 560 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>; 561 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>; 562 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>; 563 564 // Multiply logical odd. 565 def VMLO : BinaryVRRcGeneric<"vmlo", 0xE7A5>; 566 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>; 567 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; 568 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; 569 570 // Nor. 571 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; 572 def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; 573 574 // Or. 575 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; 576 577 // Population count. 578 def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; 579 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; 580 581 // Element rotate left logical (with vector shift amount). 582 def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; 583 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb, 584 v128b, v128b, 0>; 585 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh, 586 v128h, v128h, 1>; 587 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf, 588 v128f, v128f, 2>; 589 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg, 590 v128g, v128g, 3>; 591 592 // Element rotate left logical (with scalar shift amount). 593 def VERLL : BinaryVRSaGeneric<"verll", 0xE733>; 594 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>; 595 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>; 596 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>; 597 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>; 598 599 // Element rotate and insert under mask. 600 def VERIM : QuaternaryVRIdGeneric<"verim", 0xE772>; 601 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>; 602 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>; 603 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>; 604 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>; 605 606 // Element shift left (with vector shift amount). 607 def VESLV : BinaryVRRcGeneric<"veslv", 0xE770>; 608 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>; 609 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>; 610 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>; 611 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>; 612 613 // Element shift left (with scalar shift amount). 614 def VESL : BinaryVRSaGeneric<"vesl", 0xE730>; 615 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>; 616 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>; 617 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>; 618 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>; 619 620 // Element shift right arithmetic (with vector shift amount). 621 def VESRAV : BinaryVRRcGeneric<"vesrav", 0xE77A>; 622 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>; 623 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>; 624 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>; 625 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>; 626 627 // Element shift right arithmetic (with scalar shift amount). 628 def VESRA : BinaryVRSaGeneric<"vesra", 0xE73A>; 629 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>; 630 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>; 631 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>; 632 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>; 633 634 // Element shift right logical (with vector shift amount). 635 def VESRLV : BinaryVRRcGeneric<"vesrlv", 0xE778>; 636 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>; 637 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>; 638 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>; 639 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>; 640 641 // Element shift right logical (with scalar shift amount). 642 def VESRL : BinaryVRSaGeneric<"vesrl", 0xE738>; 643 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>; 644 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>; 645 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>; 646 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>; 647 648 // Shift left. 649 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>; 650 651 // Shift left by byte. 652 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>; 653 654 // Shift left double by byte. 655 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>; 656 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8:$z), 657 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>; 658 659 // Shift right arithmetic. 660 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>; 661 662 // Shift right arithmetic by byte. 663 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>; 664 665 // Shift right logical. 666 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>; 667 668 // Shift right logical by byte. 669 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>; 670 671 // Subtract. 672 def VS : BinaryVRRcGeneric<"vs", 0xE7F7>; 673 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>; 674 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>; 675 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>; 676 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>; 677 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>; 678 679 // Subtract compute borrow indication. 680 def VSCBI : BinaryVRRcGeneric<"vscbi", 0xE7F5>; 681 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>; 682 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>; 683 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>; 684 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>; 685 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>; 686 687 // Subtract with borrow indication. 688 def VSBI : TernaryVRRdGeneric<"vsbi", 0xE7BF>; 689 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>; 690 691 // Subtract with borrow compute borrow indication. 692 def VSBCBI : TernaryVRRdGeneric<"vsbcbi", 0xE7BD>; 693 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq, 694 v128q, v128q, 4>; 695 696 // Sum across doubleword. 697 def VSUMG : BinaryVRRcGeneric<"vsumg", 0xE765>; 698 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>; 699 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>; 700 701 // Sum across quadword. 702 def VSUMQ : BinaryVRRcGeneric<"vsumq", 0xE767>; 703 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>; 704 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>; 705 706 // Sum across word. 707 def VSUM : BinaryVRRcGeneric<"vsum", 0xE764>; 708 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>; 709 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>; 710} 711 712// Instantiate the bitwise ops for type TYPE. 713multiclass BitwiseVectorOps<ValueType type> { 714 let Predicates = [FeatureVector] in { 715 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>; 716 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))), 717 (VNC VR128:$x, VR128:$y)>; 718 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>; 719 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>; 720 def : Pat<(type (or (and VR128:$x, VR128:$z), 721 (and VR128:$y, (z_vnot VR128:$z)))), 722 (VSEL VR128:$x, VR128:$y, VR128:$z)>; 723 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))), 724 (VNO VR128:$x, VR128:$y)>; 725 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; 726 } 727} 728 729defm : BitwiseVectorOps<v16i8>; 730defm : BitwiseVectorOps<v8i16>; 731defm : BitwiseVectorOps<v4i32>; 732defm : BitwiseVectorOps<v2i64>; 733 734// Instantiate additional patterns for absolute-related expressions on 735// type TYPE. LC is the negate instruction for TYPE and LP is the absolute 736// instruction. 737multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc, 738 Instruction lp, int shift> { 739 let Predicates = [FeatureVector] in { 740 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)), 741 (z_vneg VR128:$x), VR128:$x)), 742 (lc (lp VR128:$x))>; 743 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))), 744 VR128:$x, (z_vneg VR128:$x))), 745 (lc (lp VR128:$x))>; 746 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)), 747 VR128:$x, (z_vneg VR128:$x))), 748 (lc (lp VR128:$x))>; 749 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))), 750 (z_vneg VR128:$x), VR128:$x)), 751 (lc (lp VR128:$x))>; 752 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 753 (z_vneg VR128:$x)), 754 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 755 VR128:$x))), 756 (lp VR128:$x)>; 757 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)), 758 VR128:$x), 759 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))), 760 (z_vneg VR128:$x)))), 761 (lc (lp VR128:$x))>; 762 } 763} 764 765defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>; 766defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>; 767defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>; 768defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>; 769 770// Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the 771// signed or unsigned "set if greater than" comparison instruction and 772// MIN and MAX are the associated minimum and maximum instructions. 773multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph, 774 Instruction min, Instruction max> { 775 let Predicates = [FeatureVector] in { 776 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)), 777 (max VR128:$x, VR128:$y)>; 778 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)), 779 (min VR128:$x, VR128:$y)>; 780 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 781 VR128:$x, VR128:$y)), 782 (min VR128:$x, VR128:$y)>; 783 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)), 784 VR128:$y, VR128:$x)), 785 (max VR128:$x, VR128:$y)>; 786 } 787} 788 789// Signed min/max. 790defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>; 791defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>; 792defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>; 793defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>; 794 795// Unsigned min/max. 796defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>; 797defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>; 798defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>; 799defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>; 800 801//===----------------------------------------------------------------------===// 802// Integer comparison 803//===----------------------------------------------------------------------===// 804 805let Predicates = [FeatureVector] in { 806 // Element compare. 807 let Defs = [CC] in { 808 def VEC : CompareVRRaGeneric<"vec", 0xE7DB>; 809 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>; 810 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>; 811 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>; 812 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>; 813 } 814 815 // Element compare logical. 816 let Defs = [CC] in { 817 def VECL : CompareVRRaGeneric<"vecl", 0xE7D9>; 818 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>; 819 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>; 820 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>; 821 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>; 822 } 823 824 // Compare equal. 825 def VCEQ : BinaryVRRbSPairGeneric<"vceq", 0xE7F8>; 826 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes, 827 v128b, v128b, 0>; 828 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes, 829 v128h, v128h, 1>; 830 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes, 831 v128f, v128f, 2>; 832 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes, 833 v128g, v128g, 3>; 834 835 // Compare high. 836 def VCH : BinaryVRRbSPairGeneric<"vch", 0xE7FB>; 837 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs, 838 v128b, v128b, 0>; 839 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs, 840 v128h, v128h, 1>; 841 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs, 842 v128f, v128f, 2>; 843 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs, 844 v128g, v128g, 3>; 845 846 // Compare high logical. 847 def VCHL : BinaryVRRbSPairGeneric<"vchl", 0xE7F9>; 848 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls, 849 v128b, v128b, 0>; 850 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls, 851 v128h, v128h, 1>; 852 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls, 853 v128f, v128f, 2>; 854 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls, 855 v128g, v128g, 3>; 856 857 // Test under mask. 858 let Defs = [CC] in 859 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>; 860} 861 862//===----------------------------------------------------------------------===// 863// Floating-point arithmetic 864//===----------------------------------------------------------------------===// 865 866// See comments in SystemZInstrFP.td for the suppression flags and 867// rounding modes. 868multiclass VectorRounding<Instruction insn, TypedReg tr> { 869 def : FPConversion<insn, frint, tr, tr, 0, 0>; 870 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>; 871 def : FPConversion<insn, ffloor, tr, tr, 4, 7>; 872 def : FPConversion<insn, fceil, tr, tr, 4, 6>; 873 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>; 874 def : FPConversion<insn, fround, tr, tr, 4, 1>; 875} 876 877let Predicates = [FeatureVector] in { 878 // Add. 879 def VFA : BinaryVRRcFloatGeneric<"vfa", 0xE7E3>; 880 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>; 881 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, fadd, v64db, v64db, 3, 8>; 882 883 // Convert from fixed 64-bit. 884 def VCDG : TernaryVRRaFloatGeneric<"vcdg", 0xE7C3>; 885 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>; 886 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>; 887 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>; 888 889 // Convert from logical 64-bit. 890 def VCDLG : TernaryVRRaFloatGeneric<"vcdlg", 0xE7C1>; 891 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>; 892 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>; 893 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>; 894 895 // Convert to fixed 64-bit. 896 def VCGD : TernaryVRRaFloatGeneric<"vcgd", 0xE7C2>; 897 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>; 898 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>; 899 // Rounding mode should agree with SystemZInstrFP.td. 900 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>; 901 902 // Convert to logical 64-bit. 903 def VCLGD : TernaryVRRaFloatGeneric<"vclgd", 0xE7C0>; 904 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>; 905 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>; 906 // Rounding mode should agree with SystemZInstrFP.td. 907 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>; 908 909 // Divide. 910 def VFD : BinaryVRRcFloatGeneric<"vfd", 0xE7E5>; 911 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>; 912 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, fdiv, v64db, v64db, 3, 8>; 913 914 // Load FP integer. 915 def VFI : TernaryVRRaFloatGeneric<"vfi", 0xE7C7>; 916 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>; 917 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>; 918 defm : VectorRounding<VFIDB, v128db>; 919 defm : VectorRounding<WFIDB, v64db>; 920 921 // Load lengthened. 922 def VLDE : UnaryVRRaFloatGeneric<"vlde", 0xE7C4>; 923 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128eb, 2, 0>; 924 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, fpextend, v64db, v32eb, 2, 8>; 925 926 // Load rounded, 927 def VLED : TernaryVRRaFloatGeneric<"vled", 0xE7C5>; 928 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>; 929 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>; 930 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; 931 def : FPConversion<WLEDB, fpround, v32eb, v64db, 0, 0>; 932 933 // Multiply. 934 def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; 935 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>; 936 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, fmul, v64db, v64db, 3, 8>; 937 938 // Multiply and add. 939 def VFMA : TernaryVRReFloatGeneric<"vfma", 0xE78F>; 940 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>; 941 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, fma, v64db, v64db, 8, 3>; 942 943 // Multiply and subtract. 944 def VFMS : TernaryVRReFloatGeneric<"vfms", 0xE78E>; 945 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>; 946 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>; 947 948 // Perform sign operation. 949 def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; 950 def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; 951 def WFPSODB : BinaryVRRa<"wfpsodb", 0xE7CC, null_frag, v64db, v64db, 3, 8>; 952 953 // Load complement. 954 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>; 955 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>; 956 957 // Load negative. 958 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>; 959 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>; 960 961 // Load positive. 962 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>; 963 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>; 964 965 // Square root. 966 def VFSQ : UnaryVRRaFloatGeneric<"vfsq", 0xE7CE>; 967 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>; 968 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, fsqrt, v64db, v64db, 3, 8>; 969 970 // Subtract. 971 def VFS : BinaryVRRcFloatGeneric<"vfs", 0xE7E2>; 972 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>; 973 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, fsub, v64db, v64db, 3, 8>; 974 975 // Test data class immediate. 976 let Defs = [CC] in { 977 def VFTCI : BinaryVRIeFloatGeneric<"vftci", 0xE74A>; 978 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>; 979 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>; 980 } 981} 982 983//===----------------------------------------------------------------------===// 984// Floating-point comparison 985//===----------------------------------------------------------------------===// 986 987let Predicates = [FeatureVector] in { 988 // Compare scalar. 989 let Defs = [CC] in { 990 def WFC : CompareVRRaFloatGeneric<"wfc", 0xE7CB>; 991 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>; 992 } 993 994 // Compare and signal scalar. 995 let Defs = [CC] in { 996 def WFK : CompareVRRaFloatGeneric<"wfk", 0xE7CA>; 997 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>; 998 } 999 1000 // Compare equal. 1001 def VFCE : BinaryVRRcSPairFloatGeneric<"vfce", 0xE7E8>; 1002 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, z_vfcmpes, 1003 v128g, v128db, 3, 0>; 1004 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, 1005 v64g, v64db, 3, 8>; 1006 1007 // Compare high. 1008 def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; 1009 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs, 1010 v128g, v128db, 3, 0>; 1011 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, 1012 v64g, v64db, 3, 8>; 1013 1014 // Compare high or equal. 1015 def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; 1016 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes, 1017 v128g, v128db, 3, 0>; 1018 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, 1019 v64g, v64db, 3, 8>; 1020} 1021 1022//===----------------------------------------------------------------------===// 1023// Conversions 1024//===----------------------------------------------------------------------===// 1025 1026def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>; 1027def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>; 1028def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>; 1029def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>; 1030def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>; 1031 1032def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>; 1033def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>; 1034def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>; 1035def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>; 1036def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>; 1037 1038def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>; 1039def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>; 1040def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>; 1041def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>; 1042def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>; 1043 1044def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>; 1045def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>; 1046def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>; 1047def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>; 1048def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>; 1049 1050def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>; 1051def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>; 1052def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>; 1053def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>; 1054def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>; 1055 1056def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>; 1057def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>; 1058def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>; 1059def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>; 1060def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>; 1061 1062//===----------------------------------------------------------------------===// 1063// Replicating scalars 1064//===----------------------------------------------------------------------===// 1065 1066// Define patterns for replicating a scalar GR32 into a vector of type TYPE. 1067// INDEX is 8 minus the element size in bytes. 1068class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index> 1069 : Pat<(type (z_replicate GR32:$scalar)), 1070 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>; 1071 1072def : VectorReplicateScalar<v16i8, VREPB, 7>; 1073def : VectorReplicateScalar<v8i16, VREPH, 3>; 1074def : VectorReplicateScalar<v4i32, VREPF, 1>; 1075 1076// i64 replications are just a single isntruction. 1077def : Pat<(v2i64 (z_replicate GR64:$scalar)), 1078 (VLVGP GR64:$scalar, GR64:$scalar)>; 1079 1080//===----------------------------------------------------------------------===// 1081// Floating-point insertion and extraction 1082//===----------------------------------------------------------------------===// 1083 1084// Moving 32-bit values between GPRs and FPRs can be done using VLVGF 1085// and VLGVF. 1086let Predicates = [FeatureVector] in { 1087 def LEFR : UnaryAliasVRS<VR32, GR32>; 1088 def LFER : UnaryAliasVRS<GR64, VR32>; 1089 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>; 1090 def : Pat<(i32 (bitconvert (f32 VR32:$src))), 1091 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>; 1092} 1093 1094// Floating-point values are stored in element 0 of the corresponding 1095// vector register. Scalar to vector conversion is just a subreg and 1096// scalar replication can just replicate element 0 of the vector register. 1097multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls, 1098 SubRegIndex subreg> { 1099 def : Pat<(vt (scalar_to_vector cls:$scalar)), 1100 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>; 1101 def : Pat<(vt (z_replicate cls:$scalar)), 1102 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, 1103 subreg), 0)>; 1104} 1105defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_r32>; 1106defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>; 1107 1108// Match v2f64 insertions. The AddedComplexity counters the 3 added by 1109// TableGen for the base register operand in VLVG-based integer insertions 1110// and ensures that this version is strictly better. 1111let AddedComplexity = 4 in { 1112 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0), 1113 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1114 subreg_r64), VR128:$vec, 1)>; 1115 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1), 1116 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt, 1117 subreg_r64), 0)>; 1118} 1119 1120// We extract floating-point element X by replicating (for elements other 1121// than 0) and then taking a high subreg. The AddedComplexity counters the 1122// 3 added by TableGen for the base register operand in VLGV-based integer 1123// extractions and ensures that this version is strictly better. 1124let AddedComplexity = 4 in { 1125 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)), 1126 (EXTRACT_SUBREG VR128:$vec, subreg_r32)>; 1127 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)), 1128 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_r32)>; 1129 1130 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)), 1131 (EXTRACT_SUBREG VR128:$vec, subreg_r64)>; 1132 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)), 1133 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>; 1134} 1135 1136//===----------------------------------------------------------------------===// 1137// String instructions 1138//===----------------------------------------------------------------------===// 1139 1140let Predicates = [FeatureVector] in { 1141 defm VFAE : TernaryOptVRRbSPairGeneric<"vfae", 0xE782>; 1142 defm VFAEB : TernaryOptVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, 1143 z_vfae_cc, v128b, v128b, 0>; 1144 defm VFAEH : TernaryOptVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, 1145 z_vfae_cc, v128h, v128h, 1>; 1146 defm VFAEF : TernaryOptVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, 1147 z_vfae_cc, v128f, v128f, 2>; 1148 defm VFAEZB : TernaryOptVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, 1149 z_vfaez_cc, v128b, v128b, 0, 2>; 1150 defm VFAEZH : TernaryOptVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, 1151 z_vfaez_cc, v128h, v128h, 1, 2>; 1152 defm VFAEZF : TernaryOptVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, 1153 z_vfaez_cc, v128f, v128f, 2, 2>; 1154 1155 defm VFEE : BinaryExtraVRRbSPairGeneric<"vfee", 0xE780>; 1156 defm VFEEB : BinaryExtraVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, 1157 z_vfee_cc, v128b, v128b, 0>; 1158 defm VFEEH : BinaryExtraVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, 1159 z_vfee_cc, v128h, v128h, 1>; 1160 defm VFEEF : BinaryExtraVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, 1161 z_vfee_cc, v128f, v128f, 2>; 1162 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, 1163 z_vfeez_cc, v128b, v128b, 0, 2>; 1164 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, 1165 z_vfeez_cc, v128h, v128h, 1, 2>; 1166 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, 1167 z_vfeez_cc, v128f, v128f, 2, 2>; 1168 1169 defm VFENE : BinaryExtraVRRbSPairGeneric<"vfene", 0xE781>; 1170 defm VFENEB : BinaryExtraVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, 1171 z_vfene_cc, v128b, v128b, 0>; 1172 defm VFENEH : BinaryExtraVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, 1173 z_vfene_cc, v128h, v128h, 1>; 1174 defm VFENEF : BinaryExtraVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, 1175 z_vfene_cc, v128f, v128f, 2>; 1176 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb, 1177 z_vfenez_cc, v128b, v128b, 0, 2>; 1178 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh, 1179 z_vfenez_cc, v128h, v128h, 1, 2>; 1180 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf, 1181 z_vfenez_cc, v128f, v128f, 2, 2>; 1182 1183 defm VISTR : UnaryExtraVRRaSPairGeneric<"vistr", 0xE75C>; 1184 defm VISTRB : UnaryExtraVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, 1185 z_vistr_cc, v128b, v128b, 0>; 1186 defm VISTRH : UnaryExtraVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, 1187 z_vistr_cc, v128h, v128h, 1>; 1188 defm VISTRF : UnaryExtraVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, 1189 z_vistr_cc, v128f, v128f, 2>; 1190 1191 defm VSTRC : QuaternaryOptVRRdSPairGeneric<"vstrc", 0xE78A>; 1192 defm VSTRCB : QuaternaryOptVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb, 1193 z_vstrc_cc, v128b, v128b, 0>; 1194 defm VSTRCH : QuaternaryOptVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch, 1195 z_vstrc_cc, v128h, v128h, 1>; 1196 defm VSTRCF : QuaternaryOptVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf, 1197 z_vstrc_cc, v128f, v128f, 2>; 1198 defm VSTRCZB : QuaternaryOptVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb, 1199 z_vstrcz_cc, v128b, v128b, 0, 2>; 1200 defm VSTRCZH : QuaternaryOptVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh, 1201 z_vstrcz_cc, v128h, v128h, 1, 2>; 1202 defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, 1203 z_vstrcz_cc, v128f, v128f, 2, 2>; 1204} 1205