1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Stack allocation
12//===----------------------------------------------------------------------===//
13
14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15                              [(callseq_start timm:$amt)]>;
16def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17                              [(callseq_end timm:$amt1, timm:$amt2)]>;
18
19let hasSideEffects = 0 in {
20  // Takes as input the value of the stack pointer after a dynamic allocation
21  // has been made.  Sets the output to the address of the dynamically-
22  // allocated area itself, skipping the outgoing arguments.
23  //
24  // This expands to an LA or LAY instruction.  We restrict the offset
25  // to the range of LA and keep the LAY range in reserve for when
26  // the size of the outgoing arguments is added.
27  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28                           [(set GR64:$dst, dynalloc12only:$src)]>;
29}
30
31//===----------------------------------------------------------------------===//
32// Control flow instructions
33//===----------------------------------------------------------------------===//
34
35// A return instruction (br %r14).
36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37  def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
38
39// A conditional return instruction (bcr <cond>, %r14).
40let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in
41  def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
42
43// Fused compare and conditional returns.
44let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in {
45  def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
46  def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
47  def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
48  def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
49  def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
50  def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
51  def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
52  def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
53}
54
55// Unconditional branches.  R1 is the condition-code mask (all 1s).
56let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
57  let isIndirectBranch = 1 in
58    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
59                    "br\t$R2", [(brind ADDR64:$R2)]>;
60
61  // An assembler extended mnemonic for BRC.
62  def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
63                 [(br bb:$I2)]>;
64
65  // An assembler extended mnemonic for BRCL.  (The extension is "G"
66  // rather than "L" because "JL" is "Jump if Less".)
67  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
68}
69
70// FIXME: This trap instruction should be marked as isTerminator, but there is
71// currently a general bug that allows non-terminators to be placed between
72// terminators. Temporarily leave this unmarked until the bug is fixed.
73let isBarrier = 1, hasCtrlDep = 1 in {
74  def Trap : Alias<4, (outs), (ins), [(trap)]>;
75}
76
77let isTerminator = 1, hasCtrlDep = 1, Uses = [CC] in {
78  def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>;
79}
80
81// Conditional branches.  It's easier for LLVM to handle these branches
82// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
83// the first operand.  It seems friendlier to use mnemonic forms like
84// JE and JLH when writing out the assembly though.
85let isBranch = 1, isTerminator = 1, Uses = [CC] in {
86  let isCodeGenOnly = 1, CCMaskFirst = 1 in {
87    def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
88                                         brtarget16:$I2), "j$R1\t$I2",
89                     [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
90    def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
91                                           brtarget32:$I2), "jg$R1\t$I2", []>;
92    let isIndirectBranch = 1 in
93      def BCR : InstRR<0x07, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
94                       "b${R1}r\t$R2", []>;
95  }
96  def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2),
97                      "brc\t$R1, $I2", []>;
98  def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2),
99                        "brcl\t$R1, $I2", []>;
100  let isIndirectBranch = 1 in {
101    def AsmBC : InstRX<0x47, (outs), (ins imm32zx4:$R1, bdxaddr12only:$XBD2),
102                       "bc\t$R1, $XBD2", []>;
103    def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2),
104                        "bcr\t$R1, $R2", []>;
105  }
106}
107
108def AsmNop  : InstAlias<"nop\t$XBD", (AsmBC 0, bdxaddr12only:$XBD), 0>;
109def AsmNopR : InstAlias<"nopr\t$R", (AsmBCR 0, GR64:$R), 0>;
110
111// Fused compare-and-branch instructions.  As for normal branches,
112// we handle these instructions internally in their raw CRJ-like form,
113// but use assembly macros like CRJE when writing them out.
114//
115// These instructions do not use or clobber the condition codes.
116// We nevertheless pretend that they clobber CC, so that we can lower
117// them to separate comparisons and BRCLs if the branch ends up being
118// out of range.
119multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
120  let isBranch = 1, isTerminator = 1, Defs = [CC] in {
121    def RJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
122                                            brtarget16:$RI4),
123                       "crj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>;
124    def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
125                                            brtarget16:$RI4),
126                       "cgrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>;
127    def IJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
128                                            brtarget16:$RI4),
129                       "cij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>;
130    def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
131                                            brtarget16:$RI4),
132                       "cgij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>;
133    def LRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
134                                             brtarget16:$RI4),
135                        "clrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>;
136    def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
137                                             brtarget16:$RI4),
138                        "clgrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>;
139    def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
140                                             brtarget16:$RI4),
141                        "clij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>;
142    def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
143                                             brtarget16:$RI4),
144                        "clgij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>;
145    let isIndirectBranch = 1 in {
146      def RB  : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
147                                             bdaddr12only:$BD4),
148                        "crb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>;
149      def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
150                                             bdaddr12only:$BD4),
151                        "cgrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>;
152      def IB  : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
153                                             bdaddr12only:$BD4),
154                        "cib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>;
155      def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
156                                             bdaddr12only:$BD4),
157                        "cgib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>;
158      def LRB  : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
159                                              bdaddr12only:$BD4),
160                         "clrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>;
161      def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
162                                              bdaddr12only:$BD4),
163                         "clgrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>;
164      def LIB  : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
165                                              bdaddr12only:$BD4),
166                         "clib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>;
167      def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
168                                              bdaddr12only:$BD4),
169                         "clgib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>;
170    }
171  }
172
173  let isTerminator = 1, hasCtrlDep = 1 in {
174    def RT   : InstRRFc<0xB972, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3),
175                        "crt"##pos1##"\t$R1, $R2"##pos2, []>;
176    def GRT  : InstRRFc<0xB960, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3),
177                        "cgrt"##pos1##"\t$R1, $R2"##pos2, []>;
178    def LRT  : InstRRFc<0xB973, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3),
179                        "clrt"##pos1##"\t$R1, $R2"##pos2, []>;
180    def LGRT : InstRRFc<0xB961, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3),
181                        "clgrt"##pos1##"\t$R1, $R2"##pos2, []>;
182    def IT   : InstRIEa<0xEC72, (outs), (ins GR32:$R1, imm32sx16:$I2, ccmask:$M3),
183                         "cit"##pos1##"\t$R1, $I2"##pos2, []>;
184    def GIT  : InstRIEa<0xEC70, (outs), (ins GR64:$R1, imm32sx16:$I2, ccmask:$M3),
185                         "cgit"##pos1##"\t$R1, $I2"##pos2, []>;
186    def LFIT : InstRIEa<0xEC73, (outs), (ins GR32:$R1, imm32zx16:$I2, ccmask:$M3),
187                         "clfit"##pos1##"\t$R1, $I2"##pos2, []>;
188    def LGIT : InstRIEa<0xEC71, (outs), (ins GR64:$R1, imm32zx16:$I2, ccmask:$M3),
189                         "clgit"##pos1##"\t$R1, $I2"##pos2, []>;
190  }
191}
192let isCodeGenOnly = 1 in
193  defm C : CompareBranches<cond4, "$M3", "">;
194defm AsmC : CompareBranches<imm32zx4, "", ", $M3">;
195
196// Define AsmParser mnemonics for each general condition-code mask
197// (integer or floating-point)
198multiclass CondExtendedMnemonicA<bits<4> ccmask, string name> {
199  let isBranch = 1, isTerminator = 1, R1 = ccmask in {
200    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
201                   "j"##name##"\t$I2", []>;
202    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
203                     "jg"##name##"\t$I2", []>;
204    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>;
205  }
206  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
207  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
208  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
209  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
210  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
211  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
212}
213
214multiclass CondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
215  : CondExtendedMnemonicA<ccmask, name1> {
216  let isAsmParserOnly = 1 in
217    defm Alt : CondExtendedMnemonicA<ccmask, name2>;
218}
219
220defm AsmO   : CondExtendedMnemonicA<1,  "o">;
221defm AsmH   : CondExtendedMnemonic<2,  "h", "p">;
222defm AsmNLE : CondExtendedMnemonicA<3,  "nle">;
223defm AsmL   : CondExtendedMnemonic<4,  "l", "m">;
224defm AsmNHE : CondExtendedMnemonicA<5,  "nhe">;
225defm AsmLH  : CondExtendedMnemonicA<6,  "lh">;
226defm AsmNE  : CondExtendedMnemonic<7,  "ne", "nz">;
227defm AsmE   : CondExtendedMnemonic<8,  "e", "z">;
228defm AsmNLH : CondExtendedMnemonicA<9,  "nlh">;
229defm AsmHE  : CondExtendedMnemonicA<10, "he">;
230defm AsmNL  : CondExtendedMnemonic<11, "nl", "nm">;
231defm AsmLE  : CondExtendedMnemonicA<12, "le">;
232defm AsmNH  : CondExtendedMnemonic<13, "nh", "np">;
233defm AsmNO  : CondExtendedMnemonicA<14, "no">;
234
235// Define AsmParser mnemonics for each integer condition-code mask.
236// This is like the list above, except that condition 3 is not possible
237// and that the low bit of the mask is therefore always 0.  This means
238// that each condition has two names.  Conditions "o" and "no" are not used.
239//
240// We don't make one of the two names an alias of the other because
241// we need the custom parsing routines to select the correct register class.
242multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
243  let isBranch = 1, isTerminator = 1, M3 = ccmask in {
244    def CRJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
245                                             brtarget16:$RI4),
246                        "crj"##name##"\t$R1, $R2, $RI4", []>;
247    def CGRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
248                                             brtarget16:$RI4),
249                        "cgrj"##name##"\t$R1, $R2, $RI4", []>;
250    def CIJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
251                                             brtarget16:$RI4),
252                        "cij"##name##"\t$R1, $I2, $RI4", []>;
253    def CGIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
254                                             brtarget16:$RI4),
255                        "cgij"##name##"\t$R1, $I2, $RI4", []>;
256    def CLRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
257                                             brtarget16:$RI4),
258                         "clrj"##name##"\t$R1, $R2, $RI4", []>;
259    def CLGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
260                                              brtarget16:$RI4),
261                         "clgrj"##name##"\t$R1, $R2, $RI4", []>;
262    def CLIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
263                                              brtarget16:$RI4),
264                         "clij"##name##"\t$R1, $I2, $RI4", []>;
265    def CLGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
266                                              brtarget16:$RI4),
267                         "clgij"##name##"\t$R1, $I2, $RI4", []>;
268    let isIndirectBranch = 1 in {
269      def CRB  : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2,
270                                              bdaddr12only:$BD4),
271                         "crb"##name##"\t$R1, $R2, $BD4", []>;
272      def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2,
273                                              bdaddr12only:$BD4),
274                         "cgrb"##name##"\t$R1, $R2, $BD4", []>;
275      def CIB  : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2,
276                                              bdaddr12only:$BD4),
277                         "cib"##name##"\t$R1, $I2, $BD4", []>;
278      def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2,
279                                              bdaddr12only:$BD4),
280                         "cgib"##name##"\t$R1, $I2, $BD4", []>;
281      def CLRB  : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2,
282                                              bdaddr12only:$BD4),
283                          "clrb"##name##"\t$R1, $R2, $BD4", []>;
284      def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2,
285                                               bdaddr12only:$BD4),
286                          "clgrb"##name##"\t$R1, $R2, $BD4", []>;
287      def CLIB  : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2,
288                                               bdaddr12only:$BD4),
289                          "clib"##name##"\t$R1, $I2, $BD4", []>;
290      def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2,
291                                               bdaddr12only:$BD4),
292                          "clgib"##name##"\t$R1, $I2, $BD4", []>;
293    }
294  }
295
296  let hasCtrlDep = 1, isTerminator = 1, M3 = ccmask in {
297      def CRT   : InstRRFc<0xB972, (outs), (ins GR32:$R1, GR32:$R2),
298                          "crt"##name##"\t$R1, $R2", []>;
299      def CGRT  : InstRRFc<0xB960, (outs), (ins GR64:$R1, GR64:$R2),
300                          "cgrt"##name##"\t$R1, $R2", []>;
301      def CLRT  : InstRRFc<0xB973, (outs), (ins GR32:$R1, GR32:$R2),
302                          "clrt"##name##"\t$R1, $R2", []>;
303      def CLGRT : InstRRFc<0xB961, (outs), (ins GR64:$R1, GR64:$R2),
304                          "clgrt"##name##"\t$R1, $R2", []>;
305      def CIT   : InstRIEa<0xEC72, (outs), (ins GR32:$R1, imm32sx16:$I2),
306                           "cit"##name##"\t$R1, $I2", []>;
307      def CGIT  : InstRIEa<0xEC70, (outs), (ins GR64:$R1, imm32sx16:$I2),
308                           "cgit"##name##"\t$R1, $I2", []>;
309      def CLFIT : InstRIEa<0xEC73, (outs), (ins GR32:$R1, imm32zx16:$I2),
310                           "clfit"##name##"\t$R1, $I2", []>;
311      def CLGIT : InstRIEa<0xEC71, (outs), (ins GR64:$R1, imm32zx16:$I2),
312                           "clgit"##name##"\t$R1, $I2", []>;
313  }
314}
315multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
316  : IntCondExtendedMnemonicA<ccmask, name1> {
317  let isAsmParserOnly = 1 in
318    defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
319}
320defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
321defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
322defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;
323defm AsmJE   : IntCondExtendedMnemonic<8,  "e",  "nlh">;
324defm AsmJHE  : IntCondExtendedMnemonic<10, "he", "nl">;
325defm AsmJLE  : IntCondExtendedMnemonic<12, "le", "nh">;
326
327// Decrement a register and branch if it is nonzero.  These don't clobber CC,
328// but we might need to split long branches into sequences that do.
329let Defs = [CC] in {
330  def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
331  def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
332}
333
334//===----------------------------------------------------------------------===//
335// Select instructions
336//===----------------------------------------------------------------------===//
337
338def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
339def Select32    : SelectWrapper<GR32>;
340def Select64    : SelectWrapper<GR64>;
341
342// We don't define 32-bit Mux stores because the low-only STOC should
343// always be used if possible.
344defm CondStore8Mux  : CondStores<GRX32, nonvolatile_truncstorei8,
345                                 nonvolatile_anyextloadi8, bdxaddr20only>,
346                      Requires<[FeatureHighWord]>;
347defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
348                                 nonvolatile_anyextloadi16, bdxaddr20only>,
349                      Requires<[FeatureHighWord]>;
350defm CondStore8     : CondStores<GR32, nonvolatile_truncstorei8,
351                                 nonvolatile_anyextloadi8, bdxaddr20only>;
352defm CondStore16    : CondStores<GR32, nonvolatile_truncstorei16,
353                                 nonvolatile_anyextloadi16, bdxaddr20only>;
354defm CondStore32    : CondStores<GR32, nonvolatile_store,
355                                 nonvolatile_load, bdxaddr20only>;
356
357defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
358                    nonvolatile_anyextloadi8, bdxaddr20only>;
359defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
360                    nonvolatile_anyextloadi16, bdxaddr20only>;
361defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
362                    nonvolatile_anyextloadi32, bdxaddr20only>;
363defm CondStore64 : CondStores<GR64, nonvolatile_store,
364                              nonvolatile_load, bdxaddr20only>;
365
366//===----------------------------------------------------------------------===//
367// Call instructions
368//===----------------------------------------------------------------------===//
369
370let isCall = 1, Defs = [R14D, CC] in {
371  def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
372                        [(z_call pcrel32:$I2)]>;
373  def CallBASR  : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
374                        [(z_call ADDR64:$R2)]>;
375}
376
377// Sibling calls.  Indirect sibling calls must be via R1, since R2 upwards
378// are argument registers and since branching to R0 is a no-op.
379let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
380  def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
381                     [(z_sibcall pcrel32:$I2)]>;
382  let Uses = [R1D] in
383    def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
384}
385
386let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {
387  def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
388                                   pcrel32:$I2), []>;
389
390  let Uses = [R1D] in
391    def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
392}
393
394// Fused compare and conditional sibling calls.
395let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in {
396  def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
397  def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
398  def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
399  def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
400  def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
401  def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
402  def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
403  def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
404}
405
406// TLS calls.  These will be lowered into a call to __tls_get_offset,
407// with an extra relocation specifying the TLS symbol.
408let isCall = 1, Defs = [R14D, CC] in {
409  def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
410                         [(z_tls_gdcall tglobaltlsaddr:$I2)]>;
411  def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
412                         [(z_tls_ldcall tglobaltlsaddr:$I2)]>;
413}
414
415// Define the general form of the call instructions for the asm parser.
416// These instructions don't hard-code %r14 as the return address register.
417// Allow an optional TLS marker symbol to generate TLS call relocations.
418let isCall = 1, Defs = [CC] in {
419  def BRAS  : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16tls:$I2),
420                     "bras\t$R1, $I2", []>;
421  def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32tls:$I2),
422                      "brasl\t$R1, $I2", []>;
423  def BASR  : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
424                     "basr\t$R1, $R2", []>;
425}
426
427//===----------------------------------------------------------------------===//
428// Move instructions
429//===----------------------------------------------------------------------===//
430
431// Register moves.
432let hasSideEffects = 0 in {
433  // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
434  def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
435              Requires<[FeatureHighWord]>;
436  def LR  : UnaryRR <"l",  0x18,   null_frag, GR32, GR32>;
437  def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
438}
439let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
440  def LTR  : UnaryRR <"lt",  0x12,   null_frag, GR32, GR32>;
441  def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
442}
443
444// Move on condition.
445let isCodeGenOnly = 1, Uses = [CC] in {
446  def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
447  def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
448}
449let Uses = [CC] in {
450  def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
451  def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
452}
453
454// Immediate moves.
455let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
456    isReMaterializable = 1 in {
457  // 16-bit sign-extended immediates.  LHIMux expands to LHI or IIHF,
458  // deopending on the choice of register.
459  def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
460               Requires<[FeatureHighWord]>;
461  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
462  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
463
464  // Other 16-bit immediates.
465  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
466  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
467  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
468  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
469
470  // 32-bit immediates.
471  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
472  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
473  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
474}
475
476// Register loads.
477let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
478  // Expands to L, LY or LFH, depending on the choice of register.
479  def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
480             Requires<[FeatureHighWord]>;
481  defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
482  def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
483            Requires<[FeatureHighWord]>;
484  def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
485
486  // These instructions are split after register allocation, so we don't
487  // want a custom inserter.
488  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
489    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
490                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
491  }
492}
493let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
494  def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
495  def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
496}
497
498let canFoldAsLoad = 1 in {
499  def LRL  : UnaryRILPC<"lrl",  0xC4D, aligned_load, GR32>;
500  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
501}
502
503// Load on condition.
504let isCodeGenOnly = 1, Uses = [CC] in {
505  def LOC  : CondUnaryRSY<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
506  def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
507}
508let Uses = [CC] in {
509  def AsmLOC  : AsmCondUnaryRSY<"loc",  0xEBF2, GR32, 4>;
510  def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
511}
512
513// Register stores.
514let SimpleBDXStore = 1 in {
515  // Expands to ST, STY or STFH, depending on the choice of register.
516  def STMux : StoreRXYPseudo<store, GRX32, 4>,
517              Requires<[FeatureHighWord]>;
518  defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
519  def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
520             Requires<[FeatureHighWord]>;
521  def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
522
523  // These instructions are split after register allocation, so we don't
524  // want a custom inserter.
525  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
526    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
527                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
528  }
529}
530def STRL  : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
531def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
532
533// Store on condition.
534let isCodeGenOnly = 1, Uses = [CC] in {
535  def STOC  : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
536  def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
537}
538let Uses = [CC] in {
539  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
540  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
541}
542
543// 8-bit immediate stores to 8-bit fields.
544defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
545
546// 16-bit immediate stores to 16-, 32- or 64-bit fields.
547def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
548def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
549def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;
550
551// Memory-to-memory moves.
552let mayLoad = 1, mayStore = 1 in
553  defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
554
555// String moves.
556let mayLoad = 1, mayStore = 1, Defs = [CC] in
557  defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
558
559//===----------------------------------------------------------------------===//
560// Sign extensions
561//===----------------------------------------------------------------------===//
562//
563// Note that putting these before zero extensions mean that we will prefer
564// them for anyextload*.  There's not really much to choose between the two
565// either way, but signed-extending loads have a short LH and a long LHY,
566// while zero-extending loads have only the long LLH.
567//
568//===----------------------------------------------------------------------===//
569
570// 32-bit extensions from registers.
571let hasSideEffects = 0 in {
572  def LBR : UnaryRRE<"lb", 0xB926, sext8,  GR32, GR32>;
573  def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
574}
575
576// 64-bit extensions from registers.
577let hasSideEffects = 0 in {
578  def LGBR : UnaryRRE<"lgb", 0xB906, sext8,  GR64, GR64>;
579  def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
580  def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
581}
582let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
583  def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR32>;
584
585// Match 32-to-64-bit sign extensions in which the source is already
586// in a 64-bit register.
587def : Pat<(sext_inreg GR64:$src, i32),
588          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
589
590// 32-bit extensions from 8-bit memory.  LBMux expands to LB or LBH,
591// depending on the choice of register.
592def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
593            Requires<[FeatureHighWord]>;
594def LB  : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
595def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
596          Requires<[FeatureHighWord]>;
597
598// 32-bit extensions from 16-bit memory.  LHMux expands to LH or LHH,
599// depending on the choice of register.
600def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
601            Requires<[FeatureHighWord]>;
602defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
603def  LHH  : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
604            Requires<[FeatureHighWord]>;
605def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
606
607// 64-bit extensions from memory.
608def LGB   : UnaryRXY<"lgb", 0xE377, asextloadi8,  GR64, 1>;
609def LGH   : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
610def LGF   : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
611def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
612def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
613let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
614  def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
615
616//===----------------------------------------------------------------------===//
617// Zero extensions
618//===----------------------------------------------------------------------===//
619
620// 32-bit extensions from registers.
621let hasSideEffects = 0 in {
622  // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
623  def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
624                Requires<[FeatureHighWord]>;
625  def LLCR    : UnaryRRE<"llc", 0xB994, zext8,  GR32, GR32>;
626  // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
627  def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
628                Requires<[FeatureHighWord]>;
629  def LLHR    : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
630}
631
632// 64-bit extensions from registers.
633let hasSideEffects = 0 in {
634  def LLGCR : UnaryRRE<"llgc", 0xB984, zext8,  GR64, GR64>;
635  def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
636  def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
637}
638
639// Match 32-to-64-bit zero extensions in which the source is already
640// in a 64-bit register.
641def : Pat<(and GR64:$src, 0xffffffff),
642          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
643
644// 32-bit extensions from 8-bit memory.  LLCMux expands to LLC or LLCH,
645// depending on the choice of register.
646def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
647             Requires<[FeatureHighWord]>;
648def LLC  : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
649def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>,
650           Requires<[FeatureHighWord]>;
651
652// 32-bit extensions from 16-bit memory.  LLHMux expands to LLH or LLHH,
653// depending on the choice of register.
654def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
655             Requires<[FeatureHighWord]>;
656def LLH   : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
657def LLHH  : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>,
658            Requires<[FeatureHighWord]>;
659def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
660
661// 64-bit extensions from memory.
662def LLGC   : UnaryRXY<"llgc", 0xE390, azextloadi8,  GR64, 1>;
663def LLGH   : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
664def LLGF   : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
665def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
666def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
667
668//===----------------------------------------------------------------------===//
669// Truncations
670//===----------------------------------------------------------------------===//
671
672// Truncations of 64-bit registers to 32-bit registers.
673def : Pat<(i32 (trunc GR64:$src)),
674          (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
675
676// Truncations of 32-bit registers to 8-bit memory.  STCMux expands to
677// STC, STCY or STCH, depending on the choice of register.
678def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
679             Requires<[FeatureHighWord]>;
680defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
681def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
682           Requires<[FeatureHighWord]>;
683
684// Truncations of 32-bit registers to 16-bit memory.  STHMux expands to
685// STH, STHY or STHH, depending on the choice of register.
686def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
687             Requires<[FeatureHighWord]>;
688defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
689def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
690           Requires<[FeatureHighWord]>;
691def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
692
693// Truncations of 64-bit registers to memory.
694defm : StoreGR64Pair<STC, STCY, truncstorei8>;
695defm : StoreGR64Pair<STH, STHY, truncstorei16>;
696def  : StoreGR64PC<STHRL, aligned_truncstorei16>;
697defm : StoreGR64Pair<ST, STY, truncstorei32>;
698def  : StoreGR64PC<STRL, aligned_truncstorei32>;
699
700//===----------------------------------------------------------------------===//
701// Multi-register moves
702//===----------------------------------------------------------------------===//
703
704// Multi-register loads.
705def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
706
707// Multi-register stores.
708def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
709
710//===----------------------------------------------------------------------===//
711// Byte swaps
712//===----------------------------------------------------------------------===//
713
714// Byte-swapping register moves.
715let hasSideEffects = 0 in {
716  def LRVR  : UnaryRRE<"lrv",  0xB91F, bswap, GR32, GR32>;
717  def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
718}
719
720// Byte-swapping loads.  Unlike normal loads, these instructions are
721// allowed to access storage more than once.
722def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>;
723def LRV  : UnaryRXY<"lrv",  0xE31E, z_lrv,  GR32, 4>;
724def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>;
725
726// Likewise byte-swapping stores.
727def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>;
728def STRV  : StoreRXY<"strv",  0xE33E, z_strv,  GR32, 4>;
729def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>;
730
731//===----------------------------------------------------------------------===//
732// Load address instructions
733//===----------------------------------------------------------------------===//
734
735// Load BDX-style addresses.
736let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1,
737    DispKey = "la" in {
738  let DispSize = "12" in
739    def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
740                    "la\t$R1, $XBD2",
741                    [(set GR64:$R1, laaddr12pair:$XBD2)]>;
742  let DispSize = "20" in
743    def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
744                      "lay\t$R1, $XBD2",
745                      [(set GR64:$R1, laaddr20pair:$XBD2)]>;
746}
747
748// Load a PC-relative address.  There's no version of this instruction
749// with a 16-bit offset, so there's no relaxation.
750let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
751    isReMaterializable = 1 in {
752  def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
753                     "larl\t$R1, $I2",
754                     [(set GR64:$R1, pcrel32:$I2)]>;
755}
756
757// Load the Global Offset Table address.  This will be lowered into a
758//     larl $R1, _GLOBAL_OFFSET_TABLE_
759// instruction.
760def GOT : Alias<6, (outs GR64:$R1), (ins),
761                [(set GR64:$R1, (global_offset_table))]>;
762
763//===----------------------------------------------------------------------===//
764// Absolute and Negation
765//===----------------------------------------------------------------------===//
766
767let Defs = [CC] in {
768  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
769    def LPR  : UnaryRR <"lp",  0x10,   z_iabs, GR32, GR32>;
770    def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>;
771  }
772  let CCValues = 0xE, CompareZeroCCMask = 0xE in
773    def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
774}
775def : Pat<(z_iabs32 GR32:$src), (LPR  GR32:$src)>;
776def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>;
777defm : SXU<z_iabs,   LPGFR>;
778defm : SXU<z_iabs64, LPGFR>;
779
780let Defs = [CC] in {
781  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
782    def LNR  : UnaryRR <"ln",  0x11,   z_inegabs, GR32, GR32>;
783    def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>;
784  }
785  let CCValues = 0xE, CompareZeroCCMask = 0xE in
786    def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
787}
788def : Pat<(z_inegabs32 GR32:$src), (LNR  GR32:$src)>;
789def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>;
790defm : SXU<z_inegabs,   LNGFR>;
791defm : SXU<z_inegabs64, LNGFR>;
792
793let Defs = [CC] in {
794  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
795    def LCR  : UnaryRR <"lc",  0x13,   ineg, GR32, GR32>;
796    def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
797  }
798  let CCValues = 0xE, CompareZeroCCMask = 0xE in
799    def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
800}
801defm : SXU<ineg, LCGFR>;
802
803//===----------------------------------------------------------------------===//
804// Insertion
805//===----------------------------------------------------------------------===//
806
807let isCodeGenOnly = 1 in
808  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
809defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
810
811defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
812defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
813
814defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
815defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
816
817// Insertions of a 16-bit immediate, leaving other bits unaffected.
818// We don't have or_as_insert equivalents of these operations because
819// OI is available instead.
820//
821// IIxMux expands to II[LH]x, depending on the choice of register.
822def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
823             Requires<[FeatureHighWord]>;
824def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
825             Requires<[FeatureHighWord]>;
826def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
827def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
828def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
829def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
830def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
831def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
832def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
833def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
834
835// ...likewise for 32-bit immediates.  For GR32s this is a general
836// full-width move.  (We use IILF rather than something like LLILF
837// for 32-bit moves because IILF leaves the upper 32 bits of the
838// GR64 unchanged.)
839let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
840  def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
841               Requires<[FeatureHighWord]>;
842  def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
843  def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
844}
845def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
846def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
847
848// An alternative model of inserthf, with the first operand being
849// a zero-extended value.
850def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
851          (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
852                  imm64hf32:$imm)>;
853
854//===----------------------------------------------------------------------===//
855// Addition
856//===----------------------------------------------------------------------===//
857
858// Plain addition.
859let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
860  // Addition of a register.
861  let isCommutable = 1 in {
862    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
863    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
864  }
865  def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
866
867  // Addition of signed 16-bit immediates.
868  defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
869  defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
870  defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
871
872  // Addition of signed 32-bit immediates.
873  def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
874               Requires<[FeatureHighWord]>;
875  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
876  def AIH  : BinaryRIL<"aih",  0xCC8, add, GRH32, simm32>,
877             Requires<[FeatureHighWord]>;
878  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
879
880  // Addition of memory.
881  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
882  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
883  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
884  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
885
886  // Addition to memory.
887  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
888  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
889}
890defm : SXB<add, GR64, AGFR>;
891
892// Addition producing a carry.
893let Defs = [CC] in {
894  // Addition of a register.
895  let isCommutable = 1 in {
896    defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
897    defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
898  }
899  def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
900
901  // Addition of signed 16-bit immediates.
902  def ALHSIK  : BinaryRIE<"alhsik",  0xECDA, addc, GR32, imm32sx16>,
903                Requires<[FeatureDistinctOps]>;
904  def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
905                Requires<[FeatureDistinctOps]>;
906
907  // Addition of unsigned 32-bit immediates.
908  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
909  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
910
911  // Addition of memory.
912  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
913  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
914  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load, 8>;
915}
916defm : ZXB<addc, GR64, ALGFR>;
917
918// Addition producing and using a carry.
919let Defs = [CC], Uses = [CC] in {
920  // Addition of a register.
921  def ALCR  : BinaryRRE<"alc",  0xB998, adde, GR32, GR32>;
922  def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
923
924  // Addition of memory.
925  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load, 4>;
926  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
927}
928
929//===----------------------------------------------------------------------===//
930// Subtraction
931//===----------------------------------------------------------------------===//
932
933// Plain subtraction.  Although immediate forms exist, we use the
934// add-immediate instruction instead.
935let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
936  // Subtraction of a register.
937  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
938  def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
939  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
940
941  // Subtraction of memory.
942  defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
943  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
944  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
945  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load, 8>;
946}
947defm : SXB<sub, GR64, SGFR>;
948
949// Subtraction producing a carry.
950let Defs = [CC] in {
951  // Subtraction of a register.
952  defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
953  def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
954  defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
955
956  // Subtraction of unsigned 32-bit immediates.  These don't match
957  // subc because we prefer addc for constants.
958  def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
959  def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
960
961  // Subtraction of memory.
962  defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
963  def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
964  def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
965}
966defm : ZXB<subc, GR64, SLGFR>;
967
968// Subtraction producing and using a carry.
969let Defs = [CC], Uses = [CC] in {
970  // Subtraction of a register.
971  def SLBR  : BinaryRRE<"slb",  0xB999, sube, GR32, GR32>;
972  def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
973
974  // Subtraction of memory.
975  def SLB  : BinaryRXY<"slb",  0xE399, sube, GR32, load, 4>;
976  def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
977}
978
979//===----------------------------------------------------------------------===//
980// AND
981//===----------------------------------------------------------------------===//
982
983let Defs = [CC] in {
984  // ANDs of a register.
985  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
986    defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
987    defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
988  }
989
990  let isConvertibleToThreeAddress = 1 in {
991    // ANDs of a 16-bit immediate, leaving other bits unaffected.
992    // The CC result only reflects the 16-bit field, not the full register.
993    //
994    // NIxMux expands to NI[LH]x, depending on the choice of register.
995    def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
996                 Requires<[FeatureHighWord]>;
997    def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
998                 Requires<[FeatureHighWord]>;
999    def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
1000    def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
1001    def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
1002    def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
1003    def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
1004    def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
1005    def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
1006    def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
1007
1008    // ANDs of a 32-bit immediate, leaving other bits unaffected.
1009    // The CC result only reflects the 32-bit field, which means we can
1010    // use it as a zero indicator for i32 operations but not otherwise.
1011    let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1012      // Expands to NILF or NIHF, depending on the choice of register.
1013      def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
1014                   Requires<[FeatureHighWord]>;
1015      def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
1016      def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
1017    }
1018    def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
1019    def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
1020  }
1021
1022  // ANDs of memory.
1023  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1024    defm N  : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
1025    def  NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
1026  }
1027
1028  // AND to memory
1029  defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>;
1030
1031  // Block AND.
1032  let mayLoad = 1, mayStore = 1 in
1033    defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
1034}
1035defm : RMWIByte<and, bdaddr12pair, NI>;
1036defm : RMWIByte<and, bdaddr20pair, NIY>;
1037
1038//===----------------------------------------------------------------------===//
1039// OR
1040//===----------------------------------------------------------------------===//
1041
1042let Defs = [CC] in {
1043  // ORs of a register.
1044  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1045    defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
1046    defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
1047  }
1048
1049  // ORs of a 16-bit immediate, leaving other bits unaffected.
1050  // The CC result only reflects the 16-bit field, not the full register.
1051  //
1052  // OIxMux expands to OI[LH]x, depending on the choice of register.
1053  def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
1054               Requires<[FeatureHighWord]>;
1055  def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
1056               Requires<[FeatureHighWord]>;
1057  def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
1058  def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
1059  def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
1060  def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
1061  def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
1062  def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
1063  def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
1064  def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
1065
1066  // ORs of a 32-bit immediate, leaving other bits unaffected.
1067  // The CC result only reflects the 32-bit field, which means we can
1068  // use it as a zero indicator for i32 operations but not otherwise.
1069  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1070    // Expands to OILF or OIHF, depending on the choice of register.
1071    def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
1072                 Requires<[FeatureHighWord]>;
1073    def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
1074    def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
1075  }
1076  def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
1077  def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
1078
1079  // ORs of memory.
1080  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1081    defm O  : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
1082    def  OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
1083  }
1084
1085  // OR to memory
1086  defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>;
1087
1088  // Block OR.
1089  let mayLoad = 1, mayStore = 1 in
1090    defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
1091}
1092defm : RMWIByte<or, bdaddr12pair, OI>;
1093defm : RMWIByte<or, bdaddr20pair, OIY>;
1094
1095//===----------------------------------------------------------------------===//
1096// XOR
1097//===----------------------------------------------------------------------===//
1098
1099let Defs = [CC] in {
1100  // XORs of a register.
1101  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1102    defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
1103    defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
1104  }
1105
1106  // XORs of a 32-bit immediate, leaving other bits unaffected.
1107  // The CC result only reflects the 32-bit field, which means we can
1108  // use it as a zero indicator for i32 operations but not otherwise.
1109  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1110    // Expands to XILF or XIHF, depending on the choice of register.
1111    def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
1112                 Requires<[FeatureHighWord]>;
1113    def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
1114    def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
1115  }
1116  def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
1117  def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
1118
1119  // XORs of memory.
1120  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
1121    defm X  : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
1122    def  XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
1123  }
1124
1125  // XOR to memory
1126  defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>;
1127
1128  // Block XOR.
1129  let mayLoad = 1, mayStore = 1 in
1130    defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
1131}
1132defm : RMWIByte<xor, bdaddr12pair, XI>;
1133defm : RMWIByte<xor, bdaddr20pair, XIY>;
1134
1135//===----------------------------------------------------------------------===//
1136// Multiplication
1137//===----------------------------------------------------------------------===//
1138
1139// Multiplication of a register.
1140let isCommutable = 1 in {
1141  def MSR  : BinaryRRE<"ms",  0xB252, mul, GR32, GR32>;
1142  def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
1143}
1144def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
1145defm : SXB<mul, GR64, MSGFR>;
1146
1147// Multiplication of a signed 16-bit immediate.
1148def MHI  : BinaryRI<"mhi",  0xA7C, mul, GR32, imm32sx16>;
1149def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
1150
1151// Multiplication of a signed 32-bit immediate.
1152def MSFI  : BinaryRIL<"msfi",  0xC21, mul, GR32, simm32>;
1153def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
1154
1155// Multiplication of memory.
1156defm MH   : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
1157defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
1158def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
1159def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
1160
1161// Multiplication of a register, producing two results.
1162def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
1163
1164// Multiplication of memory, producing two results.
1165def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
1166
1167//===----------------------------------------------------------------------===//
1168// Division and remainder
1169//===----------------------------------------------------------------------===//
1170
1171// Division and remainder, from registers.
1172def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
1173def DSGR  : BinaryRRE<"dsg",  0xB90D, z_sdivrem64, GR128, GR64>;
1174def DLR   : BinaryRRE<"dl",   0xB997, z_udivrem32, GR128, GR32>;
1175def DLGR  : BinaryRRE<"dlg",  0xB987, z_udivrem64, GR128, GR64>;
1176
1177// Division and remainder, from memory.
1178def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
1179def DSG  : BinaryRXY<"dsg",  0xE30D, z_sdivrem64, GR128, load, 8>;
1180def DL   : BinaryRXY<"dl",   0xE397, z_udivrem32, GR128, load, 4>;
1181def DLG  : BinaryRXY<"dlg",  0xE387, z_udivrem64, GR128, load, 8>;
1182
1183//===----------------------------------------------------------------------===//
1184// Shifts
1185//===----------------------------------------------------------------------===//
1186
1187// Shift left.
1188let hasSideEffects = 0 in {
1189  defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
1190  def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
1191}
1192
1193// Logical shift right.
1194let hasSideEffects = 0 in {
1195  defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
1196  def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
1197}
1198
1199// Arithmetic shift right.
1200let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1201  defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
1202  def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>;
1203}
1204
1205// Rotate left.
1206let hasSideEffects = 0 in {
1207  def RLL  : BinaryRSY<"rll",  0xEB1D, rotl, GR32>;
1208  def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
1209}
1210
1211// Rotate second operand left and inserted selected bits into first operand.
1212// These can act like 32-bit operands provided that the constant start and
1213// end bits (operands 2 and 3) are in the range [32, 64).
1214let Defs = [CC] in {
1215  let isCodeGenOnly = 1 in
1216    def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1217  let CCValues = 0xE, CompareZeroCCMask = 0xE in
1218    def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1219}
1220
1221// On zEC12 we have a variant of RISBG that does not set CC.
1222let Predicates = [FeatureMiscellaneousExtensions] in
1223  def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
1224
1225// Forms of RISBG that only affect one word of the destination register.
1226// They do not set CC.
1227let Predicates = [FeatureHighWord] in {
1228  def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
1229  def RISBLL  : RotateSelectAliasRIEf<GR32,  GR32>;
1230  def RISBLH  : RotateSelectAliasRIEf<GR32,  GRH32>;
1231  def RISBHL  : RotateSelectAliasRIEf<GRH32, GR32>;
1232  def RISBHH  : RotateSelectAliasRIEf<GRH32, GRH32>;
1233  def RISBLG  : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;
1234  def RISBHG  : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;
1235}
1236
1237// Rotate second operand left and perform a logical operation with selected
1238// bits of the first operand.  The CC result only describes the selected bits,
1239// so isn't useful for a full comparison against zero.
1240let Defs = [CC] in {
1241  def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1242  def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1243  def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1244}
1245
1246//===----------------------------------------------------------------------===//
1247// Comparison
1248//===----------------------------------------------------------------------===//
1249
1250// Signed comparisons.  We put these before the unsigned comparisons because
1251// some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1252// of the unsigned forms do.
1253let Defs = [CC], CCValues = 0xE in {
1254  // Comparison with a register.
1255  def CR   : CompareRR <"c",   0x19,   z_scmp,    GR32, GR32>;
1256  def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1257  def CGR  : CompareRRE<"cg",  0xB920, z_scmp,    GR64, GR64>;
1258
1259  // Comparison with a signed 16-bit immediate.
1260  def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
1261  def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1262
1263  // Comparison with a signed 32-bit immediate.  CFIMux expands to CFI or CIH,
1264  // depending on the choice of register.
1265  def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,
1266               Requires<[FeatureHighWord]>;
1267  def CFI  : CompareRIL<"cfi",  0xC2D, z_scmp, GR32, simm32>;
1268  def CIH  : CompareRIL<"cih",  0xCCD, z_scmp, GRH32, simm32>,
1269             Requires<[FeatureHighWord]>;
1270  def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1271
1272  // Comparison with memory.
1273  defm CH    : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1274  def  CMux  : CompareRXYPseudo<z_scmp, GRX32, load, 4>,
1275               Requires<[FeatureHighWord]>;
1276  defm C     : CompareRXPair<"c",  0x59, 0xE359, z_scmp, GR32, load, 4>;
1277  def  CHF   : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>,
1278               Requires<[FeatureHighWord]>;
1279  def  CGH   : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1280  def  CGF   : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1281  def  CG    : CompareRXY<"cg",  0xE320, z_scmp, GR64, load, 8>;
1282  def  CHRL  : CompareRILPC<"chrl",  0xC65, z_scmp, GR32, aligned_asextloadi16>;
1283  def  CRL   : CompareRILPC<"crl",   0xC6D, z_scmp, GR32, aligned_load>;
1284  def  CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1285  def  CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1286  def  CGRL  : CompareRILPC<"cgrl",  0xC68, z_scmp, GR64, aligned_load>;
1287
1288  // Comparison between memory and a signed 16-bit immediate.
1289  def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1290  def CHSI  : CompareSIL<"chsi",  0xE55C, z_scmp, load, imm32sx16>;
1291  def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1292}
1293defm : SXB<z_scmp, GR64, CGFR>;
1294
1295// Unsigned comparisons.
1296let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1297  // Comparison with a register.
1298  def CLR   : CompareRR <"cl",   0x15,   z_ucmp,    GR32, GR32>;
1299  def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1300  def CLGR  : CompareRRE<"clg",  0xB921, z_ucmp,    GR64, GR64>;
1301
1302  // Comparison with an unsigned 32-bit immediate.  CLFIMux expands to CLFI
1303  // or CLIH, depending on the choice of register.
1304  def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
1305                Requires<[FeatureHighWord]>;
1306  def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
1307  def CLIH  : CompareRIL<"clih",  0xCCF, z_ucmp, GRH32, uimm32>,
1308              Requires<[FeatureHighWord]>;
1309  def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1310
1311  // Comparison with memory.
1312  def  CLMux  : CompareRXYPseudo<z_ucmp, GRX32, load, 4>,
1313                Requires<[FeatureHighWord]>;
1314  defm CL     : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1315  def  CLHF   : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>,
1316                Requires<[FeatureHighWord]>;
1317  def  CLGF   : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1318  def  CLG    : CompareRXY<"clg",  0xE321, z_ucmp, GR64, load, 8>;
1319  def  CLHRL  : CompareRILPC<"clhrl",  0xC67, z_ucmp, GR32,
1320                             aligned_azextloadi16>;
1321  def  CLRL   : CompareRILPC<"clrl",   0xC6F, z_ucmp, GR32,
1322                             aligned_load>;
1323  def  CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1324                             aligned_azextloadi16>;
1325  def  CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1326                             aligned_azextloadi32>;
1327  def  CLGRL  : CompareRILPC<"clgrl",  0xC6A, z_ucmp, GR64,
1328                             aligned_load>;
1329
1330  // Comparison between memory and an unsigned 8-bit immediate.
1331  defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1332
1333  // Comparison between memory and an unsigned 16-bit immediate.
1334  def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1335  def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1336  def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1337}
1338defm : ZXB<z_ucmp, GR64, CLGFR>;
1339
1340// Memory-to-memory comparison.
1341let mayLoad = 1, Defs = [CC] in
1342  defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1343
1344// String comparison.
1345let mayLoad = 1, Defs = [CC] in
1346  defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1347
1348// Test under mask.
1349let Defs = [CC] in {
1350  // TMxMux expands to TM[LH]x, depending on the choice of register.
1351  def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
1352               Requires<[FeatureHighWord]>;
1353  def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
1354               Requires<[FeatureHighWord]>;
1355  def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1356  def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1357  def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
1358  def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
1359
1360  def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;
1361  def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;
1362  def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;
1363  def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;
1364
1365  defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1366}
1367
1368//===----------------------------------------------------------------------===//
1369// Prefetch
1370//===----------------------------------------------------------------------===//
1371
1372def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1373def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1374
1375//===----------------------------------------------------------------------===//
1376// Atomic operations
1377//===----------------------------------------------------------------------===//
1378
1379// A serialization instruction that acts as a barrier for all memory
1380// accesses, which expands to "bcr 14, 0".
1381let hasSideEffects = 1 in
1382def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
1383
1384// A pseudo instruction that serves as a compiler barrier.
1385let hasSideEffects = 1 in
1386def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
1387
1388let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
1389  def LAA   : LoadAndOpRSY<"laa",   0xEBF8, atomic_load_add_32, GR32>;
1390  def LAAG  : LoadAndOpRSY<"laag",  0xEBE8, atomic_load_add_64, GR64>;
1391  def LAAL  : LoadAndOpRSY<"laal",  0xEBFA, null_frag, GR32>;
1392  def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
1393  def LAN   : LoadAndOpRSY<"lan",   0xEBF4, atomic_load_and_32, GR32>;
1394  def LANG  : LoadAndOpRSY<"lang",  0xEBE4, atomic_load_and_64, GR64>;
1395  def LAO   : LoadAndOpRSY<"lao",   0xEBF6, atomic_load_or_32, GR32>;
1396  def LAOG  : LoadAndOpRSY<"laog",  0xEBE6, atomic_load_or_64, GR64>;
1397  def LAX   : LoadAndOpRSY<"lax",   0xEBF7, atomic_load_xor_32, GR32>;
1398  def LAXG  : LoadAndOpRSY<"laxg",  0xEBE7, atomic_load_xor_64, GR64>;
1399}
1400
1401def ATOMIC_SWAPW   : AtomicLoadWBinaryReg<z_atomic_swapw>;
1402def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
1403def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
1404
1405def ATOMIC_LOADW_AR  : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1406def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1407let Predicates = [FeatureNoInterlockedAccess1] in {
1408  def ATOMIC_LOAD_AR   : AtomicLoadBinaryReg32<atomic_load_add_32>;
1409  def ATOMIC_LOAD_AHI  : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1410  def ATOMIC_LOAD_AFI  : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1411  def ATOMIC_LOAD_AGR  : AtomicLoadBinaryReg64<atomic_load_add_64>;
1412  def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1413  def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1414}
1415
1416def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1417def ATOMIC_LOAD_SR  : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1418def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1419
1420def ATOMIC_LOADW_NR   : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1421def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1422let Predicates = [FeatureNoInterlockedAccess1] in {
1423  def ATOMIC_LOAD_NR     : AtomicLoadBinaryReg32<atomic_load_and_32>;
1424  def ATOMIC_LOAD_NILL   : AtomicLoadBinaryImm32<atomic_load_and_32,
1425                                                 imm32ll16c>;
1426  def ATOMIC_LOAD_NILH   : AtomicLoadBinaryImm32<atomic_load_and_32,
1427                                                 imm32lh16c>;
1428  def ATOMIC_LOAD_NILF   : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1429  def ATOMIC_LOAD_NGR    : AtomicLoadBinaryReg64<atomic_load_and_64>;
1430  def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1431                                                 imm64ll16c>;
1432  def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1433                                                 imm64lh16c>;
1434  def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1435                                                 imm64hl16c>;
1436  def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1437                                                 imm64hh16c>;
1438  def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1439                                                 imm64lf32c>;
1440  def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1441                                                 imm64hf32c>;
1442}
1443
1444def ATOMIC_LOADW_OR     : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1445def ATOMIC_LOADW_OILH   : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1446let Predicates = [FeatureNoInterlockedAccess1] in {
1447  def ATOMIC_LOAD_OR     : AtomicLoadBinaryReg32<atomic_load_or_32>;
1448  def ATOMIC_LOAD_OILL   : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1449  def ATOMIC_LOAD_OILH   : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1450  def ATOMIC_LOAD_OILF   : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1451  def ATOMIC_LOAD_OGR    : AtomicLoadBinaryReg64<atomic_load_or_64>;
1452  def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1453  def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1454  def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1455  def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1456  def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1457  def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1458}
1459
1460def ATOMIC_LOADW_XR     : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1461def ATOMIC_LOADW_XILF   : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1462let Predicates = [FeatureNoInterlockedAccess1] in {
1463  def ATOMIC_LOAD_XR     : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1464  def ATOMIC_LOAD_XILF   : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1465  def ATOMIC_LOAD_XGR    : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1466  def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1467  def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1468}
1469
1470def ATOMIC_LOADW_NRi    : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1471def ATOMIC_LOADW_NILHi  : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1472                                               imm32lh16c>;
1473def ATOMIC_LOAD_NRi     : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1474def ATOMIC_LOAD_NILLi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1475                                                imm32ll16c>;
1476def ATOMIC_LOAD_NILHi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1477                                                imm32lh16c>;
1478def ATOMIC_LOAD_NILFi   : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1479def ATOMIC_LOAD_NGRi    : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1480def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1481                                                imm64ll16c>;
1482def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1483                                                imm64lh16c>;
1484def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1485                                                imm64hl16c>;
1486def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1487                                                imm64hh16c>;
1488def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1489                                                imm64lf32c>;
1490def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1491                                                imm64hf32c>;
1492
1493def ATOMIC_LOADW_MIN    : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1494def ATOMIC_LOAD_MIN_32  : AtomicLoadBinaryReg32<atomic_load_min_32>;
1495def ATOMIC_LOAD_MIN_64  : AtomicLoadBinaryReg64<atomic_load_min_64>;
1496
1497def ATOMIC_LOADW_MAX    : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1498def ATOMIC_LOAD_MAX_32  : AtomicLoadBinaryReg32<atomic_load_max_32>;
1499def ATOMIC_LOAD_MAX_64  : AtomicLoadBinaryReg64<atomic_load_max_64>;
1500
1501def ATOMIC_LOADW_UMIN   : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1502def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1503def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1504
1505def ATOMIC_LOADW_UMAX   : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1506def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1507def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1508
1509def ATOMIC_CMP_SWAPW
1510  : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1511                                  ADDR32:$bitshift, ADDR32:$negbitshift,
1512                                  uimm32:$bitsize),
1513           [(set GR32:$dst,
1514                 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1515                                     ADDR32:$bitshift, ADDR32:$negbitshift,
1516                                     uimm32:$bitsize))]> {
1517  let Defs = [CC];
1518  let mayLoad = 1;
1519  let mayStore = 1;
1520  let usesCustomInserter = 1;
1521}
1522
1523let Defs = [CC] in {
1524  defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1525  def  CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1526}
1527
1528//===----------------------------------------------------------------------===//
1529// Transactional execution
1530//===----------------------------------------------------------------------===//
1531
1532let Predicates = [FeatureTransactionalExecution] in {
1533  // Transaction Begin
1534  let hasSideEffects = 1, mayStore = 1,
1535      usesCustomInserter = 1, Defs = [CC] in {
1536    def TBEGIN : InstSIL<0xE560,
1537                         (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1538                         "tbegin\t$BD1, $I2",
1539                         [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
1540    def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1541                                [(z_tbegin_nofloat bdaddr12only:$BD1,
1542                                                   imm32zx16:$I2)]>;
1543    def TBEGINC : InstSIL<0xE561,
1544                          (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1545                          "tbeginc\t$BD1, $I2",
1546                          [(int_s390_tbeginc bdaddr12only:$BD1,
1547                                             imm32zx16:$I2)]>;
1548  }
1549
1550  // Transaction End
1551  let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
1552    def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
1553
1554  // Transaction Abort
1555  let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
1556    def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
1557                       "tabort\t$BD2",
1558                       [(int_s390_tabort bdaddr12only:$BD2)]>;
1559
1560  // Nontransactional Store
1561  let hasSideEffects = 1 in
1562    def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
1563
1564  // Extract Transaction Nesting Depth
1565  let hasSideEffects = 1 in
1566    def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
1567}
1568
1569//===----------------------------------------------------------------------===//
1570// Processor assist
1571//===----------------------------------------------------------------------===//
1572
1573let Predicates = [FeatureProcessorAssist] in {
1574  let hasSideEffects = 1, R4 = 0 in
1575    def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
1576                      "ppa\t$R1, $R2, $R3", []>;
1577  def : Pat<(int_s390_ppa_txassist GR32:$src),
1578            (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
1579                 0, 1)>;
1580}
1581
1582//===----------------------------------------------------------------------===//
1583// Miscellaneous Instructions.
1584//===----------------------------------------------------------------------===//
1585
1586// Extract CC into bits 29 and 28 of a register.
1587let Uses = [CC] in
1588  def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1589
1590// Read a 32-bit access register into a GR32.  As with all GR32 operations,
1591// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1592// when a 64-bit address is stored in a pair of access registers.
1593def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1594                  "ear\t$R1, $R2",
1595                  [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1596
1597// Find leftmost one, AKA count leading zeros.  The instruction actually
1598// returns a pair of GR64s, the first giving the number of leading zeros
1599// and the second giving a copy of the source with the leftmost one bit
1600// cleared.  We only use the first result here.
1601let Defs = [CC] in {
1602  def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1603}
1604def : Pat<(ctlz GR64:$src),
1605          (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1606
1607// Population count.  Counts bits set per byte.
1608let Predicates = [FeaturePopulationCount], Defs = [CC] in {
1609  def POPCNT : InstRRE<0xB9E1, (outs GR64:$R1), (ins GR64:$R2),
1610                       "popcnt\t$R1, $R2",
1611                       [(set GR64:$R1, (z_popcnt GR64:$R2))]>;
1612}
1613
1614// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1615def : Pat<(i64 (anyext GR32:$src)),
1616          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1617
1618// Extend GR32s and GR64s to GR128s.
1619let usesCustomInserter = 1 in {
1620  def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1621  def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1622  def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1623}
1624
1625// Search a block of memory for a character.
1626let mayLoad = 1, Defs = [CC] in
1627  defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1628
1629// Other instructions for inline assembly
1630let hasSideEffects = 1, Defs = [CC], isCall = 1 in
1631  def SVC : InstI<0x0A, (outs), (ins imm32zx8:$I1),
1632                  "svc\t$I1",
1633                  []>;
1634let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1635  def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2),
1636                       "stck\t$BD2",
1637                       []>;
1638let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1639  def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2),
1640                       "stckf\t$BD2",
1641                       []>;
1642let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1643  def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2),
1644                       "stcke\t$BD2",
1645                       []>;
1646let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1647  def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2),
1648                       "stfle\t$BD2",
1649                       []>;
1650
1651
1652
1653//===----------------------------------------------------------------------===//
1654// Peepholes.
1655//===----------------------------------------------------------------------===//
1656
1657// Use AL* for GR64 additions of unsigned 32-bit values.
1658defm : ZXB<add, GR64, ALGFR>;
1659def  : Pat<(add GR64:$src1, imm64zx32:$src2),
1660           (ALGFI GR64:$src1, imm64zx32:$src2)>;
1661def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1662           (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1663
1664// Use SL* for GR64 subtractions of unsigned 32-bit values.
1665defm : ZXB<sub, GR64, SLGFR>;
1666def  : Pat<(add GR64:$src1, imm64zx32n:$src2),
1667           (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1668def  : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1669           (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1670
1671// Optimize sign-extended 1/0 selects to -1/0 selects.  This is important
1672// for vector legalization.
1673def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)),
1674                         (i32 31)),
1675                    (i32 31)),
1676          (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1677def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid,
1678                                                       imm32zx4:$cc)))),
1679                    (i32 63)),
1680               (i32 63)),
1681          (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1682
1683// Avoid generating 2 XOR instructions. (xor (and x, y), y) is
1684// equivalent to (and (xor x, -1), y)
1685def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y),
1686                          (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>;
1687
1688// Shift/rotate instructions only use the last 6 bits of the second operand
1689// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the
1690// last 16 bits.
1691// Complexity is added so that we match this before we match NILF on the AND
1692// operation alone.
1693let AddedComplexity = 4 in {
1694  def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)),
1695            (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1696
1697  def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)),
1698            (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1699
1700  def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)),
1701            (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1702
1703  def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)),
1704            (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1705
1706  def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)),
1707            (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1708
1709  def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)),
1710            (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1711
1712  def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)),
1713            (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1714
1715  def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)),
1716            (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>;
1717}
1718
1719// Peepholes for turning scalar operations into block operations.
1720defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1721                      XCSequence, 1>;
1722defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1723                      XCSequence, 2>;
1724defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1725                      XCSequence, 4>;
1726defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1727                      OCSequence, XCSequence, 1>;
1728defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1729                      XCSequence, 2>;
1730defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1731                      XCSequence, 4>;
1732defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
1733                      XCSequence, 8>;
1734