1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Stack allocation
12//===----------------------------------------------------------------------===//
13
14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15                              [(callseq_start timm:$amt)]>;
16def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17                              [(callseq_end timm:$amt1, timm:$amt2)]>;
18
19let hasSideEffects = 0 in {
20  // Takes as input the value of the stack pointer after a dynamic allocation
21  // has been made.  Sets the output to the address of the dynamically-
22  // allocated area itself, skipping the outgoing arguments.
23  //
24  // This expands to an LA or LAY instruction.  We restrict the offset
25  // to the range of LA and keep the LAY range in reserve for when
26  // the size of the outgoing arguments is added.
27  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28                           [(set GR64:$dst, dynalloc12only:$src)]>;
29}
30
31//===----------------------------------------------------------------------===//
32// Control flow instructions
33//===----------------------------------------------------------------------===//
34
35// A return instruction (br %r14).
36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37  def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
38
39// Unconditional branches.  R1 is the condition-code mask (all 1s).
40let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41  let isIndirectBranch = 1 in
42    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43                    "br\t$R2", [(brind ADDR64:$R2)]>;
44
45  // An assembler extended mnemonic for BRC.
46  def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
47                 [(br bb:$I2)]>;
48
49  // An assembler extended mnemonic for BRCL.  (The extension is "G"
50  // rather than "L" because "JL" is "Jump if Less".)
51  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
52}
53
54// Conditional branches.  It's easier for LLVM to handle these branches
55// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56// the first operand.  It seems friendlier to use mnemonic forms like
57// JE and JLH when writing out the assembly though.
58let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59  let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60    def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61                                         brtarget16:$I2), "j$R1\t$I2",
62                     [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63    def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64                                           brtarget32:$I2), "jg$R1\t$I2", []>;
65  }
66  def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2),
67                      "brc\t$R1, $I2", []>;
68  def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2),
69                        "brcl\t$R1, $I2", []>;
70  def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2),
71                      "bcr\t$R1, $R2", []>;
72}
73
74// Fused compare-and-branch instructions.  As for normal branches,
75// we handle these instructions internally in their raw CRJ-like form,
76// but use assembly macros like CRJE when writing them out.
77//
78// These instructions do not use or clobber the condition codes.
79// We nevertheless pretend that they clobber CC, so that we can lower
80// them to separate comparisons and BRCLs if the branch ends up being
81// out of range.
82multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
83  let isBranch = 1, isTerminator = 1, Defs = [CC] in {
84    def RJ  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
85                                            brtarget16:$RI4),
86                       "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
87    def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
88                                            brtarget16:$RI4),
89                       "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
90    def IJ  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
91                                            brtarget16:$RI4),
92                       "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
93    def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
94                                            brtarget16:$RI4),
95                       "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
96    def LRJ  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
97                                             brtarget16:$RI4),
98                        "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
99    def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
100                                             brtarget16:$RI4),
101                        "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
102    def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
103                                             brtarget16:$RI4),
104                        "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
105    def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
106                                             brtarget16:$RI4),
107                        "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
108  }
109}
110let isCodeGenOnly = 1 in
111  defm C : CompareBranches<cond4, "$M3", "">;
112defm AsmC : CompareBranches<imm32zx4, "", "$M3, ">;
113
114// Define AsmParser mnemonics for each general condition-code mask
115// (integer or floating-point)
116multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
117  let isBranch = 1, isTerminator = 1, R1 = ccmask in {
118    def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
119                   "j"##name##"\t$I2", []>;
120    def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
121                     "jg"##name##"\t$I2", []>;
122    def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>;
123  }
124  def LOCR  : FixedCondUnaryRRF<"locr"##name,  0xB9F2, GR32, GR32, ccmask>;
125  def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
126  def LOC   : FixedCondUnaryRSY<"loc"##name,   0xEBF2, GR32, ccmask, 4>;
127  def LOCG  : FixedCondUnaryRSY<"locg"##name,  0xEBE2, GR64, ccmask, 8>;
128  def STOC  : FixedCondStoreRSY<"stoc"##name,  0xEBF3, GR32, ccmask, 4>;
129  def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
130}
131defm AsmO   : CondExtendedMnemonic<1,  "o">;
132defm AsmH   : CondExtendedMnemonic<2,  "h">;
133defm AsmNLE : CondExtendedMnemonic<3,  "nle">;
134defm AsmL   : CondExtendedMnemonic<4,  "l">;
135defm AsmNHE : CondExtendedMnemonic<5,  "nhe">;
136defm AsmLH  : CondExtendedMnemonic<6,  "lh">;
137defm AsmNE  : CondExtendedMnemonic<7,  "ne">;
138defm AsmE   : CondExtendedMnemonic<8,  "e">;
139defm AsmNLH : CondExtendedMnemonic<9,  "nlh">;
140defm AsmHE  : CondExtendedMnemonic<10, "he">;
141defm AsmNL  : CondExtendedMnemonic<11, "nl">;
142defm AsmLE  : CondExtendedMnemonic<12, "le">;
143defm AsmNH  : CondExtendedMnemonic<13, "nh">;
144defm AsmNO  : CondExtendedMnemonic<14, "no">;
145
146// Define AsmParser mnemonics for each integer condition-code mask.
147// This is like the list above, except that condition 3 is not possible
148// and that the low bit of the mask is therefore always 0.  This means
149// that each condition has two names.  Conditions "o" and "no" are not used.
150//
151// We don't make one of the two names an alias of the other because
152// we need the custom parsing routines to select the correct register class.
153multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
154  let isBranch = 1, isTerminator = 1, M3 = ccmask in {
155    def CR  : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
156                                            brtarget16:$RI4),
157                       "crj"##name##"\t$R1, $R2, $RI4", []>;
158    def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
159                                            brtarget16:$RI4),
160                       "cgrj"##name##"\t$R1, $R2, $RI4", []>;
161    def CI  : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
162                                            brtarget16:$RI4),
163                       "cij"##name##"\t$R1, $I2, $RI4", []>;
164    def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
165                                            brtarget16:$RI4),
166                       "cgij"##name##"\t$R1, $I2, $RI4", []>;
167    def CLR  : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
168                                            brtarget16:$RI4),
169                        "clrj"##name##"\t$R1, $R2, $RI4", []>;
170    def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
171                                             brtarget16:$RI4),
172                        "clgrj"##name##"\t$R1, $R2, $RI4", []>;
173    def CLI  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
174                                             brtarget16:$RI4),
175                        "clij"##name##"\t$R1, $I2, $RI4", []>;
176    def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
177                                             brtarget16:$RI4),
178                        "clgij"##name##"\t$R1, $I2, $RI4", []>;
179  }
180}
181multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
182  : IntCondExtendedMnemonicA<ccmask, name1> {
183  let isAsmParserOnly = 1 in
184    defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
185}
186defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
187defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
188defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;
189defm AsmJE   : IntCondExtendedMnemonic<8,  "e",  "nlh">;
190defm AsmJHE  : IntCondExtendedMnemonic<10, "he", "nl">;
191defm AsmJLE  : IntCondExtendedMnemonic<12, "le", "nh">;
192
193// Decrement a register and branch if it is nonzero.  These don't clobber CC,
194// but we might need to split long branches into sequences that do.
195let Defs = [CC] in {
196  def BRCT  : BranchUnaryRI<"brct",  0xA76, GR32>;
197  def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
198}
199
200//===----------------------------------------------------------------------===//
201// Select instructions
202//===----------------------------------------------------------------------===//
203
204def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
205def Select32    : SelectWrapper<GR32>;
206def Select64    : SelectWrapper<GR64>;
207
208// We don't define 32-bit Mux stores because the low-only STOC should
209// always be used if possible.
210defm CondStore8Mux  : CondStores<GRX32, nonvolatile_truncstorei8,
211                                 nonvolatile_anyextloadi8, bdxaddr20only>,
212                      Requires<[FeatureHighWord]>;
213defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
214                                 nonvolatile_anyextloadi16, bdxaddr20only>,
215                      Requires<[FeatureHighWord]>;
216defm CondStore8     : CondStores<GR32, nonvolatile_truncstorei8,
217                                 nonvolatile_anyextloadi8, bdxaddr20only>;
218defm CondStore16    : CondStores<GR32, nonvolatile_truncstorei16,
219                                 nonvolatile_anyextloadi16, bdxaddr20only>;
220defm CondStore32    : CondStores<GR32, nonvolatile_store,
221                                 nonvolatile_load, bdxaddr20only>;
222
223defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
224                    nonvolatile_anyextloadi8, bdxaddr20only>;
225defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
226                    nonvolatile_anyextloadi16, bdxaddr20only>;
227defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
228                    nonvolatile_anyextloadi32, bdxaddr20only>;
229defm CondStore64 : CondStores<GR64, nonvolatile_store,
230                              nonvolatile_load, bdxaddr20only>;
231
232//===----------------------------------------------------------------------===//
233// Call instructions
234//===----------------------------------------------------------------------===//
235
236let isCall = 1, Defs = [R14D, CC] in {
237  def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
238                        [(z_call pcrel32:$I2)]>;
239  def CallBASR  : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
240                        [(z_call ADDR64:$R2)]>;
241}
242
243// Sibling calls.  Indirect sibling calls must be via R1, since R2 upwards
244// are argument registers and since branching to R0 is a no-op.
245let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
246  def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
247                     [(z_sibcall pcrel32:$I2)]>;
248  let Uses = [R1D] in
249    def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
250}
251
252// TLS calls.  These will be lowered into a call to __tls_get_offset,
253// with an extra relocation specifying the TLS symbol.
254let isCall = 1, Defs = [R14D, CC] in {
255  def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
256                         [(z_tls_gdcall tglobaltlsaddr:$I2)]>;
257  def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
258                         [(z_tls_ldcall tglobaltlsaddr:$I2)]>;
259}
260
261// Define the general form of the call instructions for the asm parser.
262// These instructions don't hard-code %r14 as the return address register.
263// Allow an optional TLS marker symbol to generate TLS call relocations.
264let isCall = 1, Defs = [CC] in {
265  def BRAS  : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16tls:$I2),
266                     "bras\t$R1, $I2", []>;
267  def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32tls:$I2),
268                      "brasl\t$R1, $I2", []>;
269  def BASR  : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
270                     "basr\t$R1, $R2", []>;
271}
272
273//===----------------------------------------------------------------------===//
274// Move instructions
275//===----------------------------------------------------------------------===//
276
277// Register moves.
278let hasSideEffects = 0 in {
279  // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
280  def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
281              Requires<[FeatureHighWord]>;
282  def LR  : UnaryRR <"l",  0x18,   null_frag, GR32, GR32>;
283  def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
284}
285let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
286  def LTR  : UnaryRR <"lt",  0x12,   null_frag, GR32, GR32>;
287  def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
288}
289
290// Move on condition.
291let isCodeGenOnly = 1, Uses = [CC] in {
292  def LOCR  : CondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
293  def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
294}
295let Uses = [CC] in {
296  def AsmLOCR  : AsmCondUnaryRRF<"loc",  0xB9F2, GR32, GR32>;
297  def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
298}
299
300// Immediate moves.
301let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
302    isReMaterializable = 1 in {
303  // 16-bit sign-extended immediates.  LHIMux expands to LHI or IIHF,
304  // deopending on the choice of register.
305  def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
306               Requires<[FeatureHighWord]>;
307  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
308  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
309
310  // Other 16-bit immediates.
311  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
312  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
313  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
314  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
315
316  // 32-bit immediates.
317  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
318  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
319  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
320}
321
322// Register loads.
323let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
324  // Expands to L, LY or LFH, depending on the choice of register.
325  def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
326             Requires<[FeatureHighWord]>;
327  defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
328  def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
329            Requires<[FeatureHighWord]>;
330  def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
331
332  // These instructions are split after register allocation, so we don't
333  // want a custom inserter.
334  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
335    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
336                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
337  }
338}
339let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
340  def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
341  def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
342}
343
344let canFoldAsLoad = 1 in {
345  def LRL  : UnaryRILPC<"lrl",  0xC4D, aligned_load, GR32>;
346  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
347}
348
349// Load on condition.
350let isCodeGenOnly = 1, Uses = [CC] in {
351  def LOC  : CondUnaryRSY<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
352  def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
353}
354let Uses = [CC] in {
355  def AsmLOC  : AsmCondUnaryRSY<"loc",  0xEBF2, GR32, 4>;
356  def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
357}
358
359// Register stores.
360let SimpleBDXStore = 1 in {
361  // Expands to ST, STY or STFH, depending on the choice of register.
362  def STMux : StoreRXYPseudo<store, GRX32, 4>,
363              Requires<[FeatureHighWord]>;
364  defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
365  def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
366             Requires<[FeatureHighWord]>;
367  def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
368
369  // These instructions are split after register allocation, so we don't
370  // want a custom inserter.
371  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
372    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
373                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
374  }
375}
376def STRL  : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
377def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
378
379// Store on condition.
380let isCodeGenOnly = 1, Uses = [CC] in {
381  def STOC  : CondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
382  def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
383}
384let Uses = [CC] in {
385  def AsmSTOC  : AsmCondStoreRSY<"stoc",  0xEBF3, GR32, 4>;
386  def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
387}
388
389// 8-bit immediate stores to 8-bit fields.
390defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
391
392// 16-bit immediate stores to 16-, 32- or 64-bit fields.
393def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
394def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
395def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;
396
397// Memory-to-memory moves.
398let mayLoad = 1, mayStore = 1 in
399  defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
400
401// String moves.
402let mayLoad = 1, mayStore = 1, Defs = [CC] in
403  defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
404
405//===----------------------------------------------------------------------===//
406// Sign extensions
407//===----------------------------------------------------------------------===//
408//
409// Note that putting these before zero extensions mean that we will prefer
410// them for anyextload*.  There's not really much to choose between the two
411// either way, but signed-extending loads have a short LH and a long LHY,
412// while zero-extending loads have only the long LLH.
413//
414//===----------------------------------------------------------------------===//
415
416// 32-bit extensions from registers.
417let hasSideEffects = 0 in {
418  def LBR : UnaryRRE<"lb", 0xB926, sext8,  GR32, GR32>;
419  def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
420}
421
422// 64-bit extensions from registers.
423let hasSideEffects = 0 in {
424  def LGBR : UnaryRRE<"lgb", 0xB906, sext8,  GR64, GR64>;
425  def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
426  def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
427}
428let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
429  def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR32>;
430
431// Match 32-to-64-bit sign extensions in which the source is already
432// in a 64-bit register.
433def : Pat<(sext_inreg GR64:$src, i32),
434          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
435
436// 32-bit extensions from 8-bit memory.  LBMux expands to LB or LBH,
437// depending on the choice of register.
438def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
439            Requires<[FeatureHighWord]>;
440def LB  : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
441def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
442          Requires<[FeatureHighWord]>;
443
444// 32-bit extensions from 16-bit memory.  LHMux expands to LH or LHH,
445// depending on the choice of register.
446def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
447            Requires<[FeatureHighWord]>;
448defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
449def  LHH  : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
450            Requires<[FeatureHighWord]>;
451def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
452
453// 64-bit extensions from memory.
454def LGB   : UnaryRXY<"lgb", 0xE377, asextloadi8,  GR64, 1>;
455def LGH   : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
456def LGF   : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
457def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
458def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
459let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
460  def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
461
462//===----------------------------------------------------------------------===//
463// Zero extensions
464//===----------------------------------------------------------------------===//
465
466// 32-bit extensions from registers.
467let hasSideEffects = 0 in {
468  // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
469  def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
470                Requires<[FeatureHighWord]>;
471  def LLCR    : UnaryRRE<"llc", 0xB994, zext8,  GR32, GR32>;
472  // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
473  def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
474                Requires<[FeatureHighWord]>;
475  def LLHR    : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
476}
477
478// 64-bit extensions from registers.
479let hasSideEffects = 0 in {
480  def LLGCR : UnaryRRE<"llgc", 0xB984, zext8,  GR64, GR64>;
481  def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
482  def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
483}
484
485// Match 32-to-64-bit zero extensions in which the source is already
486// in a 64-bit register.
487def : Pat<(and GR64:$src, 0xffffffff),
488          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
489
490// 32-bit extensions from 8-bit memory.  LLCMux expands to LLC or LLCH,
491// depending on the choice of register.
492def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
493             Requires<[FeatureHighWord]>;
494def LLC  : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
495def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>,
496           Requires<[FeatureHighWord]>;
497
498// 32-bit extensions from 16-bit memory.  LLHMux expands to LLH or LLHH,
499// depending on the choice of register.
500def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
501             Requires<[FeatureHighWord]>;
502def LLH   : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
503def LLHH  : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>,
504            Requires<[FeatureHighWord]>;
505def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
506
507// 64-bit extensions from memory.
508def LLGC   : UnaryRXY<"llgc", 0xE390, azextloadi8,  GR64, 1>;
509def LLGH   : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
510def LLGF   : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
511def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
512def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
513
514//===----------------------------------------------------------------------===//
515// Truncations
516//===----------------------------------------------------------------------===//
517
518// Truncations of 64-bit registers to 32-bit registers.
519def : Pat<(i32 (trunc GR64:$src)),
520          (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
521
522// Truncations of 32-bit registers to 8-bit memory.  STCMux expands to
523// STC, STCY or STCH, depending on the choice of register.
524def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
525             Requires<[FeatureHighWord]>;
526defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
527def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
528           Requires<[FeatureHighWord]>;
529
530// Truncations of 32-bit registers to 16-bit memory.  STHMux expands to
531// STH, STHY or STHH, depending on the choice of register.
532def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
533             Requires<[FeatureHighWord]>;
534defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
535def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
536           Requires<[FeatureHighWord]>;
537def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
538
539// Truncations of 64-bit registers to memory.
540defm : StoreGR64Pair<STC, STCY, truncstorei8>;
541defm : StoreGR64Pair<STH, STHY, truncstorei16>;
542def  : StoreGR64PC<STHRL, aligned_truncstorei16>;
543defm : StoreGR64Pair<ST, STY, truncstorei32>;
544def  : StoreGR64PC<STRL, aligned_truncstorei32>;
545
546//===----------------------------------------------------------------------===//
547// Multi-register moves
548//===----------------------------------------------------------------------===//
549
550// Multi-register loads.
551def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
552
553// Multi-register stores.
554def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
555
556//===----------------------------------------------------------------------===//
557// Byte swaps
558//===----------------------------------------------------------------------===//
559
560// Byte-swapping register moves.
561let hasSideEffects = 0 in {
562  def LRVR  : UnaryRRE<"lrv",  0xB91F, bswap, GR32, GR32>;
563  def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
564}
565
566// Byte-swapping loads.  Unlike normal loads, these instructions are
567// allowed to access storage more than once.
568def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
569def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
570
571// Likewise byte-swapping stores.
572def STRV  : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
573def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
574                     GR64, 8>;
575
576//===----------------------------------------------------------------------===//
577// Load address instructions
578//===----------------------------------------------------------------------===//
579
580// Load BDX-style addresses.
581let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1,
582    DispKey = "la" in {
583  let DispSize = "12" in
584    def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
585                    "la\t$R1, $XBD2",
586                    [(set GR64:$R1, laaddr12pair:$XBD2)]>;
587  let DispSize = "20" in
588    def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
589                      "lay\t$R1, $XBD2",
590                      [(set GR64:$R1, laaddr20pair:$XBD2)]>;
591}
592
593// Load a PC-relative address.  There's no version of this instruction
594// with a 16-bit offset, so there's no relaxation.
595let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
596    isReMaterializable = 1 in {
597  def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
598                     "larl\t$R1, $I2",
599                     [(set GR64:$R1, pcrel32:$I2)]>;
600}
601
602// Load the Global Offset Table address.  This will be lowered into a
603//     larl $R1, _GLOBAL_OFFSET_TABLE_
604// instruction.
605def GOT : Alias<6, (outs GR64:$R1), (ins),
606                [(set GR64:$R1, (global_offset_table))]>;
607
608//===----------------------------------------------------------------------===//
609// Absolute and Negation
610//===----------------------------------------------------------------------===//
611
612let Defs = [CC] in {
613  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
614    def LPR  : UnaryRR <"lp",  0x10,   z_iabs, GR32, GR32>;
615    def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>;
616  }
617  let CCValues = 0xE, CompareZeroCCMask = 0xE in
618    def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
619}
620def : Pat<(z_iabs32 GR32:$src), (LPR  GR32:$src)>;
621def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>;
622defm : SXU<z_iabs,   LPGFR>;
623defm : SXU<z_iabs64, LPGFR>;
624
625let Defs = [CC] in {
626  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
627    def LNR  : UnaryRR <"ln",  0x11,   z_inegabs, GR32, GR32>;
628    def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>;
629  }
630  let CCValues = 0xE, CompareZeroCCMask = 0xE in
631    def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
632}
633def : Pat<(z_inegabs32 GR32:$src), (LNR  GR32:$src)>;
634def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>;
635defm : SXU<z_inegabs,   LNGFR>;
636defm : SXU<z_inegabs64, LNGFR>;
637
638let Defs = [CC] in {
639  let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
640    def LCR  : UnaryRR <"lc",  0x13,   ineg, GR32, GR32>;
641    def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
642  }
643  let CCValues = 0xE, CompareZeroCCMask = 0xE in
644    def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
645}
646defm : SXU<ineg, LCGFR>;
647
648//===----------------------------------------------------------------------===//
649// Insertion
650//===----------------------------------------------------------------------===//
651
652let isCodeGenOnly = 1 in
653  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
654defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
655
656defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
657defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
658
659defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
660defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
661
662// Insertions of a 16-bit immediate, leaving other bits unaffected.
663// We don't have or_as_insert equivalents of these operations because
664// OI is available instead.
665//
666// IIxMux expands to II[LH]x, depending on the choice of register.
667def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
668             Requires<[FeatureHighWord]>;
669def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
670             Requires<[FeatureHighWord]>;
671def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
672def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
673def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
674def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
675def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
676def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
677def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
678def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
679
680// ...likewise for 32-bit immediates.  For GR32s this is a general
681// full-width move.  (We use IILF rather than something like LLILF
682// for 32-bit moves because IILF leaves the upper 32 bits of the
683// GR64 unchanged.)
684let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
685  def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
686               Requires<[FeatureHighWord]>;
687  def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
688  def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
689}
690def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
691def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
692
693// An alternative model of inserthf, with the first operand being
694// a zero-extended value.
695def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
696          (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
697                  imm64hf32:$imm)>;
698
699//===----------------------------------------------------------------------===//
700// Addition
701//===----------------------------------------------------------------------===//
702
703// Plain addition.
704let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
705  // Addition of a register.
706  let isCommutable = 1 in {
707    defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
708    defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
709  }
710  def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
711
712  // Addition of signed 16-bit immediates.
713  defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
714  defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
715  defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
716
717  // Addition of signed 32-bit immediates.
718  def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
719               Requires<[FeatureHighWord]>;
720  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
721  def AIH  : BinaryRIL<"aih",  0xCC8, add, GRH32, simm32>,
722             Requires<[FeatureHighWord]>;
723  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
724
725  // Addition of memory.
726  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
727  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
728  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
729  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
730
731  // Addition to memory.
732  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
733  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
734}
735defm : SXB<add, GR64, AGFR>;
736
737// Addition producing a carry.
738let Defs = [CC] in {
739  // Addition of a register.
740  let isCommutable = 1 in {
741    defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
742    defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
743  }
744  def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
745
746  // Addition of signed 16-bit immediates.
747  def ALHSIK  : BinaryRIE<"alhsik",  0xECDA, addc, GR32, imm32sx16>,
748                Requires<[FeatureDistinctOps]>;
749  def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
750                Requires<[FeatureDistinctOps]>;
751
752  // Addition of unsigned 32-bit immediates.
753  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
754  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
755
756  // Addition of memory.
757  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
758  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
759  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load, 8>;
760}
761defm : ZXB<addc, GR64, ALGFR>;
762
763// Addition producing and using a carry.
764let Defs = [CC], Uses = [CC] in {
765  // Addition of a register.
766  def ALCR  : BinaryRRE<"alc",  0xB998, adde, GR32, GR32>;
767  def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
768
769  // Addition of memory.
770  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load, 4>;
771  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
772}
773
774//===----------------------------------------------------------------------===//
775// Subtraction
776//===----------------------------------------------------------------------===//
777
778// Plain subtraction.  Although immediate forms exist, we use the
779// add-immediate instruction instead.
780let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
781  // Subtraction of a register.
782  defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
783  def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
784  defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
785
786  // Subtraction of memory.
787  defm SH  : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
788  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
789  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
790  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load, 8>;
791}
792defm : SXB<sub, GR64, SGFR>;
793
794// Subtraction producing a carry.
795let Defs = [CC] in {
796  // Subtraction of a register.
797  defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
798  def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
799  defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
800
801  // Subtraction of unsigned 32-bit immediates.  These don't match
802  // subc because we prefer addc for constants.
803  def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
804  def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
805
806  // Subtraction of memory.
807  defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
808  def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
809  def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
810}
811defm : ZXB<subc, GR64, SLGFR>;
812
813// Subtraction producing and using a carry.
814let Defs = [CC], Uses = [CC] in {
815  // Subtraction of a register.
816  def SLBR  : BinaryRRE<"slb",  0xB999, sube, GR32, GR32>;
817  def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
818
819  // Subtraction of memory.
820  def SLB  : BinaryRXY<"slb",  0xE399, sube, GR32, load, 4>;
821  def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
822}
823
824//===----------------------------------------------------------------------===//
825// AND
826//===----------------------------------------------------------------------===//
827
828let Defs = [CC] in {
829  // ANDs of a register.
830  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
831    defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
832    defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
833  }
834
835  let isConvertibleToThreeAddress = 1 in {
836    // ANDs of a 16-bit immediate, leaving other bits unaffected.
837    // The CC result only reflects the 16-bit field, not the full register.
838    //
839    // NIxMux expands to NI[LH]x, depending on the choice of register.
840    def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
841                 Requires<[FeatureHighWord]>;
842    def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
843                 Requires<[FeatureHighWord]>;
844    def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
845    def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
846    def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
847    def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
848    def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
849    def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
850    def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
851    def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
852
853    // ANDs of a 32-bit immediate, leaving other bits unaffected.
854    // The CC result only reflects the 32-bit field, which means we can
855    // use it as a zero indicator for i32 operations but not otherwise.
856    let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
857      // Expands to NILF or NIHF, depending on the choice of register.
858      def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
859                   Requires<[FeatureHighWord]>;
860      def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
861      def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
862    }
863    def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
864    def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
865  }
866
867  // ANDs of memory.
868  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
869    defm N  : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
870    def  NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
871  }
872
873  // AND to memory
874  defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>;
875
876  // Block AND.
877  let mayLoad = 1, mayStore = 1 in
878    defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
879}
880defm : RMWIByte<and, bdaddr12pair, NI>;
881defm : RMWIByte<and, bdaddr20pair, NIY>;
882
883//===----------------------------------------------------------------------===//
884// OR
885//===----------------------------------------------------------------------===//
886
887let Defs = [CC] in {
888  // ORs of a register.
889  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
890    defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
891    defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
892  }
893
894  // ORs of a 16-bit immediate, leaving other bits unaffected.
895  // The CC result only reflects the 16-bit field, not the full register.
896  //
897  // OIxMux expands to OI[LH]x, depending on the choice of register.
898  def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
899               Requires<[FeatureHighWord]>;
900  def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
901               Requires<[FeatureHighWord]>;
902  def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
903  def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
904  def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
905  def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
906  def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
907  def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
908  def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
909  def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
910
911  // ORs of a 32-bit immediate, leaving other bits unaffected.
912  // The CC result only reflects the 32-bit field, which means we can
913  // use it as a zero indicator for i32 operations but not otherwise.
914  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
915    // Expands to OILF or OIHF, depending on the choice of register.
916    def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
917                 Requires<[FeatureHighWord]>;
918    def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
919    def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
920  }
921  def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
922  def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
923
924  // ORs of memory.
925  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
926    defm O  : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
927    def  OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
928  }
929
930  // OR to memory
931  defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>;
932
933  // Block OR.
934  let mayLoad = 1, mayStore = 1 in
935    defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
936}
937defm : RMWIByte<or, bdaddr12pair, OI>;
938defm : RMWIByte<or, bdaddr20pair, OIY>;
939
940//===----------------------------------------------------------------------===//
941// XOR
942//===----------------------------------------------------------------------===//
943
944let Defs = [CC] in {
945  // XORs of a register.
946  let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
947    defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
948    defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
949  }
950
951  // XORs of a 32-bit immediate, leaving other bits unaffected.
952  // The CC result only reflects the 32-bit field, which means we can
953  // use it as a zero indicator for i32 operations but not otherwise.
954  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
955    // Expands to XILF or XIHF, depending on the choice of register.
956    def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
957                 Requires<[FeatureHighWord]>;
958    def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
959    def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
960  }
961  def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
962  def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
963
964  // XORs of memory.
965  let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
966    defm X  : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
967    def  XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
968  }
969
970  // XOR to memory
971  defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>;
972
973  // Block XOR.
974  let mayLoad = 1, mayStore = 1 in
975    defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
976}
977defm : RMWIByte<xor, bdaddr12pair, XI>;
978defm : RMWIByte<xor, bdaddr20pair, XIY>;
979
980//===----------------------------------------------------------------------===//
981// Multiplication
982//===----------------------------------------------------------------------===//
983
984// Multiplication of a register.
985let isCommutable = 1 in {
986  def MSR  : BinaryRRE<"ms",  0xB252, mul, GR32, GR32>;
987  def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
988}
989def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
990defm : SXB<mul, GR64, MSGFR>;
991
992// Multiplication of a signed 16-bit immediate.
993def MHI  : BinaryRI<"mhi",  0xA7C, mul, GR32, imm32sx16>;
994def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
995
996// Multiplication of a signed 32-bit immediate.
997def MSFI  : BinaryRIL<"msfi",  0xC21, mul, GR32, simm32>;
998def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
999
1000// Multiplication of memory.
1001defm MH   : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
1002defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
1003def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
1004def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
1005
1006// Multiplication of a register, producing two results.
1007def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
1008
1009// Multiplication of memory, producing two results.
1010def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
1011
1012//===----------------------------------------------------------------------===//
1013// Division and remainder
1014//===----------------------------------------------------------------------===//
1015
1016// Division and remainder, from registers.
1017def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
1018def DSGR  : BinaryRRE<"dsg",  0xB90D, z_sdivrem64, GR128, GR64>;
1019def DLR   : BinaryRRE<"dl",   0xB997, z_udivrem32, GR128, GR32>;
1020def DLGR  : BinaryRRE<"dlg",  0xB987, z_udivrem64, GR128, GR64>;
1021
1022// Division and remainder, from memory.
1023def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
1024def DSG  : BinaryRXY<"dsg",  0xE30D, z_sdivrem64, GR128, load, 8>;
1025def DL   : BinaryRXY<"dl",   0xE397, z_udivrem32, GR128, load, 4>;
1026def DLG  : BinaryRXY<"dlg",  0xE387, z_udivrem64, GR128, load, 8>;
1027
1028//===----------------------------------------------------------------------===//
1029// Shifts
1030//===----------------------------------------------------------------------===//
1031
1032// Shift left.
1033let hasSideEffects = 0 in {
1034  defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
1035  def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
1036}
1037
1038// Logical shift right.
1039let hasSideEffects = 0 in {
1040  defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
1041  def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
1042}
1043
1044// Arithmetic shift right.
1045let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1046  defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
1047  def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>;
1048}
1049
1050// Rotate left.
1051let hasSideEffects = 0 in {
1052  def RLL  : BinaryRSY<"rll",  0xEB1D, rotl, GR32>;
1053  def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
1054}
1055
1056// Rotate second operand left and inserted selected bits into first operand.
1057// These can act like 32-bit operands provided that the constant start and
1058// end bits (operands 2 and 3) are in the range [32, 64).
1059let Defs = [CC] in {
1060  let isCodeGenOnly = 1 in
1061    def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1062  let CCValues = 0xE, CompareZeroCCMask = 0xE in
1063    def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1064}
1065
1066// On zEC12 we have a variant of RISBG that does not set CC.
1067let Predicates = [FeatureMiscellaneousExtensions] in
1068  def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
1069
1070// Forms of RISBG that only affect one word of the destination register.
1071// They do not set CC.
1072let Predicates = [FeatureHighWord] in {
1073  def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
1074  def RISBLL  : RotateSelectAliasRIEf<GR32,  GR32>;
1075  def RISBLH  : RotateSelectAliasRIEf<GR32,  GRH32>;
1076  def RISBHL  : RotateSelectAliasRIEf<GRH32, GR32>;
1077  def RISBHH  : RotateSelectAliasRIEf<GRH32, GRH32>;
1078  def RISBLG  : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;
1079  def RISBHG  : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;
1080}
1081
1082// Rotate second operand left and perform a logical operation with selected
1083// bits of the first operand.  The CC result only describes the selected bits,
1084// so isn't useful for a full comparison against zero.
1085let Defs = [CC] in {
1086  def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1087  def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1088  def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1089}
1090
1091//===----------------------------------------------------------------------===//
1092// Comparison
1093//===----------------------------------------------------------------------===//
1094
1095// Signed comparisons.  We put these before the unsigned comparisons because
1096// some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1097// of the unsigned forms do.
1098let Defs = [CC], CCValues = 0xE in {
1099  // Comparison with a register.
1100  def CR   : CompareRR <"c",   0x19,   z_scmp,    GR32, GR32>;
1101  def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1102  def CGR  : CompareRRE<"cg",  0xB920, z_scmp,    GR64, GR64>;
1103
1104  // Comparison with a signed 16-bit immediate.
1105  def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
1106  def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1107
1108  // Comparison with a signed 32-bit immediate.  CFIMux expands to CFI or CIH,
1109  // depending on the choice of register.
1110  def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,
1111               Requires<[FeatureHighWord]>;
1112  def CFI  : CompareRIL<"cfi",  0xC2D, z_scmp, GR32, simm32>;
1113  def CIH  : CompareRIL<"cih",  0xCCD, z_scmp, GRH32, simm32>,
1114             Requires<[FeatureHighWord]>;
1115  def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1116
1117  // Comparison with memory.
1118  defm CH    : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1119  def  CMux  : CompareRXYPseudo<z_scmp, GRX32, load, 4>,
1120               Requires<[FeatureHighWord]>;
1121  defm C     : CompareRXPair<"c",  0x59, 0xE359, z_scmp, GR32, load, 4>;
1122  def  CHF   : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>,
1123               Requires<[FeatureHighWord]>;
1124  def  CGH   : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1125  def  CGF   : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1126  def  CG    : CompareRXY<"cg",  0xE320, z_scmp, GR64, load, 8>;
1127  def  CHRL  : CompareRILPC<"chrl",  0xC65, z_scmp, GR32, aligned_asextloadi16>;
1128  def  CRL   : CompareRILPC<"crl",   0xC6D, z_scmp, GR32, aligned_load>;
1129  def  CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1130  def  CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1131  def  CGRL  : CompareRILPC<"cgrl",  0xC68, z_scmp, GR64, aligned_load>;
1132
1133  // Comparison between memory and a signed 16-bit immediate.
1134  def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1135  def CHSI  : CompareSIL<"chsi",  0xE55C, z_scmp, load, imm32sx16>;
1136  def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1137}
1138defm : SXB<z_scmp, GR64, CGFR>;
1139
1140// Unsigned comparisons.
1141let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1142  // Comparison with a register.
1143  def CLR   : CompareRR <"cl",   0x15,   z_ucmp,    GR32, GR32>;
1144  def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1145  def CLGR  : CompareRRE<"clg",  0xB921, z_ucmp,    GR64, GR64>;
1146
1147  // Comparison with an unsigned 32-bit immediate.  CLFIMux expands to CLFI
1148  // or CLIH, depending on the choice of register.
1149  def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
1150                Requires<[FeatureHighWord]>;
1151  def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
1152  def CLIH  : CompareRIL<"clih",  0xCCF, z_ucmp, GRH32, uimm32>,
1153              Requires<[FeatureHighWord]>;
1154  def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1155
1156  // Comparison with memory.
1157  def  CLMux  : CompareRXYPseudo<z_ucmp, GRX32, load, 4>,
1158                Requires<[FeatureHighWord]>;
1159  defm CL     : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1160  def  CLHF   : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>,
1161                Requires<[FeatureHighWord]>;
1162  def  CLGF   : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1163  def  CLG    : CompareRXY<"clg",  0xE321, z_ucmp, GR64, load, 8>;
1164  def  CLHRL  : CompareRILPC<"clhrl",  0xC67, z_ucmp, GR32,
1165                             aligned_azextloadi16>;
1166  def  CLRL   : CompareRILPC<"clrl",   0xC6F, z_ucmp, GR32,
1167                             aligned_load>;
1168  def  CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1169                             aligned_azextloadi16>;
1170  def  CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1171                             aligned_azextloadi32>;
1172  def  CLGRL  : CompareRILPC<"clgrl",  0xC6A, z_ucmp, GR64,
1173                             aligned_load>;
1174
1175  // Comparison between memory and an unsigned 8-bit immediate.
1176  defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1177
1178  // Comparison between memory and an unsigned 16-bit immediate.
1179  def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1180  def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1181  def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1182}
1183defm : ZXB<z_ucmp, GR64, CLGFR>;
1184
1185// Memory-to-memory comparison.
1186let mayLoad = 1, Defs = [CC] in
1187  defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1188
1189// String comparison.
1190let mayLoad = 1, Defs = [CC] in
1191  defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1192
1193// Test under mask.
1194let Defs = [CC] in {
1195  // TMxMux expands to TM[LH]x, depending on the choice of register.
1196  def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
1197               Requires<[FeatureHighWord]>;
1198  def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
1199               Requires<[FeatureHighWord]>;
1200  def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1201  def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1202  def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
1203  def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
1204
1205  def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;
1206  def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;
1207  def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;
1208  def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;
1209
1210  defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1211}
1212
1213//===----------------------------------------------------------------------===//
1214// Prefetch
1215//===----------------------------------------------------------------------===//
1216
1217def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1218def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1219
1220//===----------------------------------------------------------------------===//
1221// Atomic operations
1222//===----------------------------------------------------------------------===//
1223
1224// A serialization instruction that acts as a barrier for all memory
1225// accesses, which expands to "bcr 14, 0".
1226let hasSideEffects = 1 in
1227def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
1228
1229let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
1230  def LAA   : LoadAndOpRSY<"laa",   0xEBF8, atomic_load_add_32, GR32>;
1231  def LAAG  : LoadAndOpRSY<"laag",  0xEBE8, atomic_load_add_64, GR64>;
1232  def LAAL  : LoadAndOpRSY<"laal",  0xEBFA, null_frag, GR32>;
1233  def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
1234  def LAN   : LoadAndOpRSY<"lan",   0xEBF4, atomic_load_and_32, GR32>;
1235  def LANG  : LoadAndOpRSY<"lang",  0xEBE4, atomic_load_and_64, GR64>;
1236  def LAO   : LoadAndOpRSY<"lao",   0xEBF6, atomic_load_or_32, GR32>;
1237  def LAOG  : LoadAndOpRSY<"laog",  0xEBE6, atomic_load_or_64, GR64>;
1238  def LAX   : LoadAndOpRSY<"lax",   0xEBF7, atomic_load_xor_32, GR32>;
1239  def LAXG  : LoadAndOpRSY<"laxg",  0xEBE7, atomic_load_xor_64, GR64>;
1240}
1241
1242def ATOMIC_SWAPW   : AtomicLoadWBinaryReg<z_atomic_swapw>;
1243def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
1244def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
1245
1246def ATOMIC_LOADW_AR  : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1247def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1248let Predicates = [FeatureNoInterlockedAccess1] in {
1249  def ATOMIC_LOAD_AR   : AtomicLoadBinaryReg32<atomic_load_add_32>;
1250  def ATOMIC_LOAD_AHI  : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1251  def ATOMIC_LOAD_AFI  : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1252  def ATOMIC_LOAD_AGR  : AtomicLoadBinaryReg64<atomic_load_add_64>;
1253  def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1254  def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1255}
1256
1257def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1258def ATOMIC_LOAD_SR  : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1259def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1260
1261def ATOMIC_LOADW_NR   : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1262def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1263let Predicates = [FeatureNoInterlockedAccess1] in {
1264  def ATOMIC_LOAD_NR     : AtomicLoadBinaryReg32<atomic_load_and_32>;
1265  def ATOMIC_LOAD_NILL   : AtomicLoadBinaryImm32<atomic_load_and_32,
1266                                                 imm32ll16c>;
1267  def ATOMIC_LOAD_NILH   : AtomicLoadBinaryImm32<atomic_load_and_32,
1268                                                 imm32lh16c>;
1269  def ATOMIC_LOAD_NILF   : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1270  def ATOMIC_LOAD_NGR    : AtomicLoadBinaryReg64<atomic_load_and_64>;
1271  def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1272                                                 imm64ll16c>;
1273  def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1274                                                 imm64lh16c>;
1275  def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1276                                                 imm64hl16c>;
1277  def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1278                                                 imm64hh16c>;
1279  def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1280                                                 imm64lf32c>;
1281  def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1282                                                 imm64hf32c>;
1283}
1284
1285def ATOMIC_LOADW_OR     : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1286def ATOMIC_LOADW_OILH   : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1287let Predicates = [FeatureNoInterlockedAccess1] in {
1288  def ATOMIC_LOAD_OR     : AtomicLoadBinaryReg32<atomic_load_or_32>;
1289  def ATOMIC_LOAD_OILL   : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1290  def ATOMIC_LOAD_OILH   : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1291  def ATOMIC_LOAD_OILF   : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1292  def ATOMIC_LOAD_OGR    : AtomicLoadBinaryReg64<atomic_load_or_64>;
1293  def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1294  def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1295  def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1296  def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1297  def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1298  def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1299}
1300
1301def ATOMIC_LOADW_XR     : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1302def ATOMIC_LOADW_XILF   : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1303let Predicates = [FeatureNoInterlockedAccess1] in {
1304  def ATOMIC_LOAD_XR     : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1305  def ATOMIC_LOAD_XILF   : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1306  def ATOMIC_LOAD_XGR    : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1307  def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1308  def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1309}
1310
1311def ATOMIC_LOADW_NRi    : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1312def ATOMIC_LOADW_NILHi  : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1313                                               imm32lh16c>;
1314def ATOMIC_LOAD_NRi     : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1315def ATOMIC_LOAD_NILLi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1316                                                imm32ll16c>;
1317def ATOMIC_LOAD_NILHi   : AtomicLoadBinaryImm32<atomic_load_nand_32,
1318                                                imm32lh16c>;
1319def ATOMIC_LOAD_NILFi   : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1320def ATOMIC_LOAD_NGRi    : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1321def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1322                                                imm64ll16c>;
1323def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1324                                                imm64lh16c>;
1325def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1326                                                imm64hl16c>;
1327def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1328                                                imm64hh16c>;
1329def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1330                                                imm64lf32c>;
1331def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1332                                                imm64hf32c>;
1333
1334def ATOMIC_LOADW_MIN    : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1335def ATOMIC_LOAD_MIN_32  : AtomicLoadBinaryReg32<atomic_load_min_32>;
1336def ATOMIC_LOAD_MIN_64  : AtomicLoadBinaryReg64<atomic_load_min_64>;
1337
1338def ATOMIC_LOADW_MAX    : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1339def ATOMIC_LOAD_MAX_32  : AtomicLoadBinaryReg32<atomic_load_max_32>;
1340def ATOMIC_LOAD_MAX_64  : AtomicLoadBinaryReg64<atomic_load_max_64>;
1341
1342def ATOMIC_LOADW_UMIN   : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1343def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1344def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1345
1346def ATOMIC_LOADW_UMAX   : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1347def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1348def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1349
1350def ATOMIC_CMP_SWAPW
1351  : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1352                                  ADDR32:$bitshift, ADDR32:$negbitshift,
1353                                  uimm32:$bitsize),
1354           [(set GR32:$dst,
1355                 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1356                                     ADDR32:$bitshift, ADDR32:$negbitshift,
1357                                     uimm32:$bitsize))]> {
1358  let Defs = [CC];
1359  let mayLoad = 1;
1360  let mayStore = 1;
1361  let usesCustomInserter = 1;
1362}
1363
1364let Defs = [CC] in {
1365  defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1366  def  CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1367}
1368
1369//===----------------------------------------------------------------------===//
1370// Transactional execution
1371//===----------------------------------------------------------------------===//
1372
1373let Predicates = [FeatureTransactionalExecution] in {
1374  // Transaction Begin
1375  let hasSideEffects = 1, mayStore = 1,
1376      usesCustomInserter = 1, Defs = [CC] in {
1377    def TBEGIN : InstSIL<0xE560,
1378                         (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1379                         "tbegin\t$BD1, $I2",
1380                         [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
1381    def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1382                                [(z_tbegin_nofloat bdaddr12only:$BD1,
1383                                                   imm32zx16:$I2)]>;
1384    def TBEGINC : InstSIL<0xE561,
1385                          (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1386                          "tbeginc\t$BD1, $I2",
1387                          [(int_s390_tbeginc bdaddr12only:$BD1,
1388                                             imm32zx16:$I2)]>;
1389  }
1390
1391  // Transaction End
1392  let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
1393    def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
1394
1395  // Transaction Abort
1396  let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
1397    def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
1398                       "tabort\t$BD2",
1399                       [(int_s390_tabort bdaddr12only:$BD2)]>;
1400
1401  // Nontransactional Store
1402  let hasSideEffects = 1 in
1403    def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
1404
1405  // Extract Transaction Nesting Depth
1406  let hasSideEffects = 1 in
1407    def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
1408}
1409
1410//===----------------------------------------------------------------------===//
1411// Processor assist
1412//===----------------------------------------------------------------------===//
1413
1414let Predicates = [FeatureProcessorAssist] in {
1415  let hasSideEffects = 1, R4 = 0 in
1416    def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
1417                      "ppa\t$R1, $R2, $R3", []>;
1418  def : Pat<(int_s390_ppa_txassist GR32:$src),
1419            (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
1420                 0, 1)>;
1421}
1422
1423//===----------------------------------------------------------------------===//
1424// Miscellaneous Instructions.
1425//===----------------------------------------------------------------------===//
1426
1427// Extract CC into bits 29 and 28 of a register.
1428let Uses = [CC] in
1429  def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1430
1431// Read a 32-bit access register into a GR32.  As with all GR32 operations,
1432// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1433// when a 64-bit address is stored in a pair of access registers.
1434def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1435                  "ear\t$R1, $R2",
1436                  [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1437
1438// Find leftmost one, AKA count leading zeros.  The instruction actually
1439// returns a pair of GR64s, the first giving the number of leading zeros
1440// and the second giving a copy of the source with the leftmost one bit
1441// cleared.  We only use the first result here.
1442let Defs = [CC] in {
1443  def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1444}
1445def : Pat<(ctlz GR64:$src),
1446          (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1447
1448// Population count.  Counts bits set per byte.
1449let Predicates = [FeaturePopulationCount], Defs = [CC] in {
1450  def POPCNT : InstRRE<0xB9E1, (outs GR64:$R1), (ins GR64:$R2),
1451                       "popcnt\t$R1, $R2",
1452                       [(set GR64:$R1, (z_popcnt GR64:$R2))]>;
1453}
1454
1455// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1456def : Pat<(i64 (anyext GR32:$src)),
1457          (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1458
1459// Extend GR32s and GR64s to GR128s.
1460let usesCustomInserter = 1 in {
1461  def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1462  def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1463  def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1464}
1465
1466// Search a block of memory for a character.
1467let mayLoad = 1, Defs = [CC] in
1468  defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1469
1470// Other instructions for inline assembly
1471let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1472  def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2),
1473                       "stck\t$BD2",
1474                       []>;
1475let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1476  def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2),
1477                       "stckf\t$BD2",
1478                       []>;
1479let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1480  def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2),
1481                       "stcke\t$BD2",
1482                       []>;
1483let hasSideEffects = 1, Defs = [CC], mayStore = 1 in
1484  def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2),
1485                       "stfle\t$BD2",
1486                       []>;
1487
1488
1489
1490//===----------------------------------------------------------------------===//
1491// Peepholes.
1492//===----------------------------------------------------------------------===//
1493
1494// Use AL* for GR64 additions of unsigned 32-bit values.
1495defm : ZXB<add, GR64, ALGFR>;
1496def  : Pat<(add GR64:$src1, imm64zx32:$src2),
1497           (ALGFI GR64:$src1, imm64zx32:$src2)>;
1498def  : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1499           (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1500
1501// Use SL* for GR64 subtractions of unsigned 32-bit values.
1502defm : ZXB<sub, GR64, SLGFR>;
1503def  : Pat<(add GR64:$src1, imm64zx32n:$src2),
1504           (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1505def  : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1506           (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1507
1508// Optimize sign-extended 1/0 selects to -1/0 selects.  This is important
1509// for vector legalization.
1510def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)),
1511                         (i32 31)),
1512                    (i32 31)),
1513          (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1514def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid,
1515                                                       imm32zx4:$cc)))),
1516                    (i32 63)),
1517               (i32 63)),
1518          (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1519
1520// Peepholes for turning scalar operations into block operations.
1521defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1522                      XCSequence, 1>;
1523defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1524                      XCSequence, 2>;
1525defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1526                      XCSequence, 4>;
1527defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1528                      OCSequence, XCSequence, 1>;
1529defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1530                      XCSequence, 2>;
1531defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1532                      XCSequence, 4>;
1533defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
1534                      XCSequence, 8>;
1535