1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14let hasNoSchedulingInfo = 1 in { 15 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 16 [(callseq_start timm:$amt1, timm:$amt2)]>; 17 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_end timm:$amt1, timm:$amt2)]>; 19} 20 21let hasSideEffects = 0 in { 22 // Takes as input the value of the stack pointer after a dynamic allocation 23 // has been made. Sets the output to the address of the dynamically- 24 // allocated area itself, skipping the outgoing arguments. 25 // 26 // This expands to an LA or LAY instruction. We restrict the offset 27 // to the range of LA and keep the LAY range in reserve for when 28 // the size of the outgoing arguments is added. 29 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31} 32 33//===----------------------------------------------------------------------===// 34// Branch instructions 35//===----------------------------------------------------------------------===// 36 37// Conditional branches. 38let isBranch = 1, isTerminator = 1, Uses = [CC] in { 39 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 40 // with the condition-code mask being the first operand. It seems friendlier 41 // to use mnemonic forms like JE and JLH when writing out the assembly though. 42 let isCodeGenOnly = 1 in { 43 // An assembler extended mnemonic for BRC. 44 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 45 // An assembler extended mnemonic for BRCL. (The extension is "G" 46 // rather than "L" because "JL" is "Jump if Less".) 47 def BRCL : CondBranchRIL<"jg#", 0xC04>; 48 let isIndirectBranch = 1 in { 49 def BC : CondBranchRX<"b#", 0x47>; 50 def BCR : CondBranchRR<"b#r", 0x07>; 51 } 52 } 53 54 // Allow using the raw forms directly from the assembler (and occasional 55 // special code generation needs) as well. 56 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 57 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 58 let isIndirectBranch = 1 in { 59 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 60 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 61 } 62 63 // Define AsmParser extended mnemonics for each general condition-code mask 64 // (integer or floating-point) 65 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 66 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 67 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 68 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 69 let isIndirectBranch = 1 in { 70 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 71 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 72 } 73 } 74} 75 76// Unconditional branches. These are in fact simply variants of the 77// conditional branches with the condition mask set to "always". 78let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 79 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 80 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 81 let isIndirectBranch = 1 in { 82 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 83 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 84 } 85} 86 87// NOPs. These are again variants of the conditional branches, 88// with the condition mask set to "never". 89def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 90def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 91 92// Fused compare-and-branch instructions. 93// 94// These instructions do not use or clobber the condition codes. 95// We nevertheless pretend that the relative compare-and-branch 96// instructions clobber CC, so that we can lower them to separate 97// comparisons and BRCLs if the branch ends up being out of range. 98let isBranch = 1, isTerminator = 1 in { 99 // As for normal branches, we handle these instructions internally in 100 // their raw CRJ-like form, but use assembly macros like CRJE when writing 101 // them out. Using the *Pair multiclasses, we also create the raw forms. 102 let Defs = [CC] in { 103 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 104 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 105 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 106 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 107 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 108 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 109 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 110 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 111 } 112 let isIndirectBranch = 1 in { 113 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 114 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 115 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 116 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 117 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 118 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 119 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 120 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 121 } 122 123 // Define AsmParser mnemonics for each integer condition-code mask. 124 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 125 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 126 let Defs = [CC] in { 127 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 128 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 129 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 130 imm32sx8>; 131 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 132 imm64sx8>; 133 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 134 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 135 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 136 imm32zx8>; 137 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 138 imm64zx8>; 139 } 140 let isIndirectBranch = 1 in { 141 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 142 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 143 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 144 imm32sx8>; 145 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 146 imm64sx8>; 147 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 148 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 149 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 150 imm32zx8>; 151 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 152 imm64zx8>; 153 } 154 } 155} 156 157// Decrement a register and branch if it is nonzero. These don't clobber CC, 158// but we might need to split long relative branches into sequences that do. 159let isBranch = 1, isTerminator = 1 in { 160 let Defs = [CC] in { 161 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 162 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 163 } 164 // This doesn't need to clobber CC since we never need to split it. 165 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 166 Requires<[FeatureHighWord]>; 167 168 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 169 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 170 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 171 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 172} 173 174let isBranch = 1, isTerminator = 1 in { 175 let Defs = [CC] in { 176 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 177 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 178 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 179 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 180 } 181 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 182 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 183 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 184 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 185} 186 187//===----------------------------------------------------------------------===// 188// Trap instructions 189//===----------------------------------------------------------------------===// 190 191// Unconditional trap. 192let hasCtrlDep = 1 in 193 def Trap : Alias<4, (outs), (ins), [(trap)]>; 194 195// Conditional trap. 196let hasCtrlDep = 1, Uses = [CC] in 197 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 198 199// Fused compare-and-trap instructions. 200let hasCtrlDep = 1 in { 201 // These patterns work the same way as for compare-and-branch. 202 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 203 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 204 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 205 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 206 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 207 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 208 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 209 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 210 let Predicates = [FeatureMiscellaneousExtensions] in { 211 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 212 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 213 } 214 215 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 216 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 217 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 218 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 219 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 220 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 221 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 222 imm32sx16>; 223 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 224 imm64sx16>; 225 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 226 imm32zx16>; 227 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 228 imm64zx16>; 229 let Predicates = [FeatureMiscellaneousExtensions] in { 230 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 231 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 232 } 233 } 234} 235 236//===----------------------------------------------------------------------===// 237// Call and return instructions 238//===----------------------------------------------------------------------===// 239 240// Define the general form of the call instructions for the asm parser. 241// These instructions don't hard-code %r14 as the return address register. 242let isCall = 1, Defs = [CC] in { 243 def BRAS : CallRI <"bras", 0xA75>; 244 def BRASL : CallRIL<"brasl", 0xC05>; 245 def BAS : CallRX <"bas", 0x4D>; 246 def BASR : CallRR <"basr", 0x0D>; 247} 248 249// Regular calls. 250let isCall = 1, Defs = [R14D, CC] in { 251 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 252 [(z_call pcrel32:$I2)]>; 253 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 254 [(z_call ADDR64:$R2)]>; 255} 256 257// TLS calls. These will be lowered into a call to __tls_get_offset, 258// with an extra relocation specifying the TLS symbol. 259let isCall = 1, Defs = [R14D, CC] in { 260 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 261 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 262 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 263 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 264} 265 266// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 267// are argument registers and since branching to R0 is a no-op. 268let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 269 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 270 [(z_sibcall pcrel32:$I2)]>; 271 let Uses = [R1D] in 272 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 273} 274 275// Conditional sibling calls. 276let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 277 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 278 pcrel32:$I2), []>; 279 let Uses = [R1D] in 280 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 281} 282 283// Fused compare and conditional sibling calls. 284let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 285 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 286 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 287 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 288 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 289 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 290 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 291 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 292 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 293} 294 295// A return instruction (br %r14). 296let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 297 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 298 299// A conditional return instruction (bcr <cond>, %r14). 300let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 301 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 302 303// Fused compare and conditional returns. 304let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 305 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 306 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 307 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 308 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 309 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 310 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 311 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 312 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 313} 314 315//===----------------------------------------------------------------------===// 316// Select instructions 317//===----------------------------------------------------------------------===// 318 319def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>; 320def Select32 : SelectWrapper<GR32>; 321def Select64 : SelectWrapper<GR64>; 322 323// We don't define 32-bit Mux stores if we don't have STOCFH, because the 324// low-only STOC should then always be used if possible. 325defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 326 nonvolatile_anyextloadi8, bdxaddr20only>, 327 Requires<[FeatureHighWord]>; 328defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 329 nonvolatile_anyextloadi16, bdxaddr20only>, 330 Requires<[FeatureHighWord]>; 331defm CondStore32Mux : CondStores<GRX32, nonvolatile_store, 332 nonvolatile_load, bdxaddr20only>, 333 Requires<[FeatureLoadStoreOnCond2]>; 334defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 335 nonvolatile_anyextloadi8, bdxaddr20only>; 336defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 337 nonvolatile_anyextloadi16, bdxaddr20only>; 338defm CondStore32 : CondStores<GR32, nonvolatile_store, 339 nonvolatile_load, bdxaddr20only>; 340 341defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 342 nonvolatile_anyextloadi8, bdxaddr20only>; 343defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 344 nonvolatile_anyextloadi16, bdxaddr20only>; 345defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 346 nonvolatile_anyextloadi32, bdxaddr20only>; 347defm CondStore64 : CondStores<GR64, nonvolatile_store, 348 nonvolatile_load, bdxaddr20only>; 349 350//===----------------------------------------------------------------------===// 351// Move instructions 352//===----------------------------------------------------------------------===// 353 354// Register moves. 355let hasSideEffects = 0 in { 356 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 357 def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>, 358 Requires<[FeatureHighWord]>; 359 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 360 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 361} 362let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 363 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 364 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 365} 366 367// Immediate moves. 368let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 369 isReMaterializable = 1 in { 370 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 371 // deopending on the choice of register. 372 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 373 Requires<[FeatureHighWord]>; 374 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 375 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 376 377 // Other 16-bit immediates. 378 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 379 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 380 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 381 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 382 383 // 32-bit immediates. 384 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 385 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 386 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 387} 388 389// Register loads. 390let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 391 // Expands to L, LY or LFH, depending on the choice of register. 392 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 393 Requires<[FeatureHighWord]>; 394 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 395 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 396 Requires<[FeatureHighWord]>; 397 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 398 399 // These instructions are split after register allocation, so we don't 400 // want a custom inserter. 401 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 402 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 403 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 404 } 405} 406let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 407 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 408 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 409} 410 411let canFoldAsLoad = 1 in { 412 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 413 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 414} 415 416// Load and zero rightmost byte. 417let Predicates = [FeatureLoadAndZeroRightmostByte] in { 418 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 419 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 420 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 421 (LZRF bdxaddr20only:$src)>; 422 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 423 (LZRG bdxaddr20only:$src)>; 424} 425 426// Load and trap. 427let Predicates = [FeatureLoadAndTrap] in { 428 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 429 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 430 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 431} 432 433// Register stores. 434let SimpleBDXStore = 1 in { 435 // Expands to ST, STY or STFH, depending on the choice of register. 436 def STMux : StoreRXYPseudo<store, GRX32, 4>, 437 Requires<[FeatureHighWord]>; 438 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 439 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 440 Requires<[FeatureHighWord]>; 441 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 442 443 // These instructions are split after register allocation, so we don't 444 // want a custom inserter. 445 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 446 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 447 [(store GR128:$src, bdxaddr20only128:$dst)]>; 448 } 449} 450def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 451def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 452 453// 8-bit immediate stores to 8-bit fields. 454defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 455 456// 16-bit immediate stores to 16-, 32- or 64-bit fields. 457def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 458def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 459def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 460 461// Memory-to-memory moves. 462let mayLoad = 1, mayStore = 1 in 463 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 464let mayLoad = 1, mayStore = 1, Defs = [CC] in { 465 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 466 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 467 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 468} 469 470// String moves. 471let mayLoad = 1, mayStore = 1, Defs = [CC] in 472 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 473 474//===----------------------------------------------------------------------===// 475// Conditional move instructions 476//===----------------------------------------------------------------------===// 477 478let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 479 // Load immediate on condition. Matched via DAG pattern and created 480 // by the PeepholeOptimizer via FoldImmediate. 481 let hasSideEffects = 0 in { 482 // Expands to LOCHI or LOCHHI, depending on the choice of register. 483 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 484 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 485 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 486 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 487 } 488 489 // Move register on condition. Expanded from Select* pseudos and 490 // created by early if-conversion. 491 let hasSideEffects = 0, isCommutable = 1 in { 492 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 493 // depending on the choice of registers. 494 def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>; 495 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 496 } 497 498 // Load on condition. Matched via DAG pattern. 499 // Expands to LOC or LOCFH, depending on the choice of register. 500 def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>; 501 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>; 502 503 // Store on condition. Expanded from CondStore* pseudos. 504 // Expands to STOC or STOCFH, depending on the choice of register. 505 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 506 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 507 508 // Define AsmParser extended mnemonics for each general condition-code mask. 509 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 510 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 511 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 512 imm32sx16>; 513 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 514 imm64sx16>; 515 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 516 imm32sx16>; 517 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 518 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 519 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 520 } 521} 522 523let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 524 // Move register on condition. Expanded from Select* pseudos and 525 // created by early if-conversion. 526 let hasSideEffects = 0, isCommutable = 1 in { 527 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 528 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 529 } 530 531 // Load on condition. Matched via DAG pattern. 532 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 533 defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 534 535 // Store on condition. Expanded from CondStore* pseudos. 536 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 537 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 538 539 // Define AsmParser extended mnemonics for each general condition-code mask. 540 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 541 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 542 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 543 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 544 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 545 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 546 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 547 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 548 } 549} 550//===----------------------------------------------------------------------===// 551// Sign extensions 552//===----------------------------------------------------------------------===// 553// 554// Note that putting these before zero extensions mean that we will prefer 555// them for anyextload*. There's not really much to choose between the two 556// either way, but signed-extending loads have a short LH and a long LHY, 557// while zero-extending loads have only the long LLH. 558// 559//===----------------------------------------------------------------------===// 560 561// 32-bit extensions from registers. 562let hasSideEffects = 0 in { 563 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 564 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 565} 566 567// 64-bit extensions from registers. 568let hasSideEffects = 0 in { 569 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 570 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 571 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 572} 573let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 574 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 575 576// Match 32-to-64-bit sign extensions in which the source is already 577// in a 64-bit register. 578def : Pat<(sext_inreg GR64:$src, i32), 579 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 580 581// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 582// depending on the choice of register. 583def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 584 Requires<[FeatureHighWord]>; 585def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 586def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 587 Requires<[FeatureHighWord]>; 588 589// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 590// depending on the choice of register. 591def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 592 Requires<[FeatureHighWord]>; 593defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 594def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 595 Requires<[FeatureHighWord]>; 596def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 597 598// 64-bit extensions from memory. 599def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 600def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 601def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 602def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 603def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 604let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 605 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 606 607//===----------------------------------------------------------------------===// 608// Zero extensions 609//===----------------------------------------------------------------------===// 610 611// 32-bit extensions from registers. 612let hasSideEffects = 0 in { 613 // Expands to LLCR or RISB[LH]G, depending on the choice of registers. 614 def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 615 Requires<[FeatureHighWord]>; 616 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 617 // Expands to LLHR or RISB[LH]G, depending on the choice of registers. 618 def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 619 Requires<[FeatureHighWord]>; 620 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 621} 622 623// 64-bit extensions from registers. 624let hasSideEffects = 0 in { 625 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 626 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 627 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 628} 629 630// Match 32-to-64-bit zero extensions in which the source is already 631// in a 64-bit register. 632def : Pat<(and GR64:$src, 0xffffffff), 633 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 634 635// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 636// depending on the choice of register. 637def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 638 Requires<[FeatureHighWord]>; 639def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 640def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 641 Requires<[FeatureHighWord]>; 642 643// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 644// depending on the choice of register. 645def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 646 Requires<[FeatureHighWord]>; 647def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 648def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 649 Requires<[FeatureHighWord]>; 650def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 651 652// 64-bit extensions from memory. 653def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 654def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 655def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 656def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 657def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 658 659// 31-to-64-bit zero extensions. 660def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 661def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 662def : Pat<(and GR64:$src, 0x7fffffff), 663 (LLGTR GR64:$src)>; 664def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 665 (LLGT bdxaddr20only:$src)>; 666 667// Load and zero rightmost byte. 668let Predicates = [FeatureLoadAndZeroRightmostByte] in { 669 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 670 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 671 (LLZRGF bdxaddr20only:$src)>; 672} 673 674// Load and trap. 675let Predicates = [FeatureLoadAndTrap] in { 676 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 677 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 678} 679 680//===----------------------------------------------------------------------===// 681// Truncations 682//===----------------------------------------------------------------------===// 683 684// Truncations of 64-bit registers to 32-bit registers. 685def : Pat<(i32 (trunc GR64:$src)), 686 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 687 688// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 689// STC, STCY or STCH, depending on the choice of register. 690def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 691 Requires<[FeatureHighWord]>; 692defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 693def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 694 Requires<[FeatureHighWord]>; 695 696// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 697// STH, STHY or STHH, depending on the choice of register. 698def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 699 Requires<[FeatureHighWord]>; 700defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 701def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 702 Requires<[FeatureHighWord]>; 703def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 704 705// Truncations of 64-bit registers to memory. 706defm : StoreGR64Pair<STC, STCY, truncstorei8>; 707defm : StoreGR64Pair<STH, STHY, truncstorei16>; 708def : StoreGR64PC<STHRL, aligned_truncstorei16>; 709defm : StoreGR64Pair<ST, STY, truncstorei32>; 710def : StoreGR64PC<STRL, aligned_truncstorei32>; 711 712// Store characters under mask -- not (yet) used for codegen. 713defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 714def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 715 716//===----------------------------------------------------------------------===// 717// Multi-register moves 718//===----------------------------------------------------------------------===// 719 720// Multi-register loads. 721defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 722def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 723def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 724def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 725 726// Multi-register stores. 727defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 728def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 729def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 730 731//===----------------------------------------------------------------------===// 732// Byte swaps 733//===----------------------------------------------------------------------===// 734 735// Byte-swapping register moves. 736let hasSideEffects = 0 in { 737 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 738 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 739} 740 741// Byte-swapping loads. Unlike normal loads, these instructions are 742// allowed to access storage more than once. 743def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 744def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 745def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 746 747// Likewise byte-swapping stores. 748def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 749def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 750def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 751 752// Byte-swapping memory-to-memory moves. 753let mayLoad = 1, mayStore = 1 in 754 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 755 756//===----------------------------------------------------------------------===// 757// Load address instructions 758//===----------------------------------------------------------------------===// 759 760// Load BDX-style addresses. 761let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1 in 762 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 763 764// Load a PC-relative address. There's no version of this instruction 765// with a 16-bit offset, so there's no relaxation. 766let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 767 isReMaterializable = 1 in 768 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 769 770// Load the Global Offset Table address. This will be lowered into a 771// larl $R1, _GLOBAL_OFFSET_TABLE_ 772// instruction. 773def GOT : Alias<6, (outs GR64:$R1), (ins), 774 [(set GR64:$R1, (global_offset_table))]>; 775 776//===----------------------------------------------------------------------===// 777// Absolute and Negation 778//===----------------------------------------------------------------------===// 779 780let Defs = [CC] in { 781 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 782 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 783 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 784 } 785 let CCValues = 0xE, CompareZeroCCMask = 0xE in 786 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 787} 788def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 789def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 790defm : SXU<z_iabs, LPGFR>; 791defm : SXU<z_iabs64, LPGFR>; 792 793let Defs = [CC] in { 794 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 795 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 796 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 797 } 798 let CCValues = 0xE, CompareZeroCCMask = 0xE in 799 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 800} 801def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 802def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 803defm : SXU<z_inegabs, LNGFR>; 804defm : SXU<z_inegabs64, LNGFR>; 805 806let Defs = [CC] in { 807 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 808 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 809 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 810 } 811 let CCValues = 0xE, CompareZeroCCMask = 0xE in 812 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 813} 814defm : SXU<ineg, LCGFR>; 815 816//===----------------------------------------------------------------------===// 817// Insertion 818//===----------------------------------------------------------------------===// 819 820let isCodeGenOnly = 1 in 821 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 822defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 823 824defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 825defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 826 827defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 828defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 829 830// Insert characters under mask -- not (yet) used for codegen. 831let Defs = [CC] in { 832 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 833 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 834} 835 836// Insertions of a 16-bit immediate, leaving other bits unaffected. 837// We don't have or_as_insert equivalents of these operations because 838// OI is available instead. 839// 840// IIxMux expands to II[LH]x, depending on the choice of register. 841def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 842 Requires<[FeatureHighWord]>; 843def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 844 Requires<[FeatureHighWord]>; 845def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 846def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 847def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 848def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 849def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 850def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 851def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 852def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 853 854// ...likewise for 32-bit immediates. For GR32s this is a general 855// full-width move. (We use IILF rather than something like LLILF 856// for 32-bit moves because IILF leaves the upper 32 bits of the 857// GR64 unchanged.) 858let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 859 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 860 Requires<[FeatureHighWord]>; 861 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 862 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 863} 864def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 865def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 866 867// An alternative model of inserthf, with the first operand being 868// a zero-extended value. 869def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 870 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 871 imm64hf32:$imm)>; 872 873//===----------------------------------------------------------------------===// 874// Addition 875//===----------------------------------------------------------------------===// 876 877// Plain addition. 878let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 879 // Addition of a register. 880 let isCommutable = 1 in { 881 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, add, GR32, GR32>; 882 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, add, GR64, GR64>; 883 } 884 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 885 886 // Addition to a high register. 887 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 888 Requires<[FeatureHighWord]>; 889 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 890 Requires<[FeatureHighWord]>; 891 892 // Addition of signed 16-bit immediates. 893 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 894 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 895 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 896 897 // Addition of signed 32-bit immediates. 898 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 899 Requires<[FeatureHighWord]>; 900 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 901 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 902 Requires<[FeatureHighWord]>; 903 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 904 905 // Addition of memory. 906 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 907 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 908 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 909 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 910 911 // Addition to memory. 912 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 913 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 914} 915defm : SXB<add, GR64, AGFR>; 916 917// Addition producing a carry. 918let Defs = [CC] in { 919 // Addition of a register. 920 let isCommutable = 1 in { 921 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, addc, GR32, GR32>; 922 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, addc, GR64, GR64>; 923 } 924 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 925 926 // Addition to a high register. 927 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 928 Requires<[FeatureHighWord]>; 929 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 930 Requires<[FeatureHighWord]>; 931 932 // Addition of signed 16-bit immediates. 933 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 934 Requires<[FeatureDistinctOps]>; 935 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 936 Requires<[FeatureDistinctOps]>; 937 938 // Addition of unsigned 32-bit immediates. 939 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 940 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 941 942 // Addition of signed 32-bit immediates. 943 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 944 Requires<[FeatureHighWord]>; 945 946 // Addition of memory. 947 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 948 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 949 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 950 951 // Addition to memory. 952 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 953 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 954} 955defm : ZXB<addc, GR64, ALGFR>; 956 957// Addition producing and using a carry. 958let Defs = [CC], Uses = [CC] in { 959 // Addition of a register. 960 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>; 961 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>; 962 963 // Addition of memory. 964 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 965 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 966} 967 968// Addition that does not modify the condition code. 969def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 970 Requires<[FeatureHighWord]>; 971 972//===----------------------------------------------------------------------===// 973// Subtraction 974//===----------------------------------------------------------------------===// 975 976// Plain subtraction. Although immediate forms exist, we use the 977// add-immediate instruction instead. 978let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 979 // Subtraction of a register. 980 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, sub, GR32, GR32>; 981 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 982 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, sub, GR64, GR64>; 983 984 // Subtraction from a high register. 985 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 986 Requires<[FeatureHighWord]>; 987 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 988 Requires<[FeatureHighWord]>; 989 990 // Subtraction of memory. 991 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 992 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 993 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 994 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 995} 996defm : SXB<sub, GR64, SGFR>; 997 998// Subtraction producing a carry. 999let Defs = [CC] in { 1000 // Subtraction of a register. 1001 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, subc, GR32, GR32>; 1002 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1003 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, subc, GR64, GR64>; 1004 1005 // Subtraction from a high register. 1006 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1007 Requires<[FeatureHighWord]>; 1008 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1009 Requires<[FeatureHighWord]>; 1010 1011 // Subtraction of unsigned 32-bit immediates. These don't match 1012 // subc because we prefer addc for constants. 1013 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 1014 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 1015 1016 // Subtraction of memory. 1017 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 1018 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 1019 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 1020} 1021defm : ZXB<subc, GR64, SLGFR>; 1022 1023// Subtraction producing and using a carry. 1024let Defs = [CC], Uses = [CC] in { 1025 // Subtraction of a register. 1026 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>; 1027 def SLBGR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>; 1028 1029 // Subtraction of memory. 1030 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 1031 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 1032} 1033 1034//===----------------------------------------------------------------------===// 1035// AND 1036//===----------------------------------------------------------------------===// 1037 1038let Defs = [CC] in { 1039 // ANDs of a register. 1040 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1041 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1042 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1043 } 1044 1045 let isConvertibleToThreeAddress = 1 in { 1046 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1047 // The CC result only reflects the 16-bit field, not the full register. 1048 // 1049 // NIxMux expands to NI[LH]x, depending on the choice of register. 1050 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1051 Requires<[FeatureHighWord]>; 1052 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1053 Requires<[FeatureHighWord]>; 1054 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1055 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1056 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1057 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1058 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1059 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1060 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1061 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1062 1063 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1064 // The CC result only reflects the 32-bit field, which means we can 1065 // use it as a zero indicator for i32 operations but not otherwise. 1066 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1067 // Expands to NILF or NIHF, depending on the choice of register. 1068 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1069 Requires<[FeatureHighWord]>; 1070 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1071 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1072 } 1073 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1074 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1075 } 1076 1077 // ANDs of memory. 1078 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1079 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1080 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1081 } 1082 1083 // AND to memory 1084 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1085 1086 // Block AND. 1087 let mayLoad = 1, mayStore = 1 in 1088 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1089} 1090defm : RMWIByte<and, bdaddr12pair, NI>; 1091defm : RMWIByte<and, bdaddr20pair, NIY>; 1092 1093//===----------------------------------------------------------------------===// 1094// OR 1095//===----------------------------------------------------------------------===// 1096 1097let Defs = [CC] in { 1098 // ORs of a register. 1099 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1100 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1101 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1102 } 1103 1104 // ORs of a 16-bit immediate, leaving other bits unaffected. 1105 // The CC result only reflects the 16-bit field, not the full register. 1106 // 1107 // OIxMux expands to OI[LH]x, depending on the choice of register. 1108 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1109 Requires<[FeatureHighWord]>; 1110 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1111 Requires<[FeatureHighWord]>; 1112 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1113 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1114 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1115 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1116 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1117 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1118 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1119 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1120 1121 // ORs of a 32-bit immediate, leaving other bits unaffected. 1122 // The CC result only reflects the 32-bit field, which means we can 1123 // use it as a zero indicator for i32 operations but not otherwise. 1124 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1125 // Expands to OILF or OIHF, depending on the choice of register. 1126 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1127 Requires<[FeatureHighWord]>; 1128 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1129 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1130 } 1131 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1132 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1133 1134 // ORs of memory. 1135 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1136 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1137 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1138 } 1139 1140 // OR to memory 1141 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1142 1143 // Block OR. 1144 let mayLoad = 1, mayStore = 1 in 1145 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1146} 1147defm : RMWIByte<or, bdaddr12pair, OI>; 1148defm : RMWIByte<or, bdaddr20pair, OIY>; 1149 1150//===----------------------------------------------------------------------===// 1151// XOR 1152//===----------------------------------------------------------------------===// 1153 1154let Defs = [CC] in { 1155 // XORs of a register. 1156 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1157 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1158 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1159 } 1160 1161 // XORs of a 32-bit immediate, leaving other bits unaffected. 1162 // The CC result only reflects the 32-bit field, which means we can 1163 // use it as a zero indicator for i32 operations but not otherwise. 1164 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1165 // Expands to XILF or XIHF, depending on the choice of register. 1166 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1167 Requires<[FeatureHighWord]>; 1168 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1169 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1170 } 1171 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1172 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1173 1174 // XORs of memory. 1175 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1176 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1177 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1178 } 1179 1180 // XOR to memory 1181 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1182 1183 // Block XOR. 1184 let mayLoad = 1, mayStore = 1 in 1185 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1186} 1187defm : RMWIByte<xor, bdaddr12pair, XI>; 1188defm : RMWIByte<xor, bdaddr20pair, XIY>; 1189 1190//===----------------------------------------------------------------------===// 1191// Multiplication 1192//===----------------------------------------------------------------------===// 1193 1194// Multiplication of a register. 1195let isCommutable = 1 in { 1196 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1197 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1198} 1199def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1200defm : SXB<mul, GR64, MSGFR>; 1201 1202// Multiplication of a signed 16-bit immediate. 1203def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1204def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1205 1206// Multiplication of a signed 32-bit immediate. 1207def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1208def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1209 1210// Multiplication of memory. 1211defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1212defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1213def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1214def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1215 1216// Multiplication of a register, producing two results. 1217def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1218def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1219def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>; 1220 1221// Multiplication of memory, producing two results. 1222def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1223def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1224def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1225def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>; 1226 1227//===----------------------------------------------------------------------===// 1228// Division and remainder 1229//===----------------------------------------------------------------------===// 1230 1231let hasSideEffects = 1 in { // Do not speculatively execute. 1232 // Division and remainder, from registers. 1233 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1234 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, z_sdivrem32, GR128, GR32>; 1235 def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>; 1236 def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>; 1237 def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>; 1238 1239 // Division and remainder, from memory. 1240 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1241 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>; 1242 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>; 1243 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>; 1244 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>; 1245} 1246 1247//===----------------------------------------------------------------------===// 1248// Shifts 1249//===----------------------------------------------------------------------===// 1250 1251// Logical shift left. 1252let hasSideEffects = 0 in { 1253 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1254 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1255 def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1256} 1257 1258// Arithmetic shift left. 1259let Defs = [CC] in { 1260 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1261 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1262 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1263} 1264 1265// Logical shift right. 1266let hasSideEffects = 0 in { 1267 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1268 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1269 def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1270} 1271 1272// Arithmetic shift right. 1273let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1274 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1275 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1276 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1277} 1278 1279// Rotate left. 1280let hasSideEffects = 0 in { 1281 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1282 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1283} 1284 1285// Rotate second operand left and inserted selected bits into first operand. 1286// These can act like 32-bit operands provided that the constant start and 1287// end bits (operands 2 and 3) are in the range [32, 64). 1288let Defs = [CC] in { 1289 let isCodeGenOnly = 1 in 1290 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1291 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1292 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1293} 1294 1295// On zEC12 we have a variant of RISBG that does not set CC. 1296let Predicates = [FeatureMiscellaneousExtensions] in 1297 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1298 1299// Forms of RISBG that only affect one word of the destination register. 1300// They do not set CC. 1301let Predicates = [FeatureHighWord] in { 1302 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1303 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1304 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1305 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1306 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1307 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1308 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1309} 1310 1311// Rotate second operand left and perform a logical operation with selected 1312// bits of the first operand. The CC result only describes the selected bits, 1313// so isn't useful for a full comparison against zero. 1314let Defs = [CC] in { 1315 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1316 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1317 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1318} 1319 1320//===----------------------------------------------------------------------===// 1321// Comparison 1322//===----------------------------------------------------------------------===// 1323 1324// Signed comparisons. We put these before the unsigned comparisons because 1325// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1326// of the unsigned forms do. 1327let Defs = [CC], CCValues = 0xE in { 1328 // Comparison with a register. 1329 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1330 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1331 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1332 1333 // Comparison with a high register. 1334 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1335 Requires<[FeatureHighWord]>; 1336 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1337 Requires<[FeatureHighWord]>; 1338 1339 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1340 // depending on the choice of register. 1341 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1342 Requires<[FeatureHighWord]>; 1343 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1344 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1345 1346 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1347 // depending on the choice of register. 1348 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1349 Requires<[FeatureHighWord]>; 1350 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1351 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1352 Requires<[FeatureHighWord]>; 1353 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1354 1355 // Comparison with memory. 1356 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1357 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1358 Requires<[FeatureHighWord]>; 1359 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1360 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1361 Requires<[FeatureHighWord]>; 1362 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1363 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1364 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1365 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1366 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1367 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1368 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1369 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1370 1371 // Comparison between memory and a signed 16-bit immediate. 1372 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1373 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1374 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1375} 1376defm : SXB<z_scmp, GR64, CGFR>; 1377 1378// Unsigned comparisons. 1379let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1380 // Comparison with a register. 1381 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1382 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1383 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1384 1385 // Comparison with a high register. 1386 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1387 Requires<[FeatureHighWord]>; 1388 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1389 Requires<[FeatureHighWord]>; 1390 1391 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1392 // or CLIH, depending on the choice of register. 1393 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1394 Requires<[FeatureHighWord]>; 1395 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1396 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1397 Requires<[FeatureHighWord]>; 1398 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1399 1400 // Comparison with memory. 1401 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1402 Requires<[FeatureHighWord]>; 1403 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1404 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1405 Requires<[FeatureHighWord]>; 1406 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1407 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1408 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1409 aligned_azextloadi16>; 1410 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1411 aligned_load>; 1412 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1413 aligned_azextloadi16>; 1414 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1415 aligned_azextloadi32>; 1416 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1417 aligned_load>; 1418 1419 // Comparison between memory and an unsigned 8-bit immediate. 1420 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1421 1422 // Comparison between memory and an unsigned 16-bit immediate. 1423 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1424 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1425 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1426} 1427defm : ZXB<z_ucmp, GR64, CLGFR>; 1428 1429// Memory-to-memory comparison. 1430let mayLoad = 1, Defs = [CC] in { 1431 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1432 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1433 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1434 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1435} 1436 1437// String comparison. 1438let mayLoad = 1, Defs = [CC] in 1439 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1440 1441// Test under mask. 1442let Defs = [CC] in { 1443 // TMxMux expands to TM[LH]x, depending on the choice of register. 1444 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1445 Requires<[FeatureHighWord]>; 1446 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1447 Requires<[FeatureHighWord]>; 1448 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1449 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1450 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1451 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1452 1453 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1454 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1455 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1456 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1457 1458 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1459} 1460 1461def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1462def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1463 1464// Compare logical characters under mask -- not (yet) used for codegen. 1465let Defs = [CC] in { 1466 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1467 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1468} 1469 1470//===----------------------------------------------------------------------===// 1471// Prefetch and execution hint 1472//===----------------------------------------------------------------------===// 1473 1474def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1475def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1476 1477let Predicates = [FeatureExecutionHint] in { 1478 // Branch Prediction Preload 1479 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1480 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1481 1482 // Next Instruction Access Intent 1483 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1484} 1485 1486//===----------------------------------------------------------------------===// 1487// Atomic operations 1488//===----------------------------------------------------------------------===// 1489 1490// A serialization instruction that acts as a barrier for all memory 1491// accesses, which expands to "bcr 14, 0". 1492let hasSideEffects = 1 in 1493def Serialize : Alias<2, (outs), (ins), []>; 1494 1495// A pseudo instruction that serves as a compiler barrier. 1496let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1497def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1498 1499let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1500 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1501 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1502 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1503 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1504 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1505 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1506 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1507 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1508 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1509 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1510} 1511 1512def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1513def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1514def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1515 1516def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1517def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1518let Predicates = [FeatureNoInterlockedAccess1] in { 1519 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1520 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1521 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1522 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1523 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1524 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1525} 1526 1527def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1528def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1529def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1530 1531def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1532def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1533let Predicates = [FeatureNoInterlockedAccess1] in { 1534 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1535 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1536 imm32ll16c>; 1537 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1538 imm32lh16c>; 1539 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1540 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1541 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1542 imm64ll16c>; 1543 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1544 imm64lh16c>; 1545 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1546 imm64hl16c>; 1547 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1548 imm64hh16c>; 1549 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1550 imm64lf32c>; 1551 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1552 imm64hf32c>; 1553} 1554 1555def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1556def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1557let Predicates = [FeatureNoInterlockedAccess1] in { 1558 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1559 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1560 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1561 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1562 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1563 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1564 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1565 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1566 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1567 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1568 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1569} 1570 1571def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1572def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1573let Predicates = [FeatureNoInterlockedAccess1] in { 1574 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1575 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1576 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1577 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1578 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1579} 1580 1581def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1582def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1583 imm32lh16c>; 1584def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1585def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1586 imm32ll16c>; 1587def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1588 imm32lh16c>; 1589def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1590def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1591def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1592 imm64ll16c>; 1593def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1594 imm64lh16c>; 1595def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1596 imm64hl16c>; 1597def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1598 imm64hh16c>; 1599def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1600 imm64lf32c>; 1601def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1602 imm64hf32c>; 1603 1604def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1605def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1606def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1607 1608def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1609def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1610def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1611 1612def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1613def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1614def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1615 1616def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1617def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1618def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1619 1620def ATOMIC_CMP_SWAPW 1621 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1622 ADDR32:$bitshift, ADDR32:$negbitshift, 1623 uimm32:$bitsize), 1624 [(set GR32:$dst, 1625 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1626 ADDR32:$bitshift, ADDR32:$negbitshift, 1627 uimm32:$bitsize))]> { 1628 let Defs = [CC]; 1629 let mayLoad = 1; 1630 let mayStore = 1; 1631 let usesCustomInserter = 1; 1632 let hasNoSchedulingInfo = 1; 1633} 1634 1635// Test and set. 1636let mayLoad = 1, Defs = [CC] in 1637 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1638 1639// Compare and swap. 1640let Defs = [CC] in { 1641 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1642 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1643} 1644 1645// Compare double and swap. 1646let Defs = [CC] in { 1647 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1648 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, null_frag, GR128>; 1649} 1650 1651// Compare and swap and store. 1652let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1653 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1654 1655// Perform locked operation. 1656let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1657 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1658 1659// Load/store pair from/to quadword. 1660def LPQ : UnaryRXY<"lpq", 0xE38F, null_frag, GR128, 16>; 1661def STPQ : StoreRXY<"stpq", 0xE38E, null_frag, GR128, 16>; 1662 1663// Load pair disjoint. 1664let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1665 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1666 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1667} 1668 1669//===----------------------------------------------------------------------===// 1670// Translate and convert 1671//===----------------------------------------------------------------------===// 1672 1673let mayLoad = 1, mayStore = 1 in 1674 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1675 1676let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1677 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1678 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1679} 1680 1681let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1682 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1683 1684let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1685 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1686 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1687} 1688 1689let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1690 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1691 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1692 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1693 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1694} 1695 1696let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1697 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1698 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1699 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1700 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1701 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1702 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1703 1704 let isAsmParserOnly = 1 in { 1705 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1706 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1707 } 1708} 1709 1710//===----------------------------------------------------------------------===// 1711// Message-security assist 1712//===----------------------------------------------------------------------===// 1713 1714let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1715 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1716 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1717 1718 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1719 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1720 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1721 1722 let Predicates = [FeatureMessageSecurityAssist4] in { 1723 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1724 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1725 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1726 GR128, GR128, GR128>; 1727 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1728 } 1729 let Predicates = [FeatureMessageSecurityAssist5] in 1730 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1731} 1732 1733//===----------------------------------------------------------------------===// 1734// Decimal arithmetic 1735//===----------------------------------------------------------------------===// 1736 1737defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1738def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1739 1740defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1741def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1742 1743let mayLoad = 1, mayStore = 1 in { 1744 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1745 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1746 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1747 1748 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1749 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1750 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1751 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1752 let Defs = [CC] in { 1753 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1754 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1755 } 1756} 1757 1758let mayLoad = 1, mayStore = 1 in { 1759 let Defs = [CC] in { 1760 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1761 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1762 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1763 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1764 } 1765 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1766 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1767 let Defs = [CC] in { 1768 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1769 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1770 } 1771} 1772 1773let Defs = [CC] in { 1774 def CP : CompareSSb<"cp", 0xF9>; 1775 def TP : TestRSL<"tp", 0xEBC0>; 1776} 1777 1778//===----------------------------------------------------------------------===// 1779// Access registers 1780//===----------------------------------------------------------------------===// 1781 1782// Read a 32-bit access register into a GR32. As with all GR32 operations, 1783// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1784// when a 64-bit address is stored in a pair of access registers. 1785def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1786 1787// Set access register. 1788def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1789 1790// Copy access register. 1791def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1792 1793// Load address extended. 1794defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1795 1796// Load access multiple. 1797defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1798 1799// Load access multiple. 1800defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1801 1802//===----------------------------------------------------------------------===// 1803// Program mask and addressing mode 1804//===----------------------------------------------------------------------===// 1805 1806// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1807let Uses = [CC] in 1808 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1809 1810// Set CC and program mask from a register. 1811let hasSideEffects = 1, Defs = [CC] in 1812 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1813 1814// Branch and link - like BAS, but also extracts CC and program mask. 1815let isCall = 1, Uses = [CC], Defs = [CC] in { 1816 def BAL : CallRX<"bal", 0x45>; 1817 def BALR : CallRR<"balr", 0x05>; 1818} 1819 1820// Test addressing mode. 1821let Defs = [CC] in 1822 def TAM : SideEffectInherentE<"tam", 0x010B>; 1823 1824// Set addressing mode. 1825let hasSideEffects = 1 in { 1826 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 1827 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 1828 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 1829} 1830 1831// Branch and set mode. Not really a call, but also sets an output register. 1832let isBranch = 1, isTerminator = 1, isBarrier = 1 in 1833 def BSM : CallRR<"bsm", 0x0B>; 1834 1835// Branch and save and set mode. 1836let isCall = 1, Defs = [CC] in 1837 def BASSM : CallRR<"bassm", 0x0C>; 1838 1839//===----------------------------------------------------------------------===// 1840// Transactional execution 1841//===----------------------------------------------------------------------===// 1842 1843let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 1844 // Transaction Begin 1845 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 1846 def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 1847 def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 1848 1849 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 1850 int_s390_tbeginc, imm32zx16>; 1851 } 1852 1853 // Transaction End 1854 let Defs = [CC] in 1855 def TEND : SideEffectInherentS<"tend", 0xB2F8, z_tend>; 1856 1857 // Transaction Abort 1858 let isTerminator = 1, isBarrier = 1 in 1859 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 1860 1861 // Nontransactional Store 1862 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1863 1864 // Extract Transaction Nesting Depth 1865 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 1866} 1867 1868//===----------------------------------------------------------------------===// 1869// Processor assist 1870//===----------------------------------------------------------------------===// 1871 1872let Predicates = [FeatureProcessorAssist] in { 1873 let hasSideEffects = 1 in 1874 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 1875 def : Pat<(int_s390_ppa_txassist GR32:$src), 1876 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1877 0, 1)>; 1878} 1879 1880//===----------------------------------------------------------------------===// 1881// Miscellaneous Instructions. 1882//===----------------------------------------------------------------------===// 1883 1884// Find leftmost one, AKA count leading zeros. The instruction actually 1885// returns a pair of GR64s, the first giving the number of leading zeros 1886// and the second giving a copy of the source with the leftmost one bit 1887// cleared. We only use the first result here. 1888let Defs = [CC] in 1889 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 1890def : Pat<(ctlz GR64:$src), 1891 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1892 1893// Population count. Counts bits set per byte. 1894let Predicates = [FeaturePopulationCount], Defs = [CC] in 1895 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 1896 1897// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 1898def : Pat<(i64 (anyext GR32:$src)), 1899 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 1900 1901// Extend GR32s and GR64s to GR128s. 1902let usesCustomInserter = 1 in { 1903 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1904 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 1905 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1906} 1907 1908// Search a block of memory for a character. 1909let mayLoad = 1, Defs = [CC] in 1910 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 1911let mayLoad = 1, Defs = [CC], Uses = [R0L] in 1912 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 1913 1914// Compare until substring equal. 1915let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 1916 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 1917 1918// Compare and form codeword. 1919let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 1920 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 1921 1922// Update tree. 1923let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 1924 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 1925 def UPT : SideEffectInherentE<"upt", 0x0102>; 1926 1927// Checksum. 1928let mayLoad = 1, Defs = [CC] in 1929 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 1930 1931// Compression call. 1932let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 1933 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 1934 1935// Execute. 1936let hasSideEffects = 1 in { 1937 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 1938 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 1939} 1940 1941//===----------------------------------------------------------------------===// 1942// .insn directive instructions 1943//===----------------------------------------------------------------------===// 1944 1945let isCodeGenOnly = 1 in { 1946 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 1947 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 1948 imm32sx16:$I2), 1949 ".insn ri,$enc,$R1,$I2", []>; 1950 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1951 AnyReg:$R3, brtarget16:$I2), 1952 ".insn rie,$enc,$R1,$R3,$I2", []>; 1953 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1954 brtarget32:$I2), 1955 ".insn ril,$enc,$R1,$I2", []>; 1956 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1957 uimm32:$I2), 1958 ".insn rilu,$enc,$R1,$I2", []>; 1959 def InsnRIS : DirectiveInsnRIS<(outs), 1960 (ins imm64zx48:$enc, AnyReg:$R1, 1961 imm32sx8:$I2, imm32zx4:$M3, 1962 bdaddr12only:$BD4), 1963 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 1964 def InsnRR : DirectiveInsnRR<(outs), 1965 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 1966 ".insn rr,$enc,$R1,$R2", []>; 1967 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 1968 AnyReg:$R1, AnyReg:$R2), 1969 ".insn rre,$enc,$R1,$R2", []>; 1970 def InsnRRF : DirectiveInsnRRF<(outs), 1971 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 1972 AnyReg:$R3, imm32zx4:$M4), 1973 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 1974 def InsnRRS : DirectiveInsnRRS<(outs), 1975 (ins imm64zx48:$enc, AnyReg:$R1, 1976 AnyReg:$R2, imm32zx4:$M3, 1977 bdaddr12only:$BD4), 1978 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 1979 def InsnRS : DirectiveInsnRS<(outs), 1980 (ins imm64zx32:$enc, AnyReg:$R1, 1981 AnyReg:$R3, bdaddr12only:$BD2), 1982 ".insn rs,$enc,$R1,$R3,$BD2", []>; 1983 def InsnRSE : DirectiveInsnRSE<(outs), 1984 (ins imm64zx48:$enc, AnyReg:$R1, 1985 AnyReg:$R3, bdaddr12only:$BD2), 1986 ".insn rse,$enc,$R1,$R3,$BD2", []>; 1987 def InsnRSI : DirectiveInsnRSI<(outs), 1988 (ins imm64zx48:$enc, AnyReg:$R1, 1989 AnyReg:$R3, brtarget16:$RI2), 1990 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 1991 def InsnRSY : DirectiveInsnRSY<(outs), 1992 (ins imm64zx48:$enc, AnyReg:$R1, 1993 AnyReg:$R3, bdaddr20only:$BD2), 1994 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 1995 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 1996 bdxaddr12only:$XBD2), 1997 ".insn rx,$enc,$R1,$XBD2", []>; 1998 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1999 bdxaddr12only:$XBD2), 2000 ".insn rxe,$enc,$R1,$XBD2", []>; 2001 def InsnRXF : DirectiveInsnRXF<(outs), 2002 (ins imm64zx48:$enc, AnyReg:$R1, 2003 AnyReg:$R3, bdxaddr12only:$XBD2), 2004 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2005 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2006 bdxaddr20only:$XBD2), 2007 ".insn rxy,$enc,$R1,$XBD2", []>; 2008 def InsnS : DirectiveInsnS<(outs), 2009 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2010 ".insn s,$enc,$BD2", []>; 2011 def InsnSI : DirectiveInsnSI<(outs), 2012 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2013 imm32sx8:$I2), 2014 ".insn si,$enc,$BD1,$I2", []>; 2015 def InsnSIY : DirectiveInsnSIY<(outs), 2016 (ins imm64zx48:$enc, 2017 bdaddr20only:$BD1, imm32zx8:$I2), 2018 ".insn siy,$enc,$BD1,$I2", []>; 2019 def InsnSIL : DirectiveInsnSIL<(outs), 2020 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2021 imm32zx16:$I2), 2022 ".insn sil,$enc,$BD1,$I2", []>; 2023 def InsnSS : DirectiveInsnSS<(outs), 2024 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2025 bdaddr12only:$BD2, AnyReg:$R3), 2026 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2027 def InsnSSE : DirectiveInsnSSE<(outs), 2028 (ins imm64zx48:$enc, 2029 bdaddr12only:$BD1,bdaddr12only:$BD2), 2030 ".insn sse,$enc,$BD1,$BD2", []>; 2031 def InsnSSF : DirectiveInsnSSF<(outs), 2032 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2033 bdaddr12only:$BD2, AnyReg:$R3), 2034 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2035} 2036 2037//===----------------------------------------------------------------------===// 2038// Peepholes. 2039//===----------------------------------------------------------------------===// 2040 2041// Use AL* for GR64 additions of unsigned 32-bit values. 2042defm : ZXB<add, GR64, ALGFR>; 2043def : Pat<(add GR64:$src1, imm64zx32:$src2), 2044 (ALGFI GR64:$src1, imm64zx32:$src2)>; 2045def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2046 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 2047 2048// Use SL* for GR64 subtractions of unsigned 32-bit values. 2049defm : ZXB<sub, GR64, SLGFR>; 2050def : Pat<(add GR64:$src1, imm64zx32n:$src2), 2051 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 2052def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2053 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 2054 2055// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 2056// for vector legalization. 2057def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)), 2058 (i32 31)), 2059 (i32 31)), 2060 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 2061def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, 2062 imm32zx4:$cc)))), 2063 (i32 63)), 2064 (i32 63)), 2065 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 2066 2067// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2068// equivalent to (and (xor x, -1), y) 2069def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2070 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2071 2072// Shift/rotate instructions only use the last 6 bits of the second operand 2073// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2074// last 16 bits. 2075// Complexity is added so that we match this before we match NILF on the AND 2076// operation alone. 2077let AddedComplexity = 4 in { 2078 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2079 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2080 2081 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 2082 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2083 2084 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2085 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2086 2087 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2088 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2089 2090 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 2091 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2092 2093 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2094 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2095 2096 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2097 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2098 2099 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2100 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2101} 2102 2103// Peepholes for turning scalar operations into block operations. 2104defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2105 XCSequence, 1>; 2106defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2107 XCSequence, 2>; 2108defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2109 XCSequence, 4>; 2110defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2111 OCSequence, XCSequence, 1>; 2112defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2113 XCSequence, 2>; 2114defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2115 XCSequence, 4>; 2116defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2117 XCSequence, 8>; 2118