1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14let hasNoSchedulingInfo = 1 in { 15 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 16 [(callseq_start timm:$amt1, timm:$amt2)]>; 17 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_end timm:$amt1, timm:$amt2)]>; 19} 20 21let hasSideEffects = 0 in { 22 // Takes as input the value of the stack pointer after a dynamic allocation 23 // has been made. Sets the output to the address of the dynamically- 24 // allocated area itself, skipping the outgoing arguments. 25 // 26 // This expands to an LA or LAY instruction. We restrict the offset 27 // to the range of LA and keep the LAY range in reserve for when 28 // the size of the outgoing arguments is added. 29 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31} 32 33//===----------------------------------------------------------------------===// 34// Branch instructions 35//===----------------------------------------------------------------------===// 36 37// Conditional branches. 38let isBranch = 1, isTerminator = 1, Uses = [CC] in { 39 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 40 // with the condition-code mask being the first operand. It seems friendlier 41 // to use mnemonic forms like JE and JLH when writing out the assembly though. 42 let isCodeGenOnly = 1 in { 43 // An assembler extended mnemonic for BRC. 44 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 45 // An assembler extended mnemonic for BRCL. (The extension is "G" 46 // rather than "L" because "JL" is "Jump if Less".) 47 def BRCL : CondBranchRIL<"jg#", 0xC04>; 48 let isIndirectBranch = 1 in { 49 def BC : CondBranchRX<"b#", 0x47>; 50 def BCR : CondBranchRR<"b#r", 0x07>; 51 def BIC : CondBranchRXY<"bi#", 0xe347>, 52 Requires<[FeatureMiscellaneousExtensions2]>; 53 } 54 } 55 56 // Allow using the raw forms directly from the assembler (and occasional 57 // special code generation needs) as well. 58 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 59 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 60 let isIndirectBranch = 1 in { 61 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 62 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 63 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 64 Requires<[FeatureMiscellaneousExtensions2]>; 65 } 66 67 // Define AsmParser extended mnemonics for each general condition-code mask 68 // (integer or floating-point) 69 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 70 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 71 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 72 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 73 let isIndirectBranch = 1 in { 74 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 75 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 76 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 77 Requires<[FeatureMiscellaneousExtensions2]>; 78 } 79 } 80} 81 82// Unconditional branches. These are in fact simply variants of the 83// conditional branches with the condition mask set to "always". 84let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 85 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 86 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 87 let isIndirectBranch = 1 in { 88 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 89 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 90 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 91 Requires<[FeatureMiscellaneousExtensions2]>; 92 } 93} 94 95// NOPs. These are again variants of the conditional branches, 96// with the condition mask set to "never". 97def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 98def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 99 100// Fused compare-and-branch instructions. 101// 102// These instructions do not use or clobber the condition codes. 103// We nevertheless pretend that the relative compare-and-branch 104// instructions clobber CC, so that we can lower them to separate 105// comparisons and BRCLs if the branch ends up being out of range. 106let isBranch = 1, isTerminator = 1 in { 107 // As for normal branches, we handle these instructions internally in 108 // their raw CRJ-like form, but use assembly macros like CRJE when writing 109 // them out. Using the *Pair multiclasses, we also create the raw forms. 110 let Defs = [CC] in { 111 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 112 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 113 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 114 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 115 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 116 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 117 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 118 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 119 } 120 let isIndirectBranch = 1 in { 121 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 122 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 123 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 124 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 125 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 126 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 127 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 128 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 129 } 130 131 // Define AsmParser mnemonics for each integer condition-code mask. 132 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 133 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 134 let Defs = [CC] in { 135 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 136 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 137 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 138 imm32sx8>; 139 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 140 imm64sx8>; 141 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 142 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 143 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 144 imm32zx8>; 145 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 146 imm64zx8>; 147 } 148 let isIndirectBranch = 1 in { 149 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 150 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 151 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 152 imm32sx8>; 153 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 154 imm64sx8>; 155 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 156 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 157 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 158 imm32zx8>; 159 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 160 imm64zx8>; 161 } 162 } 163} 164 165// Decrement a register and branch if it is nonzero. These don't clobber CC, 166// but we might need to split long relative branches into sequences that do. 167let isBranch = 1, isTerminator = 1 in { 168 let Defs = [CC] in { 169 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 170 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 171 } 172 // This doesn't need to clobber CC since we never need to split it. 173 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 174 Requires<[FeatureHighWord]>; 175 176 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 177 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 178 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 179 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 180} 181 182let isBranch = 1, isTerminator = 1 in { 183 let Defs = [CC] in { 184 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 185 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 186 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 187 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 188 } 189 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 190 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 191 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 192 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 193} 194 195//===----------------------------------------------------------------------===// 196// Trap instructions 197//===----------------------------------------------------------------------===// 198 199// Unconditional trap. 200let hasCtrlDep = 1 in 201 def Trap : Alias<4, (outs), (ins), [(trap)]>; 202 203// Conditional trap. 204let hasCtrlDep = 1, Uses = [CC] in 205 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 206 207// Fused compare-and-trap instructions. 208let hasCtrlDep = 1 in { 209 // These patterns work the same way as for compare-and-branch. 210 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 211 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 212 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 213 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 214 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 215 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 216 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 217 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 218 let Predicates = [FeatureMiscellaneousExtensions] in { 219 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 220 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 221 } 222 223 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 224 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 225 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 226 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 227 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 228 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 229 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 230 imm32sx16>; 231 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 232 imm64sx16>; 233 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 234 imm32zx16>; 235 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 236 imm64zx16>; 237 let Predicates = [FeatureMiscellaneousExtensions] in { 238 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 239 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 240 } 241 } 242} 243 244//===----------------------------------------------------------------------===// 245// Call and return instructions 246//===----------------------------------------------------------------------===// 247 248// Define the general form of the call instructions for the asm parser. 249// These instructions don't hard-code %r14 as the return address register. 250let isCall = 1, Defs = [CC] in { 251 def BRAS : CallRI <"bras", 0xA75>; 252 def BRASL : CallRIL<"brasl", 0xC05>; 253 def BAS : CallRX <"bas", 0x4D>; 254 def BASR : CallRR <"basr", 0x0D>; 255} 256 257// Regular calls. 258let isCall = 1, Defs = [R14D, CC] in { 259 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 260 [(z_call pcrel32:$I2)]>; 261 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 262 [(z_call ADDR64:$R2)]>; 263} 264 265// TLS calls. These will be lowered into a call to __tls_get_offset, 266// with an extra relocation specifying the TLS symbol. 267let isCall = 1, Defs = [R14D, CC] in { 268 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 269 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 270 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 271 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 272} 273 274// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 275// are argument registers and since branching to R0 is a no-op. 276let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 277 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 278 [(z_sibcall pcrel32:$I2)]>; 279 let Uses = [R1D] in 280 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 281} 282 283// Conditional sibling calls. 284let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 285 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 286 pcrel32:$I2), []>; 287 let Uses = [R1D] in 288 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 289} 290 291// Fused compare and conditional sibling calls. 292let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 293 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 294 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 295 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 296 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 297 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 298 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 299 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 300 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 301} 302 303// A return instruction (br %r14). 304let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 305 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 306 307// A conditional return instruction (bcr <cond>, %r14). 308let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 309 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 310 311// Fused compare and conditional returns. 312let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 313 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 314 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 315 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 316 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 317 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 318 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 319 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 320 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 321} 322 323//===----------------------------------------------------------------------===// 324// Select instructions 325//===----------------------------------------------------------------------===// 326 327def Select32Mux : SelectWrapper<i32, GRX32>, Requires<[FeatureHighWord]>; 328def Select32 : SelectWrapper<i32, GR32>; 329def Select64 : SelectWrapper<i64, GR64>; 330 331// We don't define 32-bit Mux stores if we don't have STOCFH, because the 332// low-only STOC should then always be used if possible. 333defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 334 nonvolatile_anyextloadi8, bdxaddr20only>, 335 Requires<[FeatureHighWord]>; 336defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 337 nonvolatile_anyextloadi16, bdxaddr20only>, 338 Requires<[FeatureHighWord]>; 339defm CondStore32Mux : CondStores<GRX32, nonvolatile_store, 340 nonvolatile_load, bdxaddr20only>, 341 Requires<[FeatureLoadStoreOnCond2]>; 342defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 343 nonvolatile_anyextloadi8, bdxaddr20only>; 344defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 345 nonvolatile_anyextloadi16, bdxaddr20only>; 346defm CondStore32 : CondStores<GR32, nonvolatile_store, 347 nonvolatile_load, bdxaddr20only>; 348 349defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 350 nonvolatile_anyextloadi8, bdxaddr20only>; 351defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 352 nonvolatile_anyextloadi16, bdxaddr20only>; 353defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 354 nonvolatile_anyextloadi32, bdxaddr20only>; 355defm CondStore64 : CondStores<GR64, nonvolatile_store, 356 nonvolatile_load, bdxaddr20only>; 357 358//===----------------------------------------------------------------------===// 359// Move instructions 360//===----------------------------------------------------------------------===// 361 362// Register moves. 363let hasSideEffects = 0 in { 364 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 365 def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>, 366 Requires<[FeatureHighWord]>; 367 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 368 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 369} 370let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 371 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 372 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 373} 374 375let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 376 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 377 378// Immediate moves. 379let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 380 isReMaterializable = 1 in { 381 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 382 // deopending on the choice of register. 383 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 384 Requires<[FeatureHighWord]>; 385 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 386 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 387 388 // Other 16-bit immediates. 389 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 390 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 391 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 392 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 393 394 // 32-bit immediates. 395 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 396 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 397 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 398} 399 400// Register loads. 401let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 402 // Expands to L, LY or LFH, depending on the choice of register. 403 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 404 Requires<[FeatureHighWord]>; 405 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 406 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 407 Requires<[FeatureHighWord]>; 408 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 409 410 // These instructions are split after register allocation, so we don't 411 // want a custom inserter. 412 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 413 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 414 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 415 } 416} 417let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 418 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 419 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 420} 421 422let canFoldAsLoad = 1 in { 423 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 424 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 425} 426 427// Load and zero rightmost byte. 428let Predicates = [FeatureLoadAndZeroRightmostByte] in { 429 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 430 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 431 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 432 (LZRF bdxaddr20only:$src)>; 433 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 434 (LZRG bdxaddr20only:$src)>; 435} 436 437// Load and trap. 438let Predicates = [FeatureLoadAndTrap] in { 439 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 440 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 441 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 442} 443 444// Register stores. 445let SimpleBDXStore = 1 in { 446 // Expands to ST, STY or STFH, depending on the choice of register. 447 def STMux : StoreRXYPseudo<store, GRX32, 4>, 448 Requires<[FeatureHighWord]>; 449 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 450 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 451 Requires<[FeatureHighWord]>; 452 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 453 454 // These instructions are split after register allocation, so we don't 455 // want a custom inserter. 456 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 457 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 458 [(store GR128:$src, bdxaddr20only128:$dst)]>; 459 } 460} 461def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 462def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 463 464// 8-bit immediate stores to 8-bit fields. 465defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 466 467// 16-bit immediate stores to 16-, 32- or 64-bit fields. 468def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 469def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 470def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 471 472// Memory-to-memory moves. 473let mayLoad = 1, mayStore = 1 in 474 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 475let mayLoad = 1, mayStore = 1, Defs = [CC] in { 476 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 477 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 478 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 479} 480 481// String moves. 482let mayLoad = 1, mayStore = 1, Defs = [CC] in 483 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 484 485//===----------------------------------------------------------------------===// 486// Conditional move instructions 487//===----------------------------------------------------------------------===// 488 489let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 490 // Load immediate on condition. Matched via DAG pattern and created 491 // by the PeepholeOptimizer via FoldImmediate. 492 let hasSideEffects = 0 in { 493 // Expands to LOCHI or LOCHHI, depending on the choice of register. 494 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 495 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 496 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 497 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 498 } 499 500 // Move register on condition. Expanded from Select* pseudos and 501 // created by early if-conversion. 502 let hasSideEffects = 0, isCommutable = 1 in { 503 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 504 // depending on the choice of registers. 505 def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>; 506 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 507 } 508 509 // Load on condition. Matched via DAG pattern. 510 // Expands to LOC or LOCFH, depending on the choice of register. 511 def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>; 512 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>; 513 514 // Store on condition. Expanded from CondStore* pseudos. 515 // Expands to STOC or STOCFH, depending on the choice of register. 516 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 517 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 518 519 // Define AsmParser extended mnemonics for each general condition-code mask. 520 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 521 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 522 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 523 imm32sx16>; 524 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 525 imm64sx16>; 526 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 527 imm32sx16>; 528 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 529 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 530 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 531 } 532} 533 534let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 535 // Move register on condition. Expanded from Select* pseudos and 536 // created by early if-conversion. 537 let hasSideEffects = 0, isCommutable = 1 in { 538 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 539 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 540 } 541 542 // Load on condition. Matched via DAG pattern. 543 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 544 defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 545 546 // Store on condition. Expanded from CondStore* pseudos. 547 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 548 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 549 550 // Define AsmParser extended mnemonics for each general condition-code mask. 551 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 552 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 553 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 554 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 555 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 556 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 557 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 558 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 559 } 560} 561//===----------------------------------------------------------------------===// 562// Sign extensions 563//===----------------------------------------------------------------------===// 564// 565// Note that putting these before zero extensions mean that we will prefer 566// them for anyextload*. There's not really much to choose between the two 567// either way, but signed-extending loads have a short LH and a long LHY, 568// while zero-extending loads have only the long LLH. 569// 570//===----------------------------------------------------------------------===// 571 572// 32-bit extensions from registers. 573let hasSideEffects = 0 in { 574 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 575 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 576} 577 578// 64-bit extensions from registers. 579let hasSideEffects = 0 in { 580 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 581 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 582 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 583} 584let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 585 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 586 587// Match 32-to-64-bit sign extensions in which the source is already 588// in a 64-bit register. 589def : Pat<(sext_inreg GR64:$src, i32), 590 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 591 592// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 593// depending on the choice of register. 594def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 595 Requires<[FeatureHighWord]>; 596def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 597def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 598 Requires<[FeatureHighWord]>; 599 600// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 601// depending on the choice of register. 602def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 603 Requires<[FeatureHighWord]>; 604defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 605def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 606 Requires<[FeatureHighWord]>; 607def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 608 609// 64-bit extensions from memory. 610def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 611def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 612def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 613def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 614def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 615let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 616 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 617 618//===----------------------------------------------------------------------===// 619// Zero extensions 620//===----------------------------------------------------------------------===// 621 622// 32-bit extensions from registers. 623let hasSideEffects = 0 in { 624 // Expands to LLCR or RISB[LH]G, depending on the choice of registers. 625 def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 626 Requires<[FeatureHighWord]>; 627 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 628 // Expands to LLHR or RISB[LH]G, depending on the choice of registers. 629 def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 630 Requires<[FeatureHighWord]>; 631 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 632} 633 634// 64-bit extensions from registers. 635let hasSideEffects = 0 in { 636 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 637 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 638 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 639} 640 641// Match 32-to-64-bit zero extensions in which the source is already 642// in a 64-bit register. 643def : Pat<(and GR64:$src, 0xffffffff), 644 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 645 646// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 647// depending on the choice of register. 648def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 649 Requires<[FeatureHighWord]>; 650def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 651def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 652 Requires<[FeatureHighWord]>; 653 654// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 655// depending on the choice of register. 656def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 657 Requires<[FeatureHighWord]>; 658def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 659def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 660 Requires<[FeatureHighWord]>; 661def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 662 663// 64-bit extensions from memory. 664def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 665def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 666def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 667def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 668def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 669 670// 31-to-64-bit zero extensions. 671def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 672def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 673def : Pat<(and GR64:$src, 0x7fffffff), 674 (LLGTR GR64:$src)>; 675def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 676 (LLGT bdxaddr20only:$src)>; 677 678// Load and zero rightmost byte. 679let Predicates = [FeatureLoadAndZeroRightmostByte] in { 680 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 681 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 682 (LLZRGF bdxaddr20only:$src)>; 683} 684 685// Load and trap. 686let Predicates = [FeatureLoadAndTrap] in { 687 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 688 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 689} 690 691// Extend GR64s to GR128s. 692let usesCustomInserter = 1 in 693 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 694 695//===----------------------------------------------------------------------===// 696// "Any" extensions 697//===----------------------------------------------------------------------===// 698 699// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 700def : Pat<(i64 (anyext GR32:$src)), 701 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 702 703// Extend GR64s to GR128s. 704let usesCustomInserter = 1 in 705 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 706 707//===----------------------------------------------------------------------===// 708// Truncations 709//===----------------------------------------------------------------------===// 710 711// Truncations of 64-bit registers to 32-bit registers. 712def : Pat<(i32 (trunc GR64:$src)), 713 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 714 715// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 716// STC, STCY or STCH, depending on the choice of register. 717def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 718 Requires<[FeatureHighWord]>; 719defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 720def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 721 Requires<[FeatureHighWord]>; 722 723// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 724// STH, STHY or STHH, depending on the choice of register. 725def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 726 Requires<[FeatureHighWord]>; 727defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 728def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 729 Requires<[FeatureHighWord]>; 730def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 731 732// Truncations of 64-bit registers to memory. 733defm : StoreGR64Pair<STC, STCY, truncstorei8>; 734defm : StoreGR64Pair<STH, STHY, truncstorei16>; 735def : StoreGR64PC<STHRL, aligned_truncstorei16>; 736defm : StoreGR64Pair<ST, STY, truncstorei32>; 737def : StoreGR64PC<STRL, aligned_truncstorei32>; 738 739// Store characters under mask -- not (yet) used for codegen. 740defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 741def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 742 743//===----------------------------------------------------------------------===// 744// Multi-register moves 745//===----------------------------------------------------------------------===// 746 747// Multi-register loads. 748defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 749def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 750def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 751def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 752 753// Multi-register stores. 754defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 755def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 756def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 757 758//===----------------------------------------------------------------------===// 759// Byte swaps 760//===----------------------------------------------------------------------===// 761 762// Byte-swapping register moves. 763let hasSideEffects = 0 in { 764 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 765 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 766} 767 768// Byte-swapping loads. Unlike normal loads, these instructions are 769// allowed to access storage more than once. 770def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 771def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 772def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 773 774// Likewise byte-swapping stores. 775def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 776def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 777def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 778 779// Byte-swapping memory-to-memory moves. 780let mayLoad = 1, mayStore = 1 in 781 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 782 783//===----------------------------------------------------------------------===// 784// Load address instructions 785//===----------------------------------------------------------------------===// 786 787// Load BDX-style addresses. 788let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1 in 789 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 790 791// Load a PC-relative address. There's no version of this instruction 792// with a 16-bit offset, so there's no relaxation. 793let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 794 isReMaterializable = 1 in 795 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 796 797// Load the Global Offset Table address. This will be lowered into a 798// larl $R1, _GLOBAL_OFFSET_TABLE_ 799// instruction. 800def GOT : Alias<6, (outs GR64:$R1), (ins), 801 [(set GR64:$R1, (global_offset_table))]>; 802 803//===----------------------------------------------------------------------===// 804// Absolute and Negation 805//===----------------------------------------------------------------------===// 806 807let Defs = [CC] in { 808 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 809 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 810 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 811 } 812 let CCValues = 0xE, CompareZeroCCMask = 0xE in 813 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 814} 815def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 816def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 817defm : SXU<z_iabs, LPGFR>; 818defm : SXU<z_iabs64, LPGFR>; 819 820let Defs = [CC] in { 821 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 822 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 823 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 824 } 825 let CCValues = 0xE, CompareZeroCCMask = 0xE in 826 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 827} 828def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 829def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 830defm : SXU<z_inegabs, LNGFR>; 831defm : SXU<z_inegabs64, LNGFR>; 832 833let Defs = [CC] in { 834 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 835 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 836 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 837 } 838 let CCValues = 0xE, CompareZeroCCMask = 0xE in 839 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 840} 841defm : SXU<ineg, LCGFR>; 842 843//===----------------------------------------------------------------------===// 844// Insertion 845//===----------------------------------------------------------------------===// 846 847let isCodeGenOnly = 1 in 848 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 849defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 850 851defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 852defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 853 854defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 855defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 856 857// Insert characters under mask -- not (yet) used for codegen. 858let Defs = [CC] in { 859 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 860 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 861} 862 863// Insertions of a 16-bit immediate, leaving other bits unaffected. 864// We don't have or_as_insert equivalents of these operations because 865// OI is available instead. 866// 867// IIxMux expands to II[LH]x, depending on the choice of register. 868def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 869 Requires<[FeatureHighWord]>; 870def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 871 Requires<[FeatureHighWord]>; 872def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 873def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 874def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 875def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 876def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 877def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 878def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 879def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 880 881// ...likewise for 32-bit immediates. For GR32s this is a general 882// full-width move. (We use IILF rather than something like LLILF 883// for 32-bit moves because IILF leaves the upper 32 bits of the 884// GR64 unchanged.) 885let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 886 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 887 Requires<[FeatureHighWord]>; 888 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 889 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 890} 891def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 892def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 893 894// An alternative model of inserthf, with the first operand being 895// a zero-extended value. 896def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 897 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 898 imm64hf32:$imm)>; 899 900//===----------------------------------------------------------------------===// 901// Addition 902//===----------------------------------------------------------------------===// 903 904// Plain addition. 905let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 906 // Addition of a register. 907 let isCommutable = 1 in { 908 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, add, GR32, GR32>; 909 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, add, GR64, GR64>; 910 } 911 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 912 913 // Addition to a high register. 914 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 915 Requires<[FeatureHighWord]>; 916 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 917 Requires<[FeatureHighWord]>; 918 919 // Addition of signed 16-bit immediates. 920 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 921 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 922 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 923 924 // Addition of signed 32-bit immediates. 925 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 926 Requires<[FeatureHighWord]>; 927 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 928 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 929 Requires<[FeatureHighWord]>; 930 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 931 932 // Addition of memory. 933 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 934 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 935 def AGH : BinaryRXY<"agh", 0xE338, add, GR64, asextloadi16, 2>, 936 Requires<[FeatureMiscellaneousExtensions2]>; 937 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 938 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 939 940 // Addition to memory. 941 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 942 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 943} 944defm : SXB<add, GR64, AGFR>; 945 946// Addition producing a carry. 947let Defs = [CC] in { 948 // Addition of a register. 949 let isCommutable = 1 in { 950 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, addc, GR32, GR32>; 951 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, addc, GR64, GR64>; 952 } 953 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 954 955 // Addition to a high register. 956 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 957 Requires<[FeatureHighWord]>; 958 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 959 Requires<[FeatureHighWord]>; 960 961 // Addition of signed 16-bit immediates. 962 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 963 Requires<[FeatureDistinctOps]>; 964 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 965 Requires<[FeatureDistinctOps]>; 966 967 // Addition of unsigned 32-bit immediates. 968 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 969 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 970 971 // Addition of signed 32-bit immediates. 972 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 973 Requires<[FeatureHighWord]>; 974 975 // Addition of memory. 976 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 977 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 978 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 979 980 // Addition to memory. 981 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 982 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 983} 984defm : ZXB<addc, GR64, ALGFR>; 985 986// Addition producing and using a carry. 987let Defs = [CC], Uses = [CC] in { 988 // Addition of a register. 989 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>; 990 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>; 991 992 // Addition of memory. 993 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 994 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 995} 996 997// Addition that does not modify the condition code. 998def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 999 Requires<[FeatureHighWord]>; 1000 1001//===----------------------------------------------------------------------===// 1002// Subtraction 1003//===----------------------------------------------------------------------===// 1004 1005// Plain subtraction. Although immediate forms exist, we use the 1006// add-immediate instruction instead. 1007let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 1008 // Subtraction of a register. 1009 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, sub, GR32, GR32>; 1010 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1011 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, sub, GR64, GR64>; 1012 1013 // Subtraction from a high register. 1014 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1015 Requires<[FeatureHighWord]>; 1016 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1017 Requires<[FeatureHighWord]>; 1018 1019 // Subtraction of memory. 1020 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 1021 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 1022 def SGH : BinaryRXY<"sgh", 0xE339, sub, GR64, asextloadi16, 2>, 1023 Requires<[FeatureMiscellaneousExtensions2]>; 1024 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 1025 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 1026} 1027defm : SXB<sub, GR64, SGFR>; 1028 1029// Subtraction producing a carry. 1030let Defs = [CC] in { 1031 // Subtraction of a register. 1032 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, subc, GR32, GR32>; 1033 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1034 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, subc, GR64, GR64>; 1035 1036 // Subtraction from a high register. 1037 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1038 Requires<[FeatureHighWord]>; 1039 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1040 Requires<[FeatureHighWord]>; 1041 1042 // Subtraction of unsigned 32-bit immediates. These don't match 1043 // subc because we prefer addc for constants. 1044 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 1045 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 1046 1047 // Subtraction of memory. 1048 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 1049 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 1050 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 1051} 1052defm : ZXB<subc, GR64, SLGFR>; 1053 1054// Subtraction producing and using a carry. 1055let Defs = [CC], Uses = [CC] in { 1056 // Subtraction of a register. 1057 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>; 1058 def SLBGR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>; 1059 1060 // Subtraction of memory. 1061 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 1062 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 1063} 1064 1065//===----------------------------------------------------------------------===// 1066// AND 1067//===----------------------------------------------------------------------===// 1068 1069let Defs = [CC] in { 1070 // ANDs of a register. 1071 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1072 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1073 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1074 } 1075 1076 let isConvertibleToThreeAddress = 1 in { 1077 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1078 // The CC result only reflects the 16-bit field, not the full register. 1079 // 1080 // NIxMux expands to NI[LH]x, depending on the choice of register. 1081 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1082 Requires<[FeatureHighWord]>; 1083 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1084 Requires<[FeatureHighWord]>; 1085 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1086 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1087 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1088 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1089 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1090 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1091 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1092 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1093 1094 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1095 // The CC result only reflects the 32-bit field, which means we can 1096 // use it as a zero indicator for i32 operations but not otherwise. 1097 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1098 // Expands to NILF or NIHF, depending on the choice of register. 1099 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1100 Requires<[FeatureHighWord]>; 1101 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1102 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1103 } 1104 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1105 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1106 } 1107 1108 // ANDs of memory. 1109 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1110 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1111 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1112 } 1113 1114 // AND to memory 1115 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1116 1117 // Block AND. 1118 let mayLoad = 1, mayStore = 1 in 1119 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1120} 1121defm : RMWIByte<and, bdaddr12pair, NI>; 1122defm : RMWIByte<and, bdaddr20pair, NIY>; 1123 1124//===----------------------------------------------------------------------===// 1125// OR 1126//===----------------------------------------------------------------------===// 1127 1128let Defs = [CC] in { 1129 // ORs of a register. 1130 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1131 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1132 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1133 } 1134 1135 // ORs of a 16-bit immediate, leaving other bits unaffected. 1136 // The CC result only reflects the 16-bit field, not the full register. 1137 // 1138 // OIxMux expands to OI[LH]x, depending on the choice of register. 1139 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1140 Requires<[FeatureHighWord]>; 1141 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1142 Requires<[FeatureHighWord]>; 1143 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1144 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1145 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1146 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1147 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1148 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1149 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1150 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1151 1152 // ORs of a 32-bit immediate, leaving other bits unaffected. 1153 // The CC result only reflects the 32-bit field, which means we can 1154 // use it as a zero indicator for i32 operations but not otherwise. 1155 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1156 // Expands to OILF or OIHF, depending on the choice of register. 1157 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1158 Requires<[FeatureHighWord]>; 1159 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1160 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1161 } 1162 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1163 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1164 1165 // ORs of memory. 1166 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1167 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1168 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1169 } 1170 1171 // OR to memory 1172 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1173 1174 // Block OR. 1175 let mayLoad = 1, mayStore = 1 in 1176 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1177} 1178defm : RMWIByte<or, bdaddr12pair, OI>; 1179defm : RMWIByte<or, bdaddr20pair, OIY>; 1180 1181//===----------------------------------------------------------------------===// 1182// XOR 1183//===----------------------------------------------------------------------===// 1184 1185let Defs = [CC] in { 1186 // XORs of a register. 1187 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1188 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1189 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1190 } 1191 1192 // XORs of a 32-bit immediate, leaving other bits unaffected. 1193 // The CC result only reflects the 32-bit field, which means we can 1194 // use it as a zero indicator for i32 operations but not otherwise. 1195 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1196 // Expands to XILF or XIHF, depending on the choice of register. 1197 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1198 Requires<[FeatureHighWord]>; 1199 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1200 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1201 } 1202 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1203 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1204 1205 // XORs of memory. 1206 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1207 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1208 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1209 } 1210 1211 // XOR to memory 1212 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1213 1214 // Block XOR. 1215 let mayLoad = 1, mayStore = 1 in 1216 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1217} 1218defm : RMWIByte<xor, bdaddr12pair, XI>; 1219defm : RMWIByte<xor, bdaddr20pair, XIY>; 1220 1221//===----------------------------------------------------------------------===// 1222// Multiplication 1223//===----------------------------------------------------------------------===// 1224 1225// Multiplication of a register, setting the condition code. We prefer these 1226// over MS(G)R if available, even though we cannot use the condition code, 1227// since they are three-operand instructions. 1228let Predicates = [FeatureMiscellaneousExtensions2], 1229 Defs = [CC], isCommutable = 1 in { 1230 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1231 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1232} 1233 1234// Multiplication of a register. 1235let isCommutable = 1 in { 1236 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1237 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1238} 1239def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1240defm : SXB<mul, GR64, MSGFR>; 1241 1242// Multiplication of a signed 16-bit immediate. 1243def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1244def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1245 1246// Multiplication of a signed 32-bit immediate. 1247def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1248def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1249 1250// Multiplication of memory. 1251defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1252defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1253def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1254 Requires<[FeatureMiscellaneousExtensions2]>; 1255def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1256def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1257 1258// Multiplication of memory, setting the condition code. 1259let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1260 def MSC : BinaryRXY<"msc", 0xE353, null_frag, GR32, load, 4>; 1261 def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>; 1262} 1263 1264// Multiplication of a register, producing two results. 1265def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1266def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1267 Requires<[FeatureMiscellaneousExtensions2]>; 1268def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1269def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1270def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1271 (MGRK GR64:$src1, GR64:$src2)>; 1272def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1273 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1274 1275// Multiplication of memory, producing two results. 1276def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1277def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1278def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1279 Requires<[FeatureMiscellaneousExtensions2]>; 1280def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1281def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1282def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1283 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1284def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1285 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1286 1287//===----------------------------------------------------------------------===// 1288// Division and remainder 1289//===----------------------------------------------------------------------===// 1290 1291let hasSideEffects = 1 in { // Do not speculatively execute. 1292 // Division and remainder, from registers. 1293 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1294 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1295 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1296 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1297 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1298 1299 // Division and remainder, from memory. 1300 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1301 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1302 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1303 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1304 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1305} 1306def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1307 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1308def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1309 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1310def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1311 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1312def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1313 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1314 1315def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1316 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1317 subreg_l32)), GR32:$src2)>; 1318def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1319 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1320 subreg_l32)), bdxaddr20only:$src2)>; 1321def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1322 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1323def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1324 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1325 1326//===----------------------------------------------------------------------===// 1327// Shifts 1328//===----------------------------------------------------------------------===// 1329 1330// Logical shift left. 1331let hasSideEffects = 0 in { 1332 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1333 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1334 def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1335} 1336 1337// Arithmetic shift left. 1338let Defs = [CC] in { 1339 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1340 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1341 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1342} 1343 1344// Logical shift right. 1345let hasSideEffects = 0 in { 1346 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1347 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1348 def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1349} 1350 1351// Arithmetic shift right. 1352let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1353 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1354 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1355 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1356} 1357 1358// Rotate left. 1359let hasSideEffects = 0 in { 1360 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1361 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1362} 1363 1364// Rotate second operand left and inserted selected bits into first operand. 1365// These can act like 32-bit operands provided that the constant start and 1366// end bits (operands 2 and 3) are in the range [32, 64). 1367let Defs = [CC] in { 1368 let isCodeGenOnly = 1 in 1369 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1370 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1371 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1372} 1373 1374// On zEC12 we have a variant of RISBG that does not set CC. 1375let Predicates = [FeatureMiscellaneousExtensions] in 1376 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1377 1378// Forms of RISBG that only affect one word of the destination register. 1379// They do not set CC. 1380let Predicates = [FeatureHighWord] in { 1381 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1382 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1383 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1384 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1385 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1386 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1387 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1388} 1389 1390// Rotate second operand left and perform a logical operation with selected 1391// bits of the first operand. The CC result only describes the selected bits, 1392// so isn't useful for a full comparison against zero. 1393let Defs = [CC] in { 1394 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1395 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1396 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1397} 1398 1399//===----------------------------------------------------------------------===// 1400// Comparison 1401//===----------------------------------------------------------------------===// 1402 1403// Signed comparisons. We put these before the unsigned comparisons because 1404// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1405// of the unsigned forms do. 1406let Defs = [CC], CCValues = 0xE in { 1407 // Comparison with a register. 1408 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1409 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1410 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1411 1412 // Comparison with a high register. 1413 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1414 Requires<[FeatureHighWord]>; 1415 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1416 Requires<[FeatureHighWord]>; 1417 1418 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1419 // depending on the choice of register. 1420 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1421 Requires<[FeatureHighWord]>; 1422 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1423 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1424 1425 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1426 // depending on the choice of register. 1427 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1428 Requires<[FeatureHighWord]>; 1429 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1430 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1431 Requires<[FeatureHighWord]>; 1432 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1433 1434 // Comparison with memory. 1435 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1436 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1437 Requires<[FeatureHighWord]>; 1438 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1439 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1440 Requires<[FeatureHighWord]>; 1441 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1442 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1443 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1444 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1445 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1446 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1447 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1448 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1449 1450 // Comparison between memory and a signed 16-bit immediate. 1451 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1452 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1453 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1454} 1455defm : SXB<z_scmp, GR64, CGFR>; 1456 1457// Unsigned comparisons. 1458let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1459 // Comparison with a register. 1460 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1461 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1462 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1463 1464 // Comparison with a high register. 1465 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1466 Requires<[FeatureHighWord]>; 1467 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1468 Requires<[FeatureHighWord]>; 1469 1470 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1471 // or CLIH, depending on the choice of register. 1472 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1473 Requires<[FeatureHighWord]>; 1474 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1475 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1476 Requires<[FeatureHighWord]>; 1477 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1478 1479 // Comparison with memory. 1480 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1481 Requires<[FeatureHighWord]>; 1482 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1483 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1484 Requires<[FeatureHighWord]>; 1485 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1486 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1487 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1488 aligned_azextloadi16>; 1489 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1490 aligned_load>; 1491 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1492 aligned_azextloadi16>; 1493 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1494 aligned_azextloadi32>; 1495 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1496 aligned_load>; 1497 1498 // Comparison between memory and an unsigned 8-bit immediate. 1499 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1500 1501 // Comparison between memory and an unsigned 16-bit immediate. 1502 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1503 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1504 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1505} 1506defm : ZXB<z_ucmp, GR64, CLGFR>; 1507 1508// Memory-to-memory comparison. 1509let mayLoad = 1, Defs = [CC] in { 1510 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1511 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1512 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1513 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1514} 1515 1516// String comparison. 1517let mayLoad = 1, Defs = [CC] in 1518 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1519 1520// Test under mask. 1521let Defs = [CC] in { 1522 // TMxMux expands to TM[LH]x, depending on the choice of register. 1523 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1524 Requires<[FeatureHighWord]>; 1525 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1526 Requires<[FeatureHighWord]>; 1527 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1528 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1529 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1530 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1531 1532 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1533 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1534 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1535 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1536 1537 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1538} 1539 1540def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1541def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1542 1543// Compare logical characters under mask -- not (yet) used for codegen. 1544let Defs = [CC] in { 1545 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1546 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1547} 1548 1549//===----------------------------------------------------------------------===// 1550// Prefetch and execution hint 1551//===----------------------------------------------------------------------===// 1552 1553def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1554def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1555 1556let Predicates = [FeatureExecutionHint] in { 1557 // Branch Prediction Preload 1558 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1559 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1560 1561 // Next Instruction Access Intent 1562 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1563} 1564 1565//===----------------------------------------------------------------------===// 1566// Atomic operations 1567//===----------------------------------------------------------------------===// 1568 1569// A serialization instruction that acts as a barrier for all memory 1570// accesses, which expands to "bcr 14, 0". 1571let hasSideEffects = 1 in 1572def Serialize : Alias<2, (outs), (ins), []>; 1573 1574// A pseudo instruction that serves as a compiler barrier. 1575let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1576def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1577 1578let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1579 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1580 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1581 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1582 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1583 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1584 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1585 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1586 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1587 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1588 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1589} 1590 1591def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1592def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1593def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1594 1595def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1596def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1597let Predicates = [FeatureNoInterlockedAccess1] in { 1598 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1599 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1600 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1601 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1602 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1603 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1604} 1605 1606def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1607def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1608def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1609 1610def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1611def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1612let Predicates = [FeatureNoInterlockedAccess1] in { 1613 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1614 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1615 imm32ll16c>; 1616 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1617 imm32lh16c>; 1618 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1619 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1620 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1621 imm64ll16c>; 1622 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1623 imm64lh16c>; 1624 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1625 imm64hl16c>; 1626 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1627 imm64hh16c>; 1628 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1629 imm64lf32c>; 1630 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1631 imm64hf32c>; 1632} 1633 1634def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1635def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1636let Predicates = [FeatureNoInterlockedAccess1] in { 1637 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1638 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1639 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1640 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1641 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1642 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1643 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1644 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1645 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1646 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1647 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1648} 1649 1650def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1651def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1652let Predicates = [FeatureNoInterlockedAccess1] in { 1653 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1654 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1655 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1656 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1657 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1658} 1659 1660def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1661def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1662 imm32lh16c>; 1663def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1664def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1665 imm32ll16c>; 1666def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1667 imm32lh16c>; 1668def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1669def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1670def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1671 imm64ll16c>; 1672def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1673 imm64lh16c>; 1674def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1675 imm64hl16c>; 1676def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1677 imm64hh16c>; 1678def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1679 imm64lf32c>; 1680def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1681 imm64hf32c>; 1682 1683def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1684def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1685def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1686 1687def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1688def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1689def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1690 1691def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1692def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1693def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1694 1695def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1696def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1697def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1698 1699def ATOMIC_CMP_SWAPW 1700 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1701 ADDR32:$bitshift, ADDR32:$negbitshift, 1702 uimm32:$bitsize), 1703 [(set GR32:$dst, 1704 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1705 ADDR32:$bitshift, ADDR32:$negbitshift, 1706 uimm32:$bitsize))]> { 1707 let Defs = [CC]; 1708 let mayLoad = 1; 1709 let mayStore = 1; 1710 let usesCustomInserter = 1; 1711 let hasNoSchedulingInfo = 1; 1712} 1713 1714// Test and set. 1715let mayLoad = 1, Defs = [CC] in 1716 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1717 1718// Compare and swap. 1719let Defs = [CC] in { 1720 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1721 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1722} 1723 1724// Compare double and swap. 1725let Defs = [CC] in { 1726 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1727 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1728} 1729 1730// Compare and swap and store. 1731let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1732 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1733 1734// Perform locked operation. 1735let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1736 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1737 1738// Load/store pair from/to quadword. 1739def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1740def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1741 1742// Load pair disjoint. 1743let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1744 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1745 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1746} 1747 1748//===----------------------------------------------------------------------===// 1749// Translate and convert 1750//===----------------------------------------------------------------------===// 1751 1752let mayLoad = 1, mayStore = 1 in 1753 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1754 1755let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1756 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1757 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1758} 1759 1760let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1761 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1762 1763let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1764 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1765 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1766} 1767 1768let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1769 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1770 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1771 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1772 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1773} 1774 1775let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1776 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1777 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1778 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1779 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1780 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1781 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1782 1783 let isAsmParserOnly = 1 in { 1784 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1785 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1786 } 1787} 1788 1789//===----------------------------------------------------------------------===// 1790// Message-security assist 1791//===----------------------------------------------------------------------===// 1792 1793let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1794 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1795 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1796 1797 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1798 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1799 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1800 1801 let Predicates = [FeatureMessageSecurityAssist4] in { 1802 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1803 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1804 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1805 GR128, GR128, GR128>; 1806 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1807 } 1808 1809 let Predicates = [FeatureMessageSecurityAssist5] in 1810 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1811 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1812 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1813 1814 let Predicates = [FeatureMessageSecurityAssist8] in 1815 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1816 GR128, GR128, GR128>; 1817} 1818 1819//===----------------------------------------------------------------------===// 1820// Guarded storage 1821//===----------------------------------------------------------------------===// 1822 1823let Predicates = [FeatureGuardedStorage] in { 1824 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1825 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1826 1827 let mayLoad = 1 in 1828 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1829 let mayStore = 1 in 1830 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1831} 1832 1833//===----------------------------------------------------------------------===// 1834// Decimal arithmetic 1835//===----------------------------------------------------------------------===// 1836 1837defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1838def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1839 1840defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1841def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1842 1843let mayLoad = 1, mayStore = 1 in { 1844 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1845 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1846 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1847 1848 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1849 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1850 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1851 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1852 let Defs = [CC] in { 1853 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1854 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1855 } 1856} 1857 1858let mayLoad = 1, mayStore = 1 in { 1859 let Defs = [CC] in { 1860 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1861 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1862 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1863 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1864 } 1865 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1866 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1867 let Defs = [CC] in { 1868 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1869 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1870 } 1871} 1872 1873let Defs = [CC] in { 1874 def CP : CompareSSb<"cp", 0xF9>; 1875 def TP : TestRSL<"tp", 0xEBC0>; 1876} 1877 1878//===----------------------------------------------------------------------===// 1879// Access registers 1880//===----------------------------------------------------------------------===// 1881 1882// Read a 32-bit access register into a GR32. As with all GR32 operations, 1883// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1884// when a 64-bit address is stored in a pair of access registers. 1885def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1886 1887// Set access register. 1888def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1889 1890// Copy access register. 1891def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1892 1893// Load address extended. 1894defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1895 1896// Load access multiple. 1897defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1898 1899// Load access multiple. 1900defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1901 1902//===----------------------------------------------------------------------===// 1903// Program mask and addressing mode 1904//===----------------------------------------------------------------------===// 1905 1906// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1907let Uses = [CC] in 1908 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1909 1910// Set CC and program mask from a register. 1911let hasSideEffects = 1, Defs = [CC] in 1912 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1913 1914// Branch and link - like BAS, but also extracts CC and program mask. 1915let isCall = 1, Uses = [CC], Defs = [CC] in { 1916 def BAL : CallRX<"bal", 0x45>; 1917 def BALR : CallRR<"balr", 0x05>; 1918} 1919 1920// Test addressing mode. 1921let Defs = [CC] in 1922 def TAM : SideEffectInherentE<"tam", 0x010B>; 1923 1924// Set addressing mode. 1925let hasSideEffects = 1 in { 1926 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 1927 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 1928 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 1929} 1930 1931// Branch and set mode. Not really a call, but also sets an output register. 1932let isBranch = 1, isTerminator = 1, isBarrier = 1 in 1933 def BSM : CallRR<"bsm", 0x0B>; 1934 1935// Branch and save and set mode. 1936let isCall = 1, Defs = [CC] in 1937 def BASSM : CallRR<"bassm", 0x0C>; 1938 1939//===----------------------------------------------------------------------===// 1940// Transactional execution 1941//===----------------------------------------------------------------------===// 1942 1943let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 1944 // Transaction Begin 1945 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 1946 def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 1947 def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 1948 1949 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 1950 int_s390_tbeginc, imm32zx16>; 1951 } 1952 1953 // Transaction End 1954 let Defs = [CC] in 1955 def TEND : SideEffectInherentS<"tend", 0xB2F8, z_tend>; 1956 1957 // Transaction Abort 1958 let isTerminator = 1, isBarrier = 1 in 1959 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 1960 1961 // Nontransactional Store 1962 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1963 1964 // Extract Transaction Nesting Depth 1965 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 1966} 1967 1968//===----------------------------------------------------------------------===// 1969// Processor assist 1970//===----------------------------------------------------------------------===// 1971 1972let Predicates = [FeatureProcessorAssist] in { 1973 let hasSideEffects = 1 in 1974 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 1975 def : Pat<(int_s390_ppa_txassist GR32:$src), 1976 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1977 0, 1)>; 1978} 1979 1980//===----------------------------------------------------------------------===// 1981// Miscellaneous Instructions. 1982//===----------------------------------------------------------------------===// 1983 1984// Find leftmost one, AKA count leading zeros. The instruction actually 1985// returns a pair of GR64s, the first giving the number of leading zeros 1986// and the second giving a copy of the source with the leftmost one bit 1987// cleared. We only use the first result here. 1988let Defs = [CC] in 1989 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 1990def : Pat<(ctlz GR64:$src), 1991 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1992 1993// Population count. Counts bits set per byte. 1994let Predicates = [FeaturePopulationCount], Defs = [CC] in 1995 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 1996 1997// Search a block of memory for a character. 1998let mayLoad = 1, Defs = [CC] in 1999 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2000let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2001 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2002 2003// Compare until substring equal. 2004let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2005 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2006 2007// Compare and form codeword. 2008let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2009 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2010 2011// Update tree. 2012let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2013 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2014 def UPT : SideEffectInherentE<"upt", 0x0102>; 2015 2016// Checksum. 2017let mayLoad = 1, Defs = [CC] in 2018 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2019 2020// Compression call. 2021let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2022 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2023 2024// Execute. 2025let hasSideEffects = 1 in { 2026 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2027 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2028} 2029 2030//===----------------------------------------------------------------------===// 2031// .insn directive instructions 2032//===----------------------------------------------------------------------===// 2033 2034let isCodeGenOnly = 1 in { 2035 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2036 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2037 imm32sx16:$I2), 2038 ".insn ri,$enc,$R1,$I2", []>; 2039 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2040 AnyReg:$R3, brtarget16:$I2), 2041 ".insn rie,$enc,$R1,$R3,$I2", []>; 2042 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2043 brtarget32:$I2), 2044 ".insn ril,$enc,$R1,$I2", []>; 2045 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2046 uimm32:$I2), 2047 ".insn rilu,$enc,$R1,$I2", []>; 2048 def InsnRIS : DirectiveInsnRIS<(outs), 2049 (ins imm64zx48:$enc, AnyReg:$R1, 2050 imm32sx8:$I2, imm32zx4:$M3, 2051 bdaddr12only:$BD4), 2052 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2053 def InsnRR : DirectiveInsnRR<(outs), 2054 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2055 ".insn rr,$enc,$R1,$R2", []>; 2056 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2057 AnyReg:$R1, AnyReg:$R2), 2058 ".insn rre,$enc,$R1,$R2", []>; 2059 def InsnRRF : DirectiveInsnRRF<(outs), 2060 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2061 AnyReg:$R3, imm32zx4:$M4), 2062 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2063 def InsnRRS : DirectiveInsnRRS<(outs), 2064 (ins imm64zx48:$enc, AnyReg:$R1, 2065 AnyReg:$R2, imm32zx4:$M3, 2066 bdaddr12only:$BD4), 2067 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2068 def InsnRS : DirectiveInsnRS<(outs), 2069 (ins imm64zx32:$enc, AnyReg:$R1, 2070 AnyReg:$R3, bdaddr12only:$BD2), 2071 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2072 def InsnRSE : DirectiveInsnRSE<(outs), 2073 (ins imm64zx48:$enc, AnyReg:$R1, 2074 AnyReg:$R3, bdaddr12only:$BD2), 2075 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2076 def InsnRSI : DirectiveInsnRSI<(outs), 2077 (ins imm64zx48:$enc, AnyReg:$R1, 2078 AnyReg:$R3, brtarget16:$RI2), 2079 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2080 def InsnRSY : DirectiveInsnRSY<(outs), 2081 (ins imm64zx48:$enc, AnyReg:$R1, 2082 AnyReg:$R3, bdaddr20only:$BD2), 2083 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2084 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2085 bdxaddr12only:$XBD2), 2086 ".insn rx,$enc,$R1,$XBD2", []>; 2087 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2088 bdxaddr12only:$XBD2), 2089 ".insn rxe,$enc,$R1,$XBD2", []>; 2090 def InsnRXF : DirectiveInsnRXF<(outs), 2091 (ins imm64zx48:$enc, AnyReg:$R1, 2092 AnyReg:$R3, bdxaddr12only:$XBD2), 2093 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2094 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2095 bdxaddr20only:$XBD2), 2096 ".insn rxy,$enc,$R1,$XBD2", []>; 2097 def InsnS : DirectiveInsnS<(outs), 2098 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2099 ".insn s,$enc,$BD2", []>; 2100 def InsnSI : DirectiveInsnSI<(outs), 2101 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2102 imm32sx8:$I2), 2103 ".insn si,$enc,$BD1,$I2", []>; 2104 def InsnSIY : DirectiveInsnSIY<(outs), 2105 (ins imm64zx48:$enc, 2106 bdaddr20only:$BD1, imm32zx8:$I2), 2107 ".insn siy,$enc,$BD1,$I2", []>; 2108 def InsnSIL : DirectiveInsnSIL<(outs), 2109 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2110 imm32zx16:$I2), 2111 ".insn sil,$enc,$BD1,$I2", []>; 2112 def InsnSS : DirectiveInsnSS<(outs), 2113 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2114 bdaddr12only:$BD2, AnyReg:$R3), 2115 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2116 def InsnSSE : DirectiveInsnSSE<(outs), 2117 (ins imm64zx48:$enc, 2118 bdaddr12only:$BD1,bdaddr12only:$BD2), 2119 ".insn sse,$enc,$BD1,$BD2", []>; 2120 def InsnSSF : DirectiveInsnSSF<(outs), 2121 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2122 bdaddr12only:$BD2, AnyReg:$R3), 2123 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2124} 2125 2126//===----------------------------------------------------------------------===// 2127// Peepholes. 2128//===----------------------------------------------------------------------===// 2129 2130// Use AL* for GR64 additions of unsigned 32-bit values. 2131defm : ZXB<add, GR64, ALGFR>; 2132def : Pat<(add GR64:$src1, imm64zx32:$src2), 2133 (ALGFI GR64:$src1, imm64zx32:$src2)>; 2134def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2135 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 2136 2137// Use SL* for GR64 subtractions of unsigned 32-bit values. 2138defm : ZXB<sub, GR64, SLGFR>; 2139def : Pat<(add GR64:$src1, imm64zx32n:$src2), 2140 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 2141def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2142 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 2143 2144// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 2145// for vector legalization. 2146def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)), 2147 (i32 31)), 2148 (i32 31)), 2149 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 2150def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, 2151 imm32zx4:$cc)))), 2152 (i32 63)), 2153 (i32 63)), 2154 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 2155 2156// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2157// equivalent to (and (xor x, -1), y) 2158def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2159 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2160 2161// Shift/rotate instructions only use the last 6 bits of the second operand 2162// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2163// last 16 bits. 2164// Complexity is added so that we match this before we match NILF on the AND 2165// operation alone. 2166let AddedComplexity = 4 in { 2167 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2168 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2169 2170 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 2171 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2172 2173 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2174 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2175 2176 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2177 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2178 2179 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 2180 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2181 2182 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2183 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2184 2185 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2186 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2187 2188 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2189 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2190} 2191 2192// Peepholes for turning scalar operations into block operations. 2193defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2194 XCSequence, 1>; 2195defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2196 XCSequence, 2>; 2197defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2198 XCSequence, 4>; 2199defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2200 OCSequence, XCSequence, 1>; 2201defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2202 XCSequence, 2>; 2203defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2204 XCSequence, 4>; 2205defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2206 XCSequence, 8>; 2207