1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 10 11//===----------------------------------------------------------------------===// 12// Stack allocation 13//===----------------------------------------------------------------------===// 14 15// The callseq_start node requires the hasSideEffects flag, even though these 16// instructions are noops on SystemZ. 17let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 18 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 19 [(callseq_start timm:$amt1, timm:$amt2)]>; 20 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 21 [(callseq_end timm:$amt1, timm:$amt2)]>; 22} 23 24// Takes as input the value of the stack pointer after a dynamic allocation 25// has been made. Sets the output to the address of the dynamically- 26// allocated area itself, skipping the outgoing arguments. 27// 28// This expands to an LA or LAY instruction. We restrict the offset 29// to the range of LA and keep the LAY range in reserve for when 30// the size of the outgoing arguments is added. 31def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 32 [(set GR64:$dst, dynalloc12only:$src)]>; 33 34let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 35 usesCustomInserter = 1 in 36 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 37 (ins GR64:$oldSP, GR64:$space), 38 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 39 40let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 41 hasSideEffects = 1 in 42 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 43 44//===----------------------------------------------------------------------===// 45// Branch instructions 46//===----------------------------------------------------------------------===// 47 48// Conditional branches. 49let isBranch = 1, isTerminator = 1, Uses = [CC] in { 50 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 51 // with the condition-code mask being the first operand. It seems friendlier 52 // to use mnemonic forms like JE and JLH when writing out the assembly though. 53 let isCodeGenOnly = 1 in { 54 // An assembler extended mnemonic for BRC. 55 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 56 // An assembler extended mnemonic for BRCL. (The extension is "G" 57 // rather than "L" because "JL" is "Jump if Less".) 58 def BRCL : CondBranchRIL<"jg#", 0xC04>; 59 let isIndirectBranch = 1 in { 60 def BC : CondBranchRX<"b#", 0x47>; 61 def BCR : CondBranchRR<"b#r", 0x07>; 62 def BIC : CondBranchRXY<"bi#", 0xe347>, 63 Requires<[FeatureMiscellaneousExtensions2]>; 64 } 65 } 66 67 // Allow using the raw forms directly from the assembler (and occasional 68 // special code generation needs) as well. 69 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 70 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 71 let isIndirectBranch = 1 in { 72 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 73 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 74 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 75 Requires<[FeatureMiscellaneousExtensions2]>; 76 } 77 78 // Define AsmParser extended mnemonics for each general condition-code mask 79 // (integer or floating-point) 80 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 81 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 82 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 83 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 84 let isIndirectBranch = 1 in { 85 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 86 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 87 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 88 Requires<[FeatureMiscellaneousExtensions2]>; 89 } 90 } 91} 92 93// Unconditional branches. These are in fact simply variants of the 94// conditional branches with the condition mask set to "always". 95let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 96 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 97 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 98 let isIndirectBranch = 1 in { 99 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 100 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 101 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 102 Requires<[FeatureMiscellaneousExtensions2]>; 103 } 104} 105 106// NOPs. These are again variants of the conditional branches, with the 107// condition mask set to "never". NOP_bare can't be an InstAlias since it 108// would need R0D hard coded which is not part of ADDR64BitRegClass. 109def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 110let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 111 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 112def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 113def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 114 115// An alias of BRC 0, label 116def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 117 118// An alias of BRCL 0, label 119def JGNOP : InstAlias<"jgnop\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 120 121// Fused compare-and-branch instructions. 122// 123// These instructions do not use or clobber the condition codes. 124// We nevertheless pretend that the relative compare-and-branch 125// instructions clobber CC, so that we can lower them to separate 126// comparisons and BRCLs if the branch ends up being out of range. 127let isBranch = 1, isTerminator = 1 in { 128 // As for normal branches, we handle these instructions internally in 129 // their raw CRJ-like form, but use assembly macros like CRJE when writing 130 // them out. Using the *Pair multiclasses, we also create the raw forms. 131 let Defs = [CC] in { 132 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 133 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 134 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 135 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 136 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 137 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 138 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 139 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 140 } 141 let isIndirectBranch = 1 in { 142 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 143 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 144 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 145 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 146 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 147 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 148 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 149 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 150 } 151 152 // Define AsmParser mnemonics for each integer condition-code mask. 153 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 154 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 155 let Defs = [CC] in { 156 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 157 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 158 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 159 imm32sx8>; 160 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 161 imm64sx8>; 162 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 163 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 164 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 165 imm32zx8>; 166 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 167 imm64zx8>; 168 } 169 let isIndirectBranch = 1 in { 170 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 171 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 172 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 173 imm32sx8>; 174 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 175 imm64sx8>; 176 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 177 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 178 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 179 imm32zx8>; 180 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 181 imm64zx8>; 182 } 183 } 184} 185 186// Decrement a register and branch if it is nonzero. These don't clobber CC, 187// but we might need to split long relative branches into sequences that do. 188let isBranch = 1, isTerminator = 1 in { 189 let Defs = [CC] in { 190 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 191 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 192 } 193 // This doesn't need to clobber CC since we never need to split it. 194 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 195 Requires<[FeatureHighWord]>; 196 197 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 198 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 199 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 200 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 201} 202 203let isBranch = 1, isTerminator = 1 in { 204 let Defs = [CC] in { 205 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 206 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 207 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 208 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 209 } 210 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 211 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 212 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 213 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 214} 215 216//===----------------------------------------------------------------------===// 217// Trap instructions 218//===----------------------------------------------------------------------===// 219 220// Unconditional trap. 221let hasCtrlDep = 1, hasSideEffects = 1 in 222 def Trap : Alias<4, (outs), (ins), [(trap)]>; 223 224// Conditional trap. 225let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 226 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 227 228// Fused compare-and-trap instructions. 229let hasCtrlDep = 1, hasSideEffects = 1 in { 230 // These patterns work the same way as for compare-and-branch. 231 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 232 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 233 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 234 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 235 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 236 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 237 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 238 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 239 let Predicates = [FeatureMiscellaneousExtensions] in { 240 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 241 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 242 } 243 244 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 245 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 246 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 247 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 248 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 249 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 250 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 251 imm32sx16>; 252 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 253 imm64sx16>; 254 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 255 imm32zx16>; 256 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 257 imm64zx16>; 258 let Predicates = [FeatureMiscellaneousExtensions] in { 259 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 260 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 261 } 262 } 263} 264 265//===----------------------------------------------------------------------===// 266// Call and return instructions 267//===----------------------------------------------------------------------===// 268 269// Define the general form of the call instructions for the asm parser. 270// These instructions don't hard-code %r14 as the return address register. 271let isCall = 1, Defs = [CC] in { 272 def BRAS : CallRI <"bras", 0xA75>; 273 def BRASL : CallRIL<"brasl", 0xC05>; 274 def BAS : CallRX <"bas", 0x4D>; 275 def BASR : CallRR <"basr", 0x0D>; 276} 277 278// Regular calls. 279// z/Linux ELF 280let Predicates = [IsTargetELF] in { 281 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 282 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 283 [(z_call pcrel32:$I2)]>; 284 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 285 [(z_call ADDR64:$R2)]>; 286 } 287 288 // TLS calls. These will be lowered into a call to __tls_get_offset, 289 // with an extra relocation specifying the TLS symbol. 290 let isCall = 1, Defs = [R14D, CC] in { 291 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 292 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 293 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 294 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 295 } 296} 297 298// Sibling calls. 299let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 300 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 301 [(z_sibcall pcrel32:$I2)]>; 302 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 303 [(z_sibcall ADDR64:$R2)]>; 304} 305 306// Conditional sibling calls. 307let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 308 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 309 pcrel32:$I2), []>; 310 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 311 ADDR64:$R2), []>; 312} 313 314// Fused compare and conditional sibling calls. 315let isCall = 1, isTerminator = 1, isReturn = 1 in { 316 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 317 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 318 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 319 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 320 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 321 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 322 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 323 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 324} 325 326// A return instruction (br %r14). 327let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 328 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 329 330// A conditional return instruction (bcr <cond>, %r14). 331let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 332 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 333 334// Fused compare and conditional returns. 335let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 336 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 337 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 338 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 339 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 340 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 341 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 342 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 343 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 344} 345 346//===----------------------------------------------------------------------===// 347// Select instructions 348//===----------------------------------------------------------------------===// 349 350def Select32 : SelectWrapper<i32, GR32>, 351 Requires<[FeatureNoLoadStoreOnCond]>; 352def Select64 : SelectWrapper<i64, GR64>, 353 Requires<[FeatureNoLoadStoreOnCond]>; 354 355// We don't define 32-bit Mux stores if we don't have STOCFH, because the 356// low-only STOC should then always be used if possible. 357defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 358 nonvolatile_anyextloadi8, bdxaddr20only>, 359 Requires<[FeatureHighWord]>; 360defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 361 nonvolatile_anyextloadi16, bdxaddr20only>, 362 Requires<[FeatureHighWord]>; 363defm CondStore32Mux : CondStores<GRX32, simple_store, 364 simple_load, bdxaddr20only>, 365 Requires<[FeatureLoadStoreOnCond2]>; 366defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 367 nonvolatile_anyextloadi8, bdxaddr20only>; 368defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 369 nonvolatile_anyextloadi16, bdxaddr20only>; 370defm CondStore32 : CondStores<GR32, simple_store, 371 simple_load, bdxaddr20only>; 372 373defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 374 nonvolatile_anyextloadi8, bdxaddr20only>; 375defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 376 nonvolatile_anyextloadi16, bdxaddr20only>; 377defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 378 nonvolatile_anyextloadi32, bdxaddr20only>; 379defm CondStore64 : CondStores<GR64, simple_store, 380 simple_load, bdxaddr20only>; 381 382//===----------------------------------------------------------------------===// 383// Move instructions 384//===----------------------------------------------------------------------===// 385 386// Register moves. 387def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 388def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 389 390let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 391 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 392 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 393} 394 395let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 396 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 397 398// Immediate moves. 399let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 400 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 401 // deopending on the choice of register. 402 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 403 Requires<[FeatureHighWord]>; 404 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 405 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 406 407 // Other 16-bit immediates. 408 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 409 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 410 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 411 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 412 413 // 32-bit immediates. 414 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 415 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 416 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 417} 418 419// Register loads. 420let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 421 // Expands to L, LY or LFH, depending on the choice of register. 422 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 423 Requires<[FeatureHighWord]>; 424 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 425 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 426 Requires<[FeatureHighWord]>; 427 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 428 429 // These instructions are split after register allocation, so we don't 430 // want a custom inserter. 431 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 432 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 433 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 434 } 435} 436let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 437 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 438 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 439} 440 441let canFoldAsLoad = 1 in { 442 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 443 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 444} 445 446// Load and zero rightmost byte. 447let Predicates = [FeatureLoadAndZeroRightmostByte] in { 448 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 449 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 450 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 451 (LZRF bdxaddr20only:$src)>; 452 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 453 (LZRG bdxaddr20only:$src)>; 454} 455 456// Load and trap. 457let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 458 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 459 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 460 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 461} 462 463// Register stores. 464let SimpleBDXStore = 1, mayStore = 1 in { 465 // Expands to ST, STY or STFH, depending on the choice of register. 466 def STMux : StoreRXYPseudo<store, GRX32, 4>, 467 Requires<[FeatureHighWord]>; 468 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 469 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 470 Requires<[FeatureHighWord]>; 471 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 472 473 // These instructions are split after register allocation, so we don't 474 // want a custom inserter. 475 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 476 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 477 [(store GR128:$src, bdxaddr20only128:$dst)]>; 478 } 479} 480def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 481def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 482 483// 8-bit immediate stores to 8-bit fields. 484defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 485 486// 16-bit immediate stores to 16-, 32- or 64-bit fields. 487def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 488def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 489def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 490 491// Memory-to-memory moves. 492let mayLoad = 1, mayStore = 1 in 493 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 494let mayLoad = 1, mayStore = 1, Defs = [CC] in { 495 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 496 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 497 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 498} 499 500// Move right. 501let Predicates = [FeatureMiscellaneousExtensions3], 502 mayLoad = 1, mayStore = 1, Uses = [R0L] in 503 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 504 505// String moves. 506let mayLoad = 1, mayStore = 1, Defs = [CC] in 507 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 508 509//===----------------------------------------------------------------------===// 510// Conditional move instructions 511//===----------------------------------------------------------------------===// 512 513let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 514 // Select. 515 let isCommutable = 1 in { 516 // Expands to SELR or SELFHR or a branch-and-move sequence, 517 // depending on the choice of registers. 518 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 519 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 520 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 521 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 522 } 523 524 // Define AsmParser extended mnemonics for each general condition-code mask. 525 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 526 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 527 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 528 GR32, GR32, GR32>; 529 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 530 GRH32, GRH32, GRH32>; 531 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 532 GR64, GR64, GR64>; 533 } 534} 535 536let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 537 // Load immediate on condition. Matched via DAG pattern and created 538 // by the PeepholeOptimizer via FoldImmediate. 539 540 // Expands to LOCHI or LOCHHI, depending on the choice of register. 541 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 542 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 543 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 544 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 545 546 // Move register on condition. Matched via DAG pattern and 547 // created by early if-conversion. 548 let isCommutable = 1 in { 549 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 550 // depending on the choice of registers. 551 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 552 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 553 } 554 555 // Load on condition. Matched via DAG pattern. 556 // Expands to LOC or LOCFH, depending on the choice of register. 557 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 558 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 559 560 // Store on condition. Expanded from CondStore* pseudos. 561 // Expands to STOC or STOCFH, depending on the choice of register. 562 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 563 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 564 565 // Define AsmParser extended mnemonics for each general condition-code mask. 566 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 567 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 568 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 569 imm32sx16>; 570 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 571 imm64sx16>; 572 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 573 imm32sx16>; 574 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 575 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 576 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 577 } 578} 579 580let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 581 // Move register on condition. Matched via DAG pattern and 582 // created by early if-conversion. 583 let isCommutable = 1 in { 584 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 585 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 586 } 587 588 // Load on condition. Matched via DAG pattern. 589 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 590 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 591 592 // Store on condition. Expanded from CondStore* pseudos. 593 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 594 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 595 596 // Define AsmParser extended mnemonics for each general condition-code mask. 597 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 598 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 599 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 600 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 601 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 602 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 603 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 604 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 605 } 606} 607//===----------------------------------------------------------------------===// 608// Sign extensions 609//===----------------------------------------------------------------------===// 610// 611// Note that putting these before zero extensions mean that we will prefer 612// them for anyextload*. There's not really much to choose between the two 613// either way, but signed-extending loads have a short LH and a long LHY, 614// while zero-extending loads have only the long LLH. 615// 616//===----------------------------------------------------------------------===// 617 618// 32-bit extensions from registers. 619def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 620def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 621 622// 64-bit extensions from registers. 623def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 624def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 625def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 626 627let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 628 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 629 630// Match 32-to-64-bit sign extensions in which the source is already 631// in a 64-bit register. 632def : Pat<(sext_inreg GR64:$src, i32), 633 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 634 635// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 636// depending on the choice of register. 637def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 638 Requires<[FeatureHighWord]>; 639def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 640def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 641 Requires<[FeatureHighWord]>; 642 643// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 644// depending on the choice of register. 645def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 646 Requires<[FeatureHighWord]>; 647defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 648def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 649 Requires<[FeatureHighWord]>; 650def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 651 652// 64-bit extensions from memory. 653def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 654def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 655def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 656def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 657def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 658let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 659 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 660 661//===----------------------------------------------------------------------===// 662// Zero extensions 663//===----------------------------------------------------------------------===// 664 665// 32-bit extensions from registers. 666 667// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 668def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 669 Requires<[FeatureHighWord]>; 670def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 671// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 672def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 673 Requires<[FeatureHighWord]>; 674def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 675 676// 64-bit extensions from registers. 677def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 678def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 679def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 680 681// Match 32-to-64-bit zero extensions in which the source is already 682// in a 64-bit register. 683def : Pat<(and GR64:$src, 0xffffffff), 684 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 685 686// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 687// depending on the choice of register. 688def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 689 Requires<[FeatureHighWord]>; 690def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 691def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 692 Requires<[FeatureHighWord]>; 693 694// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 695// depending on the choice of register. 696def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 697 Requires<[FeatureHighWord]>; 698def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 699def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 700 Requires<[FeatureHighWord]>; 701def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 702 703// 64-bit extensions from memory. 704def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 705def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 706def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 707def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 708def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 709 710// 31-to-64-bit zero extensions. 711def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 712def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 713def : Pat<(and GR64:$src, 0x7fffffff), 714 (LLGTR GR64:$src)>; 715def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 716 (LLGT bdxaddr20only:$src)>; 717 718// Load and zero rightmost byte. 719let Predicates = [FeatureLoadAndZeroRightmostByte] in { 720 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 721 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 722 (LLZRGF bdxaddr20only:$src)>; 723} 724 725// Load and trap. 726let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 727 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 728 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 729} 730 731// Extend GR64s to GR128s. 732let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 733 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 734 735//===----------------------------------------------------------------------===// 736// "Any" extensions 737//===----------------------------------------------------------------------===// 738 739// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 740def : Pat<(i64 (anyext GR32:$src)), 741 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 742 743// Extend GR64s to GR128s. 744let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 745 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 746 747//===----------------------------------------------------------------------===// 748// Truncations 749//===----------------------------------------------------------------------===// 750 751// Truncations of 64-bit registers to 32-bit registers. 752def : Pat<(i32 (trunc GR64:$src)), 753 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 754 755// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 756// STC, STCY or STCH, depending on the choice of register. 757def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 758 Requires<[FeatureHighWord]>; 759defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 760def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 761 Requires<[FeatureHighWord]>; 762 763// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 764// STH, STHY or STHH, depending on the choice of register. 765def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 766 Requires<[FeatureHighWord]>; 767defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 768def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 769 Requires<[FeatureHighWord]>; 770def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 771 772// Truncations of 64-bit registers to memory. 773defm : StoreGR64Pair<STC, STCY, truncstorei8>; 774defm : StoreGR64Pair<STH, STHY, truncstorei16>; 775def : StoreGR64PC<STHRL, aligned_truncstorei16>; 776defm : StoreGR64Pair<ST, STY, truncstorei32>; 777def : StoreGR64PC<STRL, aligned_truncstorei32>; 778 779// Store characters under mask -- not (yet) used for codegen. 780defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 781def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 782 783//===----------------------------------------------------------------------===// 784// Multi-register moves 785//===----------------------------------------------------------------------===// 786 787// Multi-register loads. 788defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 789def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 790def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 791def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 792 793// Multi-register stores. 794defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 795def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 796def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 797 798//===----------------------------------------------------------------------===// 799// Byte swaps 800//===----------------------------------------------------------------------===// 801 802// Byte-swapping register moves. 803def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 804def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 805 806// Byte-swapping loads. 807def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 808def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 809def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 810 811// Byte-swapping stores. 812def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 813def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 814def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 815 816// Byte-swapping memory-to-memory moves. 817let mayLoad = 1, mayStore = 1 in 818 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 819 820//===----------------------------------------------------------------------===// 821// Load address instructions 822//===----------------------------------------------------------------------===// 823 824// Load BDX-style addresses. 825let isAsCheapAsAMove = 1, isReMaterializable = 1 in 826 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 827 828// Load a PC-relative address. There's no version of this instruction 829// with a 16-bit offset, so there's no relaxation. 830let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 831 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 832 833// Load the Global Offset Table address. This will be lowered into a 834// larl $R1, _GLOBAL_OFFSET_TABLE_ 835// instruction. 836def GOT : Alias<6, (outs GR64:$R1), (ins), 837 [(set GR64:$R1, (global_offset_table))]>; 838 839//===----------------------------------------------------------------------===// 840// Absolute and Negation 841//===----------------------------------------------------------------------===// 842 843let Defs = [CC] in { 844 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 845 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 846 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 847 } 848 let CCValues = 0xE, CompareZeroCCMask = 0xE in 849 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 850} 851defm : SXU<abs, LPGFR>; 852 853let Defs = [CC] in { 854 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 855 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 856 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 857 } 858 let CCValues = 0xE, CompareZeroCCMask = 0xE in 859 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 860} 861defm : SXU<z_inegabs, LNGFR>; 862 863let Defs = [CC] in { 864 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 865 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 866 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 867 } 868 let CCValues = 0xE, CompareZeroCCMask = 0xE in 869 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 870} 871defm : SXU<ineg, LCGFR>; 872 873//===----------------------------------------------------------------------===// 874// Insertion 875//===----------------------------------------------------------------------===// 876 877let isCodeGenOnly = 1 in 878 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 879defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 880 881defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 882defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 883 884defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 885defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 886 887// Insert characters under mask -- not (yet) used for codegen. 888let Defs = [CC] in { 889 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 890 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 891} 892 893// Insertions of a 16-bit immediate, leaving other bits unaffected. 894// We don't have or_as_insert equivalents of these operations because 895// OI is available instead. 896// 897// IIxMux expands to II[LH]x, depending on the choice of register. 898def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 899 Requires<[FeatureHighWord]>; 900def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 901 Requires<[FeatureHighWord]>; 902def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 903def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 904def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 905def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 906def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 907def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 908def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 909def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 910 911// ...likewise for 32-bit immediates. For GR32s this is a general 912// full-width move. (We use IILF rather than something like LLILF 913// for 32-bit moves because IILF leaves the upper 32 bits of the 914// GR64 unchanged.) 915let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 916 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 917 Requires<[FeatureHighWord]>; 918 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 919 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 920} 921def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 922def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 923 924// An alternative model of inserthf, with the first operand being 925// a zero-extended value. 926def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 927 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 928 imm64hf32:$imm)>; 929 930//===----------------------------------------------------------------------===// 931// Addition 932//===----------------------------------------------------------------------===// 933 934// Addition producing a signed overflow flag. 935let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 936 // Addition of a register. 937 let isCommutable = 1 in { 938 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 939 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 940 } 941 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 942 943 // Addition to a high register. 944 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 945 Requires<[FeatureHighWord]>; 946 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 947 Requires<[FeatureHighWord]>; 948 949 // Addition of signed 16-bit immediates. 950 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 951 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 952 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 953 954 // Addition of signed 32-bit immediates. 955 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 956 Requires<[FeatureHighWord]>; 957 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 958 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 959 Requires<[FeatureHighWord]>; 960 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 961 962 // Addition of memory. 963 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 964 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 965 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 966 Requires<[FeatureMiscellaneousExtensions2]>; 967 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 968 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 969 970 // Addition to memory. 971 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 972 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 973} 974defm : SXB<z_sadd, GR64, AGFR>; 975 976// Addition producing a carry. 977let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 978 // Addition of a register. 979 let isCommutable = 1 in { 980 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 981 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 982 } 983 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 984 985 // Addition to a high register. 986 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 987 Requires<[FeatureHighWord]>; 988 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 989 Requires<[FeatureHighWord]>; 990 991 // Addition of signed 16-bit immediates. 992 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 993 Requires<[FeatureDistinctOps]>; 994 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 995 Requires<[FeatureDistinctOps]>; 996 997 // Addition of unsigned 32-bit immediates. 998 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 999 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1000 1001 // Addition of signed 32-bit immediates. 1002 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1003 Requires<[FeatureHighWord]>; 1004 1005 // Addition of memory. 1006 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1007 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1008 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1009 1010 // Addition to memory. 1011 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1012 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1013} 1014defm : ZXB<z_uadd, GR64, ALGFR>; 1015 1016// Addition producing and using a carry. 1017let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1018 // Addition of a register. 1019 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1020 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1021 1022 // Addition of memory. 1023 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1024 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1025} 1026 1027// Addition that does not modify the condition code. 1028def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1029 Requires<[FeatureHighWord]>; 1030 1031 1032//===----------------------------------------------------------------------===// 1033// Subtraction 1034//===----------------------------------------------------------------------===// 1035 1036// Subtraction producing a signed overflow flag. 1037let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1038 CCIfNoSignedWrap = 1 in { 1039 // Subtraction of a register. 1040 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1041 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1042 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1043 1044 // Subtraction from a high register. 1045 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1046 Requires<[FeatureHighWord]>; 1047 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1048 Requires<[FeatureHighWord]>; 1049 1050 // Subtraction of memory. 1051 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1052 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1053 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1054 Requires<[FeatureMiscellaneousExtensions2]>; 1055 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1056 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1057} 1058defm : SXB<z_ssub, GR64, SGFR>; 1059 1060// Subtracting an immediate is the same as adding the negated immediate. 1061let AddedComplexity = 1 in { 1062 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1063 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1064 Requires<[FeatureHighWord]>; 1065 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1066 (AFIMux GR32:$src1, simm32n:$src2)>, 1067 Requires<[FeatureHighWord]>; 1068 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1069 (AHI GR32:$src1, imm32sx16n:$src2)>; 1070 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1071 (AFI GR32:$src1, simm32n:$src2)>; 1072 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1073 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1074 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1075 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1076} 1077 1078// And vice versa in one special case, where we need to load a 1079// constant into a register in any case, but the negated constant 1080// requires fewer instructions to load. 1081def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1082 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1083def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1084 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1085 1086// Subtraction producing a carry. 1087let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1088 // Subtraction of a register. 1089 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1090 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1091 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1092 1093 // Subtraction from a high register. 1094 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1095 Requires<[FeatureHighWord]>; 1096 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1097 Requires<[FeatureHighWord]>; 1098 1099 // Subtraction of unsigned 32-bit immediates. 1100 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1101 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1102 1103 // Subtraction of memory. 1104 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1105 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1106 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1107} 1108defm : ZXB<z_usub, GR64, SLGFR>; 1109 1110// Subtracting an immediate is the same as adding the negated immediate. 1111let AddedComplexity = 1 in { 1112 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1113 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1114 Requires<[FeatureDistinctOps]>; 1115 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1116 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1117 Requires<[FeatureDistinctOps]>; 1118} 1119 1120// And vice versa in one special case (but we prefer addition). 1121def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1122 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1123 1124// Subtraction producing and using a carry. 1125let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1126 // Subtraction of a register. 1127 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1128 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1129 1130 // Subtraction of memory. 1131 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1132 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1133} 1134 1135 1136//===----------------------------------------------------------------------===// 1137// AND 1138//===----------------------------------------------------------------------===// 1139 1140let Defs = [CC] in { 1141 // ANDs of a register. 1142 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1143 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1144 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1145 } 1146 1147 let isConvertibleToThreeAddress = 1 in { 1148 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1149 // The CC result only reflects the 16-bit field, not the full register. 1150 // 1151 // NIxMux expands to NI[LH]x, depending on the choice of register. 1152 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1153 Requires<[FeatureHighWord]>; 1154 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1155 Requires<[FeatureHighWord]>; 1156 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1157 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1158 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1159 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1160 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1161 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1162 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1163 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1164 1165 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1166 // The CC result only reflects the 32-bit field, which means we can 1167 // use it as a zero indicator for i32 operations but not otherwise. 1168 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1169 // Expands to NILF or NIHF, depending on the choice of register. 1170 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1171 Requires<[FeatureHighWord]>; 1172 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1173 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1174 } 1175 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1176 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1177 } 1178 1179 // ANDs of memory. 1180 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1181 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1182 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1183 } 1184 1185 // AND to memory 1186 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1187 1188 // Block AND. 1189 let mayLoad = 1, mayStore = 1 in 1190 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1191} 1192defm : RMWIByte<and, bdaddr12pair, NI>; 1193defm : RMWIByte<and, bdaddr20pair, NIY>; 1194 1195//===----------------------------------------------------------------------===// 1196// OR 1197//===----------------------------------------------------------------------===// 1198 1199let Defs = [CC] in { 1200 // ORs of a register. 1201 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1202 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1203 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1204 } 1205 1206 // ORs of a 16-bit immediate, leaving other bits unaffected. 1207 // The CC result only reflects the 16-bit field, not the full register. 1208 // 1209 // OIxMux expands to OI[LH]x, depending on the choice of register. 1210 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1211 Requires<[FeatureHighWord]>; 1212 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1213 Requires<[FeatureHighWord]>; 1214 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1215 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1216 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1217 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1218 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1219 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1220 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1221 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1222 1223 // ORs of a 32-bit immediate, leaving other bits unaffected. 1224 // The CC result only reflects the 32-bit field, which means we can 1225 // use it as a zero indicator for i32 operations but not otherwise. 1226 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1227 // Expands to OILF or OIHF, depending on the choice of register. 1228 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1229 Requires<[FeatureHighWord]>; 1230 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1231 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1232 } 1233 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1234 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1235 1236 // ORs of memory. 1237 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1238 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1239 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1240 } 1241 1242 // OR to memory 1243 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1244 1245 // Block OR. 1246 let mayLoad = 1, mayStore = 1 in 1247 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1248} 1249defm : RMWIByte<or, bdaddr12pair, OI>; 1250defm : RMWIByte<or, bdaddr20pair, OIY>; 1251 1252//===----------------------------------------------------------------------===// 1253// XOR 1254//===----------------------------------------------------------------------===// 1255 1256let Defs = [CC] in { 1257 // XORs of a register. 1258 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1259 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1260 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1261 } 1262 1263 // XORs of a 32-bit immediate, leaving other bits unaffected. 1264 // The CC result only reflects the 32-bit field, which means we can 1265 // use it as a zero indicator for i32 operations but not otherwise. 1266 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1267 // Expands to XILF or XIHF, depending on the choice of register. 1268 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1269 Requires<[FeatureHighWord]>; 1270 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1271 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1272 } 1273 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1274 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1275 1276 // XORs of memory. 1277 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1278 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1279 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1280 } 1281 1282 // XOR to memory 1283 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1284 1285 // Block XOR. 1286 let mayLoad = 1, mayStore = 1 in 1287 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1288} 1289defm : RMWIByte<xor, bdaddr12pair, XI>; 1290defm : RMWIByte<xor, bdaddr20pair, XIY>; 1291 1292//===----------------------------------------------------------------------===// 1293// Combined logical operations 1294//===----------------------------------------------------------------------===// 1295 1296let Predicates = [FeatureMiscellaneousExtensions3], 1297 Defs = [CC] in { 1298 // AND with complement. 1299 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1300 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1301 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1302 } 1303 1304 // OR with complement. 1305 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1306 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1307 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1308 } 1309 1310 // NAND. 1311 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1312 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1313 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1314 } 1315 1316 // NOR. 1317 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1318 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1319 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1320 } 1321 1322 // NXOR. 1323 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1324 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1325 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1326 } 1327} 1328 1329//===----------------------------------------------------------------------===// 1330// Multiplication 1331//===----------------------------------------------------------------------===// 1332 1333// Multiplication of a register, setting the condition code. We prefer these 1334// over MS(G)R if available, even though we cannot use the condition code, 1335// since they are three-operand instructions. 1336let Predicates = [FeatureMiscellaneousExtensions2], 1337 Defs = [CC], isCommutable = 1 in { 1338 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1339 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1340} 1341 1342// Multiplication of a register. 1343let isCommutable = 1 in { 1344 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1345 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1346} 1347def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1348defm : SXB<mul, GR64, MSGFR>; 1349 1350// Multiplication of a signed 16-bit immediate. 1351def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1352def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1353 1354// Multiplication of a signed 32-bit immediate. 1355def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1356def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1357 1358// Multiplication of memory. 1359defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1360defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1361def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1362 Requires<[FeatureMiscellaneousExtensions2]>; 1363def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1364def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1365 1366// Multiplication of memory, setting the condition code. 1367let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1368 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1369 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1370} 1371 1372// Multiplication of a register, producing two results. 1373def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1374def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1375 Requires<[FeatureMiscellaneousExtensions2]>; 1376def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1377def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1378 1379def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1380 (MGRK GR64:$src1, GR64:$src2)>; 1381def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1382 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1383 1384// Multiplication of memory, producing two results. 1385def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1386def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1387def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1388 Requires<[FeatureMiscellaneousExtensions2]>; 1389def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1390def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1391 1392def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1393 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1394def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1395 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1396 1397//===----------------------------------------------------------------------===// 1398// Division and remainder 1399//===----------------------------------------------------------------------===// 1400 1401let hasSideEffects = 1 in { // Do not speculatively execute. 1402 // Division and remainder, from registers. 1403 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1404 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1405 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1406 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1407 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1408 1409 // Division and remainder, from memory. 1410 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1411 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1412 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1413 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1414 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1415} 1416def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1417 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1418def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1419 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1420def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1421 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1422def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1423 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1424 1425def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1426 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1427 subreg_l32)), GR32:$src2)>; 1428def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1429 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1430 subreg_l32)), bdxaddr20only:$src2)>; 1431def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1432 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1433def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1434 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1435 1436//===----------------------------------------------------------------------===// 1437// Shifts 1438//===----------------------------------------------------------------------===// 1439 1440// Logical shift left. 1441defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1442def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1443def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1444 1445// Arithmetic shift left. 1446let Defs = [CC] in { 1447 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1448 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1449 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1450} 1451 1452// Logical shift right. 1453defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1454def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1455def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1456 1457// Arithmetic shift right. 1458let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1459 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1460 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1461 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1462} 1463 1464// Rotate left. 1465def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1466def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1467 1468// Rotate second operand left and inserted selected bits into first operand. 1469// These can act like 32-bit operands provided that the constant start and 1470// end bits (operands 2 and 3) are in the range [32, 64). 1471let Defs = [CC] in { 1472 let isCodeGenOnly = 1 in 1473 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1474 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1475 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1476} 1477 1478// On zEC12 we have a variant of RISBG that does not set CC. 1479let Predicates = [FeatureMiscellaneousExtensions] in 1480 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1481 1482// Forms of RISBG that only affect one word of the destination register. 1483// They do not set CC. 1484let Predicates = [FeatureHighWord] in { 1485 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1486 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1487 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1488 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1489 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1490 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1491 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1492} 1493 1494// Rotate second operand left and perform a logical operation with selected 1495// bits of the first operand. The CC result only describes the selected bits, 1496// so isn't useful for a full comparison against zero. 1497let Defs = [CC] in { 1498 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1499 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1500 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1501} 1502 1503//===----------------------------------------------------------------------===// 1504// Comparison 1505//===----------------------------------------------------------------------===// 1506 1507// Signed comparisons. We put these before the unsigned comparisons because 1508// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1509// of the unsigned forms do. 1510let Defs = [CC], CCValues = 0xE in { 1511 // Comparison with a register. 1512 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1513 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1514 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1515 1516 // Comparison with a high register. 1517 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1518 Requires<[FeatureHighWord]>; 1519 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1520 Requires<[FeatureHighWord]>; 1521 1522 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1523 // depending on the choice of register. 1524 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1525 Requires<[FeatureHighWord]>; 1526 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1527 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1528 1529 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1530 // depending on the choice of register. 1531 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1532 Requires<[FeatureHighWord]>; 1533 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1534 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1535 Requires<[FeatureHighWord]>; 1536 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1537 1538 // Comparison with memory. 1539 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1540 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1541 Requires<[FeatureHighWord]>; 1542 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1543 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1544 Requires<[FeatureHighWord]>; 1545 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1546 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1547 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1548 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1549 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1550 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1551 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1552 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1553 1554 // Comparison between memory and a signed 16-bit immediate. 1555 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1556 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1557 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1558} 1559defm : SXB<z_scmp, GR64, CGFR>; 1560 1561// Unsigned comparisons. 1562let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1563 // Comparison with a register. 1564 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1565 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1566 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1567 1568 // Comparison with a high register. 1569 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1570 Requires<[FeatureHighWord]>; 1571 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1572 Requires<[FeatureHighWord]>; 1573 1574 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1575 // or CLIH, depending on the choice of register. 1576 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1577 Requires<[FeatureHighWord]>; 1578 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1579 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1580 Requires<[FeatureHighWord]>; 1581 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1582 1583 // Comparison with memory. 1584 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1585 Requires<[FeatureHighWord]>; 1586 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1587 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1588 Requires<[FeatureHighWord]>; 1589 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1590 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1591 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1592 aligned_azextloadi16>; 1593 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1594 aligned_load>; 1595 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1596 aligned_azextloadi16>; 1597 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1598 aligned_azextloadi32>; 1599 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1600 aligned_load>; 1601 1602 // Comparison between memory and an unsigned 8-bit immediate. 1603 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1604 1605 // Comparison between memory and an unsigned 16-bit immediate. 1606 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1607 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1608 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1609} 1610defm : ZXB<z_ucmp, GR64, CLGFR>; 1611 1612// Memory-to-memory comparison. 1613let mayLoad = 1, Defs = [CC] in { 1614 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1615 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1616 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1617 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1618} 1619 1620// String comparison. 1621let mayLoad = 1, Defs = [CC] in 1622 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1623 1624// Test under mask. 1625let Defs = [CC] in { 1626 // TMxMux expands to TM[LH]x, depending on the choice of register. 1627 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1628 Requires<[FeatureHighWord]>; 1629 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1630 Requires<[FeatureHighWord]>; 1631 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1632 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1633 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1634 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1635 1636 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1637 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1638 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1639 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1640 1641 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1642} 1643 1644def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1645def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1646 1647// Compare logical characters under mask -- not (yet) used for codegen. 1648let Defs = [CC] in { 1649 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1650 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1651} 1652 1653//===----------------------------------------------------------------------===// 1654// Prefetch and execution hint 1655//===----------------------------------------------------------------------===// 1656 1657let mayLoad = 1, mayStore = 1 in { 1658 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1659 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1660} 1661 1662let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1663 // Branch Prediction Preload 1664 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1665 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1666 1667 // Next Instruction Access Intent 1668 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1669} 1670 1671//===----------------------------------------------------------------------===// 1672// Atomic operations 1673//===----------------------------------------------------------------------===// 1674 1675// A serialization instruction that acts as a barrier for all memory 1676// accesses, which expands to "bcr 14, 0". 1677let hasSideEffects = 1 in 1678def Serialize : Alias<2, (outs), (ins), []>; 1679 1680// A pseudo instruction that serves as a compiler barrier. 1681let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1682def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1683 1684let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1685 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1686 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1687 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1688 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1689 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1690 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1691 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1692 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1693 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1694 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1695} 1696 1697def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1698def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1699def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1700 1701def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1702def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1703let Predicates = [FeatureNoInterlockedAccess1] in { 1704 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1705 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1706 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1707 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1708 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1709 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1710} 1711 1712def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1713def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1714def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1715 1716def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1717def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1718let Predicates = [FeatureNoInterlockedAccess1] in { 1719 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1720 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1721 imm32ll16c>; 1722 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1723 imm32lh16c>; 1724 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1725 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1726 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1727 imm64ll16c>; 1728 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1729 imm64lh16c>; 1730 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1731 imm64hl16c>; 1732 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1733 imm64hh16c>; 1734 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1735 imm64lf32c>; 1736 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1737 imm64hf32c>; 1738} 1739 1740def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1741def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1742let Predicates = [FeatureNoInterlockedAccess1] in { 1743 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1744 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1745 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1746 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1747 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1748 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1749 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1750 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1751 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1752 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1753 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1754} 1755 1756def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1757def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1758let Predicates = [FeatureNoInterlockedAccess1] in { 1759 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1760 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1761 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1762 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1763 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1764} 1765 1766def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1767def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1768 imm32lh16c>; 1769def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1770def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1771 imm32ll16c>; 1772def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1773 imm32lh16c>; 1774def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1775def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1776def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1777 imm64ll16c>; 1778def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1779 imm64lh16c>; 1780def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1781 imm64hl16c>; 1782def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1783 imm64hh16c>; 1784def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1785 imm64lf32c>; 1786def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1787 imm64hf32c>; 1788 1789def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1790def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1791def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1792 1793def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1794def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1795def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1796 1797def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1798def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1799def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1800 1801def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1802def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1803def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1804 1805def ATOMIC_CMP_SWAPW 1806 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1807 ADDR32:$bitshift, ADDR32:$negbitshift, 1808 uimm32:$bitsize), 1809 [(set GR32:$dst, 1810 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1811 ADDR32:$bitshift, ADDR32:$negbitshift, 1812 uimm32:$bitsize))]> { 1813 let Defs = [CC]; 1814 let mayLoad = 1; 1815 let mayStore = 1; 1816 let usesCustomInserter = 1; 1817 let hasNoSchedulingInfo = 1; 1818} 1819 1820// Test and set. 1821let mayLoad = 1, Defs = [CC] in 1822 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1823 1824// Compare and swap. 1825let Defs = [CC] in { 1826 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1827 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1828} 1829 1830// Compare double and swap. 1831let Defs = [CC] in { 1832 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1833 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1834} 1835 1836// Compare and swap and store. 1837let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1838 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1839 1840// Perform locked operation. 1841let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1842 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1843 1844// Load/store pair from/to quadword. 1845def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1846def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1847 1848// Load pair disjoint. 1849let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1850 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1851 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1852} 1853 1854//===----------------------------------------------------------------------===// 1855// Translate and convert 1856//===----------------------------------------------------------------------===// 1857 1858let mayLoad = 1, mayStore = 1 in 1859 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1860 1861let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1862 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1863 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1864} 1865 1866let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1867 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1868 1869let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1870 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1871 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1872} 1873 1874let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1875 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1876 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1877 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1878 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1879} 1880 1881let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1882 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1883 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1884 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1885 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1886 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1887 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1888 1889 let isAsmParserOnly = 1 in { 1890 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1891 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1892 } 1893} 1894 1895//===----------------------------------------------------------------------===// 1896// Message-security assist 1897//===----------------------------------------------------------------------===// 1898 1899let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1900 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1901 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1902 1903 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1904 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1905 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1906 1907 let Predicates = [FeatureMessageSecurityAssist4] in { 1908 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1909 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1910 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1911 GR128, GR128, GR128>; 1912 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1913 } 1914 1915 let Predicates = [FeatureMessageSecurityAssist5] in 1916 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1917 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1918 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1919 1920 let Predicates = [FeatureMessageSecurityAssist8] in 1921 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1922 GR128, GR128, GR128>; 1923 1924 let Predicates = [FeatureMessageSecurityAssist9] in 1925 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1926} 1927 1928//===----------------------------------------------------------------------===// 1929// Guarded storage 1930//===----------------------------------------------------------------------===// 1931 1932// These instructions use and/or modify the guarded storage control 1933// registers, which we do not otherwise model, so they should have 1934// hasSideEffects. 1935let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1936 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1937 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1938 1939 let mayLoad = 1 in 1940 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1941 let mayStore = 1 in 1942 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1943} 1944 1945//===----------------------------------------------------------------------===// 1946// Decimal arithmetic 1947//===----------------------------------------------------------------------===// 1948 1949defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1950def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1951 1952defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1953def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1954 1955let mayLoad = 1, mayStore = 1 in { 1956 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1957 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1958 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1959 1960 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1961 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1962 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1963 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1964 let Defs = [CC] in { 1965 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1966 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1967 } 1968} 1969 1970let mayLoad = 1, mayStore = 1 in { 1971 let Defs = [CC] in { 1972 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1973 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1974 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1975 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1976 } 1977 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1978 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1979 let Defs = [CC] in { 1980 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1981 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1982 } 1983} 1984 1985let Defs = [CC] in { 1986 def CP : CompareSSb<"cp", 0xF9>; 1987 def TP : TestRSL<"tp", 0xEBC0>; 1988} 1989 1990//===----------------------------------------------------------------------===// 1991// Access registers 1992//===----------------------------------------------------------------------===// 1993 1994// Read a 32-bit access register into a GR32. As with all GR32 operations, 1995// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1996// when a 64-bit address is stored in a pair of access registers. 1997def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1998 1999// Set access register. 2000def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 2001 2002// Copy access register. 2003def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2004 2005// Load address extended. 2006defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2007 2008// Load access multiple. 2009defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2010 2011// Store access multiple. 2012defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2013 2014//===----------------------------------------------------------------------===// 2015// Program mask and addressing mode 2016//===----------------------------------------------------------------------===// 2017 2018// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2019let Uses = [CC] in 2020 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2021 2022// Set CC and program mask from a register. 2023let hasSideEffects = 1, Defs = [CC] in 2024 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2025 2026// Branch and link - like BAS, but also extracts CC and program mask. 2027let isCall = 1, Uses = [CC], Defs = [CC] in { 2028 def BAL : CallRX<"bal", 0x45>; 2029 def BALR : CallRR<"balr", 0x05>; 2030} 2031 2032// Test addressing mode. 2033let Defs = [CC] in 2034 def TAM : SideEffectInherentE<"tam", 0x010B>; 2035 2036// Set addressing mode. 2037let hasSideEffects = 1 in { 2038 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2039 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2040 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2041} 2042 2043// Branch and set mode. Not really a call, but also sets an output register. 2044let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2045 def BSM : CallRR<"bsm", 0x0B>; 2046 2047// Branch and save and set mode. 2048let isCall = 1, Defs = [CC] in 2049 def BASSM : CallRR<"bassm", 0x0C>; 2050 2051//===----------------------------------------------------------------------===// 2052// Transactional execution 2053//===----------------------------------------------------------------------===// 2054 2055let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2056 // Transaction Begin 2057 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2058 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2059 let hasNoSchedulingInfo = 1 in 2060 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2061 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2062 int_s390_tbeginc, imm32zx16>; 2063 } 2064 2065 // Transaction End 2066 let Defs = [CC] in 2067 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2068 2069 // Transaction Abort 2070 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2071 hasSideEffects = 1 in 2072 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2073 2074 // Nontransactional Store 2075 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2076 2077 // Extract Transaction Nesting Depth 2078 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2079} 2080 2081//===----------------------------------------------------------------------===// 2082// Processor assist 2083//===----------------------------------------------------------------------===// 2084 2085let Predicates = [FeatureProcessorAssist] in { 2086 let hasSideEffects = 1 in 2087 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2088 def : Pat<(int_s390_ppa_txassist GR32:$src), 2089 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2090 zero_reg, 1)>; 2091} 2092 2093//===----------------------------------------------------------------------===// 2094// Miscellaneous Instructions. 2095//===----------------------------------------------------------------------===// 2096 2097// Find leftmost one, AKA count leading zeros. The instruction actually 2098// returns a pair of GR64s, the first giving the number of leading zeros 2099// and the second giving a copy of the source with the leftmost one bit 2100// cleared. We only use the first result here. 2101let Defs = [CC] in 2102 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2103def : Pat<(i64 (ctlz GR64:$src)), 2104 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2105 2106// Population count. Counts bits set per byte or doubleword. 2107let Predicates = [FeatureMiscellaneousExtensions3] in { 2108 let Defs = [CC] in 2109 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2110 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2111} 2112let Predicates = [FeaturePopulationCount], Defs = [CC] in 2113 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2114 2115// Search a block of memory for a character. 2116let mayLoad = 1, Defs = [CC] in 2117 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2118let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2119 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2120 2121// Compare until substring equal. 2122let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2123 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2124 2125// Compare and form codeword. 2126let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2127 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2128 2129// Update tree. 2130let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2131 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2132 def UPT : SideEffectInherentE<"upt", 0x0102>; 2133 2134// Checksum. 2135let mayLoad = 1, Defs = [CC] in 2136 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2137 2138// Compression call. 2139let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2140 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2141 2142// Sort lists. 2143let Predicates = [FeatureEnhancedSort], 2144 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2145 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2146 2147// Deflate conversion call. 2148let Predicates = [FeatureDeflateConversion], 2149 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2150 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2151 GR128, GR128, GR64>; 2152 2153// Execute. 2154let hasSideEffects = 1 in { 2155 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2156 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2157} 2158 2159//===----------------------------------------------------------------------===// 2160// .insn directive instructions 2161//===----------------------------------------------------------------------===// 2162 2163let isCodeGenOnly = 1, hasSideEffects = 1 in { 2164 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2165 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2166 imm32sx16:$I2), 2167 ".insn ri,$enc,$R1,$I2", []>; 2168 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2169 AnyReg:$R3, brtarget16:$I2), 2170 ".insn rie,$enc,$R1,$R3,$I2", []>; 2171 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2172 brtarget32:$I2), 2173 ".insn ril,$enc,$R1,$I2", []>; 2174 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2175 uimm32:$I2), 2176 ".insn rilu,$enc,$R1,$I2", []>; 2177 def InsnRIS : DirectiveInsnRIS<(outs), 2178 (ins imm64zx48:$enc, AnyReg:$R1, 2179 imm32sx8:$I2, imm32zx4:$M3, 2180 bdaddr12only:$BD4), 2181 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2182 def InsnRR : DirectiveInsnRR<(outs), 2183 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2184 ".insn rr,$enc,$R1,$R2", []>; 2185 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2186 AnyReg:$R1, AnyReg:$R2), 2187 ".insn rre,$enc,$R1,$R2", []>; 2188 def InsnRRF : DirectiveInsnRRF<(outs), 2189 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2190 AnyReg:$R3, imm32zx4:$M4), 2191 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2192 def InsnRRS : DirectiveInsnRRS<(outs), 2193 (ins imm64zx48:$enc, AnyReg:$R1, 2194 AnyReg:$R2, imm32zx4:$M3, 2195 bdaddr12only:$BD4), 2196 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2197 def InsnRS : DirectiveInsnRS<(outs), 2198 (ins imm64zx32:$enc, AnyReg:$R1, 2199 AnyReg:$R3, bdaddr12only:$BD2), 2200 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2201 def InsnRSE : DirectiveInsnRSE<(outs), 2202 (ins imm64zx48:$enc, AnyReg:$R1, 2203 AnyReg:$R3, bdaddr12only:$BD2), 2204 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2205 def InsnRSI : DirectiveInsnRSI<(outs), 2206 (ins imm64zx48:$enc, AnyReg:$R1, 2207 AnyReg:$R3, brtarget16:$RI2), 2208 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2209 def InsnRSY : DirectiveInsnRSY<(outs), 2210 (ins imm64zx48:$enc, AnyReg:$R1, 2211 AnyReg:$R3, bdaddr20only:$BD2), 2212 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2213 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2214 bdxaddr12only:$XBD2), 2215 ".insn rx,$enc,$R1,$XBD2", []>; 2216 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2217 bdxaddr12only:$XBD2), 2218 ".insn rxe,$enc,$R1,$XBD2", []>; 2219 def InsnRXF : DirectiveInsnRXF<(outs), 2220 (ins imm64zx48:$enc, AnyReg:$R1, 2221 AnyReg:$R3, bdxaddr12only:$XBD2), 2222 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2223 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2224 bdxaddr20only:$XBD2), 2225 ".insn rxy,$enc,$R1,$XBD2", []>; 2226 def InsnS : DirectiveInsnS<(outs), 2227 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2228 ".insn s,$enc,$BD2", []>; 2229 def InsnSI : DirectiveInsnSI<(outs), 2230 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2231 imm32sx8:$I2), 2232 ".insn si,$enc,$BD1,$I2", []>; 2233 def InsnSIY : DirectiveInsnSIY<(outs), 2234 (ins imm64zx48:$enc, 2235 bdaddr20only:$BD1, imm32zx8:$I2), 2236 ".insn siy,$enc,$BD1,$I2", []>; 2237 def InsnSIL : DirectiveInsnSIL<(outs), 2238 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2239 imm32zx16:$I2), 2240 ".insn sil,$enc,$BD1,$I2", []>; 2241 def InsnSS : DirectiveInsnSS<(outs), 2242 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2243 bdaddr12only:$BD2, AnyReg:$R3), 2244 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2245 def InsnSSE : DirectiveInsnSSE<(outs), 2246 (ins imm64zx48:$enc, 2247 bdaddr12only:$BD1,bdaddr12only:$BD2), 2248 ".insn sse,$enc,$BD1,$BD2", []>; 2249 def InsnSSF : DirectiveInsnSSF<(outs), 2250 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2251 bdaddr12only:$BD2, AnyReg:$R3), 2252 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2253 def InsnVRI : DirectiveInsnVRI<(outs), 2254 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2255 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2256 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2257 def InsnVRR : DirectiveInsnVRR<(outs), 2258 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2259 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2260 imm32zx4:$M6), 2261 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2262 def InsnVRS : DirectiveInsnVRS<(outs), 2263 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2264 bdaddr12only:$BD2, imm32zx4:$M4), 2265 ".insn vrs,$enc,$BD2,$M4", []>; 2266 def InsnVRV : DirectiveInsnVRV<(outs), 2267 (ins imm64zx48:$enc, VR128:$V1, 2268 bdvaddr12only:$VBD2, imm32zx4:$M3), 2269 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2270 def InsnVRX : DirectiveInsnVRX<(outs), 2271 (ins imm64zx48:$enc, VR128:$V1, 2272 bdxaddr12only:$XBD2, imm32zx4:$M3), 2273 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2274 def InsnVSI : DirectiveInsnVSI<(outs), 2275 (ins imm64zx48:$enc, VR128:$V1, 2276 bdaddr12only:$BD2, imm32zx8:$I3), 2277 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2278} 2279 2280//===----------------------------------------------------------------------===// 2281// Peepholes. 2282//===----------------------------------------------------------------------===// 2283 2284// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2285// equivalent to (and (xor x, -1), y) 2286def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2287 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2288 2289// Shift/rotate instructions only use the last 6 bits of the second operand 2290// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2291// last 16 bits. 2292// Complexity is added so that we match this before we match NILF on the AND 2293// operation alone. 2294let AddedComplexity = 4 in { 2295 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2296 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2297 2298 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2299 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2300 2301 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2302 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2303 2304 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2305 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2306 2307 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2308 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2309 2310 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2311 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2312 2313 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2314 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2315 2316 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2317 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2318} 2319 2320// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2321// use the last 6 bits of the second operand register (making it modulo 64). 2322let AddedComplexity = 4 in { 2323 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2324 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2325 2326 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2327 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2328 2329 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2330 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2331 2332 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2333 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2334} 2335 2336// Peepholes for turning scalar operations into block operations. 2337defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2338 XCSequence, 1>; 2339defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2340 XCSequence, 2>; 2341defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2342 XCSequence, 4>; 2343defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2344 OCSequence, XCSequence, 1>; 2345defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2346 XCSequence, 2>; 2347defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2348 XCSequence, 4>; 2349defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2350 XCSequence, 8>; 2351 2352//===----------------------------------------------------------------------===// 2353// Mnemonic Aliases 2354//===----------------------------------------------------------------------===// 2355 2356def JCT : MnemonicAlias<"jct", "brct">; 2357def JCTG : MnemonicAlias<"jctg", "brctg">; 2358def JAS : MnemonicAlias<"jas", "bras">; 2359def JASL : MnemonicAlias<"jasl", "brasl">; 2360def JXH : MnemonicAlias<"jxh", "brxh">; 2361def JXLE : MnemonicAlias<"jxle", "brxle">; 2362def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2363def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2364 2365def BRU : MnemonicAlias<"bru", "j">; 2366def BRUL : MnemonicAlias<"brul", "jg">; 2367 2368foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2369 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2370 def BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2371 def BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#">; 2372} 2373