1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14let hasNoSchedulingInfo = 1 in { 15 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 16 [(callseq_start timm:$amt)]>; 17 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_end timm:$amt1, timm:$amt2)]>; 19} 20 21let hasSideEffects = 0 in { 22 // Takes as input the value of the stack pointer after a dynamic allocation 23 // has been made. Sets the output to the address of the dynamically- 24 // allocated area itself, skipping the outgoing arguments. 25 // 26 // This expands to an LA or LAY instruction. We restrict the offset 27 // to the range of LA and keep the LAY range in reserve for when 28 // the size of the outgoing arguments is added. 29 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31} 32 33//===----------------------------------------------------------------------===// 34// Control flow instructions 35//===----------------------------------------------------------------------===// 36 37// A return instruction (br %r14). 38let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 39 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 40 41// A conditional return instruction (bcr <cond>, %r14). 42let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 43 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 44 45// Fused compare and conditional returns. 46let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 47 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 48 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 49 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 50 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 51 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 52 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 53 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 54 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 55} 56 57// Unconditional branches. R1 is the condition-code mask (all 1s). 58let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { 59 let isIndirectBranch = 1 in 60 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), 61 "br\t$R2", [(brind ADDR64:$R2)]>; 62 63 // An assembler extended mnemonic for BRC. 64 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", 65 [(br bb:$I2)]>; 66 67 // An assembler extended mnemonic for BRCL. (The extension is "G" 68 // rather than "L" because "JL" is "Jump if Less".) 69 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>; 70} 71 72// FIXME: This trap instruction should be marked as isTerminator, but there is 73// currently a general bug that allows non-terminators to be placed between 74// terminators. Temporarily leave this unmarked until the bug is fixed. 75let isBarrier = 1, hasCtrlDep = 1 in { 76 def Trap : Alias<4, (outs), (ins), [(trap)]>; 77} 78 79let isTerminator = 1, hasCtrlDep = 1, Uses = [CC] in { 80 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 81} 82 83// Conditional branches. It's easier for LLVM to handle these branches 84// in their raw BRC/BRCL form, with the 4-bit condition-code mask being 85// the first operand. It seems friendlier to use mnemonic forms like 86// JE and JLH when writing out the assembly though. 87let isBranch = 1, isTerminator = 1, Uses = [CC] in { 88 let isCodeGenOnly = 1, CCMaskFirst = 1 in { 89 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1, 90 brtarget16:$I2), "j$R1\t$I2", 91 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>; 92 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1, 93 brtarget32:$I2), "jg$R1\t$I2", []>; 94 let isIndirectBranch = 1 in 95 def BCR : InstRR<0x07, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2), 96 "b${R1}r\t$R2", []>; 97 } 98 def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2), 99 "brc\t$R1, $I2", []>; 100 def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2), 101 "brcl\t$R1, $I2", []>; 102 let isIndirectBranch = 1 in { 103 def AsmBC : InstRX<0x47, (outs), (ins imm32zx4:$R1, bdxaddr12only:$XBD2), 104 "bc\t$R1, $XBD2", []>; 105 def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2), 106 "bcr\t$R1, $R2", []>; 107 } 108} 109 110def AsmNop : InstAlias<"nop\t$XBD", (AsmBC 0, bdxaddr12only:$XBD), 0>; 111def AsmNopR : InstAlias<"nopr\t$R", (AsmBCR 0, GR64:$R), 0>; 112 113// Fused compare-and-branch instructions. As for normal branches, 114// we handle these instructions internally in their raw CRJ-like form, 115// but use assembly macros like CRJE when writing them out. 116// 117// These instructions do not use or clobber the condition codes. 118// We nevertheless pretend that they clobber CC, so that we can lower 119// them to separate comparisons and BRCLs if the branch ends up being 120// out of range. 121multiclass CompareBranches<Operand ccmask, string pos1, string pos2> { 122 let isBranch = 1, isTerminator = 1, Defs = [CC] in { 123 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 124 brtarget16:$RI4), 125 "crj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 126 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 127 brtarget16:$RI4), 128 "cgrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 129 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 130 brtarget16:$RI4), 131 "cij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 132 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 133 brtarget16:$RI4), 134 "cgij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 135 def LRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 136 brtarget16:$RI4), 137 "clrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 138 def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 139 brtarget16:$RI4), 140 "clgrj"##pos1##"\t$R1, $R2"##pos2##", $RI4", []>; 141 def LIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3, 142 brtarget16:$RI4), 143 "clij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 144 def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3, 145 brtarget16:$RI4), 146 "clgij"##pos1##"\t$R1, $I2"##pos2##", $RI4", []>; 147 let isIndirectBranch = 1 in { 148 def RB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 149 bdaddr12only:$BD4), 150 "crb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 151 def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 152 bdaddr12only:$BD4), 153 "cgrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 154 def IB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 155 bdaddr12only:$BD4), 156 "cib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 157 def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 158 bdaddr12only:$BD4), 159 "cgib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 160 def LRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 161 bdaddr12only:$BD4), 162 "clrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 163 def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 164 bdaddr12only:$BD4), 165 "clgrb"##pos1##"\t$R1, $R2"##pos2##", $BD4", []>; 166 def LIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3, 167 bdaddr12only:$BD4), 168 "clib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 169 def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3, 170 bdaddr12only:$BD4), 171 "clgib"##pos1##"\t$R1, $I2"##pos2##", $BD4", []>; 172 } 173 } 174 175 let isTerminator = 1, hasCtrlDep = 1 in { 176 def RT : InstRRFc<0xB972, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3), 177 "crt"##pos1##"\t$R1, $R2"##pos2, []>; 178 def GRT : InstRRFc<0xB960, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3), 179 "cgrt"##pos1##"\t$R1, $R2"##pos2, []>; 180 def LRT : InstRRFc<0xB973, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3), 181 "clrt"##pos1##"\t$R1, $R2"##pos2, []>; 182 def LGRT : InstRRFc<0xB961, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3), 183 "clgrt"##pos1##"\t$R1, $R2"##pos2, []>; 184 def IT : InstRIEa<0xEC72, (outs), (ins GR32:$R1, imm32sx16:$I2, ccmask:$M3), 185 "cit"##pos1##"\t$R1, $I2"##pos2, []>; 186 def GIT : InstRIEa<0xEC70, (outs), (ins GR64:$R1, imm32sx16:$I2, ccmask:$M3), 187 "cgit"##pos1##"\t$R1, $I2"##pos2, []>; 188 def LFIT : InstRIEa<0xEC73, (outs), (ins GR32:$R1, imm32zx16:$I2, ccmask:$M3), 189 "clfit"##pos1##"\t$R1, $I2"##pos2, []>; 190 def LGIT : InstRIEa<0xEC71, (outs), (ins GR64:$R1, imm32zx16:$I2, ccmask:$M3), 191 "clgit"##pos1##"\t$R1, $I2"##pos2, []>; 192 } 193} 194let isCodeGenOnly = 1 in 195 defm C : CompareBranches<cond4, "$M3", "">; 196defm AsmC : CompareBranches<imm32zx4, "", ", $M3">; 197 198// Define AsmParser mnemonics for each general condition-code mask 199// (integer or floating-point) 200multiclass CondExtendedMnemonicA<bits<4> ccmask, string name> { 201 let isBranch = 1, isTerminator = 1, R1 = ccmask in { 202 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), 203 "j"##name##"\t$I2", []>; 204 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), 205 "jg"##name##"\t$I2", []>; 206 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>; 207 } 208 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>; 209 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>; 210 def LOCHI : FixedCondUnaryRIE<"lochi"##name, 0xEC42, GR64, imm32sx16, 211 ccmask>; 212 def LOCGHI: FixedCondUnaryRIE<"locghi"##name, 0xEC46, GR64, imm64sx16, 213 ccmask>; 214 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>; 215 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>; 216 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>; 217 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>; 218} 219 220multiclass CondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 221 : CondExtendedMnemonicA<ccmask, name1> { 222 let isAsmParserOnly = 1 in 223 defm Alt : CondExtendedMnemonicA<ccmask, name2>; 224} 225 226defm AsmO : CondExtendedMnemonicA<1, "o">; 227defm AsmH : CondExtendedMnemonic<2, "h", "p">; 228defm AsmNLE : CondExtendedMnemonicA<3, "nle">; 229defm AsmL : CondExtendedMnemonic<4, "l", "m">; 230defm AsmNHE : CondExtendedMnemonicA<5, "nhe">; 231defm AsmLH : CondExtendedMnemonicA<6, "lh">; 232defm AsmNE : CondExtendedMnemonic<7, "ne", "nz">; 233defm AsmE : CondExtendedMnemonic<8, "e", "z">; 234defm AsmNLH : CondExtendedMnemonicA<9, "nlh">; 235defm AsmHE : CondExtendedMnemonicA<10, "he">; 236defm AsmNL : CondExtendedMnemonic<11, "nl", "nm">; 237defm AsmLE : CondExtendedMnemonicA<12, "le">; 238defm AsmNH : CondExtendedMnemonic<13, "nh", "np">; 239defm AsmNO : CondExtendedMnemonicA<14, "no">; 240 241// Define AsmParser mnemonics for each integer condition-code mask. 242// This is like the list above, except that condition 3 is not possible 243// and that the low bit of the mask is therefore always 0. This means 244// that each condition has two names. Conditions "o" and "no" are not used. 245// 246// We don't make one of the two names an alias of the other because 247// we need the custom parsing routines to select the correct register class. 248multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> { 249 let isBranch = 1, isTerminator = 1, M3 = ccmask in { 250 def CRJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, 251 brtarget16:$RI4), 252 "crj"##name##"\t$R1, $R2, $RI4", []>; 253 def CGRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, 254 brtarget16:$RI4), 255 "cgrj"##name##"\t$R1, $R2, $RI4", []>; 256 def CIJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, 257 brtarget16:$RI4), 258 "cij"##name##"\t$R1, $I2, $RI4", []>; 259 def CGIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, 260 brtarget16:$RI4), 261 "cgij"##name##"\t$R1, $I2, $RI4", []>; 262 def CLRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, 263 brtarget16:$RI4), 264 "clrj"##name##"\t$R1, $R2, $RI4", []>; 265 def CLGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, 266 brtarget16:$RI4), 267 "clgrj"##name##"\t$R1, $R2, $RI4", []>; 268 def CLIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, 269 brtarget16:$RI4), 270 "clij"##name##"\t$R1, $I2, $RI4", []>; 271 def CLGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, 272 brtarget16:$RI4), 273 "clgij"##name##"\t$R1, $I2, $RI4", []>; 274 let isIndirectBranch = 1 in { 275 def CRB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, 276 bdaddr12only:$BD4), 277 "crb"##name##"\t$R1, $R2, $BD4", []>; 278 def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, 279 bdaddr12only:$BD4), 280 "cgrb"##name##"\t$R1, $R2, $BD4", []>; 281 def CIB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, 282 bdaddr12only:$BD4), 283 "cib"##name##"\t$R1, $I2, $BD4", []>; 284 def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, 285 bdaddr12only:$BD4), 286 "cgib"##name##"\t$R1, $I2, $BD4", []>; 287 def CLRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, 288 bdaddr12only:$BD4), 289 "clrb"##name##"\t$R1, $R2, $BD4", []>; 290 def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, 291 bdaddr12only:$BD4), 292 "clgrb"##name##"\t$R1, $R2, $BD4", []>; 293 def CLIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, 294 bdaddr12only:$BD4), 295 "clib"##name##"\t$R1, $I2, $BD4", []>; 296 def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, 297 bdaddr12only:$BD4), 298 "clgib"##name##"\t$R1, $I2, $BD4", []>; 299 } 300 } 301 302 let hasCtrlDep = 1, isTerminator = 1, M3 = ccmask in { 303 def CRT : InstRRFc<0xB972, (outs), (ins GR32:$R1, GR32:$R2), 304 "crt"##name##"\t$R1, $R2", []>; 305 def CGRT : InstRRFc<0xB960, (outs), (ins GR64:$R1, GR64:$R2), 306 "cgrt"##name##"\t$R1, $R2", []>; 307 def CLRT : InstRRFc<0xB973, (outs), (ins GR32:$R1, GR32:$R2), 308 "clrt"##name##"\t$R1, $R2", []>; 309 def CLGRT : InstRRFc<0xB961, (outs), (ins GR64:$R1, GR64:$R2), 310 "clgrt"##name##"\t$R1, $R2", []>; 311 def CIT : InstRIEa<0xEC72, (outs), (ins GR32:$R1, imm32sx16:$I2), 312 "cit"##name##"\t$R1, $I2", []>; 313 def CGIT : InstRIEa<0xEC70, (outs), (ins GR64:$R1, imm32sx16:$I2), 314 "cgit"##name##"\t$R1, $I2", []>; 315 def CLFIT : InstRIEa<0xEC73, (outs), (ins GR32:$R1, imm32zx16:$I2), 316 "clfit"##name##"\t$R1, $I2", []>; 317 def CLGIT : InstRIEa<0xEC71, (outs), (ins GR64:$R1, imm32zx16:$I2), 318 "clgit"##name##"\t$R1, $I2", []>; 319 } 320} 321multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 322 : IntCondExtendedMnemonicA<ccmask, name1> { 323 let isAsmParserOnly = 1 in 324 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>; 325} 326defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">; 327defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">; 328defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">; 329defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">; 330defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">; 331defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">; 332 333// Decrement a register and branch if it is nonzero. These don't clobber CC, 334// but we might need to split long branches into sequences that do. 335let Defs = [CC] in { 336 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 337 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 338} 339 340def BRXH : BranchBinaryRSI<"brxh", 0x84, GR64>; 341def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR64>; 342 343//===----------------------------------------------------------------------===// 344// Select instructions 345//===----------------------------------------------------------------------===// 346 347def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>; 348def Select32 : SelectWrapper<GR32>; 349def Select64 : SelectWrapper<GR64>; 350 351// We don't define 32-bit Mux stores because the low-only STOC should 352// always be used if possible. 353defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 354 nonvolatile_anyextloadi8, bdxaddr20only>, 355 Requires<[FeatureHighWord]>; 356defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 357 nonvolatile_anyextloadi16, bdxaddr20only>, 358 Requires<[FeatureHighWord]>; 359defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 360 nonvolatile_anyextloadi8, bdxaddr20only>; 361defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 362 nonvolatile_anyextloadi16, bdxaddr20only>; 363defm CondStore32 : CondStores<GR32, nonvolatile_store, 364 nonvolatile_load, bdxaddr20only>; 365 366defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 367 nonvolatile_anyextloadi8, bdxaddr20only>; 368defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 369 nonvolatile_anyextloadi16, bdxaddr20only>; 370defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 371 nonvolatile_anyextloadi32, bdxaddr20only>; 372defm CondStore64 : CondStores<GR64, nonvolatile_store, 373 nonvolatile_load, bdxaddr20only>; 374 375//===----------------------------------------------------------------------===// 376// Call instructions 377//===----------------------------------------------------------------------===// 378 379let isCall = 1, Defs = [R14D, CC] in { 380 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 381 [(z_call pcrel32:$I2)]>; 382 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 383 [(z_call ADDR64:$R2)]>; 384} 385 386// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 387// are argument registers and since branching to R0 is a no-op. 388let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 389 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 390 [(z_sibcall pcrel32:$I2)]>; 391 let Uses = [R1D] in 392 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 393} 394 395let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 396 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 397 pcrel32:$I2), []>; 398 399 let Uses = [R1D] in 400 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 401} 402 403// Fused compare and conditional sibling calls. 404let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 405 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 406 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 407 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 408 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 409 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 410 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 411 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 412 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 413} 414 415// TLS calls. These will be lowered into a call to __tls_get_offset, 416// with an extra relocation specifying the TLS symbol. 417let isCall = 1, Defs = [R14D, CC] in { 418 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 419 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 420 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 421 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 422} 423 424// Define the general form of the call instructions for the asm parser. 425// These instructions don't hard-code %r14 as the return address register. 426// Allow an optional TLS marker symbol to generate TLS call relocations. 427let isCall = 1, Defs = [CC] in { 428 def BRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16tls:$I2), 429 "bras\t$R1, $I2", []>; 430 def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32tls:$I2), 431 "brasl\t$R1, $I2", []>; 432 def BASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), 433 "basr\t$R1, $R2", []>; 434} 435 436//===----------------------------------------------------------------------===// 437// Move instructions 438//===----------------------------------------------------------------------===// 439 440// Register moves. 441let hasSideEffects = 0 in { 442 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 443 def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>, 444 Requires<[FeatureHighWord]>; 445 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>; 446 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>; 447} 448let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 449 def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>; 450 def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>; 451} 452 453// Move on condition. 454let isCodeGenOnly = 1, Uses = [CC] in { 455 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 456 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 457} 458let Uses = [CC] in { 459 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 460 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 461} 462let isCodeGenOnly = 1, Uses = [CC] in { 463 def LOCHI : CondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>; 464 def LOCGHI : CondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>; 465} 466let Uses = [CC] in { 467 def AsmLOCHI : AsmCondUnaryRIE<"lochi", 0xEC42, GR32, imm32sx16>; 468 def AsmLOCGHI : AsmCondUnaryRIE<"locghi", 0xEC46, GR64, imm64sx16>; 469} 470 471// Immediate moves. 472let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 473 isReMaterializable = 1 in { 474 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 475 // deopending on the choice of register. 476 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 477 Requires<[FeatureHighWord]>; 478 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 479 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 480 481 // Other 16-bit immediates. 482 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 483 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 484 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 485 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 486 487 // 32-bit immediates. 488 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 489 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 490 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 491} 492 493// Register loads. 494let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 495 // Expands to L, LY or LFH, depending on the choice of register. 496 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 497 Requires<[FeatureHighWord]>; 498 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 499 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 500 Requires<[FeatureHighWord]>; 501 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 502 503 // These instructions are split after register allocation, so we don't 504 // want a custom inserter. 505 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 506 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 507 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 508 } 509} 510let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 511 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 512 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 513} 514 515let canFoldAsLoad = 1 in { 516 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 517 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 518} 519 520// Load on condition. 521let isCodeGenOnly = 1, Uses = [CC] in { 522 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 523 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 524} 525let Uses = [CC] in { 526 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>; 527 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>; 528} 529 530// Register stores. 531let SimpleBDXStore = 1 in { 532 // Expands to ST, STY or STFH, depending on the choice of register. 533 def STMux : StoreRXYPseudo<store, GRX32, 4>, 534 Requires<[FeatureHighWord]>; 535 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 536 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 537 Requires<[FeatureHighWord]>; 538 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 539 540 // These instructions are split after register allocation, so we don't 541 // want a custom inserter. 542 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 543 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 544 [(store GR128:$src, bdxaddr20only128:$dst)]>; 545 } 546} 547def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 548def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 549 550// Store on condition. 551let isCodeGenOnly = 1, Uses = [CC] in { 552 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 553 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 554} 555let Uses = [CC] in { 556 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 557 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 558} 559 560// 8-bit immediate stores to 8-bit fields. 561defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 562 563// 16-bit immediate stores to 16-, 32- or 64-bit fields. 564def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 565def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 566def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 567 568// Memory-to-memory moves. 569let mayLoad = 1, mayStore = 1 in 570 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 571 572// String moves. 573let mayLoad = 1, mayStore = 1, Defs = [CC] in 574 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 575 576//===----------------------------------------------------------------------===// 577// Sign extensions 578//===----------------------------------------------------------------------===// 579// 580// Note that putting these before zero extensions mean that we will prefer 581// them for anyextload*. There's not really much to choose between the two 582// either way, but signed-extending loads have a short LH and a long LHY, 583// while zero-extending loads have only the long LLH. 584// 585//===----------------------------------------------------------------------===// 586 587// 32-bit extensions from registers. 588let hasSideEffects = 0 in { 589 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>; 590 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>; 591} 592 593// 64-bit extensions from registers. 594let hasSideEffects = 0 in { 595 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>; 596 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>; 597 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>; 598} 599let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 600 def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR32>; 601 602// Match 32-to-64-bit sign extensions in which the source is already 603// in a 64-bit register. 604def : Pat<(sext_inreg GR64:$src, i32), 605 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 606 607// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 608// depending on the choice of register. 609def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 610 Requires<[FeatureHighWord]>; 611def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 612def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 613 Requires<[FeatureHighWord]>; 614 615// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 616// depending on the choice of register. 617def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 618 Requires<[FeatureHighWord]>; 619defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 620def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 621 Requires<[FeatureHighWord]>; 622def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 623 624// 64-bit extensions from memory. 625def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 626def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 627def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 628def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 629def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 630let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 631 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 632 633//===----------------------------------------------------------------------===// 634// Zero extensions 635//===----------------------------------------------------------------------===// 636 637// 32-bit extensions from registers. 638let hasSideEffects = 0 in { 639 // Expands to LLCR or RISB[LH]G, depending on the choice of registers. 640 def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>, 641 Requires<[FeatureHighWord]>; 642 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>; 643 // Expands to LLHR or RISB[LH]G, depending on the choice of registers. 644 def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>, 645 Requires<[FeatureHighWord]>; 646 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>; 647} 648 649// 64-bit extensions from registers. 650let hasSideEffects = 0 in { 651 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>; 652 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>; 653 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>; 654} 655 656// Match 32-to-64-bit zero extensions in which the source is already 657// in a 64-bit register. 658def : Pat<(and GR64:$src, 0xffffffff), 659 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 660 661// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 662// depending on the choice of register. 663def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 664 Requires<[FeatureHighWord]>; 665def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 666def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 667 Requires<[FeatureHighWord]>; 668 669// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 670// depending on the choice of register. 671def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 672 Requires<[FeatureHighWord]>; 673def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 674def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 675 Requires<[FeatureHighWord]>; 676def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 677 678// 64-bit extensions from memory. 679def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 680def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 681def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 682def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 683def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 684 685//===----------------------------------------------------------------------===// 686// Truncations 687//===----------------------------------------------------------------------===// 688 689// Truncations of 64-bit registers to 32-bit registers. 690def : Pat<(i32 (trunc GR64:$src)), 691 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 692 693// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 694// STC, STCY or STCH, depending on the choice of register. 695def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 696 Requires<[FeatureHighWord]>; 697defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 698def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 699 Requires<[FeatureHighWord]>; 700 701// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 702// STH, STHY or STHH, depending on the choice of register. 703def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 704 Requires<[FeatureHighWord]>; 705defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 706def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 707 Requires<[FeatureHighWord]>; 708def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 709 710// Truncations of 64-bit registers to memory. 711defm : StoreGR64Pair<STC, STCY, truncstorei8>; 712defm : StoreGR64Pair<STH, STHY, truncstorei16>; 713def : StoreGR64PC<STHRL, aligned_truncstorei16>; 714defm : StoreGR64Pair<ST, STY, truncstorei32>; 715def : StoreGR64PC<STRL, aligned_truncstorei32>; 716 717//===----------------------------------------------------------------------===// 718// Multi-register moves 719//===----------------------------------------------------------------------===// 720 721// Multi-register loads. 722defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 723def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 724def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 725 726// Multi-register stores. 727defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 728def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 729def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 730 731//===----------------------------------------------------------------------===// 732// Byte swaps 733//===----------------------------------------------------------------------===// 734 735// Byte-swapping register moves. 736let hasSideEffects = 0 in { 737 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>; 738 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>; 739} 740 741// Byte-swapping loads. Unlike normal loads, these instructions are 742// allowed to access storage more than once. 743def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 744def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 745def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 746 747// Likewise byte-swapping stores. 748def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 749def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 750def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 751 752//===----------------------------------------------------------------------===// 753// Load address instructions 754//===----------------------------------------------------------------------===// 755 756// Load BDX-style addresses. 757let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1, 758 DispKey = "la" in { 759 let DispSize = "12" in 760 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2), 761 "la\t$R1, $XBD2", 762 [(set GR64:$R1, laaddr12pair:$XBD2)]>; 763 let DispSize = "20" in 764 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2), 765 "lay\t$R1, $XBD2", 766 [(set GR64:$R1, laaddr20pair:$XBD2)]>; 767} 768 769// Load a PC-relative address. There's no version of this instruction 770// with a 16-bit offset, so there's no relaxation. 771let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 772 isReMaterializable = 1 in { 773 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2), 774 "larl\t$R1, $I2", 775 [(set GR64:$R1, pcrel32:$I2)]>; 776} 777 778// Load the Global Offset Table address. This will be lowered into a 779// larl $R1, _GLOBAL_OFFSET_TABLE_ 780// instruction. 781def GOT : Alias<6, (outs GR64:$R1), (ins), 782 [(set GR64:$R1, (global_offset_table))]>; 783 784//===----------------------------------------------------------------------===// 785// Absolute and Negation 786//===----------------------------------------------------------------------===// 787 788let Defs = [CC] in { 789 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 790 def LPR : UnaryRR <"lp", 0x10, z_iabs, GR32, GR32>; 791 def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>; 792 } 793 let CCValues = 0xE, CompareZeroCCMask = 0xE in 794 def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>; 795} 796def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 797def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 798defm : SXU<z_iabs, LPGFR>; 799defm : SXU<z_iabs64, LPGFR>; 800 801let Defs = [CC] in { 802 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 803 def LNR : UnaryRR <"ln", 0x11, z_inegabs, GR32, GR32>; 804 def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>; 805 } 806 let CCValues = 0xE, CompareZeroCCMask = 0xE in 807 def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>; 808} 809def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 810def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 811defm : SXU<z_inegabs, LNGFR>; 812defm : SXU<z_inegabs64, LNGFR>; 813 814let Defs = [CC] in { 815 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 816 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>; 817 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>; 818 } 819 let CCValues = 0xE, CompareZeroCCMask = 0xE in 820 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>; 821} 822defm : SXU<ineg, LCGFR>; 823 824//===----------------------------------------------------------------------===// 825// Insertion 826//===----------------------------------------------------------------------===// 827 828let isCodeGenOnly = 1 in 829 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 830defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 831 832defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 833defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 834 835defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 836defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 837 838let Defs = [CC] in { 839 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 840 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 841} 842 843// Insertions of a 16-bit immediate, leaving other bits unaffected. 844// We don't have or_as_insert equivalents of these operations because 845// OI is available instead. 846// 847// IIxMux expands to II[LH]x, depending on the choice of register. 848def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 849 Requires<[FeatureHighWord]>; 850def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 851 Requires<[FeatureHighWord]>; 852def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 853def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 854def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 855def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 856def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 857def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 858def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 859def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 860 861// ...likewise for 32-bit immediates. For GR32s this is a general 862// full-width move. (We use IILF rather than something like LLILF 863// for 32-bit moves because IILF leaves the upper 32 bits of the 864// GR64 unchanged.) 865let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 866 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 867 Requires<[FeatureHighWord]>; 868 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 869 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 870} 871def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 872def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 873 874// An alternative model of inserthf, with the first operand being 875// a zero-extended value. 876def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 877 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 878 imm64hf32:$imm)>; 879 880//===----------------------------------------------------------------------===// 881// Addition 882//===----------------------------------------------------------------------===// 883 884// Plain addition. 885let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 886 // Addition of a register. 887 let isCommutable = 1 in { 888 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>; 889 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>; 890 } 891 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>; 892 893 // Addition of signed 16-bit immediates. 894 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 895 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 896 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 897 898 // Addition of signed 32-bit immediates. 899 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 900 Requires<[FeatureHighWord]>; 901 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 902 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 903 Requires<[FeatureHighWord]>; 904 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 905 906 // Addition of memory. 907 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 908 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 909 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 910 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 911 912 // Addition to memory. 913 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 914 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 915} 916defm : SXB<add, GR64, AGFR>; 917 918// Addition producing a carry. 919let Defs = [CC] in { 920 // Addition of a register. 921 let isCommutable = 1 in { 922 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>; 923 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>; 924 } 925 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>; 926 927 // Addition of signed 16-bit immediates. 928 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 929 Requires<[FeatureDistinctOps]>; 930 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 931 Requires<[FeatureDistinctOps]>; 932 933 // Addition of unsigned 32-bit immediates. 934 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 935 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 936 937 // Addition of memory. 938 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 939 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 940 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 941} 942defm : ZXB<addc, GR64, ALGFR>; 943 944// Addition producing and using a carry. 945let Defs = [CC], Uses = [CC] in { 946 // Addition of a register. 947 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>; 948 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>; 949 950 // Addition of memory. 951 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 952 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 953} 954 955//===----------------------------------------------------------------------===// 956// Subtraction 957//===----------------------------------------------------------------------===// 958 959// Plain subtraction. Although immediate forms exist, we use the 960// add-immediate instruction instead. 961let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 962 // Subtraction of a register. 963 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>; 964 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>; 965 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>; 966 967 // Subtraction of memory. 968 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 969 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 970 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 971 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 972} 973defm : SXB<sub, GR64, SGFR>; 974 975// Subtraction producing a carry. 976let Defs = [CC] in { 977 // Subtraction of a register. 978 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>; 979 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>; 980 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>; 981 982 // Subtraction of unsigned 32-bit immediates. These don't match 983 // subc because we prefer addc for constants. 984 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 985 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 986 987 // Subtraction of memory. 988 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 989 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 990 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 991} 992defm : ZXB<subc, GR64, SLGFR>; 993 994// Subtraction producing and using a carry. 995let Defs = [CC], Uses = [CC] in { 996 // Subtraction of a register. 997 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>; 998 def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>; 999 1000 // Subtraction of memory. 1001 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 1002 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 1003} 1004 1005//===----------------------------------------------------------------------===// 1006// AND 1007//===----------------------------------------------------------------------===// 1008 1009let Defs = [CC] in { 1010 // ANDs of a register. 1011 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1012 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>; 1013 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>; 1014 } 1015 1016 let isConvertibleToThreeAddress = 1 in { 1017 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1018 // The CC result only reflects the 16-bit field, not the full register. 1019 // 1020 // NIxMux expands to NI[LH]x, depending on the choice of register. 1021 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1022 Requires<[FeatureHighWord]>; 1023 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1024 Requires<[FeatureHighWord]>; 1025 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1026 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1027 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1028 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1029 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1030 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1031 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1032 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1033 1034 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1035 // The CC result only reflects the 32-bit field, which means we can 1036 // use it as a zero indicator for i32 operations but not otherwise. 1037 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1038 // Expands to NILF or NIHF, depending on the choice of register. 1039 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1040 Requires<[FeatureHighWord]>; 1041 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1042 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1043 } 1044 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1045 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1046 } 1047 1048 // ANDs of memory. 1049 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1050 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1051 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1052 } 1053 1054 // AND to memory 1055 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1056 1057 // Block AND. 1058 let mayLoad = 1, mayStore = 1 in 1059 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1060} 1061defm : RMWIByte<and, bdaddr12pair, NI>; 1062defm : RMWIByte<and, bdaddr20pair, NIY>; 1063 1064//===----------------------------------------------------------------------===// 1065// OR 1066//===----------------------------------------------------------------------===// 1067 1068let Defs = [CC] in { 1069 // ORs of a register. 1070 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1071 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>; 1072 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>; 1073 } 1074 1075 // ORs of a 16-bit immediate, leaving other bits unaffected. 1076 // The CC result only reflects the 16-bit field, not the full register. 1077 // 1078 // OIxMux expands to OI[LH]x, depending on the choice of register. 1079 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1080 Requires<[FeatureHighWord]>; 1081 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1082 Requires<[FeatureHighWord]>; 1083 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1084 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1085 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1086 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1087 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1088 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1089 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1090 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1091 1092 // ORs of a 32-bit immediate, leaving other bits unaffected. 1093 // The CC result only reflects the 32-bit field, which means we can 1094 // use it as a zero indicator for i32 operations but not otherwise. 1095 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1096 // Expands to OILF or OIHF, depending on the choice of register. 1097 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1098 Requires<[FeatureHighWord]>; 1099 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1100 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1101 } 1102 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1103 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1104 1105 // ORs of memory. 1106 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1107 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1108 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1109 } 1110 1111 // OR to memory 1112 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1113 1114 // Block OR. 1115 let mayLoad = 1, mayStore = 1 in 1116 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1117} 1118defm : RMWIByte<or, bdaddr12pair, OI>; 1119defm : RMWIByte<or, bdaddr20pair, OIY>; 1120 1121//===----------------------------------------------------------------------===// 1122// XOR 1123//===----------------------------------------------------------------------===// 1124 1125let Defs = [CC] in { 1126 // XORs of a register. 1127 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1128 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>; 1129 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>; 1130 } 1131 1132 // XORs of a 32-bit immediate, leaving other bits unaffected. 1133 // The CC result only reflects the 32-bit field, which means we can 1134 // use it as a zero indicator for i32 operations but not otherwise. 1135 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1136 // Expands to XILF or XIHF, depending on the choice of register. 1137 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1138 Requires<[FeatureHighWord]>; 1139 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1140 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1141 } 1142 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1143 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1144 1145 // XORs of memory. 1146 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1147 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1148 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1149 } 1150 1151 // XOR to memory 1152 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1153 1154 // Block XOR. 1155 let mayLoad = 1, mayStore = 1 in 1156 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1157} 1158defm : RMWIByte<xor, bdaddr12pair, XI>; 1159defm : RMWIByte<xor, bdaddr20pair, XIY>; 1160 1161//===----------------------------------------------------------------------===// 1162// Multiplication 1163//===----------------------------------------------------------------------===// 1164 1165// Multiplication of a register. 1166let isCommutable = 1 in { 1167 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>; 1168 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>; 1169} 1170def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>; 1171defm : SXB<mul, GR64, MSGFR>; 1172 1173// Multiplication of a signed 16-bit immediate. 1174def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1175def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1176 1177// Multiplication of a signed 32-bit immediate. 1178def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1179def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1180 1181// Multiplication of memory. 1182defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1183defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1184def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1185def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1186 1187// Multiplication of a register, producing two results. 1188def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>; 1189 1190// Multiplication of memory, producing two results. 1191def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>; 1192 1193//===----------------------------------------------------------------------===// 1194// Division and remainder 1195//===----------------------------------------------------------------------===// 1196 1197// Division and remainder, from registers. 1198def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>; 1199def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>; 1200def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>; 1201def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>; 1202 1203// Division and remainder, from memory. 1204def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>; 1205def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>; 1206def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>; 1207def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>; 1208 1209//===----------------------------------------------------------------------===// 1210// Shifts 1211//===----------------------------------------------------------------------===// 1212 1213// Shift left. 1214let hasSideEffects = 0 in { 1215 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1216 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1217 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1218} 1219 1220// Logical shift right. 1221let hasSideEffects = 0 in { 1222 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1223 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1224} 1225 1226// Arithmetic shift right. 1227let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1228 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1229 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1230} 1231 1232// Rotate left. 1233let hasSideEffects = 0 in { 1234 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1235 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1236} 1237 1238// Rotate second operand left and inserted selected bits into first operand. 1239// These can act like 32-bit operands provided that the constant start and 1240// end bits (operands 2 and 3) are in the range [32, 64). 1241let Defs = [CC] in { 1242 let isCodeGenOnly = 1 in 1243 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1244 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1245 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1246} 1247 1248// On zEC12 we have a variant of RISBG that does not set CC. 1249let Predicates = [FeatureMiscellaneousExtensions] in 1250 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1251 1252// Forms of RISBG that only affect one word of the destination register. 1253// They do not set CC. 1254let Predicates = [FeatureHighWord] in { 1255 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1256 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1257 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1258 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1259 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1260 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1261 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1262} 1263 1264// Rotate second operand left and perform a logical operation with selected 1265// bits of the first operand. The CC result only describes the selected bits, 1266// so isn't useful for a full comparison against zero. 1267let Defs = [CC] in { 1268 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1269 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1270 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1271} 1272 1273//===----------------------------------------------------------------------===// 1274// Comparison 1275//===----------------------------------------------------------------------===// 1276 1277// Signed comparisons. We put these before the unsigned comparisons because 1278// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1279// of the unsigned forms do. 1280let Defs = [CC], CCValues = 0xE in { 1281 // Comparison with a register. 1282 def CR : CompareRR <"c", 0x19, z_scmp, GR32, GR32>; 1283 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>; 1284 def CGR : CompareRRE<"cg", 0xB920, z_scmp, GR64, GR64>; 1285 1286 // Comparison with a signed 16-bit immediate. 1287 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1288 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1289 1290 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1291 // depending on the choice of register. 1292 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1293 Requires<[FeatureHighWord]>; 1294 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1295 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1296 Requires<[FeatureHighWord]>; 1297 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1298 1299 // Comparison with memory. 1300 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1301 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1302 Requires<[FeatureHighWord]>; 1303 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1304 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1305 Requires<[FeatureHighWord]>; 1306 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1307 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1308 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1309 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1310 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1311 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1312 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1313 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1314 1315 // Comparison between memory and a signed 16-bit immediate. 1316 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1317 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1318 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1319} 1320defm : SXB<z_scmp, GR64, CGFR>; 1321 1322// Unsigned comparisons. 1323let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1324 // Comparison with a register. 1325 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>; 1326 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>; 1327 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>; 1328 1329 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1330 // or CLIH, depending on the choice of register. 1331 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1332 Requires<[FeatureHighWord]>; 1333 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1334 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1335 Requires<[FeatureHighWord]>; 1336 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1337 1338 // Comparison with memory. 1339 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1340 Requires<[FeatureHighWord]>; 1341 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1342 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1343 Requires<[FeatureHighWord]>; 1344 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1345 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1346 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1347 aligned_azextloadi16>; 1348 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1349 aligned_load>; 1350 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1351 aligned_azextloadi16>; 1352 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1353 aligned_azextloadi32>; 1354 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1355 aligned_load>; 1356 1357 // Comparison between memory and an unsigned 8-bit immediate. 1358 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1359 1360 // Comparison between memory and an unsigned 16-bit immediate. 1361 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1362 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1363 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1364} 1365defm : ZXB<z_ucmp, GR64, CLGFR>; 1366 1367// Memory-to-memory comparison. 1368let mayLoad = 1, Defs = [CC] in 1369 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1370 1371// String comparison. 1372let mayLoad = 1, Defs = [CC] in 1373 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1374 1375// Test under mask. 1376let Defs = [CC] in { 1377 // TMxMux expands to TM[LH]x, depending on the choice of register. 1378 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1379 Requires<[FeatureHighWord]>; 1380 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1381 Requires<[FeatureHighWord]>; 1382 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1383 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1384 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1385 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1386 1387 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1388 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1389 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1390 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1391 1392 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1393} 1394 1395def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1396def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1397 1398//===----------------------------------------------------------------------===// 1399// Prefetch 1400//===----------------------------------------------------------------------===// 1401 1402def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1403def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1404 1405//===----------------------------------------------------------------------===// 1406// Atomic operations 1407//===----------------------------------------------------------------------===// 1408 1409// A serialization instruction that acts as a barrier for all memory 1410// accesses, which expands to "bcr 14, 0". 1411let hasSideEffects = 1 in 1412def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>; 1413 1414// A pseudo instruction that serves as a compiler barrier. 1415let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1416def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1417 1418let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1419 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1420 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1421 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1422 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1423 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1424 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1425 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1426 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1427 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1428 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1429} 1430 1431def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1432def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1433def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1434 1435def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1436def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1437let Predicates = [FeatureNoInterlockedAccess1] in { 1438 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1439 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1440 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1441 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1442 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1443 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1444} 1445 1446def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1447def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1448def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1449 1450def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1451def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1452let Predicates = [FeatureNoInterlockedAccess1] in { 1453 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1454 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1455 imm32ll16c>; 1456 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1457 imm32lh16c>; 1458 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1459 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1460 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1461 imm64ll16c>; 1462 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1463 imm64lh16c>; 1464 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1465 imm64hl16c>; 1466 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1467 imm64hh16c>; 1468 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1469 imm64lf32c>; 1470 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1471 imm64hf32c>; 1472} 1473 1474def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1475def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1476let Predicates = [FeatureNoInterlockedAccess1] in { 1477 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1478 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1479 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1480 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1481 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1482 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1483 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1484 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1485 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1486 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1487 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1488} 1489 1490def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1491def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1492let Predicates = [FeatureNoInterlockedAccess1] in { 1493 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1494 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1495 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1496 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1497 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1498} 1499 1500def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1501def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1502 imm32lh16c>; 1503def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1504def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1505 imm32ll16c>; 1506def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1507 imm32lh16c>; 1508def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1509def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1510def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1511 imm64ll16c>; 1512def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1513 imm64lh16c>; 1514def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1515 imm64hl16c>; 1516def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1517 imm64hh16c>; 1518def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1519 imm64lf32c>; 1520def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1521 imm64hf32c>; 1522 1523def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1524def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1525def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1526 1527def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1528def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1529def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1530 1531def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1532def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1533def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1534 1535def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1536def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1537def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1538 1539def ATOMIC_CMP_SWAPW 1540 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1541 ADDR32:$bitshift, ADDR32:$negbitshift, 1542 uimm32:$bitsize), 1543 [(set GR32:$dst, 1544 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1545 ADDR32:$bitshift, ADDR32:$negbitshift, 1546 uimm32:$bitsize))]> { 1547 let Defs = [CC]; 1548 let mayLoad = 1; 1549 let mayStore = 1; 1550 let usesCustomInserter = 1; 1551 let hasNoSchedulingInfo = 1; 1552} 1553 1554let Defs = [CC] in { 1555 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1556 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1557} 1558 1559//===----------------------------------------------------------------------===// 1560// Transactional execution 1561//===----------------------------------------------------------------------===// 1562 1563let Predicates = [FeatureTransactionalExecution] in { 1564 // Transaction Begin 1565 let hasSideEffects = 1, mayStore = 1, 1566 usesCustomInserter = 1, Defs = [CC] in { 1567 def TBEGIN : InstSIL<0xE560, 1568 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1569 "tbegin\t$BD1, $I2", 1570 [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>; 1571 def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1572 [(z_tbegin_nofloat bdaddr12only:$BD1, 1573 imm32zx16:$I2)]>; 1574 def TBEGINC : InstSIL<0xE561, 1575 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1576 "tbeginc\t$BD1, $I2", 1577 [(int_s390_tbeginc bdaddr12only:$BD1, 1578 imm32zx16:$I2)]>; 1579 } 1580 1581 // Transaction End 1582 let hasSideEffects = 1, Defs = [CC], BD2 = 0 in 1583 def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>; 1584 1585 // Transaction Abort 1586 let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in 1587 def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2), 1588 "tabort\t$BD2", 1589 [(int_s390_tabort bdaddr12only:$BD2)]>; 1590 1591 // Nontransactional Store 1592 let hasSideEffects = 1 in 1593 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1594 1595 // Extract Transaction Nesting Depth 1596 let hasSideEffects = 1 in 1597 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>; 1598} 1599 1600//===----------------------------------------------------------------------===// 1601// Processor assist 1602//===----------------------------------------------------------------------===// 1603 1604let Predicates = [FeatureProcessorAssist] in { 1605 let hasSideEffects = 1, R4 = 0 in 1606 def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3), 1607 "ppa\t$R1, $R2, $R3", []>; 1608 def : Pat<(int_s390_ppa_txassist GR32:$src), 1609 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1610 0, 1)>; 1611} 1612 1613//===----------------------------------------------------------------------===// 1614// Miscellaneous Instructions. 1615//===----------------------------------------------------------------------===// 1616 1617// Extract CC into bits 29 and 28 of a register. 1618let Uses = [CC] in 1619 def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>; 1620 1621// Read a 32-bit access register into a GR32. As with all GR32 operations, 1622// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1623// when a 64-bit address is stored in a pair of access registers. 1624def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2), 1625 "ear\t$R1, $R2", 1626 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>; 1627 1628// Find leftmost one, AKA count leading zeros. The instruction actually 1629// returns a pair of GR64s, the first giving the number of leading zeros 1630// and the second giving a copy of the source with the leftmost one bit 1631// cleared. We only use the first result here. 1632let Defs = [CC] in { 1633 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>; 1634} 1635def : Pat<(ctlz GR64:$src), 1636 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1637 1638// Population count. Counts bits set per byte. 1639let Predicates = [FeaturePopulationCount], Defs = [CC] in { 1640 def POPCNT : InstRRE<0xB9E1, (outs GR64:$R1), (ins GR64:$R2), 1641 "popcnt\t$R1, $R2", 1642 [(set GR64:$R1, (z_popcnt GR64:$R2))]>; 1643} 1644 1645// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 1646def : Pat<(i64 (anyext GR32:$src)), 1647 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 1648 1649// Extend GR32s and GR64s to GR128s. 1650let usesCustomInserter = 1 in { 1651 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1652 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 1653 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1654} 1655 1656// Search a block of memory for a character. 1657let mayLoad = 1, Defs = [CC] in 1658 defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; 1659 1660// Other instructions for inline assembly 1661let hasSideEffects = 1, Defs = [CC], isCall = 1 in 1662 def SVC : InstI<0x0A, (outs), (ins imm32zx8:$I1), 1663 "svc\t$I1", 1664 []>; 1665let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1666 def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2), 1667 "stck\t$BD2", 1668 []>; 1669let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1670 def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2), 1671 "stckf\t$BD2", 1672 []>; 1673let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1674 def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2), 1675 "stcke\t$BD2", 1676 []>; 1677let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1678 def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2), 1679 "stfle\t$BD2", 1680 []>; 1681 1682let hasSideEffects = 1 in { 1683 def EX : InstRX<0x44, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2), 1684 "ex\t$R1, $XBD2", []>; 1685 def EXRL : InstRIL<0xC60, (outs), (ins GR64:$R1, pcrel32:$I2), 1686 "exrl\t$R1, $I2", []>; 1687} 1688 1689let Defs = [CC] in { 1690 let hasSideEffects = 1 in 1691 def PR : InstE<0x0101, (outs), (ins), "pr", []>; 1692 1693 let mayLoad = 1, mayStore = 1 in 1694 def MVCK : InstSSd<0xD9, (outs), 1695 (ins bdxaddr12only:$XBD1, bdaddr12only:$BD2, 1696 GR64:$R3), 1697 "mvck\t$XBD1, $BD2, $R3", []>; 1698} 1699 1700let mayStore = 1 in 1701 def STRAG : InstSSE<0xE502, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2), 1702 "strag\t$BD1, $BD2", []>; 1703 1704let Defs = [R0D, R1D], mayLoad = 1 in 1705 def ECTG : InstSSF<0xC81, (outs), 1706 (ins bdaddr12only:$BD1, bdaddr12only:$BD2, GR64:$R3), 1707 "ectg\t$BD1, $BD2, $R3", []>; 1708 1709//===----------------------------------------------------------------------===// 1710// .insn directive instructions 1711//===----------------------------------------------------------------------===// 1712 1713let isCodeGenOnly = 1 in { 1714 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 1715 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 1716 imm32sx16:$I2), 1717 ".insn ri,$enc,$R1,$I2", []>; 1718 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1719 AnyReg:$R3, brtarget16:$I2), 1720 ".insn rie,$enc,$R1,$R3,$I2", []>; 1721 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1722 brtarget32:$I2), 1723 ".insn ril,$enc,$R1,$I2", []>; 1724 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1725 uimm32:$I2), 1726 ".insn rilu,$enc,$R1,$I2", []>; 1727 def InsnRIS : DirectiveInsnRIS<(outs), 1728 (ins imm64zx48:$enc, AnyReg:$R1, 1729 imm32sx8:$I2, imm32zx4:$M3, 1730 bdaddr12only:$BD4), 1731 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 1732 def InsnRR : DirectiveInsnRR<(outs), 1733 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 1734 ".insn rr,$enc,$R1,$R2", []>; 1735 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 1736 AnyReg:$R1, AnyReg:$R2), 1737 ".insn rre,$enc,$R1,$R2", []>; 1738 def InsnRRF : DirectiveInsnRRF<(outs), 1739 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 1740 AnyReg:$R3, imm32zx4:$R4), 1741 ".insn rrf,$enc,$R1,$R2,$R3,$R4", []>; 1742 def InsnRRS : DirectiveInsnRRS<(outs), 1743 (ins imm64zx48:$enc, AnyReg:$R1, 1744 AnyReg:$R2, imm32zx4:$M3, 1745 bdaddr12only:$BD4), 1746 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 1747 def InsnRS : DirectiveInsnRS<(outs), 1748 (ins imm64zx32:$enc, AnyReg:$R1, 1749 AnyReg:$R3, bdaddr12only:$BD2), 1750 ".insn rs,$enc,$R1,$R3,$BD2", []>; 1751 def InsnRSE : DirectiveInsnRSE<(outs), 1752 (ins imm64zx48:$enc, AnyReg:$R1, 1753 AnyReg:$R3, bdaddr12only:$BD2), 1754 ".insn rse,$enc,$R1,$R3,$BD2", []>; 1755 def InsnRSI : DirectiveInsnRSI<(outs), 1756 (ins imm64zx48:$enc, AnyReg:$R1, 1757 AnyReg:$R3, brtarget16:$RI2), 1758 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 1759 def InsnRSY : DirectiveInsnRSY<(outs), 1760 (ins imm64zx48:$enc, AnyReg:$R1, 1761 AnyReg:$R3, bdaddr20only:$BD2), 1762 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 1763 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 1764 bdxaddr12only:$XBD2), 1765 ".insn rx,$enc,$R1,$XBD2", []>; 1766 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1767 bdxaddr12only:$XBD2), 1768 ".insn rxe,$enc,$R1,$XBD2", []>; 1769 def InsnRXF : DirectiveInsnRXF<(outs), 1770 (ins imm64zx48:$enc, AnyReg:$R1, 1771 AnyReg:$R3, bdxaddr12only:$XBD2), 1772 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 1773 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1774 bdxaddr20only:$XBD2), 1775 ".insn rxy,$enc,$R1,$XBD2", []>; 1776 def InsnS : DirectiveInsnS<(outs), 1777 (ins imm64zx32:$enc, bdaddr12only:$BD2), 1778 ".insn s,$enc,$BD2", []>; 1779 def InsnSI : DirectiveInsnSI<(outs), 1780 (ins imm64zx32:$enc, bdaddr12only:$BD1, 1781 imm32sx8:$I2), 1782 ".insn si,$enc,$BD1,$I2", []>; 1783 def InsnSIY : DirectiveInsnSIY<(outs), 1784 (ins imm64zx48:$enc, 1785 bdaddr20only:$BD1, imm32zx8:$I2), 1786 ".insn siy,$enc,$BD1,$I2", []>; 1787 def InsnSIL : DirectiveInsnSIL<(outs), 1788 (ins imm64zx48:$enc, bdaddr12only:$BD1, 1789 imm32zx16:$I2), 1790 ".insn sil,$enc,$BD1,$I2", []>; 1791 def InsnSS : DirectiveInsnSS<(outs), 1792 (ins imm64zx48:$enc, bdxaddr12only:$XBD1, 1793 bdaddr12only:$BD2, AnyReg:$R3), 1794 ".insn ss,$enc,$XBD1,$BD2,$R3", []>; 1795 def InsnSSE : DirectiveInsnSSE<(outs), 1796 (ins imm64zx48:$enc, 1797 bdaddr12only:$BD1,bdaddr12only:$BD2), 1798 ".insn sse,$enc,$BD1,$BD2", []>; 1799 def InsnSSF : DirectiveInsnSSF<(outs), 1800 (ins imm64zx48:$enc, bdaddr12only:$BD1, 1801 bdaddr12only:$BD2, AnyReg:$R3), 1802 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 1803} 1804 1805//===----------------------------------------------------------------------===// 1806// Peepholes. 1807//===----------------------------------------------------------------------===// 1808 1809// Use AL* for GR64 additions of unsigned 32-bit values. 1810defm : ZXB<add, GR64, ALGFR>; 1811def : Pat<(add GR64:$src1, imm64zx32:$src2), 1812 (ALGFI GR64:$src1, imm64zx32:$src2)>; 1813def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1814 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 1815 1816// Use SL* for GR64 subtractions of unsigned 32-bit values. 1817defm : ZXB<sub, GR64, SLGFR>; 1818def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1819 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1820def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1821 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 1822 1823// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 1824// for vector legalization. 1825def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)), 1826 (i32 31)), 1827 (i32 31)), 1828 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1829def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, 1830 imm32zx4:$cc)))), 1831 (i32 63)), 1832 (i32 63)), 1833 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1834 1835// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 1836// equivalent to (and (xor x, -1), y) 1837def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 1838 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 1839 1840// Shift/rotate instructions only use the last 6 bits of the second operand 1841// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 1842// last 16 bits. 1843// Complexity is added so that we match this before we match NILF on the AND 1844// operation alone. 1845let AddedComplexity = 4 in { 1846 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1847 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1848 1849 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 1850 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1851 1852 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1853 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1854 1855 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1856 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1857 1858 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 1859 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1860 1861 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1862 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1863 1864 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1865 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1866 1867 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1868 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1869} 1870 1871// Peepholes for turning scalar operations into block operations. 1872defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 1873 XCSequence, 1>; 1874defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 1875 XCSequence, 2>; 1876defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 1877 XCSequence, 4>; 1878defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 1879 OCSequence, XCSequence, 1>; 1880defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 1881 XCSequence, 2>; 1882defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 1883 XCSequence, 4>; 1884defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 1885 XCSequence, 8>; 1886