1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Stack allocation 11//===----------------------------------------------------------------------===// 12 13// The callseq_start node requires the hasSideEffects flag, even though these 14// instructions are noops on SystemZ. 15let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 16 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_start timm:$amt1, timm:$amt2)]>; 18 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 19 [(callseq_end timm:$amt1, timm:$amt2)]>; 20} 21 22// Takes as input the value of the stack pointer after a dynamic allocation 23// has been made. Sets the output to the address of the dynamically- 24// allocated area itself, skipping the outgoing arguments. 25// 26// This expands to an LA or LAY instruction. We restrict the offset 27// to the range of LA and keep the LAY range in reserve for when 28// the size of the outgoing arguments is added. 29def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31 32let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 33 usesCustomInserter = 1 in 34 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 35 (ins GR64:$oldSP, GR64:$space), 36 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 37 38let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 39 hasSideEffects = 1 in 40 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 41 42//===----------------------------------------------------------------------===// 43// Branch instructions 44//===----------------------------------------------------------------------===// 45 46// Conditional branches. 47let isBranch = 1, isTerminator = 1, Uses = [CC] in { 48 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 49 // with the condition-code mask being the first operand. It seems friendlier 50 // to use mnemonic forms like JE and JLH when writing out the assembly though. 51 let isCodeGenOnly = 1 in { 52 // An assembler extended mnemonic for BRC. 53 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 54 // An assembler extended mnemonic for BRCL. (The extension is "G" 55 // rather than "L" because "JL" is "Jump if Less".) 56 def BRCL : CondBranchRIL<"jg#", 0xC04>; 57 let isIndirectBranch = 1 in { 58 def BC : CondBranchRX<"b#", 0x47>; 59 def BCR : CondBranchRR<"b#r", 0x07>; 60 def BIC : CondBranchRXY<"bi#", 0xe347>, 61 Requires<[FeatureMiscellaneousExtensions2]>; 62 } 63 } 64 65 // Allow using the raw forms directly from the assembler (and occasional 66 // special code generation needs) as well. 67 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 68 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 69 let isIndirectBranch = 1 in { 70 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 71 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 72 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 73 Requires<[FeatureMiscellaneousExtensions2]>; 74 } 75 76 // Define AsmParser extended mnemonics for each general condition-code mask 77 // (integer or floating-point) 78 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 79 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 80 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 81 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 82 let isIndirectBranch = 1 in { 83 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 84 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 85 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 86 Requires<[FeatureMiscellaneousExtensions2]>; 87 } 88 } 89} 90 91// Unconditional branches. These are in fact simply variants of the 92// conditional branches with the condition mask set to "always". 93let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 94 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 95 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 96 let isIndirectBranch = 1 in { 97 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 98 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 99 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 100 Requires<[FeatureMiscellaneousExtensions2]>; 101 } 102} 103 104// NOPs. These are again variants of the conditional branches, with the 105// condition mask set to "never". NOP_bare can't be an InstAlias since it 106// would need R0D hard coded which is not part of ADDR64BitRegClass. 107def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 108let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 109 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 110def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 111def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 112 113// Fused compare-and-branch instructions. 114// 115// These instructions do not use or clobber the condition codes. 116// We nevertheless pretend that the relative compare-and-branch 117// instructions clobber CC, so that we can lower them to separate 118// comparisons and BRCLs if the branch ends up being out of range. 119let isBranch = 1, isTerminator = 1 in { 120 // As for normal branches, we handle these instructions internally in 121 // their raw CRJ-like form, but use assembly macros like CRJE when writing 122 // them out. Using the *Pair multiclasses, we also create the raw forms. 123 let Defs = [CC] in { 124 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 125 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 126 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 127 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 128 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 129 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 130 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 131 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 132 } 133 let isIndirectBranch = 1 in { 134 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 135 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 136 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 137 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 138 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 139 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 140 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 141 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 142 } 143 144 // Define AsmParser mnemonics for each integer condition-code mask. 145 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 146 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 147 let Defs = [CC] in { 148 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 149 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 150 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 151 imm32sx8>; 152 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 153 imm64sx8>; 154 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 155 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 156 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 157 imm32zx8>; 158 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 159 imm64zx8>; 160 } 161 let isIndirectBranch = 1 in { 162 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 163 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 164 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 165 imm32sx8>; 166 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 167 imm64sx8>; 168 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 169 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 170 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 171 imm32zx8>; 172 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 173 imm64zx8>; 174 } 175 } 176} 177 178// Decrement a register and branch if it is nonzero. These don't clobber CC, 179// but we might need to split long relative branches into sequences that do. 180let isBranch = 1, isTerminator = 1 in { 181 let Defs = [CC] in { 182 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 183 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 184 } 185 // This doesn't need to clobber CC since we never need to split it. 186 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 187 Requires<[FeatureHighWord]>; 188 189 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 190 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 191 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 192 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 193} 194 195let isBranch = 1, isTerminator = 1 in { 196 let Defs = [CC] in { 197 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 198 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 199 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 200 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 201 } 202 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 203 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 204 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 205 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 206} 207 208//===----------------------------------------------------------------------===// 209// Trap instructions 210//===----------------------------------------------------------------------===// 211 212// Unconditional trap. 213let hasCtrlDep = 1, hasSideEffects = 1 in 214 def Trap : Alias<4, (outs), (ins), [(trap)]>; 215 216// Conditional trap. 217let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 218 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 219 220// Fused compare-and-trap instructions. 221let hasCtrlDep = 1, hasSideEffects = 1 in { 222 // These patterns work the same way as for compare-and-branch. 223 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 224 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 225 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 226 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 227 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 228 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 229 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 230 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 231 let Predicates = [FeatureMiscellaneousExtensions] in { 232 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 233 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 234 } 235 236 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 237 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 238 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 239 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 240 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 241 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 242 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 243 imm32sx16>; 244 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 245 imm64sx16>; 246 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 247 imm32zx16>; 248 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 249 imm64zx16>; 250 let Predicates = [FeatureMiscellaneousExtensions] in { 251 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 252 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 253 } 254 } 255} 256 257//===----------------------------------------------------------------------===// 258// Call and return instructions 259//===----------------------------------------------------------------------===// 260 261// Define the general form of the call instructions for the asm parser. 262// These instructions don't hard-code %r14 as the return address register. 263let isCall = 1, Defs = [CC] in { 264 def BRAS : CallRI <"bras", 0xA75>; 265 def BRASL : CallRIL<"brasl", 0xC05>; 266 def BAS : CallRX <"bas", 0x4D>; 267 def BASR : CallRR <"basr", 0x0D>; 268} 269 270// Regular calls. 271let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 272 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 273 [(z_call pcrel32:$I2)]>; 274 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 275 [(z_call ADDR64:$R2)]>; 276} 277 278// TLS calls. These will be lowered into a call to __tls_get_offset, 279// with an extra relocation specifying the TLS symbol. 280let isCall = 1, Defs = [R14D, CC] in { 281 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 282 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 283 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 284 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 285} 286 287// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 288// are argument registers and since branching to R0 is a no-op. 289let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 290 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 291 [(z_sibcall pcrel32:$I2)]>; 292 let Uses = [R1D] in 293 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 294} 295 296// Conditional sibling calls. 297let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 298 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 299 pcrel32:$I2), []>; 300 let Uses = [R1D] in 301 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 302} 303 304// Fused compare and conditional sibling calls. 305let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 306 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 307 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 308 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 309 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 310 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 311 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 312 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 313 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 314} 315 316// A return instruction (br %r14). 317let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 318 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 319 320// A conditional return instruction (bcr <cond>, %r14). 321let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 322 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 323 324// Fused compare and conditional returns. 325let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 326 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 327 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 328 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 329 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 330 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 331 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 332 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 333 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 334} 335 336//===----------------------------------------------------------------------===// 337// Select instructions 338//===----------------------------------------------------------------------===// 339 340def Select32 : SelectWrapper<i32, GR32>, 341 Requires<[FeatureNoLoadStoreOnCond]>; 342def Select64 : SelectWrapper<i64, GR64>, 343 Requires<[FeatureNoLoadStoreOnCond]>; 344 345// We don't define 32-bit Mux stores if we don't have STOCFH, because the 346// low-only STOC should then always be used if possible. 347defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 348 nonvolatile_anyextloadi8, bdxaddr20only>, 349 Requires<[FeatureHighWord]>; 350defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 351 nonvolatile_anyextloadi16, bdxaddr20only>, 352 Requires<[FeatureHighWord]>; 353defm CondStore32Mux : CondStores<GRX32, simple_store, 354 simple_load, bdxaddr20only>, 355 Requires<[FeatureLoadStoreOnCond2]>; 356defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 357 nonvolatile_anyextloadi8, bdxaddr20only>; 358defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 359 nonvolatile_anyextloadi16, bdxaddr20only>; 360defm CondStore32 : CondStores<GR32, simple_store, 361 simple_load, bdxaddr20only>; 362 363defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 364 nonvolatile_anyextloadi8, bdxaddr20only>; 365defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 366 nonvolatile_anyextloadi16, bdxaddr20only>; 367defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 368 nonvolatile_anyextloadi32, bdxaddr20only>; 369defm CondStore64 : CondStores<GR64, simple_store, 370 simple_load, bdxaddr20only>; 371 372//===----------------------------------------------------------------------===// 373// Move instructions 374//===----------------------------------------------------------------------===// 375 376// Register moves. 377def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 378def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 379 380let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 381 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 382 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 383} 384 385let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 386 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 387 388// Immediate moves. 389let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 390 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 391 // deopending on the choice of register. 392 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 393 Requires<[FeatureHighWord]>; 394 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 395 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 396 397 // Other 16-bit immediates. 398 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 399 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 400 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 401 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 402 403 // 32-bit immediates. 404 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 405 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 406 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 407} 408 409// Register loads. 410let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 411 // Expands to L, LY or LFH, depending on the choice of register. 412 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 413 Requires<[FeatureHighWord]>; 414 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 415 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 416 Requires<[FeatureHighWord]>; 417 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 418 419 // These instructions are split after register allocation, so we don't 420 // want a custom inserter. 421 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 422 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 423 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 424 } 425} 426let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 427 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 428 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 429} 430 431let canFoldAsLoad = 1 in { 432 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 433 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 434} 435 436// Load and zero rightmost byte. 437let Predicates = [FeatureLoadAndZeroRightmostByte] in { 438 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 439 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 440 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 441 (LZRF bdxaddr20only:$src)>; 442 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 443 (LZRG bdxaddr20only:$src)>; 444} 445 446// Load and trap. 447let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 448 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 449 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 450 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 451} 452 453// Register stores. 454let SimpleBDXStore = 1, mayStore = 1 in { 455 // Expands to ST, STY or STFH, depending on the choice of register. 456 def STMux : StoreRXYPseudo<store, GRX32, 4>, 457 Requires<[FeatureHighWord]>; 458 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 459 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 460 Requires<[FeatureHighWord]>; 461 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 462 463 // These instructions are split after register allocation, so we don't 464 // want a custom inserter. 465 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 466 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 467 [(store GR128:$src, bdxaddr20only128:$dst)]>; 468 } 469} 470def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 471def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 472 473// 8-bit immediate stores to 8-bit fields. 474defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 475 476// 16-bit immediate stores to 16-, 32- or 64-bit fields. 477def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 478def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 479def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 480 481// Memory-to-memory moves. 482let mayLoad = 1, mayStore = 1 in 483 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 484let mayLoad = 1, mayStore = 1, Defs = [CC] in { 485 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 486 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 487 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 488} 489 490// Move right. 491let Predicates = [FeatureMiscellaneousExtensions3], 492 mayLoad = 1, mayStore = 1, Uses = [R0L] in 493 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 494 495// String moves. 496let mayLoad = 1, mayStore = 1, Defs = [CC] in 497 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 498 499//===----------------------------------------------------------------------===// 500// Conditional move instructions 501//===----------------------------------------------------------------------===// 502 503let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 504 // Select. 505 let isCommutable = 1 in { 506 // Expands to SELR or SELFHR or a branch-and-move sequence, 507 // depending on the choice of registers. 508 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 509 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 510 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 511 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 512 } 513 514 // Define AsmParser extended mnemonics for each general condition-code mask. 515 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 516 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 517 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 518 GR32, GR32, GR32>; 519 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 520 GRH32, GRH32, GRH32>; 521 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 522 GR64, GR64, GR64>; 523 } 524} 525 526let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 527 // Load immediate on condition. Matched via DAG pattern and created 528 // by the PeepholeOptimizer via FoldImmediate. 529 530 // Expands to LOCHI or LOCHHI, depending on the choice of register. 531 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 532 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 533 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 534 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 535 536 // Move register on condition. Matched via DAG pattern and 537 // created by early if-conversion. 538 let isCommutable = 1 in { 539 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 540 // depending on the choice of registers. 541 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 542 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 543 } 544 545 // Load on condition. Matched via DAG pattern. 546 // Expands to LOC or LOCFH, depending on the choice of register. 547 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 548 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 549 550 // Store on condition. Expanded from CondStore* pseudos. 551 // Expands to STOC or STOCFH, depending on the choice of register. 552 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 553 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 554 555 // Define AsmParser extended mnemonics for each general condition-code mask. 556 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 557 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 558 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 559 imm32sx16>; 560 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 561 imm64sx16>; 562 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 563 imm32sx16>; 564 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 565 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 566 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 567 } 568} 569 570let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 571 // Move register on condition. Matched via DAG pattern and 572 // created by early if-conversion. 573 let isCommutable = 1 in { 574 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 575 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 576 } 577 578 // Load on condition. Matched via DAG pattern. 579 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 580 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 581 582 // Store on condition. Expanded from CondStore* pseudos. 583 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 584 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 585 586 // Define AsmParser extended mnemonics for each general condition-code mask. 587 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 588 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 589 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 590 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 591 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 592 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 593 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 594 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 595 } 596} 597//===----------------------------------------------------------------------===// 598// Sign extensions 599//===----------------------------------------------------------------------===// 600// 601// Note that putting these before zero extensions mean that we will prefer 602// them for anyextload*. There's not really much to choose between the two 603// either way, but signed-extending loads have a short LH and a long LHY, 604// while zero-extending loads have only the long LLH. 605// 606//===----------------------------------------------------------------------===// 607 608// 32-bit extensions from registers. 609def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 610def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 611 612// 64-bit extensions from registers. 613def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 614def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 615def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 616 617let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 618 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 619 620// Match 32-to-64-bit sign extensions in which the source is already 621// in a 64-bit register. 622def : Pat<(sext_inreg GR64:$src, i32), 623 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 624 625// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 626// depending on the choice of register. 627def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 628 Requires<[FeatureHighWord]>; 629def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 630def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 631 Requires<[FeatureHighWord]>; 632 633// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 634// depending on the choice of register. 635def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 636 Requires<[FeatureHighWord]>; 637defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 638def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 639 Requires<[FeatureHighWord]>; 640def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 641 642// 64-bit extensions from memory. 643def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 644def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 645def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 646def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 647def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 648let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 649 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 650 651//===----------------------------------------------------------------------===// 652// Zero extensions 653//===----------------------------------------------------------------------===// 654 655// 32-bit extensions from registers. 656 657// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 658def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 659 Requires<[FeatureHighWord]>; 660def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 661// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 662def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 663 Requires<[FeatureHighWord]>; 664def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 665 666// 64-bit extensions from registers. 667def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 668def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 669def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 670 671// Match 32-to-64-bit zero extensions in which the source is already 672// in a 64-bit register. 673def : Pat<(and GR64:$src, 0xffffffff), 674 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 675 676// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 677// depending on the choice of register. 678def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 679 Requires<[FeatureHighWord]>; 680def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 681def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 682 Requires<[FeatureHighWord]>; 683 684// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 685// depending on the choice of register. 686def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 687 Requires<[FeatureHighWord]>; 688def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 689def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 690 Requires<[FeatureHighWord]>; 691def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 692 693// 64-bit extensions from memory. 694def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 695def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 696def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 697def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 698def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 699 700// 31-to-64-bit zero extensions. 701def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 702def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 703def : Pat<(and GR64:$src, 0x7fffffff), 704 (LLGTR GR64:$src)>; 705def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 706 (LLGT bdxaddr20only:$src)>; 707 708// Load and zero rightmost byte. 709let Predicates = [FeatureLoadAndZeroRightmostByte] in { 710 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 711 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 712 (LLZRGF bdxaddr20only:$src)>; 713} 714 715// Load and trap. 716let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 717 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 718 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 719} 720 721// Extend GR64s to GR128s. 722let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 723 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 724 725//===----------------------------------------------------------------------===// 726// "Any" extensions 727//===----------------------------------------------------------------------===// 728 729// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 730def : Pat<(i64 (anyext GR32:$src)), 731 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 732 733// Extend GR64s to GR128s. 734let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 735 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 736 737//===----------------------------------------------------------------------===// 738// Truncations 739//===----------------------------------------------------------------------===// 740 741// Truncations of 64-bit registers to 32-bit registers. 742def : Pat<(i32 (trunc GR64:$src)), 743 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 744 745// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 746// STC, STCY or STCH, depending on the choice of register. 747def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 748 Requires<[FeatureHighWord]>; 749defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 750def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 751 Requires<[FeatureHighWord]>; 752 753// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 754// STH, STHY or STHH, depending on the choice of register. 755def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 756 Requires<[FeatureHighWord]>; 757defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 758def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 759 Requires<[FeatureHighWord]>; 760def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 761 762// Truncations of 64-bit registers to memory. 763defm : StoreGR64Pair<STC, STCY, truncstorei8>; 764defm : StoreGR64Pair<STH, STHY, truncstorei16>; 765def : StoreGR64PC<STHRL, aligned_truncstorei16>; 766defm : StoreGR64Pair<ST, STY, truncstorei32>; 767def : StoreGR64PC<STRL, aligned_truncstorei32>; 768 769// Store characters under mask -- not (yet) used for codegen. 770defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 771def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 772 773//===----------------------------------------------------------------------===// 774// Multi-register moves 775//===----------------------------------------------------------------------===// 776 777// Multi-register loads. 778defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 779def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 780def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 781def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 782 783// Multi-register stores. 784defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 785def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 786def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 787 788//===----------------------------------------------------------------------===// 789// Byte swaps 790//===----------------------------------------------------------------------===// 791 792// Byte-swapping register moves. 793def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 794def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 795 796// Byte-swapping loads. 797def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 798def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 799def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 800 801// Byte-swapping stores. 802def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 803def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 804def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 805 806// Byte-swapping memory-to-memory moves. 807let mayLoad = 1, mayStore = 1 in 808 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 809 810//===----------------------------------------------------------------------===// 811// Load address instructions 812//===----------------------------------------------------------------------===// 813 814// Load BDX-style addresses. 815let isAsCheapAsAMove = 1, isReMaterializable = 1 in 816 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 817 818// Load a PC-relative address. There's no version of this instruction 819// with a 16-bit offset, so there's no relaxation. 820let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 821 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 822 823// Load the Global Offset Table address. This will be lowered into a 824// larl $R1, _GLOBAL_OFFSET_TABLE_ 825// instruction. 826def GOT : Alias<6, (outs GR64:$R1), (ins), 827 [(set GR64:$R1, (global_offset_table))]>; 828 829//===----------------------------------------------------------------------===// 830// Absolute and Negation 831//===----------------------------------------------------------------------===// 832 833let Defs = [CC] in { 834 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 835 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 836 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 837 } 838 let CCValues = 0xE, CompareZeroCCMask = 0xE in 839 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 840} 841def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 842def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 843defm : SXU<z_iabs, LPGFR>; 844defm : SXU<z_iabs64, LPGFR>; 845 846let Defs = [CC] in { 847 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 848 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 849 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 850 } 851 let CCValues = 0xE, CompareZeroCCMask = 0xE in 852 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 853} 854def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 855def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 856defm : SXU<z_inegabs, LNGFR>; 857defm : SXU<z_inegabs64, LNGFR>; 858 859let Defs = [CC] in { 860 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 861 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 862 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 863 } 864 let CCValues = 0xE, CompareZeroCCMask = 0xE in 865 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 866} 867defm : SXU<ineg, LCGFR>; 868 869//===----------------------------------------------------------------------===// 870// Insertion 871//===----------------------------------------------------------------------===// 872 873let isCodeGenOnly = 1 in 874 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 875defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 876 877defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 878defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 879 880defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 881defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 882 883// Insert characters under mask -- not (yet) used for codegen. 884let Defs = [CC] in { 885 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 886 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 887} 888 889// Insertions of a 16-bit immediate, leaving other bits unaffected. 890// We don't have or_as_insert equivalents of these operations because 891// OI is available instead. 892// 893// IIxMux expands to II[LH]x, depending on the choice of register. 894def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 895 Requires<[FeatureHighWord]>; 896def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 897 Requires<[FeatureHighWord]>; 898def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 899def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 900def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 901def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 902def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 903def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 904def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 905def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 906 907// ...likewise for 32-bit immediates. For GR32s this is a general 908// full-width move. (We use IILF rather than something like LLILF 909// for 32-bit moves because IILF leaves the upper 32 bits of the 910// GR64 unchanged.) 911let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 912 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 913 Requires<[FeatureHighWord]>; 914 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 915 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 916} 917def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 918def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 919 920// An alternative model of inserthf, with the first operand being 921// a zero-extended value. 922def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 923 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 924 imm64hf32:$imm)>; 925 926//===----------------------------------------------------------------------===// 927// Addition 928//===----------------------------------------------------------------------===// 929 930// Addition producing a signed overflow flag. 931let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 932 // Addition of a register. 933 let isCommutable = 1 in { 934 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 935 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 936 } 937 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 938 939 // Addition to a high register. 940 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 941 Requires<[FeatureHighWord]>; 942 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 943 Requires<[FeatureHighWord]>; 944 945 // Addition of signed 16-bit immediates. 946 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 947 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 948 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 949 950 // Addition of signed 32-bit immediates. 951 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 952 Requires<[FeatureHighWord]>; 953 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 954 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 955 Requires<[FeatureHighWord]>; 956 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 957 958 // Addition of memory. 959 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 960 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 961 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 962 Requires<[FeatureMiscellaneousExtensions2]>; 963 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 964 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 965 966 // Addition to memory. 967 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 968 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 969} 970defm : SXB<z_sadd, GR64, AGFR>; 971 972// Addition producing a carry. 973let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 974 // Addition of a register. 975 let isCommutable = 1 in { 976 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 977 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 978 } 979 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 980 981 // Addition to a high register. 982 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 983 Requires<[FeatureHighWord]>; 984 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 985 Requires<[FeatureHighWord]>; 986 987 // Addition of signed 16-bit immediates. 988 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 989 Requires<[FeatureDistinctOps]>; 990 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 991 Requires<[FeatureDistinctOps]>; 992 993 // Addition of unsigned 32-bit immediates. 994 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 995 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 996 997 // Addition of signed 32-bit immediates. 998 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 999 Requires<[FeatureHighWord]>; 1000 1001 // Addition of memory. 1002 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1003 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1004 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1005 1006 // Addition to memory. 1007 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1008 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1009} 1010defm : ZXB<z_uadd, GR64, ALGFR>; 1011 1012// Addition producing and using a carry. 1013let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1014 // Addition of a register. 1015 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1016 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1017 1018 // Addition of memory. 1019 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1020 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1021} 1022 1023// Addition that does not modify the condition code. 1024def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1025 Requires<[FeatureHighWord]>; 1026 1027 1028//===----------------------------------------------------------------------===// 1029// Subtraction 1030//===----------------------------------------------------------------------===// 1031 1032// Subtraction producing a signed overflow flag. 1033let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1034 CCIfNoSignedWrap = 1 in { 1035 // Subtraction of a register. 1036 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1037 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1038 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1039 1040 // Subtraction from a high register. 1041 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1042 Requires<[FeatureHighWord]>; 1043 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1044 Requires<[FeatureHighWord]>; 1045 1046 // Subtraction of memory. 1047 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1048 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1049 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1050 Requires<[FeatureMiscellaneousExtensions2]>; 1051 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1052 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1053} 1054defm : SXB<z_ssub, GR64, SGFR>; 1055 1056// Subtracting an immediate is the same as adding the negated immediate. 1057let AddedComplexity = 1 in { 1058 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1059 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1060 Requires<[FeatureHighWord]>; 1061 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1062 (AFIMux GR32:$src1, simm32n:$src2)>, 1063 Requires<[FeatureHighWord]>; 1064 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1065 (AHI GR32:$src1, imm32sx16n:$src2)>; 1066 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1067 (AFI GR32:$src1, simm32n:$src2)>; 1068 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1069 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1070 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1071 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1072} 1073 1074// And vice versa in one special case, where we need to load a 1075// constant into a register in any case, but the negated constant 1076// requires fewer instructions to load. 1077def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1078 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1079def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1080 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1081 1082// Subtraction producing a carry. 1083let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1084 // Subtraction of a register. 1085 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1086 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1087 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1088 1089 // Subtraction from a high register. 1090 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1091 Requires<[FeatureHighWord]>; 1092 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1093 Requires<[FeatureHighWord]>; 1094 1095 // Subtraction of unsigned 32-bit immediates. 1096 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1097 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1098 1099 // Subtraction of memory. 1100 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1101 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1102 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1103} 1104defm : ZXB<z_usub, GR64, SLGFR>; 1105 1106// Subtracting an immediate is the same as adding the negated immediate. 1107let AddedComplexity = 1 in { 1108 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1109 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1110 Requires<[FeatureDistinctOps]>; 1111 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1112 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1113 Requires<[FeatureDistinctOps]>; 1114} 1115 1116// And vice versa in one special case (but we prefer addition). 1117def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1118 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1119 1120// Subtraction producing and using a carry. 1121let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1122 // Subtraction of a register. 1123 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1124 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1125 1126 // Subtraction of memory. 1127 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1128 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1129} 1130 1131 1132//===----------------------------------------------------------------------===// 1133// AND 1134//===----------------------------------------------------------------------===// 1135 1136let Defs = [CC] in { 1137 // ANDs of a register. 1138 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1139 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1140 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1141 } 1142 1143 let isConvertibleToThreeAddress = 1 in { 1144 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1145 // The CC result only reflects the 16-bit field, not the full register. 1146 // 1147 // NIxMux expands to NI[LH]x, depending on the choice of register. 1148 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1149 Requires<[FeatureHighWord]>; 1150 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1151 Requires<[FeatureHighWord]>; 1152 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1153 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1154 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1155 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1156 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1157 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1158 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1159 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1160 1161 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1162 // The CC result only reflects the 32-bit field, which means we can 1163 // use it as a zero indicator for i32 operations but not otherwise. 1164 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1165 // Expands to NILF or NIHF, depending on the choice of register. 1166 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1167 Requires<[FeatureHighWord]>; 1168 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1169 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1170 } 1171 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1172 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1173 } 1174 1175 // ANDs of memory. 1176 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1177 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1178 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1179 } 1180 1181 // AND to memory 1182 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1183 1184 // Block AND. 1185 let mayLoad = 1, mayStore = 1 in 1186 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1187} 1188defm : RMWIByte<and, bdaddr12pair, NI>; 1189defm : RMWIByte<and, bdaddr20pair, NIY>; 1190 1191//===----------------------------------------------------------------------===// 1192// OR 1193//===----------------------------------------------------------------------===// 1194 1195let Defs = [CC] in { 1196 // ORs of a register. 1197 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1198 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1199 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1200 } 1201 1202 // ORs of a 16-bit immediate, leaving other bits unaffected. 1203 // The CC result only reflects the 16-bit field, not the full register. 1204 // 1205 // OIxMux expands to OI[LH]x, depending on the choice of register. 1206 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1207 Requires<[FeatureHighWord]>; 1208 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1209 Requires<[FeatureHighWord]>; 1210 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1211 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1212 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1213 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1214 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1215 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1216 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1217 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1218 1219 // ORs of a 32-bit immediate, leaving other bits unaffected. 1220 // The CC result only reflects the 32-bit field, which means we can 1221 // use it as a zero indicator for i32 operations but not otherwise. 1222 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1223 // Expands to OILF or OIHF, depending on the choice of register. 1224 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1225 Requires<[FeatureHighWord]>; 1226 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1227 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1228 } 1229 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1230 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1231 1232 // ORs of memory. 1233 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1234 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1235 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1236 } 1237 1238 // OR to memory 1239 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1240 1241 // Block OR. 1242 let mayLoad = 1, mayStore = 1 in 1243 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1244} 1245defm : RMWIByte<or, bdaddr12pair, OI>; 1246defm : RMWIByte<or, bdaddr20pair, OIY>; 1247 1248//===----------------------------------------------------------------------===// 1249// XOR 1250//===----------------------------------------------------------------------===// 1251 1252let Defs = [CC] in { 1253 // XORs of a register. 1254 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1255 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1256 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1257 } 1258 1259 // XORs of a 32-bit immediate, leaving other bits unaffected. 1260 // The CC result only reflects the 32-bit field, which means we can 1261 // use it as a zero indicator for i32 operations but not otherwise. 1262 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1263 // Expands to XILF or XIHF, depending on the choice of register. 1264 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1265 Requires<[FeatureHighWord]>; 1266 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1267 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1268 } 1269 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1270 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1271 1272 // XORs of memory. 1273 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1274 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1275 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1276 } 1277 1278 // XOR to memory 1279 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1280 1281 // Block XOR. 1282 let mayLoad = 1, mayStore = 1 in 1283 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1284} 1285defm : RMWIByte<xor, bdaddr12pair, XI>; 1286defm : RMWIByte<xor, bdaddr20pair, XIY>; 1287 1288//===----------------------------------------------------------------------===// 1289// Combined logical operations 1290//===----------------------------------------------------------------------===// 1291 1292let Predicates = [FeatureMiscellaneousExtensions3], 1293 Defs = [CC] in { 1294 // AND with complement. 1295 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1296 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1297 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1298 } 1299 1300 // OR with complement. 1301 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1302 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1303 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1304 } 1305 1306 // NAND. 1307 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1308 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1309 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1310 } 1311 1312 // NOR. 1313 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1314 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1315 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1316 } 1317 1318 // NXOR. 1319 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1320 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1321 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1322 } 1323} 1324 1325//===----------------------------------------------------------------------===// 1326// Multiplication 1327//===----------------------------------------------------------------------===// 1328 1329// Multiplication of a register, setting the condition code. We prefer these 1330// over MS(G)R if available, even though we cannot use the condition code, 1331// since they are three-operand instructions. 1332let Predicates = [FeatureMiscellaneousExtensions2], 1333 Defs = [CC], isCommutable = 1 in { 1334 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1335 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1336} 1337 1338// Multiplication of a register. 1339let isCommutable = 1 in { 1340 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1341 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1342} 1343def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1344defm : SXB<mul, GR64, MSGFR>; 1345 1346// Multiplication of a signed 16-bit immediate. 1347def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1348def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1349 1350// Multiplication of a signed 32-bit immediate. 1351def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1352def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1353 1354// Multiplication of memory. 1355defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1356defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1357def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1358 Requires<[FeatureMiscellaneousExtensions2]>; 1359def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1360def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1361 1362// Multiplication of memory, setting the condition code. 1363let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1364 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1365 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1366} 1367 1368// Multiplication of a register, producing two results. 1369def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1370def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1371 Requires<[FeatureMiscellaneousExtensions2]>; 1372def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1373def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1374 1375def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1376 (MGRK GR64:$src1, GR64:$src2)>; 1377def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1378 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1379 1380// Multiplication of memory, producing two results. 1381def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1382def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1383def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1384 Requires<[FeatureMiscellaneousExtensions2]>; 1385def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1386def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1387 1388def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1389 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1390def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1391 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1392 1393//===----------------------------------------------------------------------===// 1394// Division and remainder 1395//===----------------------------------------------------------------------===// 1396 1397let hasSideEffects = 1 in { // Do not speculatively execute. 1398 // Division and remainder, from registers. 1399 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1400 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1401 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1402 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1403 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1404 1405 // Division and remainder, from memory. 1406 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1407 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1408 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1409 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1410 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1411} 1412def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1413 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1414def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1415 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1416def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1417 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1418def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1419 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1420 1421def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1422 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1423 subreg_l32)), GR32:$src2)>; 1424def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1425 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1426 subreg_l32)), bdxaddr20only:$src2)>; 1427def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1428 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1429def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1430 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1431 1432//===----------------------------------------------------------------------===// 1433// Shifts 1434//===----------------------------------------------------------------------===// 1435 1436// Logical shift left. 1437defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1438def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1439def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1440 1441// Arithmetic shift left. 1442let Defs = [CC] in { 1443 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1444 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1445 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1446} 1447 1448// Logical shift right. 1449defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1450def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1451def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1452 1453// Arithmetic shift right. 1454let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1455 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1456 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1457 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1458} 1459 1460// Rotate left. 1461def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1462def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1463 1464// Rotate second operand left and inserted selected bits into first operand. 1465// These can act like 32-bit operands provided that the constant start and 1466// end bits (operands 2 and 3) are in the range [32, 64). 1467let Defs = [CC] in { 1468 let isCodeGenOnly = 1 in 1469 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1470 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1471 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1472} 1473 1474// On zEC12 we have a variant of RISBG that does not set CC. 1475let Predicates = [FeatureMiscellaneousExtensions] in 1476 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1477 1478// Forms of RISBG that only affect one word of the destination register. 1479// They do not set CC. 1480let Predicates = [FeatureHighWord] in { 1481 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1482 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1483 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1484 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1485 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1486 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1487 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1488} 1489 1490// Rotate second operand left and perform a logical operation with selected 1491// bits of the first operand. The CC result only describes the selected bits, 1492// so isn't useful for a full comparison against zero. 1493let Defs = [CC] in { 1494 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1495 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1496 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1497} 1498 1499//===----------------------------------------------------------------------===// 1500// Comparison 1501//===----------------------------------------------------------------------===// 1502 1503// Signed comparisons. We put these before the unsigned comparisons because 1504// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1505// of the unsigned forms do. 1506let Defs = [CC], CCValues = 0xE in { 1507 // Comparison with a register. 1508 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1509 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1510 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1511 1512 // Comparison with a high register. 1513 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1514 Requires<[FeatureHighWord]>; 1515 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1516 Requires<[FeatureHighWord]>; 1517 1518 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1519 // depending on the choice of register. 1520 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1521 Requires<[FeatureHighWord]>; 1522 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1523 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1524 1525 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1526 // depending on the choice of register. 1527 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1528 Requires<[FeatureHighWord]>; 1529 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1530 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1531 Requires<[FeatureHighWord]>; 1532 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1533 1534 // Comparison with memory. 1535 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1536 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1537 Requires<[FeatureHighWord]>; 1538 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1539 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1540 Requires<[FeatureHighWord]>; 1541 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1542 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1543 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1544 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1545 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1546 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1547 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1548 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1549 1550 // Comparison between memory and a signed 16-bit immediate. 1551 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1552 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1553 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1554} 1555defm : SXB<z_scmp, GR64, CGFR>; 1556 1557// Unsigned comparisons. 1558let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1559 // Comparison with a register. 1560 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1561 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1562 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1563 1564 // Comparison with a high register. 1565 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1566 Requires<[FeatureHighWord]>; 1567 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1568 Requires<[FeatureHighWord]>; 1569 1570 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1571 // or CLIH, depending on the choice of register. 1572 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1573 Requires<[FeatureHighWord]>; 1574 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1575 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1576 Requires<[FeatureHighWord]>; 1577 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1578 1579 // Comparison with memory. 1580 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1581 Requires<[FeatureHighWord]>; 1582 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1583 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1584 Requires<[FeatureHighWord]>; 1585 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1586 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1587 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1588 aligned_azextloadi16>; 1589 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1590 aligned_load>; 1591 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1592 aligned_azextloadi16>; 1593 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1594 aligned_azextloadi32>; 1595 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1596 aligned_load>; 1597 1598 // Comparison between memory and an unsigned 8-bit immediate. 1599 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1600 1601 // Comparison between memory and an unsigned 16-bit immediate. 1602 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1603 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1604 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1605} 1606defm : ZXB<z_ucmp, GR64, CLGFR>; 1607 1608// Memory-to-memory comparison. 1609let mayLoad = 1, Defs = [CC] in { 1610 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1611 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1612 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1613 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1614} 1615 1616// String comparison. 1617let mayLoad = 1, Defs = [CC] in 1618 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1619 1620// Test under mask. 1621let Defs = [CC] in { 1622 // TMxMux expands to TM[LH]x, depending on the choice of register. 1623 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1624 Requires<[FeatureHighWord]>; 1625 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1626 Requires<[FeatureHighWord]>; 1627 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1628 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1629 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1630 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1631 1632 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1633 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1634 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1635 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1636 1637 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1638} 1639 1640def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1641def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1642 1643// Compare logical characters under mask -- not (yet) used for codegen. 1644let Defs = [CC] in { 1645 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1646 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1647} 1648 1649//===----------------------------------------------------------------------===// 1650// Prefetch and execution hint 1651//===----------------------------------------------------------------------===// 1652 1653let mayLoad = 1, mayStore = 1 in { 1654 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1655 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1656} 1657 1658let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1659 // Branch Prediction Preload 1660 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1661 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1662 1663 // Next Instruction Access Intent 1664 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1665} 1666 1667//===----------------------------------------------------------------------===// 1668// Atomic operations 1669//===----------------------------------------------------------------------===// 1670 1671// A serialization instruction that acts as a barrier for all memory 1672// accesses, which expands to "bcr 14, 0". 1673let hasSideEffects = 1 in 1674def Serialize : Alias<2, (outs), (ins), []>; 1675 1676// A pseudo instruction that serves as a compiler barrier. 1677let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1678def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1679 1680let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1681 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1682 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1683 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1684 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1685 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1686 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1687 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1688 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1689 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1690 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1691} 1692 1693def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1694def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1695def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1696 1697def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1698def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1699let Predicates = [FeatureNoInterlockedAccess1] in { 1700 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1701 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1702 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1703 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1704 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1705 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1706} 1707 1708def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1709def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1710def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1711 1712def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1713def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1714let Predicates = [FeatureNoInterlockedAccess1] in { 1715 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1716 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1717 imm32ll16c>; 1718 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1719 imm32lh16c>; 1720 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1721 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1722 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1723 imm64ll16c>; 1724 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1725 imm64lh16c>; 1726 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1727 imm64hl16c>; 1728 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1729 imm64hh16c>; 1730 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1731 imm64lf32c>; 1732 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1733 imm64hf32c>; 1734} 1735 1736def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1737def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1738let Predicates = [FeatureNoInterlockedAccess1] in { 1739 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1740 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1741 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1742 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1743 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1744 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1745 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1746 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1747 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1748 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1749 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1750} 1751 1752def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1753def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1754let Predicates = [FeatureNoInterlockedAccess1] in { 1755 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1756 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1757 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1758 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1759 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1760} 1761 1762def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1763def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1764 imm32lh16c>; 1765def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1766def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1767 imm32ll16c>; 1768def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1769 imm32lh16c>; 1770def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1771def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1772def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1773 imm64ll16c>; 1774def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1775 imm64lh16c>; 1776def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1777 imm64hl16c>; 1778def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1779 imm64hh16c>; 1780def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1781 imm64lf32c>; 1782def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1783 imm64hf32c>; 1784 1785def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1786def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1787def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1788 1789def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1790def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1791def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1792 1793def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1794def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1795def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1796 1797def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1798def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1799def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1800 1801def ATOMIC_CMP_SWAPW 1802 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1803 ADDR32:$bitshift, ADDR32:$negbitshift, 1804 uimm32:$bitsize), 1805 [(set GR32:$dst, 1806 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1807 ADDR32:$bitshift, ADDR32:$negbitshift, 1808 uimm32:$bitsize))]> { 1809 let Defs = [CC]; 1810 let mayLoad = 1; 1811 let mayStore = 1; 1812 let usesCustomInserter = 1; 1813 let hasNoSchedulingInfo = 1; 1814} 1815 1816// Test and set. 1817let mayLoad = 1, Defs = [CC] in 1818 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1819 1820// Compare and swap. 1821let Defs = [CC] in { 1822 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1823 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1824} 1825 1826// Compare double and swap. 1827let Defs = [CC] in { 1828 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1829 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1830} 1831 1832// Compare and swap and store. 1833let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1834 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1835 1836// Perform locked operation. 1837let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1838 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1839 1840// Load/store pair from/to quadword. 1841def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1842def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1843 1844// Load pair disjoint. 1845let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1846 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1847 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1848} 1849 1850//===----------------------------------------------------------------------===// 1851// Translate and convert 1852//===----------------------------------------------------------------------===// 1853 1854let mayLoad = 1, mayStore = 1 in 1855 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1856 1857let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1858 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1859 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1860} 1861 1862let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1863 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1864 1865let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1866 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1867 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1868} 1869 1870let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1871 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1872 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1873 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1874 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1875} 1876 1877let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1878 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1879 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1880 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1881 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1882 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1883 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1884 1885 let isAsmParserOnly = 1 in { 1886 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1887 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1888 } 1889} 1890 1891//===----------------------------------------------------------------------===// 1892// Message-security assist 1893//===----------------------------------------------------------------------===// 1894 1895let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1896 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1897 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1898 1899 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1900 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1901 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1902 1903 let Predicates = [FeatureMessageSecurityAssist4] in { 1904 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1905 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1906 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1907 GR128, GR128, GR128>; 1908 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1909 } 1910 1911 let Predicates = [FeatureMessageSecurityAssist5] in 1912 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1913 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1914 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1915 1916 let Predicates = [FeatureMessageSecurityAssist8] in 1917 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1918 GR128, GR128, GR128>; 1919 1920 let Predicates = [FeatureMessageSecurityAssist9] in 1921 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1922} 1923 1924//===----------------------------------------------------------------------===// 1925// Guarded storage 1926//===----------------------------------------------------------------------===// 1927 1928// These instructions use and/or modify the guarded storage control 1929// registers, which we do not otherwise model, so they should have 1930// hasSideEffects. 1931let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1932 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1933 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1934 1935 let mayLoad = 1 in 1936 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1937 let mayStore = 1 in 1938 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1939} 1940 1941//===----------------------------------------------------------------------===// 1942// Decimal arithmetic 1943//===----------------------------------------------------------------------===// 1944 1945defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1946def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1947 1948defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1949def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1950 1951let mayLoad = 1, mayStore = 1 in { 1952 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1953 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1954 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1955 1956 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1957 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1958 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1959 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1960 let Defs = [CC] in { 1961 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1962 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1963 } 1964} 1965 1966let mayLoad = 1, mayStore = 1 in { 1967 let Defs = [CC] in { 1968 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1969 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1970 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1971 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1972 } 1973 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1974 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1975 let Defs = [CC] in { 1976 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1977 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1978 } 1979} 1980 1981let Defs = [CC] in { 1982 def CP : CompareSSb<"cp", 0xF9>; 1983 def TP : TestRSL<"tp", 0xEBC0>; 1984} 1985 1986//===----------------------------------------------------------------------===// 1987// Access registers 1988//===----------------------------------------------------------------------===// 1989 1990// Read a 32-bit access register into a GR32. As with all GR32 operations, 1991// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1992// when a 64-bit address is stored in a pair of access registers. 1993def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1994 1995// Set access register. 1996def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1997 1998// Copy access register. 1999def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2000 2001// Load address extended. 2002defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2003 2004// Load access multiple. 2005defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2006 2007// Store access multiple. 2008defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2009 2010//===----------------------------------------------------------------------===// 2011// Program mask and addressing mode 2012//===----------------------------------------------------------------------===// 2013 2014// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2015let Uses = [CC] in 2016 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2017 2018// Set CC and program mask from a register. 2019let hasSideEffects = 1, Defs = [CC] in 2020 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2021 2022// Branch and link - like BAS, but also extracts CC and program mask. 2023let isCall = 1, Uses = [CC], Defs = [CC] in { 2024 def BAL : CallRX<"bal", 0x45>; 2025 def BALR : CallRR<"balr", 0x05>; 2026} 2027 2028// Test addressing mode. 2029let Defs = [CC] in 2030 def TAM : SideEffectInherentE<"tam", 0x010B>; 2031 2032// Set addressing mode. 2033let hasSideEffects = 1 in { 2034 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2035 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2036 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2037} 2038 2039// Branch and set mode. Not really a call, but also sets an output register. 2040let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2041 def BSM : CallRR<"bsm", 0x0B>; 2042 2043// Branch and save and set mode. 2044let isCall = 1, Defs = [CC] in 2045 def BASSM : CallRR<"bassm", 0x0C>; 2046 2047//===----------------------------------------------------------------------===// 2048// Transactional execution 2049//===----------------------------------------------------------------------===// 2050 2051let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2052 // Transaction Begin 2053 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2054 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2055 let hasNoSchedulingInfo = 1 in 2056 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2057 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2058 int_s390_tbeginc, imm32zx16>; 2059 } 2060 2061 // Transaction End 2062 let Defs = [CC] in 2063 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2064 2065 // Transaction Abort 2066 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2067 hasSideEffects = 1 in 2068 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2069 2070 // Nontransactional Store 2071 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2072 2073 // Extract Transaction Nesting Depth 2074 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2075} 2076 2077//===----------------------------------------------------------------------===// 2078// Processor assist 2079//===----------------------------------------------------------------------===// 2080 2081let Predicates = [FeatureProcessorAssist] in { 2082 let hasSideEffects = 1 in 2083 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2084 def : Pat<(int_s390_ppa_txassist GR32:$src), 2085 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2086 zero_reg, 1)>; 2087} 2088 2089//===----------------------------------------------------------------------===// 2090// Miscellaneous Instructions. 2091//===----------------------------------------------------------------------===// 2092 2093// Find leftmost one, AKA count leading zeros. The instruction actually 2094// returns a pair of GR64s, the first giving the number of leading zeros 2095// and the second giving a copy of the source with the leftmost one bit 2096// cleared. We only use the first result here. 2097let Defs = [CC] in 2098 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2099def : Pat<(i64 (ctlz GR64:$src)), 2100 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2101 2102// Population count. Counts bits set per byte or doubleword. 2103let Predicates = [FeatureMiscellaneousExtensions3] in { 2104 let Defs = [CC] in 2105 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2106 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2107} 2108let Predicates = [FeaturePopulationCount], Defs = [CC] in 2109 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2110 2111// Search a block of memory for a character. 2112let mayLoad = 1, Defs = [CC] in 2113 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2114let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2115 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2116 2117// Compare until substring equal. 2118let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2119 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2120 2121// Compare and form codeword. 2122let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2123 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2124 2125// Update tree. 2126let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2127 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2128 def UPT : SideEffectInherentE<"upt", 0x0102>; 2129 2130// Checksum. 2131let mayLoad = 1, Defs = [CC] in 2132 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2133 2134// Compression call. 2135let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2136 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2137 2138// Sort lists. 2139let Predicates = [FeatureEnhancedSort], 2140 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2141 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2142 2143// Deflate conversion call. 2144let Predicates = [FeatureDeflateConversion], 2145 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2146 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2147 GR128, GR128, GR64>; 2148 2149// Execute. 2150let hasSideEffects = 1 in { 2151 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2152 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2153} 2154 2155//===----------------------------------------------------------------------===// 2156// .insn directive instructions 2157//===----------------------------------------------------------------------===// 2158 2159let isCodeGenOnly = 1, hasSideEffects = 1 in { 2160 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2161 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2162 imm32sx16:$I2), 2163 ".insn ri,$enc,$R1,$I2", []>; 2164 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2165 AnyReg:$R3, brtarget16:$I2), 2166 ".insn rie,$enc,$R1,$R3,$I2", []>; 2167 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2168 brtarget32:$I2), 2169 ".insn ril,$enc,$R1,$I2", []>; 2170 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2171 uimm32:$I2), 2172 ".insn rilu,$enc,$R1,$I2", []>; 2173 def InsnRIS : DirectiveInsnRIS<(outs), 2174 (ins imm64zx48:$enc, AnyReg:$R1, 2175 imm32sx8:$I2, imm32zx4:$M3, 2176 bdaddr12only:$BD4), 2177 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2178 def InsnRR : DirectiveInsnRR<(outs), 2179 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2180 ".insn rr,$enc,$R1,$R2", []>; 2181 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2182 AnyReg:$R1, AnyReg:$R2), 2183 ".insn rre,$enc,$R1,$R2", []>; 2184 def InsnRRF : DirectiveInsnRRF<(outs), 2185 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2186 AnyReg:$R3, imm32zx4:$M4), 2187 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2188 def InsnRRS : DirectiveInsnRRS<(outs), 2189 (ins imm64zx48:$enc, AnyReg:$R1, 2190 AnyReg:$R2, imm32zx4:$M3, 2191 bdaddr12only:$BD4), 2192 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2193 def InsnRS : DirectiveInsnRS<(outs), 2194 (ins imm64zx32:$enc, AnyReg:$R1, 2195 AnyReg:$R3, bdaddr12only:$BD2), 2196 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2197 def InsnRSE : DirectiveInsnRSE<(outs), 2198 (ins imm64zx48:$enc, AnyReg:$R1, 2199 AnyReg:$R3, bdaddr12only:$BD2), 2200 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2201 def InsnRSI : DirectiveInsnRSI<(outs), 2202 (ins imm64zx48:$enc, AnyReg:$R1, 2203 AnyReg:$R3, brtarget16:$RI2), 2204 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2205 def InsnRSY : DirectiveInsnRSY<(outs), 2206 (ins imm64zx48:$enc, AnyReg:$R1, 2207 AnyReg:$R3, bdaddr20only:$BD2), 2208 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2209 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2210 bdxaddr12only:$XBD2), 2211 ".insn rx,$enc,$R1,$XBD2", []>; 2212 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2213 bdxaddr12only:$XBD2), 2214 ".insn rxe,$enc,$R1,$XBD2", []>; 2215 def InsnRXF : DirectiveInsnRXF<(outs), 2216 (ins imm64zx48:$enc, AnyReg:$R1, 2217 AnyReg:$R3, bdxaddr12only:$XBD2), 2218 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2219 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2220 bdxaddr20only:$XBD2), 2221 ".insn rxy,$enc,$R1,$XBD2", []>; 2222 def InsnS : DirectiveInsnS<(outs), 2223 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2224 ".insn s,$enc,$BD2", []>; 2225 def InsnSI : DirectiveInsnSI<(outs), 2226 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2227 imm32sx8:$I2), 2228 ".insn si,$enc,$BD1,$I2", []>; 2229 def InsnSIY : DirectiveInsnSIY<(outs), 2230 (ins imm64zx48:$enc, 2231 bdaddr20only:$BD1, imm32zx8:$I2), 2232 ".insn siy,$enc,$BD1,$I2", []>; 2233 def InsnSIL : DirectiveInsnSIL<(outs), 2234 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2235 imm32zx16:$I2), 2236 ".insn sil,$enc,$BD1,$I2", []>; 2237 def InsnSS : DirectiveInsnSS<(outs), 2238 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2239 bdaddr12only:$BD2, AnyReg:$R3), 2240 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2241 def InsnSSE : DirectiveInsnSSE<(outs), 2242 (ins imm64zx48:$enc, 2243 bdaddr12only:$BD1,bdaddr12only:$BD2), 2244 ".insn sse,$enc,$BD1,$BD2", []>; 2245 def InsnSSF : DirectiveInsnSSF<(outs), 2246 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2247 bdaddr12only:$BD2, AnyReg:$R3), 2248 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2249 def InsnVRI : DirectiveInsnVRI<(outs), 2250 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2251 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2252 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2253 def InsnVRR : DirectiveInsnVRR<(outs), 2254 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2255 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2256 imm32zx4:$M6), 2257 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2258 def InsnVRS : DirectiveInsnVRS<(outs), 2259 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2260 bdaddr12only:$BD2, imm32zx4:$M4), 2261 ".insn vrs,$enc,$BD2,$M4", []>; 2262 def InsnVRV : DirectiveInsnVRV<(outs), 2263 (ins imm64zx48:$enc, VR128:$V1, 2264 bdvaddr12only:$VBD2, imm32zx4:$M3), 2265 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2266 def InsnVRX : DirectiveInsnVRX<(outs), 2267 (ins imm64zx48:$enc, VR128:$V1, 2268 bdxaddr12only:$XBD2, imm32zx4:$M3), 2269 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2270 def InsnVSI : DirectiveInsnVSI<(outs), 2271 (ins imm64zx48:$enc, VR128:$V1, 2272 bdaddr12only:$BD2, imm32zx8:$I3), 2273 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2274} 2275 2276//===----------------------------------------------------------------------===// 2277// Peepholes. 2278//===----------------------------------------------------------------------===// 2279 2280// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2281// equivalent to (and (xor x, -1), y) 2282def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2283 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2284 2285// Shift/rotate instructions only use the last 6 bits of the second operand 2286// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2287// last 16 bits. 2288// Complexity is added so that we match this before we match NILF on the AND 2289// operation alone. 2290let AddedComplexity = 4 in { 2291 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2292 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2293 2294 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2295 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2296 2297 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2298 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2299 2300 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2301 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2302 2303 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2304 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2305 2306 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2307 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2308 2309 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2310 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2311 2312 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2313 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2314} 2315 2316// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2317// use the last 6 bits of the second operand register (making it modulo 64). 2318let AddedComplexity = 4 in { 2319 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2320 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2321 2322 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2323 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2324 2325 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2326 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2327 2328 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2329 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2330} 2331 2332// Peepholes for turning scalar operations into block operations. 2333defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2334 XCSequence, 1>; 2335defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2336 XCSequence, 2>; 2337defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2338 XCSequence, 4>; 2339defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2340 OCSequence, XCSequence, 1>; 2341defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2342 XCSequence, 2>; 2343defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2344 XCSequence, 4>; 2345defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2346 XCSequence, 8>; 2347