1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 15 [(callseq_start timm:$amt)]>; 16def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_end timm:$amt1, timm:$amt2)]>; 18 19let hasSideEffects = 0 in { 20 // Takes as input the value of the stack pointer after a dynamic allocation 21 // has been made. Sets the output to the address of the dynamically- 22 // allocated area itself, skipping the outgoing arguments. 23 // 24 // This expands to an LA or LAY instruction. We restrict the offset 25 // to the range of LA and keep the LAY range in reserve for when 26 // the size of the outgoing arguments is added. 27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 28 [(set GR64:$dst, dynalloc12only:$src)]>; 29} 30 31//===----------------------------------------------------------------------===// 32// Control flow instructions 33//===----------------------------------------------------------------------===// 34 35// A return instruction (br %r14). 36let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 37 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 38 39// A conditional return instruction (bcr <cond>, %r14). 40let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 41 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 42 43// Fused compare and conditional returns. 44let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 45 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 46 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 47 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 48 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 49 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 50 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 51 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 52 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 53} 54 55// Unconditional branches. R1 is the condition-code mask (all 1s). 56let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { 57 let isIndirectBranch = 1 in 58 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), 59 "br\t$R2", [(brind ADDR64:$R2)]>; 60 61 // An assembler extended mnemonic for BRC. 62 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", 63 [(br bb:$I2)]>; 64 65 // An assembler extended mnemonic for BRCL. (The extension is "G" 66 // rather than "L" because "JL" is "Jump if Less".) 67 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>; 68} 69 70// Conditional branches. It's easier for LLVM to handle these branches 71// in their raw BRC/BRCL form, with the 4-bit condition-code mask being 72// the first operand. It seems friendlier to use mnemonic forms like 73// JE and JLH when writing out the assembly though. 74let isBranch = 1, isTerminator = 1, Uses = [CC] in { 75 let isCodeGenOnly = 1, CCMaskFirst = 1 in { 76 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1, 77 brtarget16:$I2), "j$R1\t$I2", 78 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>; 79 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1, 80 brtarget32:$I2), "jg$R1\t$I2", []>; 81 let isIndirectBranch = 1 in 82 def BCR : InstRR<0x07, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2), 83 "b${R1}r\t$R2", []>; 84 } 85 def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2), 86 "brc\t$R1, $I2", []>; 87 def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2), 88 "brcl\t$R1, $I2", []>; 89 let isIndirectBranch = 1 in { 90 def AsmBC : InstRX<0x47, (outs), (ins imm32zx4:$R1, bdxaddr12only:$XBD2), 91 "bc\t$R1, $XBD2", []>; 92 def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2), 93 "bcr\t$R1, $R2", []>; 94 } 95} 96 97def AsmNop : InstAlias<"nop\t$XBD", (AsmBC 0, bdxaddr12only:$XBD), 0>; 98def AsmNopR : InstAlias<"nopr\t$R", (AsmBCR 0, GR64:$R), 0>; 99 100// Fused compare-and-branch instructions. As for normal branches, 101// we handle these instructions internally in their raw CRJ-like form, 102// but use assembly macros like CRJE when writing them out. 103// 104// These instructions do not use or clobber the condition codes. 105// We nevertheless pretend that they clobber CC, so that we can lower 106// them to separate comparisons and BRCLs if the branch ends up being 107// out of range. 108multiclass CompareBranches<Operand ccmask, string pos1, string pos2> { 109 let isBranch = 1, isTerminator = 1, Defs = [CC] in { 110 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 111 brtarget16:$RI4), 112 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 113 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 114 brtarget16:$RI4), 115 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 116 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 117 brtarget16:$RI4), 118 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 119 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 120 brtarget16:$RI4), 121 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 122 def LRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 123 brtarget16:$RI4), 124 "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 125 def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 126 brtarget16:$RI4), 127 "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 128 def LIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3, 129 brtarget16:$RI4), 130 "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 131 def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3, 132 brtarget16:$RI4), 133 "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 134 let isIndirectBranch = 1 in { 135 def RB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 136 bdaddr12only:$BD4), 137 "crb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>; 138 def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 139 bdaddr12only:$BD4), 140 "cgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>; 141 def IB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 142 bdaddr12only:$BD4), 143 "cib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>; 144 def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 145 bdaddr12only:$BD4), 146 "cgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>; 147 def LRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 148 bdaddr12only:$BD4), 149 "clrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>; 150 def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 151 bdaddr12only:$BD4), 152 "clgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>; 153 def LIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3, 154 bdaddr12only:$BD4), 155 "clib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>; 156 def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3, 157 bdaddr12only:$BD4), 158 "clgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>; 159 } 160 } 161} 162let isCodeGenOnly = 1 in 163 defm C : CompareBranches<cond4, "$M3", "">; 164defm AsmC : CompareBranches<imm32zx4, "", "$M3, ">; 165 166// Define AsmParser mnemonics for each general condition-code mask 167// (integer or floating-point) 168multiclass CondExtendedMnemonic<bits<4> ccmask, string name> { 169 let isBranch = 1, isTerminator = 1, R1 = ccmask in { 170 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), 171 "j"##name##"\t$I2", []>; 172 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), 173 "jg"##name##"\t$I2", []>; 174 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>; 175 } 176 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>; 177 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>; 178 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>; 179 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>; 180 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>; 181 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>; 182} 183defm AsmO : CondExtendedMnemonic<1, "o">; 184defm AsmH : CondExtendedMnemonic<2, "h">; 185defm AsmNLE : CondExtendedMnemonic<3, "nle">; 186defm AsmL : CondExtendedMnemonic<4, "l">; 187defm AsmNHE : CondExtendedMnemonic<5, "nhe">; 188defm AsmLH : CondExtendedMnemonic<6, "lh">; 189defm AsmNE : CondExtendedMnemonic<7, "ne">; 190defm AsmE : CondExtendedMnemonic<8, "e">; 191defm AsmNLH : CondExtendedMnemonic<9, "nlh">; 192defm AsmHE : CondExtendedMnemonic<10, "he">; 193defm AsmNL : CondExtendedMnemonic<11, "nl">; 194defm AsmLE : CondExtendedMnemonic<12, "le">; 195defm AsmNH : CondExtendedMnemonic<13, "nh">; 196defm AsmNO : CondExtendedMnemonic<14, "no">; 197 198// Define AsmParser mnemonics for each integer condition-code mask. 199// This is like the list above, except that condition 3 is not possible 200// and that the low bit of the mask is therefore always 0. This means 201// that each condition has two names. Conditions "o" and "no" are not used. 202// 203// We don't make one of the two names an alias of the other because 204// we need the custom parsing routines to select the correct register class. 205multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> { 206 let isBranch = 1, isTerminator = 1, M3 = ccmask in { 207 def CRJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, 208 brtarget16:$RI4), 209 "crj"##name##"\t$R1, $R2, $RI4", []>; 210 def CGRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, 211 brtarget16:$RI4), 212 "cgrj"##name##"\t$R1, $R2, $RI4", []>; 213 def CIJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, 214 brtarget16:$RI4), 215 "cij"##name##"\t$R1, $I2, $RI4", []>; 216 def CGIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, 217 brtarget16:$RI4), 218 "cgij"##name##"\t$R1, $I2, $RI4", []>; 219 def CLRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, 220 brtarget16:$RI4), 221 "clrj"##name##"\t$R1, $R2, $RI4", []>; 222 def CLGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, 223 brtarget16:$RI4), 224 "clgrj"##name##"\t$R1, $R2, $RI4", []>; 225 def CLIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, 226 brtarget16:$RI4), 227 "clij"##name##"\t$R1, $I2, $RI4", []>; 228 def CLGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, 229 brtarget16:$RI4), 230 "clgij"##name##"\t$R1, $I2, $RI4", []>; 231 let isIndirectBranch = 1 in { 232 def CRB : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, 233 bdaddr12only:$BD4), 234 "crb"##name##"\t$R1, $R2, $BD4", []>; 235 def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, 236 bdaddr12only:$BD4), 237 "cgrb"##name##"\t$R1, $R2, $BD4", []>; 238 def CIB : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, 239 bdaddr12only:$BD4), 240 "cib"##name##"\t$R1, $I2, $BD4", []>; 241 def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, 242 bdaddr12only:$BD4), 243 "cgib"##name##"\t$R1, $I2, $BD4", []>; 244 def CLRB : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, 245 bdaddr12only:$BD4), 246 "clrb"##name##"\t$R1, $R2, $BD4", []>; 247 def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, 248 bdaddr12only:$BD4), 249 "clgrb"##name##"\t$R1, $R2, $BD4", []>; 250 def CLIB : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, 251 bdaddr12only:$BD4), 252 "clib"##name##"\t$R1, $I2, $BD4", []>; 253 def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, 254 bdaddr12only:$BD4), 255 "clgib"##name##"\t$R1, $I2, $BD4", []>; 256 } 257 } 258} 259multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 260 : IntCondExtendedMnemonicA<ccmask, name1> { 261 let isAsmParserOnly = 1 in 262 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>; 263} 264defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">; 265defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">; 266defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">; 267defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">; 268defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">; 269defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">; 270 271// Decrement a register and branch if it is nonzero. These don't clobber CC, 272// but we might need to split long branches into sequences that do. 273let Defs = [CC] in { 274 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 275 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 276} 277 278//===----------------------------------------------------------------------===// 279// Select instructions 280//===----------------------------------------------------------------------===// 281 282def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>; 283def Select32 : SelectWrapper<GR32>; 284def Select64 : SelectWrapper<GR64>; 285 286// We don't define 32-bit Mux stores because the low-only STOC should 287// always be used if possible. 288defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 289 nonvolatile_anyextloadi8, bdxaddr20only>, 290 Requires<[FeatureHighWord]>; 291defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 292 nonvolatile_anyextloadi16, bdxaddr20only>, 293 Requires<[FeatureHighWord]>; 294defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 295 nonvolatile_anyextloadi8, bdxaddr20only>; 296defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 297 nonvolatile_anyextloadi16, bdxaddr20only>; 298defm CondStore32 : CondStores<GR32, nonvolatile_store, 299 nonvolatile_load, bdxaddr20only>; 300 301defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 302 nonvolatile_anyextloadi8, bdxaddr20only>; 303defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 304 nonvolatile_anyextloadi16, bdxaddr20only>; 305defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 306 nonvolatile_anyextloadi32, bdxaddr20only>; 307defm CondStore64 : CondStores<GR64, nonvolatile_store, 308 nonvolatile_load, bdxaddr20only>; 309 310//===----------------------------------------------------------------------===// 311// Call instructions 312//===----------------------------------------------------------------------===// 313 314let isCall = 1, Defs = [R14D, CC] in { 315 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 316 [(z_call pcrel32:$I2)]>; 317 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 318 [(z_call ADDR64:$R2)]>; 319} 320 321// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 322// are argument registers and since branching to R0 is a no-op. 323let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 324 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 325 [(z_sibcall pcrel32:$I2)]>; 326 let Uses = [R1D] in 327 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 328} 329 330let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 331 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 332 pcrel32:$I2), []>; 333 334 let Uses = [R1D] in 335 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 336} 337 338// Fused compare and conditional sibling calls. 339let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 340 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 341 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 342 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 343 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 344 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 345 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 346 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 347 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 348} 349 350// TLS calls. These will be lowered into a call to __tls_get_offset, 351// with an extra relocation specifying the TLS symbol. 352let isCall = 1, Defs = [R14D, CC] in { 353 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 354 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 355 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 356 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 357} 358 359// Define the general form of the call instructions for the asm parser. 360// These instructions don't hard-code %r14 as the return address register. 361// Allow an optional TLS marker symbol to generate TLS call relocations. 362let isCall = 1, Defs = [CC] in { 363 def BRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16tls:$I2), 364 "bras\t$R1, $I2", []>; 365 def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32tls:$I2), 366 "brasl\t$R1, $I2", []>; 367 def BASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), 368 "basr\t$R1, $R2", []>; 369} 370 371//===----------------------------------------------------------------------===// 372// Move instructions 373//===----------------------------------------------------------------------===// 374 375// Register moves. 376let hasSideEffects = 0 in { 377 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 378 def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>, 379 Requires<[FeatureHighWord]>; 380 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>; 381 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>; 382} 383let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 384 def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>; 385 def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>; 386} 387 388// Move on condition. 389let isCodeGenOnly = 1, Uses = [CC] in { 390 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 391 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 392} 393let Uses = [CC] in { 394 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>; 395 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>; 396} 397 398// Immediate moves. 399let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 400 isReMaterializable = 1 in { 401 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 402 // deopending on the choice of register. 403 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 404 Requires<[FeatureHighWord]>; 405 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 406 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 407 408 // Other 16-bit immediates. 409 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 410 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 411 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 412 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 413 414 // 32-bit immediates. 415 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 416 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 417 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 418} 419 420// Register loads. 421let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 422 // Expands to L, LY or LFH, depending on the choice of register. 423 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 424 Requires<[FeatureHighWord]>; 425 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 426 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 427 Requires<[FeatureHighWord]>; 428 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 429 430 // These instructions are split after register allocation, so we don't 431 // want a custom inserter. 432 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 433 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 434 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 435 } 436} 437let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 438 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 439 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 440} 441 442let canFoldAsLoad = 1 in { 443 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 444 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 445} 446 447// Load on condition. 448let isCodeGenOnly = 1, Uses = [CC] in { 449 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 450 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 451} 452let Uses = [CC] in { 453 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>; 454 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>; 455} 456 457// Register stores. 458let SimpleBDXStore = 1 in { 459 // Expands to ST, STY or STFH, depending on the choice of register. 460 def STMux : StoreRXYPseudo<store, GRX32, 4>, 461 Requires<[FeatureHighWord]>; 462 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 463 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 464 Requires<[FeatureHighWord]>; 465 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 466 467 // These instructions are split after register allocation, so we don't 468 // want a custom inserter. 469 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 470 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 471 [(store GR128:$src, bdxaddr20only128:$dst)]>; 472 } 473} 474def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 475def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 476 477// Store on condition. 478let isCodeGenOnly = 1, Uses = [CC] in { 479 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 480 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 481} 482let Uses = [CC] in { 483 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>; 484 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>; 485} 486 487// 8-bit immediate stores to 8-bit fields. 488defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 489 490// 16-bit immediate stores to 16-, 32- or 64-bit fields. 491def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 492def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 493def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 494 495// Memory-to-memory moves. 496let mayLoad = 1, mayStore = 1 in 497 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 498 499// String moves. 500let mayLoad = 1, mayStore = 1, Defs = [CC] in 501 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 502 503//===----------------------------------------------------------------------===// 504// Sign extensions 505//===----------------------------------------------------------------------===// 506// 507// Note that putting these before zero extensions mean that we will prefer 508// them for anyextload*. There's not really much to choose between the two 509// either way, but signed-extending loads have a short LH and a long LHY, 510// while zero-extending loads have only the long LLH. 511// 512//===----------------------------------------------------------------------===// 513 514// 32-bit extensions from registers. 515let hasSideEffects = 0 in { 516 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>; 517 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>; 518} 519 520// 64-bit extensions from registers. 521let hasSideEffects = 0 in { 522 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>; 523 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>; 524 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>; 525} 526let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 527 def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR32>; 528 529// Match 32-to-64-bit sign extensions in which the source is already 530// in a 64-bit register. 531def : Pat<(sext_inreg GR64:$src, i32), 532 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 533 534// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 535// depending on the choice of register. 536def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 537 Requires<[FeatureHighWord]>; 538def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 539def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 540 Requires<[FeatureHighWord]>; 541 542// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 543// depending on the choice of register. 544def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 545 Requires<[FeatureHighWord]>; 546defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 547def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 548 Requires<[FeatureHighWord]>; 549def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 550 551// 64-bit extensions from memory. 552def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 553def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 554def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 555def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 556def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 557let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 558 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 559 560//===----------------------------------------------------------------------===// 561// Zero extensions 562//===----------------------------------------------------------------------===// 563 564// 32-bit extensions from registers. 565let hasSideEffects = 0 in { 566 // Expands to LLCR or RISB[LH]G, depending on the choice of registers. 567 def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>, 568 Requires<[FeatureHighWord]>; 569 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>; 570 // Expands to LLHR or RISB[LH]G, depending on the choice of registers. 571 def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>, 572 Requires<[FeatureHighWord]>; 573 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>; 574} 575 576// 64-bit extensions from registers. 577let hasSideEffects = 0 in { 578 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>; 579 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>; 580 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>; 581} 582 583// Match 32-to-64-bit zero extensions in which the source is already 584// in a 64-bit register. 585def : Pat<(and GR64:$src, 0xffffffff), 586 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 587 588// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 589// depending on the choice of register. 590def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 591 Requires<[FeatureHighWord]>; 592def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 593def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 594 Requires<[FeatureHighWord]>; 595 596// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 597// depending on the choice of register. 598def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 599 Requires<[FeatureHighWord]>; 600def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 601def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 602 Requires<[FeatureHighWord]>; 603def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 604 605// 64-bit extensions from memory. 606def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 607def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 608def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 609def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 610def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 611 612//===----------------------------------------------------------------------===// 613// Truncations 614//===----------------------------------------------------------------------===// 615 616// Truncations of 64-bit registers to 32-bit registers. 617def : Pat<(i32 (trunc GR64:$src)), 618 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 619 620// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 621// STC, STCY or STCH, depending on the choice of register. 622def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 623 Requires<[FeatureHighWord]>; 624defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 625def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 626 Requires<[FeatureHighWord]>; 627 628// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 629// STH, STHY or STHH, depending on the choice of register. 630def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 631 Requires<[FeatureHighWord]>; 632defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 633def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 634 Requires<[FeatureHighWord]>; 635def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 636 637// Truncations of 64-bit registers to memory. 638defm : StoreGR64Pair<STC, STCY, truncstorei8>; 639defm : StoreGR64Pair<STH, STHY, truncstorei16>; 640def : StoreGR64PC<STHRL, aligned_truncstorei16>; 641defm : StoreGR64Pair<ST, STY, truncstorei32>; 642def : StoreGR64PC<STRL, aligned_truncstorei32>; 643 644//===----------------------------------------------------------------------===// 645// Multi-register moves 646//===----------------------------------------------------------------------===// 647 648// Multi-register loads. 649def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 650 651// Multi-register stores. 652def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 653 654//===----------------------------------------------------------------------===// 655// Byte swaps 656//===----------------------------------------------------------------------===// 657 658// Byte-swapping register moves. 659let hasSideEffects = 0 in { 660 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>; 661 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>; 662} 663 664// Byte-swapping loads. Unlike normal loads, these instructions are 665// allowed to access storage more than once. 666def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>; 667def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>; 668 669// Likewise byte-swapping stores. 670def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>; 671def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>, 672 GR64, 8>; 673 674//===----------------------------------------------------------------------===// 675// Load address instructions 676//===----------------------------------------------------------------------===// 677 678// Load BDX-style addresses. 679let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1, 680 DispKey = "la" in { 681 let DispSize = "12" in 682 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2), 683 "la\t$R1, $XBD2", 684 [(set GR64:$R1, laaddr12pair:$XBD2)]>; 685 let DispSize = "20" in 686 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2), 687 "lay\t$R1, $XBD2", 688 [(set GR64:$R1, laaddr20pair:$XBD2)]>; 689} 690 691// Load a PC-relative address. There's no version of this instruction 692// with a 16-bit offset, so there's no relaxation. 693let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 694 isReMaterializable = 1 in { 695 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2), 696 "larl\t$R1, $I2", 697 [(set GR64:$R1, pcrel32:$I2)]>; 698} 699 700// Load the Global Offset Table address. This will be lowered into a 701// larl $R1, _GLOBAL_OFFSET_TABLE_ 702// instruction. 703def GOT : Alias<6, (outs GR64:$R1), (ins), 704 [(set GR64:$R1, (global_offset_table))]>; 705 706//===----------------------------------------------------------------------===// 707// Absolute and Negation 708//===----------------------------------------------------------------------===// 709 710let Defs = [CC] in { 711 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 712 def LPR : UnaryRR <"lp", 0x10, z_iabs, GR32, GR32>; 713 def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>; 714 } 715 let CCValues = 0xE, CompareZeroCCMask = 0xE in 716 def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>; 717} 718def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 719def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 720defm : SXU<z_iabs, LPGFR>; 721defm : SXU<z_iabs64, LPGFR>; 722 723let Defs = [CC] in { 724 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 725 def LNR : UnaryRR <"ln", 0x11, z_inegabs, GR32, GR32>; 726 def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>; 727 } 728 let CCValues = 0xE, CompareZeroCCMask = 0xE in 729 def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>; 730} 731def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 732def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 733defm : SXU<z_inegabs, LNGFR>; 734defm : SXU<z_inegabs64, LNGFR>; 735 736let Defs = [CC] in { 737 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 738 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>; 739 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>; 740 } 741 let CCValues = 0xE, CompareZeroCCMask = 0xE in 742 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>; 743} 744defm : SXU<ineg, LCGFR>; 745 746//===----------------------------------------------------------------------===// 747// Insertion 748//===----------------------------------------------------------------------===// 749 750let isCodeGenOnly = 1 in 751 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 752defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 753 754defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 755defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 756 757defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 758defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 759 760// Insertions of a 16-bit immediate, leaving other bits unaffected. 761// We don't have or_as_insert equivalents of these operations because 762// OI is available instead. 763// 764// IIxMux expands to II[LH]x, depending on the choice of register. 765def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 766 Requires<[FeatureHighWord]>; 767def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 768 Requires<[FeatureHighWord]>; 769def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 770def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 771def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 772def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 773def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 774def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 775def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 776def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 777 778// ...likewise for 32-bit immediates. For GR32s this is a general 779// full-width move. (We use IILF rather than something like LLILF 780// for 32-bit moves because IILF leaves the upper 32 bits of the 781// GR64 unchanged.) 782let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 783 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 784 Requires<[FeatureHighWord]>; 785 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 786 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 787} 788def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 789def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 790 791// An alternative model of inserthf, with the first operand being 792// a zero-extended value. 793def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 794 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 795 imm64hf32:$imm)>; 796 797//===----------------------------------------------------------------------===// 798// Addition 799//===----------------------------------------------------------------------===// 800 801// Plain addition. 802let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 803 // Addition of a register. 804 let isCommutable = 1 in { 805 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>; 806 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>; 807 } 808 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>; 809 810 // Addition of signed 16-bit immediates. 811 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 812 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 813 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 814 815 // Addition of signed 32-bit immediates. 816 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 817 Requires<[FeatureHighWord]>; 818 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 819 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 820 Requires<[FeatureHighWord]>; 821 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 822 823 // Addition of memory. 824 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 825 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 826 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 827 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 828 829 // Addition to memory. 830 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 831 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 832} 833defm : SXB<add, GR64, AGFR>; 834 835// Addition producing a carry. 836let Defs = [CC] in { 837 // Addition of a register. 838 let isCommutable = 1 in { 839 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>; 840 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>; 841 } 842 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>; 843 844 // Addition of signed 16-bit immediates. 845 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 846 Requires<[FeatureDistinctOps]>; 847 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 848 Requires<[FeatureDistinctOps]>; 849 850 // Addition of unsigned 32-bit immediates. 851 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 852 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 853 854 // Addition of memory. 855 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 856 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 857 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 858} 859defm : ZXB<addc, GR64, ALGFR>; 860 861// Addition producing and using a carry. 862let Defs = [CC], Uses = [CC] in { 863 // Addition of a register. 864 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>; 865 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>; 866 867 // Addition of memory. 868 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 869 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 870} 871 872//===----------------------------------------------------------------------===// 873// Subtraction 874//===----------------------------------------------------------------------===// 875 876// Plain subtraction. Although immediate forms exist, we use the 877// add-immediate instruction instead. 878let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 879 // Subtraction of a register. 880 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>; 881 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>; 882 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>; 883 884 // Subtraction of memory. 885 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 886 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 887 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 888 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 889} 890defm : SXB<sub, GR64, SGFR>; 891 892// Subtraction producing a carry. 893let Defs = [CC] in { 894 // Subtraction of a register. 895 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>; 896 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>; 897 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>; 898 899 // Subtraction of unsigned 32-bit immediates. These don't match 900 // subc because we prefer addc for constants. 901 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 902 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 903 904 // Subtraction of memory. 905 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 906 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 907 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 908} 909defm : ZXB<subc, GR64, SLGFR>; 910 911// Subtraction producing and using a carry. 912let Defs = [CC], Uses = [CC] in { 913 // Subtraction of a register. 914 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>; 915 def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>; 916 917 // Subtraction of memory. 918 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 919 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 920} 921 922//===----------------------------------------------------------------------===// 923// AND 924//===----------------------------------------------------------------------===// 925 926let Defs = [CC] in { 927 // ANDs of a register. 928 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 929 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>; 930 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>; 931 } 932 933 let isConvertibleToThreeAddress = 1 in { 934 // ANDs of a 16-bit immediate, leaving other bits unaffected. 935 // The CC result only reflects the 16-bit field, not the full register. 936 // 937 // NIxMux expands to NI[LH]x, depending on the choice of register. 938 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 939 Requires<[FeatureHighWord]>; 940 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 941 Requires<[FeatureHighWord]>; 942 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 943 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 944 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 945 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 946 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 947 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 948 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 949 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 950 951 // ANDs of a 32-bit immediate, leaving other bits unaffected. 952 // The CC result only reflects the 32-bit field, which means we can 953 // use it as a zero indicator for i32 operations but not otherwise. 954 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 955 // Expands to NILF or NIHF, depending on the choice of register. 956 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 957 Requires<[FeatureHighWord]>; 958 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 959 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 960 } 961 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 962 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 963 } 964 965 // ANDs of memory. 966 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 967 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 968 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 969 } 970 971 // AND to memory 972 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 973 974 // Block AND. 975 let mayLoad = 1, mayStore = 1 in 976 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 977} 978defm : RMWIByte<and, bdaddr12pair, NI>; 979defm : RMWIByte<and, bdaddr20pair, NIY>; 980 981//===----------------------------------------------------------------------===// 982// OR 983//===----------------------------------------------------------------------===// 984 985let Defs = [CC] in { 986 // ORs of a register. 987 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 988 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>; 989 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>; 990 } 991 992 // ORs of a 16-bit immediate, leaving other bits unaffected. 993 // The CC result only reflects the 16-bit field, not the full register. 994 // 995 // OIxMux expands to OI[LH]x, depending on the choice of register. 996 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 997 Requires<[FeatureHighWord]>; 998 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 999 Requires<[FeatureHighWord]>; 1000 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1001 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1002 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1003 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1004 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1005 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1006 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1007 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1008 1009 // ORs of a 32-bit immediate, leaving other bits unaffected. 1010 // The CC result only reflects the 32-bit field, which means we can 1011 // use it as a zero indicator for i32 operations but not otherwise. 1012 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1013 // Expands to OILF or OIHF, depending on the choice of register. 1014 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1015 Requires<[FeatureHighWord]>; 1016 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1017 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1018 } 1019 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1020 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1021 1022 // ORs of memory. 1023 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1024 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1025 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1026 } 1027 1028 // OR to memory 1029 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1030 1031 // Block OR. 1032 let mayLoad = 1, mayStore = 1 in 1033 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1034} 1035defm : RMWIByte<or, bdaddr12pair, OI>; 1036defm : RMWIByte<or, bdaddr20pair, OIY>; 1037 1038//===----------------------------------------------------------------------===// 1039// XOR 1040//===----------------------------------------------------------------------===// 1041 1042let Defs = [CC] in { 1043 // XORs of a register. 1044 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1045 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>; 1046 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>; 1047 } 1048 1049 // XORs of a 32-bit immediate, leaving other bits unaffected. 1050 // The CC result only reflects the 32-bit field, which means we can 1051 // use it as a zero indicator for i32 operations but not otherwise. 1052 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1053 // Expands to XILF or XIHF, depending on the choice of register. 1054 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1055 Requires<[FeatureHighWord]>; 1056 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1057 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1058 } 1059 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1060 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1061 1062 // XORs of memory. 1063 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1064 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1065 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1066 } 1067 1068 // XOR to memory 1069 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1070 1071 // Block XOR. 1072 let mayLoad = 1, mayStore = 1 in 1073 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1074} 1075defm : RMWIByte<xor, bdaddr12pair, XI>; 1076defm : RMWIByte<xor, bdaddr20pair, XIY>; 1077 1078//===----------------------------------------------------------------------===// 1079// Multiplication 1080//===----------------------------------------------------------------------===// 1081 1082// Multiplication of a register. 1083let isCommutable = 1 in { 1084 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>; 1085 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>; 1086} 1087def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>; 1088defm : SXB<mul, GR64, MSGFR>; 1089 1090// Multiplication of a signed 16-bit immediate. 1091def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1092def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1093 1094// Multiplication of a signed 32-bit immediate. 1095def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1096def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1097 1098// Multiplication of memory. 1099defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1100defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1101def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1102def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1103 1104// Multiplication of a register, producing two results. 1105def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>; 1106 1107// Multiplication of memory, producing two results. 1108def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>; 1109 1110//===----------------------------------------------------------------------===// 1111// Division and remainder 1112//===----------------------------------------------------------------------===// 1113 1114// Division and remainder, from registers. 1115def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>; 1116def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>; 1117def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>; 1118def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>; 1119 1120// Division and remainder, from memory. 1121def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>; 1122def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>; 1123def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>; 1124def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>; 1125 1126//===----------------------------------------------------------------------===// 1127// Shifts 1128//===----------------------------------------------------------------------===// 1129 1130// Shift left. 1131let hasSideEffects = 0 in { 1132 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1133 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1134} 1135 1136// Logical shift right. 1137let hasSideEffects = 0 in { 1138 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1139 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1140} 1141 1142// Arithmetic shift right. 1143let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1144 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1145 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1146} 1147 1148// Rotate left. 1149let hasSideEffects = 0 in { 1150 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1151 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1152} 1153 1154// Rotate second operand left and inserted selected bits into first operand. 1155// These can act like 32-bit operands provided that the constant start and 1156// end bits (operands 2 and 3) are in the range [32, 64). 1157let Defs = [CC] in { 1158 let isCodeGenOnly = 1 in 1159 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1160 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1161 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1162} 1163 1164// On zEC12 we have a variant of RISBG that does not set CC. 1165let Predicates = [FeatureMiscellaneousExtensions] in 1166 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1167 1168// Forms of RISBG that only affect one word of the destination register. 1169// They do not set CC. 1170let Predicates = [FeatureHighWord] in { 1171 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1172 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1173 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1174 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1175 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1176 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1177 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1178} 1179 1180// Rotate second operand left and perform a logical operation with selected 1181// bits of the first operand. The CC result only describes the selected bits, 1182// so isn't useful for a full comparison against zero. 1183let Defs = [CC] in { 1184 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1185 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1186 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1187} 1188 1189//===----------------------------------------------------------------------===// 1190// Comparison 1191//===----------------------------------------------------------------------===// 1192 1193// Signed comparisons. We put these before the unsigned comparisons because 1194// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1195// of the unsigned forms do. 1196let Defs = [CC], CCValues = 0xE in { 1197 // Comparison with a register. 1198 def CR : CompareRR <"c", 0x19, z_scmp, GR32, GR32>; 1199 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>; 1200 def CGR : CompareRRE<"cg", 0xB920, z_scmp, GR64, GR64>; 1201 1202 // Comparison with a signed 16-bit immediate. 1203 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1204 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1205 1206 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1207 // depending on the choice of register. 1208 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1209 Requires<[FeatureHighWord]>; 1210 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1211 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1212 Requires<[FeatureHighWord]>; 1213 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1214 1215 // Comparison with memory. 1216 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1217 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1218 Requires<[FeatureHighWord]>; 1219 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1220 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1221 Requires<[FeatureHighWord]>; 1222 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1223 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1224 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1225 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1226 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1227 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1228 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1229 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1230 1231 // Comparison between memory and a signed 16-bit immediate. 1232 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1233 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1234 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1235} 1236defm : SXB<z_scmp, GR64, CGFR>; 1237 1238// Unsigned comparisons. 1239let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1240 // Comparison with a register. 1241 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>; 1242 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>; 1243 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>; 1244 1245 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1246 // or CLIH, depending on the choice of register. 1247 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1248 Requires<[FeatureHighWord]>; 1249 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1250 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1251 Requires<[FeatureHighWord]>; 1252 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1253 1254 // Comparison with memory. 1255 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1256 Requires<[FeatureHighWord]>; 1257 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1258 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1259 Requires<[FeatureHighWord]>; 1260 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1261 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1262 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1263 aligned_azextloadi16>; 1264 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1265 aligned_load>; 1266 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1267 aligned_azextloadi16>; 1268 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1269 aligned_azextloadi32>; 1270 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1271 aligned_load>; 1272 1273 // Comparison between memory and an unsigned 8-bit immediate. 1274 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1275 1276 // Comparison between memory and an unsigned 16-bit immediate. 1277 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1278 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1279 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1280} 1281defm : ZXB<z_ucmp, GR64, CLGFR>; 1282 1283// Memory-to-memory comparison. 1284let mayLoad = 1, Defs = [CC] in 1285 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1286 1287// String comparison. 1288let mayLoad = 1, Defs = [CC] in 1289 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1290 1291// Test under mask. 1292let Defs = [CC] in { 1293 // TMxMux expands to TM[LH]x, depending on the choice of register. 1294 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1295 Requires<[FeatureHighWord]>; 1296 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1297 Requires<[FeatureHighWord]>; 1298 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1299 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1300 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1301 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1302 1303 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1304 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1305 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1306 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1307 1308 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1309} 1310 1311//===----------------------------------------------------------------------===// 1312// Prefetch 1313//===----------------------------------------------------------------------===// 1314 1315def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1316def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1317 1318//===----------------------------------------------------------------------===// 1319// Atomic operations 1320//===----------------------------------------------------------------------===// 1321 1322// A serialization instruction that acts as a barrier for all memory 1323// accesses, which expands to "bcr 14, 0". 1324let hasSideEffects = 1 in 1325def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>; 1326 1327// A pseudo instruction that serves as a compiler barrier. 1328let hasSideEffects = 1 in 1329def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1330 1331let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1332 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1333 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1334 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1335 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1336 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1337 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1338 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1339 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1340 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1341 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1342} 1343 1344def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1345def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1346def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1347 1348def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1349def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1350let Predicates = [FeatureNoInterlockedAccess1] in { 1351 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1352 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1353 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1354 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1355 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1356 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1357} 1358 1359def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1360def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1361def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1362 1363def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1364def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1365let Predicates = [FeatureNoInterlockedAccess1] in { 1366 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1367 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1368 imm32ll16c>; 1369 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1370 imm32lh16c>; 1371 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1372 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1373 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1374 imm64ll16c>; 1375 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1376 imm64lh16c>; 1377 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1378 imm64hl16c>; 1379 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1380 imm64hh16c>; 1381 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1382 imm64lf32c>; 1383 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1384 imm64hf32c>; 1385} 1386 1387def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1388def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1389let Predicates = [FeatureNoInterlockedAccess1] in { 1390 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1391 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1392 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1393 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1394 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1395 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1396 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1397 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1398 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1399 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1400 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1401} 1402 1403def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1404def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1405let Predicates = [FeatureNoInterlockedAccess1] in { 1406 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1407 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1408 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1409 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1410 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1411} 1412 1413def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1414def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1415 imm32lh16c>; 1416def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1417def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1418 imm32ll16c>; 1419def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1420 imm32lh16c>; 1421def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1422def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1423def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1424 imm64ll16c>; 1425def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1426 imm64lh16c>; 1427def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1428 imm64hl16c>; 1429def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1430 imm64hh16c>; 1431def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1432 imm64lf32c>; 1433def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1434 imm64hf32c>; 1435 1436def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1437def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1438def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1439 1440def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1441def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1442def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1443 1444def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1445def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1446def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1447 1448def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1449def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1450def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1451 1452def ATOMIC_CMP_SWAPW 1453 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1454 ADDR32:$bitshift, ADDR32:$negbitshift, 1455 uimm32:$bitsize), 1456 [(set GR32:$dst, 1457 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1458 ADDR32:$bitshift, ADDR32:$negbitshift, 1459 uimm32:$bitsize))]> { 1460 let Defs = [CC]; 1461 let mayLoad = 1; 1462 let mayStore = 1; 1463 let usesCustomInserter = 1; 1464} 1465 1466let Defs = [CC] in { 1467 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1468 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1469} 1470 1471//===----------------------------------------------------------------------===// 1472// Transactional execution 1473//===----------------------------------------------------------------------===// 1474 1475let Predicates = [FeatureTransactionalExecution] in { 1476 // Transaction Begin 1477 let hasSideEffects = 1, mayStore = 1, 1478 usesCustomInserter = 1, Defs = [CC] in { 1479 def TBEGIN : InstSIL<0xE560, 1480 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1481 "tbegin\t$BD1, $I2", 1482 [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>; 1483 def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1484 [(z_tbegin_nofloat bdaddr12only:$BD1, 1485 imm32zx16:$I2)]>; 1486 def TBEGINC : InstSIL<0xE561, 1487 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2), 1488 "tbeginc\t$BD1, $I2", 1489 [(int_s390_tbeginc bdaddr12only:$BD1, 1490 imm32zx16:$I2)]>; 1491 } 1492 1493 // Transaction End 1494 let hasSideEffects = 1, Defs = [CC], BD2 = 0 in 1495 def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>; 1496 1497 // Transaction Abort 1498 let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in 1499 def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2), 1500 "tabort\t$BD2", 1501 [(int_s390_tabort bdaddr12only:$BD2)]>; 1502 1503 // Nontransactional Store 1504 let hasSideEffects = 1 in 1505 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1506 1507 // Extract Transaction Nesting Depth 1508 let hasSideEffects = 1 in 1509 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>; 1510} 1511 1512//===----------------------------------------------------------------------===// 1513// Processor assist 1514//===----------------------------------------------------------------------===// 1515 1516let Predicates = [FeatureProcessorAssist] in { 1517 let hasSideEffects = 1, R4 = 0 in 1518 def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3), 1519 "ppa\t$R1, $R2, $R3", []>; 1520 def : Pat<(int_s390_ppa_txassist GR32:$src), 1521 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1522 0, 1)>; 1523} 1524 1525//===----------------------------------------------------------------------===// 1526// Miscellaneous Instructions. 1527//===----------------------------------------------------------------------===// 1528 1529// Extract CC into bits 29 and 28 of a register. 1530let Uses = [CC] in 1531 def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>; 1532 1533// Read a 32-bit access register into a GR32. As with all GR32 operations, 1534// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1535// when a 64-bit address is stored in a pair of access registers. 1536def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2), 1537 "ear\t$R1, $R2", 1538 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>; 1539 1540// Find leftmost one, AKA count leading zeros. The instruction actually 1541// returns a pair of GR64s, the first giving the number of leading zeros 1542// and the second giving a copy of the source with the leftmost one bit 1543// cleared. We only use the first result here. 1544let Defs = [CC] in { 1545 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>; 1546} 1547def : Pat<(ctlz GR64:$src), 1548 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1549 1550// Population count. Counts bits set per byte. 1551let Predicates = [FeaturePopulationCount], Defs = [CC] in { 1552 def POPCNT : InstRRE<0xB9E1, (outs GR64:$R1), (ins GR64:$R2), 1553 "popcnt\t$R1, $R2", 1554 [(set GR64:$R1, (z_popcnt GR64:$R2))]>; 1555} 1556 1557// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 1558def : Pat<(i64 (anyext GR32:$src)), 1559 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 1560 1561// Extend GR32s and GR64s to GR128s. 1562let usesCustomInserter = 1 in { 1563 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1564 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 1565 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1566} 1567 1568// Search a block of memory for a character. 1569let mayLoad = 1, Defs = [CC] in 1570 defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; 1571 1572// Other instructions for inline assembly 1573let hasSideEffects = 1, Defs = [CC], isCall = 1 in 1574 def SVC : InstI<0x0A, (outs), (ins imm32zx8:$I1), 1575 "svc\t$I1", 1576 []>; 1577let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1578 def STCK : InstS<0xB205, (outs), (ins bdaddr12only:$BD2), 1579 "stck\t$BD2", 1580 []>; 1581let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1582 def STCKF : InstS<0xB27C, (outs), (ins bdaddr12only:$BD2), 1583 "stckf\t$BD2", 1584 []>; 1585let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1586 def STCKE : InstS<0xB278, (outs), (ins bdaddr12only:$BD2), 1587 "stcke\t$BD2", 1588 []>; 1589let hasSideEffects = 1, Defs = [CC], mayStore = 1 in 1590 def STFLE : InstS<0xB2B0, (outs), (ins bdaddr12only:$BD2), 1591 "stfle\t$BD2", 1592 []>; 1593 1594 1595 1596//===----------------------------------------------------------------------===// 1597// Peepholes. 1598//===----------------------------------------------------------------------===// 1599 1600// Use AL* for GR64 additions of unsigned 32-bit values. 1601defm : ZXB<add, GR64, ALGFR>; 1602def : Pat<(add GR64:$src1, imm64zx32:$src2), 1603 (ALGFI GR64:$src1, imm64zx32:$src2)>; 1604def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1605 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 1606 1607// Use SL* for GR64 subtractions of unsigned 32-bit values. 1608defm : ZXB<sub, GR64, SLGFR>; 1609def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1610 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1611def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1612 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 1613 1614// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 1615// for vector legalization. 1616def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)), 1617 (i32 31)), 1618 (i32 31)), 1619 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1620def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, 1621 imm32zx4:$cc)))), 1622 (i32 63)), 1623 (i32 63)), 1624 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1625 1626// Peepholes for turning scalar operations into block operations. 1627defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 1628 XCSequence, 1>; 1629defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 1630 XCSequence, 2>; 1631defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 1632 XCSequence, 4>; 1633defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 1634 OCSequence, XCSequence, 1>; 1635defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 1636 XCSequence, 2>; 1637defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 1638 XCSequence, 4>; 1639defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 1640 XCSequence, 8>; 1641