1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// The callseq_start node requires the hasSideEffects flag, even though these 17// instructions are noops on SystemZ. 18let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45//===----------------------------------------------------------------------===// 46// Branch instructions 47//===----------------------------------------------------------------------===// 48 49// Conditional branches. 50let isBranch = 1, isTerminator = 1, Uses = [CC] in { 51 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 52 // with the condition-code mask being the first operand. It seems friendlier 53 // to use mnemonic forms like JE and JLH when writing out the assembly though. 54 let isCodeGenOnly = 1 in { 55 // An assembler extended mnemonic for BRC. 56 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 57 // An assembler extended mnemonic for BRCL. (The extension is "G" 58 // rather than "L" because "JL" is "Jump if Less".) 59 def BRCL : CondBranchRIL<"jg#", 0xC04>; 60 let isIndirectBranch = 1 in { 61 def BC : CondBranchRX<"b#", 0x47>; 62 def BCR : CondBranchRR<"b#r", 0x07>; 63 def BIC : CondBranchRXY<"bi#", 0xe347>, 64 Requires<[FeatureMiscellaneousExtensions2]>; 65 } 66 } 67 68 // Allow using the raw forms directly from the assembler (and occasional 69 // special code generation needs) as well. 70 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 71 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 72 let isIndirectBranch = 1 in { 73 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 74 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 75 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 76 Requires<[FeatureMiscellaneousExtensions2]>; 77 } 78 79 // Define AsmParser extended mnemonics for each general condition-code mask 80 // (integer or floating-point) 81 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 82 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 83 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 84 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 85 let isIndirectBranch = 1 in { 86 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 87 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 88 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 89 Requires<[FeatureMiscellaneousExtensions2]>; 90 } 91 } 92} 93 94// Unconditional branches. These are in fact simply variants of the 95// conditional branches with the condition mask set to "always". 96let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 97 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 98 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 99 let isIndirectBranch = 1 in { 100 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 101 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 102 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 103 Requires<[FeatureMiscellaneousExtensions2]>; 104 } 105} 106 107// NOPs. These are again variants of the conditional branches, with the 108// condition mask set to "never". NOP_bare can't be an InstAlias since it 109// would need R0D hard coded which is not part of ADDR64BitRegClass. 110def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 111let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 112 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 113def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 114def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 115 116// An alias of BRC 0, label 117def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 118 119// An alias of BRCL 0, label 120// jgnop on att ; jlnop on hlasm 121def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 122 123// Fused compare-and-branch instructions. 124// 125// These instructions do not use or clobber the condition codes. 126// We nevertheless pretend that the relative compare-and-branch 127// instructions clobber CC, so that we can lower them to separate 128// comparisons and BRCLs if the branch ends up being out of range. 129let isBranch = 1, isTerminator = 1 in { 130 // As for normal branches, we handle these instructions internally in 131 // their raw CRJ-like form, but use assembly macros like CRJE when writing 132 // them out. Using the *Pair multiclasses, we also create the raw forms. 133 let Defs = [CC] in { 134 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 135 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 136 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 137 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 138 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 139 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 140 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 141 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 142 } 143 let isIndirectBranch = 1 in { 144 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 145 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 146 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 147 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 148 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 149 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 150 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 151 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 152 } 153 154 // Define AsmParser mnemonics for each integer condition-code mask. 155 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 156 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 157 let Defs = [CC] in { 158 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 159 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 160 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 161 imm32sx8>; 162 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 163 imm64sx8>; 164 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 165 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 166 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 167 imm32zx8>; 168 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 169 imm64zx8>; 170 } 171 let isIndirectBranch = 1 in { 172 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 173 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 174 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 175 imm32sx8>; 176 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 177 imm64sx8>; 178 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 179 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 180 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 181 imm32zx8>; 182 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 183 imm64zx8>; 184 } 185 } 186} 187 188// Decrement a register and branch if it is nonzero. These don't clobber CC, 189// but we might need to split long relative branches into sequences that do. 190let isBranch = 1, isTerminator = 1 in { 191 let Defs = [CC] in { 192 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 193 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 194 } 195 // This doesn't need to clobber CC since we never need to split it. 196 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 197 Requires<[FeatureHighWord]>; 198 199 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 200 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 201 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 202 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 203} 204 205let isBranch = 1, isTerminator = 1 in { 206 let Defs = [CC] in { 207 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 208 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 209 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 210 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 211 } 212 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 213 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 214 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 215 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 216} 217 218//===----------------------------------------------------------------------===// 219// Trap instructions 220//===----------------------------------------------------------------------===// 221 222// Unconditional trap. 223let hasCtrlDep = 1, hasSideEffects = 1 in 224 def Trap : Alias<4, (outs), (ins), [(trap)]>; 225 226// Conditional trap. 227let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 228 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 229 230// Fused compare-and-trap instructions. 231let hasCtrlDep = 1, hasSideEffects = 1 in { 232 // These patterns work the same way as for compare-and-branch. 233 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 234 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 235 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 236 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 237 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 238 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 239 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 240 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 241 let Predicates = [FeatureMiscellaneousExtensions] in { 242 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 243 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 244 } 245 246 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 247 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 248 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 249 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 250 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 251 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 252 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 253 imm32sx16>; 254 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 255 imm64sx16>; 256 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 257 imm32zx16>; 258 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 259 imm64zx16>; 260 let Predicates = [FeatureMiscellaneousExtensions] in { 261 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 262 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 263 } 264 } 265} 266 267//===----------------------------------------------------------------------===// 268// Call and return instructions 269//===----------------------------------------------------------------------===// 270 271// Define the general form of the call instructions for the asm parser. 272// These instructions don't hard-code %r14 as the return address register. 273let isCall = 1, Defs = [CC] in { 274 def BRAS : CallRI <"bras", 0xA75>; 275 def BRASL : CallRIL<"brasl", 0xC05>; 276 def BAS : CallRX <"bas", 0x4D>; 277 def BASR : CallRR <"basr", 0x0D>; 278} 279 280// z/OS XPLINK 281let Predicates = [IsTargetXPLINK64] in { 282 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 283 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 284 [(z_call pcrel32:$I2)]>; 285 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 286 [(z_call ADDR64:$R2)]>; 287 } 288} 289 290// Regular calls. 291// z/Linux ELF 292let Predicates = [IsTargetELF] in { 293 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 294 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 295 [(z_call pcrel32:$I2)]>; 296 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 297 [(z_call ADDR64:$R2)]>; 298 } 299 300 // TLS calls. These will be lowered into a call to __tls_get_offset, 301 // with an extra relocation specifying the TLS symbol. 302 let isCall = 1, Defs = [R14D, CC] in { 303 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 304 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 305 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 306 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 307 } 308} 309 310// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 311// R1 used for ELF 312let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 313 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 314 [(z_sibcall pcrel32:$I2)]>; 315 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 316 [(z_sibcall ADDR64:$R2)]>; 317} 318 319// Conditional sibling calls. 320let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 321 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 322 pcrel32:$I2), []>; 323 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 324 ADDR64:$R2), []>; 325} 326 327// Fused compare and conditional sibling calls. 328let isCall = 1, isTerminator = 1, isReturn = 1 in { 329 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 330 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 331 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 332 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 333 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 334 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 335 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 336 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 337} 338 339let Predicates = [IsTargetXPLINK64] in { 340 // A return instruction (b 2(%r7)). 341 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 342 def Return_XPLINK : Alias<4, (outs), (ins), [(z_retflag)]>; 343 344 // A conditional return instruction (bc <cond>, 2(%r7)). 345 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 346 def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 347} 348 349let Predicates = [IsTargetELF] in { 350 // A return instruction (br %r14). 351 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 352 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 353 354 // A conditional return instruction (bcr <cond>, %r14). 355 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 356 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 357} 358 359// Fused compare and conditional returns. 360let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 361 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 362 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 363 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 364 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 365 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 366 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 367 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 368 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 369} 370 371//===----------------------------------------------------------------------===// 372// Select instructions 373//===----------------------------------------------------------------------===// 374 375def Select32 : SelectWrapper<i32, GR32>, 376 Requires<[FeatureNoLoadStoreOnCond]>; 377def Select64 : SelectWrapper<i64, GR64>, 378 Requires<[FeatureNoLoadStoreOnCond]>; 379 380// We don't define 32-bit Mux stores if we don't have STOCFH, because the 381// low-only STOC should then always be used if possible. 382defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 383 nonvolatile_anyextloadi8, bdxaddr20only>, 384 Requires<[FeatureHighWord]>; 385defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 386 nonvolatile_anyextloadi16, bdxaddr20only>, 387 Requires<[FeatureHighWord]>; 388defm CondStore32Mux : CondStores<GRX32, simple_store, 389 simple_load, bdxaddr20only>, 390 Requires<[FeatureLoadStoreOnCond2]>; 391defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 392 nonvolatile_anyextloadi8, bdxaddr20only>; 393defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 394 nonvolatile_anyextloadi16, bdxaddr20only>; 395defm CondStore32 : CondStores<GR32, simple_store, 396 simple_load, bdxaddr20only>; 397 398defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 399 nonvolatile_anyextloadi8, bdxaddr20only>; 400defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 401 nonvolatile_anyextloadi16, bdxaddr20only>; 402defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 403 nonvolatile_anyextloadi32, bdxaddr20only>; 404defm CondStore64 : CondStores<GR64, simple_store, 405 simple_load, bdxaddr20only>; 406 407//===----------------------------------------------------------------------===// 408// Move instructions 409//===----------------------------------------------------------------------===// 410 411// Register moves. 412def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 413def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 414 415let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 416 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 417 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 418} 419 420let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 421 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 422 423// Immediate moves. 424let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 425 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 426 // deopending on the choice of register. 427 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 428 Requires<[FeatureHighWord]>; 429 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 430 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 431 432 // Other 16-bit immediates. 433 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 434 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 435 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 436 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 437 438 // 32-bit immediates. 439 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 440 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 441 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 442} 443 444// Register loads. 445let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 446 // Expands to L, LY or LFH, depending on the choice of register. 447 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 448 Requires<[FeatureHighWord]>; 449 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 450 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 451 Requires<[FeatureHighWord]>; 452 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 453 454 // These instructions are split after register allocation, so we don't 455 // want a custom inserter. 456 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 457 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 458 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 459 } 460} 461let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 462 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 463 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 464} 465 466let canFoldAsLoad = 1 in { 467 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 468 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 469} 470 471// Load and zero rightmost byte. 472let Predicates = [FeatureLoadAndZeroRightmostByte] in { 473 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 474 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 475 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 476 (LZRF bdxaddr20only:$src)>; 477 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 478 (LZRG bdxaddr20only:$src)>; 479} 480 481// Load and trap. 482let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 483 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 484 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 485 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 486} 487 488// Register stores. 489let SimpleBDXStore = 1, mayStore = 1 in { 490 // Expands to ST, STY or STFH, depending on the choice of register. 491 def STMux : StoreRXYPseudo<store, GRX32, 4>, 492 Requires<[FeatureHighWord]>; 493 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 494 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 495 Requires<[FeatureHighWord]>; 496 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 497 498 // These instructions are split after register allocation, so we don't 499 // want a custom inserter. 500 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 501 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 502 [(store GR128:$src, bdxaddr20only128:$dst)]>; 503 } 504} 505def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 506def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 507 508// 8-bit immediate stores to 8-bit fields. 509defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 510 511// 16-bit immediate stores to 16-, 32- or 64-bit fields. 512def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 513def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 514def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 515 516// Memory-to-memory moves. 517let mayLoad = 1, mayStore = 1 in 518 defm MVC : MemorySS<"mvc", 0xD2, z_mvc>; 519let mayLoad = 1, mayStore = 1, Defs = [CC] in { 520 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 521 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 522 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 523} 524 525// Memset[Length][Byte] pseudos. 526def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>; 527def MemsetImmReg : MemsetPseudo<imm64, GR32>; 528def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>; 529def MemsetRegReg : MemsetPseudo<ADDR64, GR32>; 530 531// Move right. 532let Predicates = [FeatureMiscellaneousExtensions3], 533 mayLoad = 1, mayStore = 1, Uses = [R0L] in 534 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 535 536// String moves. 537let mayLoad = 1, mayStore = 1, Defs = [CC] in 538 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 539 540//===----------------------------------------------------------------------===// 541// Conditional move instructions 542//===----------------------------------------------------------------------===// 543 544let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 545 // Select. 546 let isCommutable = 1 in { 547 // Expands to SELR or SELFHR or a branch-and-move sequence, 548 // depending on the choice of registers. 549 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 550 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 551 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 552 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 553 } 554 555 // Define AsmParser extended mnemonics for each general condition-code mask. 556 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 557 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 558 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 559 GR32, GR32, GR32>; 560 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 561 GRH32, GRH32, GRH32>; 562 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 563 GR64, GR64, GR64>; 564 } 565} 566 567let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 568 // Load immediate on condition. Matched via DAG pattern and created 569 // by the PeepholeOptimizer via FoldImmediate. 570 571 // Expands to LOCHI or LOCHHI, depending on the choice of register. 572 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 573 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 574 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 575 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 576 577 // Move register on condition. Matched via DAG pattern and 578 // created by early if-conversion. 579 let isCommutable = 1 in { 580 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 581 // depending on the choice of registers. 582 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 583 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 584 } 585 586 // Load on condition. Matched via DAG pattern. 587 // Expands to LOC or LOCFH, depending on the choice of register. 588 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 589 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 590 591 // Store on condition. Expanded from CondStore* pseudos. 592 // Expands to STOC or STOCFH, depending on the choice of register. 593 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 594 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 595 596 // Define AsmParser extended mnemonics for each general condition-code mask. 597 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 598 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 599 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 600 imm32sx16>; 601 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 602 imm64sx16>; 603 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 604 imm32sx16>; 605 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 606 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 607 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 608 } 609} 610 611let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 612 // Move register on condition. Matched via DAG pattern and 613 // created by early if-conversion. 614 let isCommutable = 1 in { 615 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 616 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 617 } 618 619 // Load on condition. Matched via DAG pattern. 620 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 621 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 622 623 // Store on condition. Expanded from CondStore* pseudos. 624 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 625 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 626 627 // Define AsmParser extended mnemonics for each general condition-code mask. 628 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 629 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 630 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 631 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 632 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 633 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 634 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 635 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 636 } 637} 638//===----------------------------------------------------------------------===// 639// Sign extensions 640//===----------------------------------------------------------------------===// 641// 642// Note that putting these before zero extensions mean that we will prefer 643// them for anyextload*. There's not really much to choose between the two 644// either way, but signed-extending loads have a short LH and a long LHY, 645// while zero-extending loads have only the long LLH. 646// 647//===----------------------------------------------------------------------===// 648 649// 32-bit extensions from registers. 650def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 651def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 652 653// 64-bit extensions from registers. 654def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 655def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 656def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 657 658let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 659 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 660 661// Match 32-to-64-bit sign extensions in which the source is already 662// in a 64-bit register. 663def : Pat<(sext_inreg GR64:$src, i32), 664 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 665 666// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 667// depending on the choice of register. 668def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 669 Requires<[FeatureHighWord]>; 670def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 671def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 672 Requires<[FeatureHighWord]>; 673 674// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 675// depending on the choice of register. 676def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 677 Requires<[FeatureHighWord]>; 678defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 679def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 680 Requires<[FeatureHighWord]>; 681def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 682 683// 64-bit extensions from memory. 684def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 685def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 686def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 687def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 688def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 689let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 690 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 691 692//===----------------------------------------------------------------------===// 693// Zero extensions 694//===----------------------------------------------------------------------===// 695 696// 32-bit extensions from registers. 697 698// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 699def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 700 Requires<[FeatureHighWord]>; 701def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 702// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 703def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 704 Requires<[FeatureHighWord]>; 705def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 706 707// 64-bit extensions from registers. 708def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 709def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 710def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 711 712// Match 32-to-64-bit zero extensions in which the source is already 713// in a 64-bit register. 714def : Pat<(and GR64:$src, 0xffffffff), 715 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 716 717// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 718// depending on the choice of register. 719def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 720 Requires<[FeatureHighWord]>; 721def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 722def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 723 Requires<[FeatureHighWord]>; 724 725// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 726// depending on the choice of register. 727def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 728 Requires<[FeatureHighWord]>; 729def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 730def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 731 Requires<[FeatureHighWord]>; 732def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 733 734// 64-bit extensions from memory. 735def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 736def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 737def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 738def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 739def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 740 741// 31-to-64-bit zero extensions. 742def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 743def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 744def : Pat<(and GR64:$src, 0x7fffffff), 745 (LLGTR GR64:$src)>; 746def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 747 (LLGT bdxaddr20only:$src)>; 748 749// Load and zero rightmost byte. 750let Predicates = [FeatureLoadAndZeroRightmostByte] in { 751 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 752 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 753 (LLZRGF bdxaddr20only:$src)>; 754} 755 756// Load and trap. 757let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 758 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 759 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 760} 761 762// Extend GR64s to GR128s. 763let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 764 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 765 766//===----------------------------------------------------------------------===// 767// "Any" extensions 768//===----------------------------------------------------------------------===// 769 770// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 771def : Pat<(i64 (anyext GR32:$src)), 772 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 773 774// Extend GR64s to GR128s. 775let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 776 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 777 778//===----------------------------------------------------------------------===// 779// Truncations 780//===----------------------------------------------------------------------===// 781 782// Truncations of 64-bit registers to 32-bit registers. 783def : Pat<(i32 (trunc GR64:$src)), 784 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 785 786// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 787// STC, STCY or STCH, depending on the choice of register. 788def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 789 Requires<[FeatureHighWord]>; 790defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 791def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 792 Requires<[FeatureHighWord]>; 793 794// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 795// STH, STHY or STHH, depending on the choice of register. 796def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 797 Requires<[FeatureHighWord]>; 798defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 799def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 800 Requires<[FeatureHighWord]>; 801def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 802 803// Truncations of 64-bit registers to memory. 804defm : StoreGR64Pair<STC, STCY, truncstorei8>; 805defm : StoreGR64Pair<STH, STHY, truncstorei16>; 806def : StoreGR64PC<STHRL, aligned_truncstorei16>; 807defm : StoreGR64Pair<ST, STY, truncstorei32>; 808def : StoreGR64PC<STRL, aligned_truncstorei32>; 809 810// Store characters under mask -- not (yet) used for codegen. 811defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 812def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 813 814//===----------------------------------------------------------------------===// 815// Multi-register moves 816//===----------------------------------------------------------------------===// 817 818// Multi-register loads. 819defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 820def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 821def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 822def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 823 824// Multi-register stores. 825defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 826def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 827def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 828 829//===----------------------------------------------------------------------===// 830// Byte swaps 831//===----------------------------------------------------------------------===// 832 833// Byte-swapping register moves. 834def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 835def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 836 837// Byte-swapping loads. 838def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 839def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 840def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 841 842// Byte-swapping stores. 843def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 844def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 845def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 846 847// Byte-swapping memory-to-memory moves. 848let mayLoad = 1, mayStore = 1 in 849 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 850 851//===----------------------------------------------------------------------===// 852// Load address instructions 853//===----------------------------------------------------------------------===// 854 855// Load BDX-style addresses. 856let isAsCheapAsAMove = 1, isReMaterializable = 1 in 857 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 858 859// Load a PC-relative address. There's no version of this instruction 860// with a 16-bit offset, so there's no relaxation. 861let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 862 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 863 864// Load the Global Offset Table address. This will be lowered into a 865// larl $R1, _GLOBAL_OFFSET_TABLE_ 866// instruction. 867def GOT : Alias<6, (outs GR64:$R1), (ins), 868 [(set GR64:$R1, (global_offset_table))]>; 869 870//===----------------------------------------------------------------------===// 871// Absolute and Negation 872//===----------------------------------------------------------------------===// 873 874let Defs = [CC] in { 875 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 876 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 877 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 878 } 879 let CCValues = 0xE, CompareZeroCCMask = 0xE in 880 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 881} 882defm : SXU<abs, LPGFR>; 883 884let Defs = [CC] in { 885 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 886 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 887 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 888 } 889 let CCValues = 0xE, CompareZeroCCMask = 0xE in 890 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 891} 892defm : SXU<z_inegabs, LNGFR>; 893 894let Defs = [CC] in { 895 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 896 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 897 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 898 } 899 let CCValues = 0xE, CompareZeroCCMask = 0xE in 900 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 901} 902defm : SXU<ineg, LCGFR>; 903 904//===----------------------------------------------------------------------===// 905// Insertion 906//===----------------------------------------------------------------------===// 907 908let isCodeGenOnly = 1 in 909 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 910defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 911 912defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 913defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 914 915defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 916defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 917 918// Insert characters under mask -- not (yet) used for codegen. 919let Defs = [CC] in { 920 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 921 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 922} 923 924// Insertions of a 16-bit immediate, leaving other bits unaffected. 925// We don't have or_as_insert equivalents of these operations because 926// OI is available instead. 927// 928// IIxMux expands to II[LH]x, depending on the choice of register. 929def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 930 Requires<[FeatureHighWord]>; 931def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 932 Requires<[FeatureHighWord]>; 933def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 934def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 935def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 936def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 937def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 938def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 939def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 940def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 941 942// ...likewise for 32-bit immediates. For GR32s this is a general 943// full-width move. (We use IILF rather than something like LLILF 944// for 32-bit moves because IILF leaves the upper 32 bits of the 945// GR64 unchanged.) 946let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 947 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 948 Requires<[FeatureHighWord]>; 949 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 950 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 951} 952def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 953def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 954 955// An alternative model of inserthf, with the first operand being 956// a zero-extended value. 957def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 958 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 959 imm64hf32:$imm)>; 960 961//===----------------------------------------------------------------------===// 962// Addition 963//===----------------------------------------------------------------------===// 964 965// Addition producing a signed overflow flag. 966let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 967 // Addition of a register. 968 let isCommutable = 1 in { 969 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 970 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 971 } 972 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 973 974 // Addition to a high register. 975 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 976 Requires<[FeatureHighWord]>; 977 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 978 Requires<[FeatureHighWord]>; 979 980 // Addition of signed 16-bit immediates. 981 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 982 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 983 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 984 985 // Addition of signed 32-bit immediates. 986 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 987 Requires<[FeatureHighWord]>; 988 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 989 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 990 Requires<[FeatureHighWord]>; 991 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 992 993 // Addition of memory. 994 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 995 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 996 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 997 Requires<[FeatureMiscellaneousExtensions2]>; 998 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 999 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 1000 1001 // Addition to memory. 1002 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 1003 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 1004} 1005defm : SXB<z_sadd, GR64, AGFR>; 1006 1007// Addition producing a carry. 1008let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 1009 // Addition of a register. 1010 let isCommutable = 1 in { 1011 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 1012 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 1013 } 1014 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 1015 1016 // Addition to a high register. 1017 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 1018 Requires<[FeatureHighWord]>; 1019 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1020 Requires<[FeatureHighWord]>; 1021 1022 // Addition of signed 16-bit immediates. 1023 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1024 Requires<[FeatureDistinctOps]>; 1025 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1026 Requires<[FeatureDistinctOps]>; 1027 1028 // Addition of unsigned 32-bit immediates. 1029 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1030 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1031 1032 // Addition of signed 32-bit immediates. 1033 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1034 Requires<[FeatureHighWord]>; 1035 1036 // Addition of memory. 1037 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1038 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1039 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1040 1041 // Addition to memory. 1042 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1043 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1044} 1045defm : ZXB<z_uadd, GR64, ALGFR>; 1046 1047// Addition producing and using a carry. 1048let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1049 // Addition of a register. 1050 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1051 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1052 1053 // Addition of memory. 1054 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1055 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1056} 1057 1058// Addition that does not modify the condition code. 1059def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1060 Requires<[FeatureHighWord]>; 1061 1062 1063//===----------------------------------------------------------------------===// 1064// Subtraction 1065//===----------------------------------------------------------------------===// 1066 1067// Subtraction producing a signed overflow flag. 1068let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1069 CCIfNoSignedWrap = 1 in { 1070 // Subtraction of a register. 1071 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1072 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1073 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1074 1075 // Subtraction from a high register. 1076 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1077 Requires<[FeatureHighWord]>; 1078 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1079 Requires<[FeatureHighWord]>; 1080 1081 // Subtraction of memory. 1082 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1083 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1084 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1085 Requires<[FeatureMiscellaneousExtensions2]>; 1086 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1087 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1088} 1089defm : SXB<z_ssub, GR64, SGFR>; 1090 1091// Subtracting an immediate is the same as adding the negated immediate. 1092let AddedComplexity = 1 in { 1093 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1094 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1095 Requires<[FeatureHighWord]>; 1096 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1097 (AFIMux GR32:$src1, simm32n:$src2)>, 1098 Requires<[FeatureHighWord]>; 1099 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1100 (AHI GR32:$src1, imm32sx16n:$src2)>; 1101 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1102 (AFI GR32:$src1, simm32n:$src2)>; 1103 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1104 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1105 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1106 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1107} 1108 1109// And vice versa in one special case, where we need to load a 1110// constant into a register in any case, but the negated constant 1111// requires fewer instructions to load. 1112def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1113 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1114def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1115 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1116 1117// Subtraction producing a carry. 1118let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1119 // Subtraction of a register. 1120 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1121 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1122 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1123 1124 // Subtraction from a high register. 1125 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1126 Requires<[FeatureHighWord]>; 1127 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1128 Requires<[FeatureHighWord]>; 1129 1130 // Subtraction of unsigned 32-bit immediates. 1131 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1132 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1133 1134 // Subtraction of memory. 1135 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1136 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1137 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1138} 1139defm : ZXB<z_usub, GR64, SLGFR>; 1140 1141// Subtracting an immediate is the same as adding the negated immediate. 1142let AddedComplexity = 1 in { 1143 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1144 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1145 Requires<[FeatureDistinctOps]>; 1146 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1147 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1148 Requires<[FeatureDistinctOps]>; 1149} 1150 1151// And vice versa in one special case (but we prefer addition). 1152def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1153 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1154 1155// Subtraction producing and using a carry. 1156let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1157 // Subtraction of a register. 1158 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1159 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1160 1161 // Subtraction of memory. 1162 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1163 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1164} 1165 1166 1167//===----------------------------------------------------------------------===// 1168// AND 1169//===----------------------------------------------------------------------===// 1170 1171let Defs = [CC] in { 1172 // ANDs of a register. 1173 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1174 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1175 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1176 } 1177 1178 let isConvertibleToThreeAddress = 1 in { 1179 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1180 // The CC result only reflects the 16-bit field, not the full register. 1181 // 1182 // NIxMux expands to NI[LH]x, depending on the choice of register. 1183 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1184 Requires<[FeatureHighWord]>; 1185 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1186 Requires<[FeatureHighWord]>; 1187 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1188 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1189 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1190 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1191 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1192 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1193 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1194 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1195 1196 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1197 // The CC result only reflects the 32-bit field, which means we can 1198 // use it as a zero indicator for i32 operations but not otherwise. 1199 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1200 // Expands to NILF or NIHF, depending on the choice of register. 1201 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1202 Requires<[FeatureHighWord]>; 1203 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1204 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1205 } 1206 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1207 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1208 } 1209 1210 // ANDs of memory. 1211 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1212 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1213 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1214 } 1215 1216 // AND to memory 1217 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1218 1219 // Block AND. 1220 let mayLoad = 1, mayStore = 1 in 1221 defm NC : MemorySS<"nc", 0xD4, z_nc>; 1222} 1223defm : RMWIByte<and, bdaddr12pair, NI>; 1224defm : RMWIByte<and, bdaddr20pair, NIY>; 1225 1226//===----------------------------------------------------------------------===// 1227// OR 1228//===----------------------------------------------------------------------===// 1229 1230let Defs = [CC] in { 1231 // ORs of a register. 1232 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1233 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1234 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1235 } 1236 1237 // ORs of a 16-bit immediate, leaving other bits unaffected. 1238 // The CC result only reflects the 16-bit field, not the full register. 1239 // 1240 // OIxMux expands to OI[LH]x, depending on the choice of register. 1241 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1242 Requires<[FeatureHighWord]>; 1243 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1244 Requires<[FeatureHighWord]>; 1245 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1246 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1247 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1248 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1249 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1250 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1251 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1252 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1253 1254 // ORs of a 32-bit immediate, leaving other bits unaffected. 1255 // The CC result only reflects the 32-bit field, which means we can 1256 // use it as a zero indicator for i32 operations but not otherwise. 1257 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1258 // Expands to OILF or OIHF, depending on the choice of register. 1259 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1260 Requires<[FeatureHighWord]>; 1261 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1262 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1263 } 1264 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1265 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1266 1267 // ORs of memory. 1268 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1269 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1270 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1271 } 1272 1273 // OR to memory 1274 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1275 1276 // Block OR. 1277 let mayLoad = 1, mayStore = 1 in 1278 defm OC : MemorySS<"oc", 0xD6, z_oc>; 1279} 1280defm : RMWIByte<or, bdaddr12pair, OI>; 1281defm : RMWIByte<or, bdaddr20pair, OIY>; 1282 1283//===----------------------------------------------------------------------===// 1284// XOR 1285//===----------------------------------------------------------------------===// 1286 1287let Defs = [CC] in { 1288 // XORs of a register. 1289 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1290 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1291 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1292 } 1293 1294 // XORs of a 32-bit immediate, leaving other bits unaffected. 1295 // The CC result only reflects the 32-bit field, which means we can 1296 // use it as a zero indicator for i32 operations but not otherwise. 1297 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1298 // Expands to XILF or XIHF, depending on the choice of register. 1299 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1300 Requires<[FeatureHighWord]>; 1301 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1302 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1303 } 1304 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1305 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1306 1307 // XORs of memory. 1308 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1309 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1310 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1311 } 1312 1313 // XOR to memory 1314 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1315 1316 // Block XOR. 1317 let mayLoad = 1, mayStore = 1 in 1318 defm XC : MemorySS<"xc", 0xD7, z_xc>; 1319} 1320defm : RMWIByte<xor, bdaddr12pair, XI>; 1321defm : RMWIByte<xor, bdaddr20pair, XIY>; 1322 1323//===----------------------------------------------------------------------===// 1324// Combined logical operations 1325//===----------------------------------------------------------------------===// 1326 1327let Predicates = [FeatureMiscellaneousExtensions3], 1328 Defs = [CC] in { 1329 // AND with complement. 1330 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1331 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1332 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1333 } 1334 1335 // OR with complement. 1336 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1337 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1338 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1339 } 1340 1341 // NAND. 1342 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1343 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1344 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1345 } 1346 1347 // NOR. 1348 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1349 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1350 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1351 } 1352 1353 // NXOR. 1354 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1355 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1356 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1357 } 1358} 1359 1360//===----------------------------------------------------------------------===// 1361// Multiplication 1362//===----------------------------------------------------------------------===// 1363 1364// Multiplication of a register, setting the condition code. We prefer these 1365// over MS(G)R if available, even though we cannot use the condition code, 1366// since they are three-operand instructions. 1367let Predicates = [FeatureMiscellaneousExtensions2], 1368 Defs = [CC], isCommutable = 1 in { 1369 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1370 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1371} 1372 1373// Multiplication of a register. 1374let isCommutable = 1 in { 1375 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1376 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1377} 1378def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1379defm : SXB<mul, GR64, MSGFR>; 1380 1381// Multiplication of a signed 16-bit immediate. 1382def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1383def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1384 1385// Multiplication of a signed 32-bit immediate. 1386def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1387def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1388 1389// Multiplication of memory. 1390defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1391defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1392def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1393 Requires<[FeatureMiscellaneousExtensions2]>; 1394def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1395def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1396 1397// Multiplication of memory, setting the condition code. 1398let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1399 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1400 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1401} 1402 1403// Multiplication of a register, producing two results. 1404def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1405def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1406 Requires<[FeatureMiscellaneousExtensions2]>; 1407def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1408def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1409 1410def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1411 (MGRK GR64:$src1, GR64:$src2)>; 1412def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1413 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1414 1415// Multiplication of memory, producing two results. 1416def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1417def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1418def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1419 Requires<[FeatureMiscellaneousExtensions2]>; 1420def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1421def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1422 1423def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1424 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1425def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1426 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1427 1428//===----------------------------------------------------------------------===// 1429// Division and remainder 1430//===----------------------------------------------------------------------===// 1431 1432let hasSideEffects = 1 in { // Do not speculatively execute. 1433 // Division and remainder, from registers. 1434 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1435 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1436 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1437 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1438 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1439 1440 // Division and remainder, from memory. 1441 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1442 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1443 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1444 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1445 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1446} 1447def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1448 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1449def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1450 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1451def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1452 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1453def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1454 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1455 1456def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1457 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1458 subreg_l32)), GR32:$src2)>; 1459def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1460 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1461 subreg_l32)), bdxaddr20only:$src2)>; 1462def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1463 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1464def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1465 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1466 1467//===----------------------------------------------------------------------===// 1468// Shifts 1469//===----------------------------------------------------------------------===// 1470 1471// Logical shift left. 1472defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1473def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1474def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1475 1476// Arithmetic shift left. 1477let Defs = [CC] in { 1478 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1479 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1480 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1481} 1482 1483// Logical shift right. 1484defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1485def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1486def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1487 1488// Arithmetic shift right. 1489let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1490 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1491 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1492 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1493} 1494 1495// Rotate left. 1496def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1497def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1498 1499// Rotate second operand left and inserted selected bits into first operand. 1500// These can act like 32-bit operands provided that the constant start and 1501// end bits (operands 2 and 3) are in the range [32, 64). 1502let Defs = [CC] in { 1503 let isCodeGenOnly = 1 in 1504 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1505 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1506 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1507} 1508 1509// On zEC12 we have a variant of RISBG that does not set CC. 1510let Predicates = [FeatureMiscellaneousExtensions] in 1511 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1512 1513// Forms of RISBG that only affect one word of the destination register. 1514// They do not set CC. 1515let Predicates = [FeatureHighWord] in { 1516 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1517 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1518 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1519 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1520 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1521 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1522 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1523} 1524 1525// Rotate second operand left and perform a logical operation with selected 1526// bits of the first operand. The CC result only describes the selected bits, 1527// so isn't useful for a full comparison against zero. 1528let Defs = [CC] in { 1529 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1530 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1531 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1532} 1533 1534//===----------------------------------------------------------------------===// 1535// Comparison 1536//===----------------------------------------------------------------------===// 1537 1538// Signed comparisons. We put these before the unsigned comparisons because 1539// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1540// of the unsigned forms do. 1541let Defs = [CC], CCValues = 0xE in { 1542 // Comparison with a register. 1543 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1544 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1545 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1546 1547 // Comparison with a high register. 1548 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1549 Requires<[FeatureHighWord]>; 1550 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1551 Requires<[FeatureHighWord]>; 1552 1553 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1554 // depending on the choice of register. 1555 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1556 Requires<[FeatureHighWord]>; 1557 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1558 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1559 1560 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1561 // depending on the choice of register. 1562 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1563 Requires<[FeatureHighWord]>; 1564 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1565 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1566 Requires<[FeatureHighWord]>; 1567 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1568 1569 // Comparison with memory. 1570 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1571 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1572 Requires<[FeatureHighWord]>; 1573 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1574 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1575 Requires<[FeatureHighWord]>; 1576 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1577 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1578 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1579 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1580 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1581 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1582 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1583 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1584 1585 // Comparison between memory and a signed 16-bit immediate. 1586 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1587 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1588 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1589} 1590defm : SXB<z_scmp, GR64, CGFR>; 1591 1592// Unsigned comparisons. 1593let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1594 // Comparison with a register. 1595 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1596 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1597 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1598 1599 // Comparison with a high register. 1600 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1601 Requires<[FeatureHighWord]>; 1602 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1603 Requires<[FeatureHighWord]>; 1604 1605 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1606 // or CLIH, depending on the choice of register. 1607 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1608 Requires<[FeatureHighWord]>; 1609 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1610 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1611 Requires<[FeatureHighWord]>; 1612 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1613 1614 // Comparison with memory. 1615 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1616 Requires<[FeatureHighWord]>; 1617 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1618 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1619 Requires<[FeatureHighWord]>; 1620 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1621 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1622 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1623 aligned_azextloadi16>; 1624 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1625 aligned_load>; 1626 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1627 aligned_azextloadi16>; 1628 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1629 aligned_azextloadi32>; 1630 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1631 aligned_load>; 1632 1633 // Comparison between memory and an unsigned 8-bit immediate. 1634 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1635 1636 // Comparison between memory and an unsigned 16-bit immediate. 1637 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1638 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1639 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1640} 1641defm : ZXB<z_ucmp, GR64, CLGFR>; 1642 1643// Memory-to-memory comparison. 1644let mayLoad = 1, Defs = [CC] in { 1645 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>; 1646 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1647 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1648 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1649} 1650 1651// String comparison. 1652let mayLoad = 1, Defs = [CC] in 1653 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1654 1655// Test under mask. 1656let Defs = [CC] in { 1657 // TMxMux expands to TM[LH]x, depending on the choice of register. 1658 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1659 Requires<[FeatureHighWord]>; 1660 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1661 Requires<[FeatureHighWord]>; 1662 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1663 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1664 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1665 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1666 1667 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1668 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1669 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1670 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1671 1672 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1673} 1674 1675def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1676def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1677 1678// Compare logical characters under mask -- not (yet) used for codegen. 1679let Defs = [CC] in { 1680 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1681 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1682} 1683 1684//===----------------------------------------------------------------------===// 1685// Prefetch and execution hint 1686//===----------------------------------------------------------------------===// 1687 1688let mayLoad = 1, mayStore = 1 in { 1689 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1690 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1691} 1692 1693let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1694 // Branch Prediction Preload 1695 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1696 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1697 1698 // Next Instruction Access Intent 1699 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1700} 1701 1702//===----------------------------------------------------------------------===// 1703// Atomic operations 1704//===----------------------------------------------------------------------===// 1705 1706// A serialization instruction that acts as a barrier for all memory 1707// accesses, which expands to "bcr 14, 0". 1708let hasSideEffects = 1 in 1709def Serialize : Alias<2, (outs), (ins), []>; 1710 1711// A pseudo instruction that serves as a compiler barrier. 1712let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1713def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1714 1715let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1716 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1717 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1718 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1719 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1720 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1721 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1722 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1723 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1724 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1725 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1726} 1727 1728def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1729def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1730def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1731 1732def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1733def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1734let Predicates = [FeatureNoInterlockedAccess1] in { 1735 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1736 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1737 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1738 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1739 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1740 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1741} 1742 1743def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1744def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1745def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1746 1747def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1748def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1749let Predicates = [FeatureNoInterlockedAccess1] in { 1750 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1751 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1752 imm32ll16c>; 1753 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1754 imm32lh16c>; 1755 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1756 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1757 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1758 imm64ll16c>; 1759 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1760 imm64lh16c>; 1761 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1762 imm64hl16c>; 1763 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1764 imm64hh16c>; 1765 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1766 imm64lf32c>; 1767 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1768 imm64hf32c>; 1769} 1770 1771def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1772def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1773let Predicates = [FeatureNoInterlockedAccess1] in { 1774 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1775 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1776 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1777 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1778 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1779 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1780 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1781 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1782 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1783 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1784 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1785} 1786 1787def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1788def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1789let Predicates = [FeatureNoInterlockedAccess1] in { 1790 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1791 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1792 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1793 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1794 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1795} 1796 1797def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1798def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1799 imm32lh16c>; 1800def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1801def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1802 imm32ll16c>; 1803def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1804 imm32lh16c>; 1805def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1806def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1807def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1808 imm64ll16c>; 1809def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1810 imm64lh16c>; 1811def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1812 imm64hl16c>; 1813def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1814 imm64hh16c>; 1815def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1816 imm64lf32c>; 1817def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1818 imm64hf32c>; 1819 1820def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1821def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1822def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1823 1824def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1825def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1826def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1827 1828def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1829def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1830def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1831 1832def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1833def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1834def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1835 1836def ATOMIC_CMP_SWAPW 1837 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1838 ADDR32:$bitshift, ADDR32:$negbitshift, 1839 uimm32:$bitsize), 1840 [(set GR32:$dst, 1841 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1842 ADDR32:$bitshift, ADDR32:$negbitshift, 1843 uimm32:$bitsize))]> { 1844 let Defs = [CC]; 1845 let mayLoad = 1; 1846 let mayStore = 1; 1847 let usesCustomInserter = 1; 1848 let hasNoSchedulingInfo = 1; 1849} 1850 1851// Test and set. 1852let mayLoad = 1, Defs = [CC] in 1853 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1854 1855// Compare and swap. 1856let Defs = [CC] in { 1857 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1858 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1859} 1860 1861// Compare double and swap. 1862let Defs = [CC] in { 1863 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1864 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1865} 1866 1867// Compare and swap and store. 1868let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1869 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1870 1871// Perform locked operation. 1872let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1873 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1874 1875// Load/store pair from/to quadword. 1876def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1877def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1878 1879// Load pair disjoint. 1880let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1881 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1882 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1883} 1884 1885//===----------------------------------------------------------------------===// 1886// Translate and convert 1887//===----------------------------------------------------------------------===// 1888 1889let mayLoad = 1, mayStore = 1 in 1890 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1891 1892let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1893 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1894 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1895} 1896 1897let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1898 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1899 1900let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1901 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1902 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1903} 1904 1905let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1906 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1907 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1908 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1909 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1910} 1911 1912let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1913 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1914 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1915 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1916 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1917 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1918 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1919 1920 let isAsmParserOnly = 1 in { 1921 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1922 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1923 } 1924} 1925 1926//===----------------------------------------------------------------------===// 1927// Message-security assist 1928//===----------------------------------------------------------------------===// 1929 1930let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1931 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1932 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1933 1934 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1935 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1936 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1937 1938 let Predicates = [FeatureMessageSecurityAssist4] in { 1939 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1940 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1941 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1942 GR128, GR128, GR128>; 1943 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1944 } 1945 1946 let Predicates = [FeatureMessageSecurityAssist5] in 1947 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1948 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1949 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1950 1951 let Predicates = [FeatureMessageSecurityAssist8] in 1952 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1953 GR128, GR128, GR128>; 1954 1955 let Predicates = [FeatureMessageSecurityAssist9] in 1956 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1957} 1958 1959//===----------------------------------------------------------------------===// 1960// Guarded storage 1961//===----------------------------------------------------------------------===// 1962 1963// These instructions use and/or modify the guarded storage control 1964// registers, which we do not otherwise model, so they should have 1965// hasSideEffects. 1966let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1967 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1968 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1969 1970 let mayLoad = 1 in 1971 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1972 let mayStore = 1 in 1973 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1974} 1975 1976//===----------------------------------------------------------------------===// 1977// Decimal arithmetic 1978//===----------------------------------------------------------------------===// 1979 1980defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1981def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1982 1983defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1984def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1985 1986let mayLoad = 1, mayStore = 1 in { 1987 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1988 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1989 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1990 1991 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1992 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1993 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1994 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1995 let Defs = [CC] in { 1996 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1997 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1998 } 1999} 2000 2001let mayLoad = 1, mayStore = 1 in { 2002 let Defs = [CC] in { 2003 def AP : SideEffectBinarySSb<"ap", 0xFA>; 2004 def SP : SideEffectBinarySSb<"sp", 0xFB>; 2005 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 2006 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 2007 } 2008 def MP : SideEffectBinarySSb<"mp", 0xFC>; 2009 def DP : SideEffectBinarySSb<"dp", 0xFD>; 2010 let Defs = [CC] in { 2011 def ED : SideEffectBinarySSa<"ed", 0xDE>; 2012 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 2013 } 2014} 2015 2016let Defs = [CC] in { 2017 def CP : CompareSSb<"cp", 0xF9>; 2018 def TP : TestRSL<"tp", 0xEBC0>; 2019} 2020 2021//===----------------------------------------------------------------------===// 2022// Access registers 2023//===----------------------------------------------------------------------===// 2024 2025// Read a 32-bit access register into a GR32. As with all GR32 operations, 2026// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 2027// when a 64-bit address is stored in a pair of access registers. 2028def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 2029 2030// Set access register. 2031def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 2032 2033// Copy access register. 2034def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2035 2036// Load address extended. 2037defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2038 2039// Load access multiple. 2040defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2041 2042// Store access multiple. 2043defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2044 2045//===----------------------------------------------------------------------===// 2046// Program mask and addressing mode 2047//===----------------------------------------------------------------------===// 2048 2049// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2050let Uses = [CC] in 2051 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2052 2053// Set CC and program mask from a register. 2054let hasSideEffects = 1, Defs = [CC] in 2055 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2056 2057// Branch and link - like BAS, but also extracts CC and program mask. 2058let isCall = 1, Uses = [CC], Defs = [CC] in { 2059 def BAL : CallRX<"bal", 0x45>; 2060 def BALR : CallRR<"balr", 0x05>; 2061} 2062 2063// Test addressing mode. 2064let Defs = [CC] in 2065 def TAM : SideEffectInherentE<"tam", 0x010B>; 2066 2067// Set addressing mode. 2068let hasSideEffects = 1 in { 2069 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2070 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2071 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2072} 2073 2074// Branch and set mode. Not really a call, but also sets an output register. 2075let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2076 def BSM : CallRR<"bsm", 0x0B>; 2077 2078// Branch and save and set mode. 2079let isCall = 1, Defs = [CC] in 2080 def BASSM : CallRR<"bassm", 0x0C>; 2081 2082//===----------------------------------------------------------------------===// 2083// Transactional execution 2084//===----------------------------------------------------------------------===// 2085 2086let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2087 // Transaction Begin 2088 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2089 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2090 let hasNoSchedulingInfo = 1 in 2091 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2092 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2093 int_s390_tbeginc, imm32zx16>; 2094 } 2095 2096 // Transaction End 2097 let Defs = [CC] in 2098 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2099 2100 // Transaction Abort 2101 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2102 hasSideEffects = 1 in 2103 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2104 2105 // Nontransactional Store 2106 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2107 2108 // Extract Transaction Nesting Depth 2109 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2110} 2111 2112//===----------------------------------------------------------------------===// 2113// Processor assist 2114//===----------------------------------------------------------------------===// 2115 2116let Predicates = [FeatureProcessorAssist] in { 2117 let hasSideEffects = 1 in 2118 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2119 def : Pat<(int_s390_ppa_txassist GR32:$src), 2120 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2121 zero_reg, 1)>; 2122} 2123 2124//===----------------------------------------------------------------------===// 2125// Miscellaneous Instructions. 2126//===----------------------------------------------------------------------===// 2127 2128// Find leftmost one, AKA count leading zeros. The instruction actually 2129// returns a pair of GR64s, the first giving the number of leading zeros 2130// and the second giving a copy of the source with the leftmost one bit 2131// cleared. We only use the first result here. 2132let Defs = [CC] in 2133 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2134def : Pat<(i64 (ctlz GR64:$src)), 2135 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2136 2137// Population count. Counts bits set per byte or doubleword. 2138let Predicates = [FeatureMiscellaneousExtensions3] in { 2139 let Defs = [CC] in 2140 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2141 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2142} 2143let Predicates = [FeaturePopulationCount], Defs = [CC] in 2144 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2145 2146// Search a block of memory for a character. 2147let mayLoad = 1, Defs = [CC] in 2148 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2149let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2150 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2151 2152// Compare until substring equal. 2153let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2154 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2155 2156// Compare and form codeword. 2157let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2158 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2159 2160// Update tree. 2161let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2162 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2163 def UPT : SideEffectInherentE<"upt", 0x0102>; 2164 2165// Checksum. 2166let mayLoad = 1, Defs = [CC] in 2167 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2168 2169// Compression call. 2170let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2171 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2172 2173// Sort lists. 2174let Predicates = [FeatureEnhancedSort], 2175 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2176 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2177 2178// Deflate conversion call. 2179let Predicates = [FeatureDeflateConversion], 2180 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2181 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2182 GR128, GR128, GR64>; 2183 2184// NNPA. 2185let Predicates = [FeatureNNPAssist], 2186 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2187 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2188 2189// Execute. 2190let hasSideEffects = 1 in { 2191 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2192 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2193 let hasNoSchedulingInfo = 1 in 2194 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2195 bdaddr12only:$bdl1, bdaddr12only:$bd2), 2196 []>; 2197} 2198 2199//===----------------------------------------------------------------------===// 2200// .insn directive instructions 2201//===----------------------------------------------------------------------===// 2202 2203let isCodeGenOnly = 1, hasSideEffects = 1 in { 2204 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2205 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2206 imm32sx16:$I2), 2207 ".insn ri,$enc,$R1,$I2", []>; 2208 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2209 AnyReg:$R3, brtarget16:$I2), 2210 ".insn rie,$enc,$R1,$R3,$I2", []>; 2211 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2212 brtarget32:$I2), 2213 ".insn ril,$enc,$R1,$I2", []>; 2214 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2215 uimm32:$I2), 2216 ".insn rilu,$enc,$R1,$I2", []>; 2217 def InsnRIS : DirectiveInsnRIS<(outs), 2218 (ins imm64zx48:$enc, AnyReg:$R1, 2219 imm32sx8:$I2, imm32zx4:$M3, 2220 bdaddr12only:$BD4), 2221 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2222 def InsnRR : DirectiveInsnRR<(outs), 2223 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2224 ".insn rr,$enc,$R1,$R2", []>; 2225 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2226 AnyReg:$R1, AnyReg:$R2), 2227 ".insn rre,$enc,$R1,$R2", []>; 2228 def InsnRRF : DirectiveInsnRRF<(outs), 2229 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2230 AnyReg:$R3, imm32zx4:$M4), 2231 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2232 def InsnRRS : DirectiveInsnRRS<(outs), 2233 (ins imm64zx48:$enc, AnyReg:$R1, 2234 AnyReg:$R2, imm32zx4:$M3, 2235 bdaddr12only:$BD4), 2236 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2237 def InsnRS : DirectiveInsnRS<(outs), 2238 (ins imm64zx32:$enc, AnyReg:$R1, 2239 AnyReg:$R3, bdaddr12only:$BD2), 2240 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2241 def InsnRSE : DirectiveInsnRSE<(outs), 2242 (ins imm64zx48:$enc, AnyReg:$R1, 2243 AnyReg:$R3, bdaddr12only:$BD2), 2244 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2245 def InsnRSI : DirectiveInsnRSI<(outs), 2246 (ins imm64zx48:$enc, AnyReg:$R1, 2247 AnyReg:$R3, brtarget16:$RI2), 2248 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2249 def InsnRSY : DirectiveInsnRSY<(outs), 2250 (ins imm64zx48:$enc, AnyReg:$R1, 2251 AnyReg:$R3, bdaddr20only:$BD2), 2252 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2253 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2254 bdxaddr12only:$XBD2), 2255 ".insn rx,$enc,$R1,$XBD2", []>; 2256 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2257 bdxaddr12only:$XBD2), 2258 ".insn rxe,$enc,$R1,$XBD2", []>; 2259 def InsnRXF : DirectiveInsnRXF<(outs), 2260 (ins imm64zx48:$enc, AnyReg:$R1, 2261 AnyReg:$R3, bdxaddr12only:$XBD2), 2262 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2263 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2264 bdxaddr20only:$XBD2), 2265 ".insn rxy,$enc,$R1,$XBD2", []>; 2266 def InsnS : DirectiveInsnS<(outs), 2267 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2268 ".insn s,$enc,$BD2", []>; 2269 def InsnSI : DirectiveInsnSI<(outs), 2270 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2271 imm32sx8:$I2), 2272 ".insn si,$enc,$BD1,$I2", []>; 2273 def InsnSIY : DirectiveInsnSIY<(outs), 2274 (ins imm64zx48:$enc, 2275 bdaddr20only:$BD1, imm32zx8:$I2), 2276 ".insn siy,$enc,$BD1,$I2", []>; 2277 def InsnSIL : DirectiveInsnSIL<(outs), 2278 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2279 imm32zx16:$I2), 2280 ".insn sil,$enc,$BD1,$I2", []>; 2281 def InsnSS : DirectiveInsnSS<(outs), 2282 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2283 bdaddr12only:$BD2, AnyReg:$R3), 2284 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2285 def InsnSSE : DirectiveInsnSSE<(outs), 2286 (ins imm64zx48:$enc, 2287 bdaddr12only:$BD1,bdaddr12only:$BD2), 2288 ".insn sse,$enc,$BD1,$BD2", []>; 2289 def InsnSSF : DirectiveInsnSSF<(outs), 2290 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2291 bdaddr12only:$BD2, AnyReg:$R3), 2292 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2293 def InsnVRI : DirectiveInsnVRI<(outs), 2294 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2295 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2296 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2297 def InsnVRR : DirectiveInsnVRR<(outs), 2298 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2299 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2300 imm32zx4:$M6), 2301 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2302 def InsnVRS : DirectiveInsnVRS<(outs), 2303 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2304 bdaddr12only:$BD2, imm32zx4:$M4), 2305 ".insn vrs,$enc,$BD2,$M4", []>; 2306 def InsnVRV : DirectiveInsnVRV<(outs), 2307 (ins imm64zx48:$enc, VR128:$V1, 2308 bdvaddr12only:$VBD2, imm32zx4:$M3), 2309 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2310 def InsnVRX : DirectiveInsnVRX<(outs), 2311 (ins imm64zx48:$enc, VR128:$V1, 2312 bdxaddr12only:$XBD2, imm32zx4:$M3), 2313 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2314 def InsnVSI : DirectiveInsnVSI<(outs), 2315 (ins imm64zx48:$enc, VR128:$V1, 2316 bdaddr12only:$BD2, imm32zx8:$I3), 2317 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2318} 2319 2320//===----------------------------------------------------------------------===// 2321// Peepholes. 2322//===----------------------------------------------------------------------===// 2323 2324// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2325// equivalent to (and (xor x, -1), y) 2326def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2327 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2328 2329// Shift/rotate instructions only use the last 6 bits of the second operand 2330// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2331// last 16 bits. 2332// Complexity is added so that we match this before we match NILF on the AND 2333// operation alone. 2334let AddedComplexity = 4 in { 2335 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2336 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2337 2338 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2339 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2340 2341 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2342 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2343 2344 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2345 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2346 2347 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2348 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2349 2350 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2351 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2352 2353 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2354 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2355 2356 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2357 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2358} 2359 2360// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2361// use the last 6 bits of the second operand register (making it modulo 64). 2362let AddedComplexity = 4 in { 2363 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2364 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2365 2366 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2367 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2368 2369 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2370 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2371 2372 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2373 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2374} 2375 2376// Peepholes for turning scalar operations into block operations. The length 2377// is given as one less for these pseudos. 2378defm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>; 2379defm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>; 2380defm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>; 2381defm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>; 2382defm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>; 2383defm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>; 2384defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>; 2385 2386//===----------------------------------------------------------------------===// 2387// Mnemonic Aliases 2388//===----------------------------------------------------------------------===// 2389 2390def JCT : MnemonicAlias<"jct", "brct">; 2391def JCTG : MnemonicAlias<"jctg", "brctg">; 2392def JAS : MnemonicAlias<"jas", "bras">; 2393def JASL : MnemonicAlias<"jasl", "brasl">; 2394def JXH : MnemonicAlias<"jxh", "brxh">; 2395def JXLE : MnemonicAlias<"jxle", "brxle">; 2396def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2397def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2398 2399def BRU : MnemonicAlias<"bru", "j">; 2400def BRUL : MnemonicAlias<"brul", "jg", "att">; 2401def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2402 2403foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2404 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2405 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2406 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; 2407 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2408} 2409