1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14// The callseq_start node requires the hasSideEffects flag, even though these 15// instructions are noops on SystemZ. 16let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 17 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_start timm:$amt1, timm:$amt2)]>; 19 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_end timm:$amt1, timm:$amt2)]>; 21} 22 23// Takes as input the value of the stack pointer after a dynamic allocation 24// has been made. Sets the output to the address of the dynamically- 25// allocated area itself, skipping the outgoing arguments. 26// 27// This expands to an LA or LAY instruction. We restrict the offset 28// to the range of LA and keep the LAY range in reserve for when 29// the size of the outgoing arguments is added. 30def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 31 [(set GR64:$dst, dynalloc12only:$src)]>; 32 33 34//===----------------------------------------------------------------------===// 35// Branch instructions 36//===----------------------------------------------------------------------===// 37 38// Conditional branches. 39let isBranch = 1, isTerminator = 1, Uses = [CC] in { 40 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 41 // with the condition-code mask being the first operand. It seems friendlier 42 // to use mnemonic forms like JE and JLH when writing out the assembly though. 43 let isCodeGenOnly = 1 in { 44 // An assembler extended mnemonic for BRC. 45 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 46 // An assembler extended mnemonic for BRCL. (The extension is "G" 47 // rather than "L" because "JL" is "Jump if Less".) 48 def BRCL : CondBranchRIL<"jg#", 0xC04>; 49 let isIndirectBranch = 1 in { 50 def BC : CondBranchRX<"b#", 0x47>; 51 def BCR : CondBranchRR<"b#r", 0x07>; 52 def BIC : CondBranchRXY<"bi#", 0xe347>, 53 Requires<[FeatureMiscellaneousExtensions2]>; 54 } 55 } 56 57 // Allow using the raw forms directly from the assembler (and occasional 58 // special code generation needs) as well. 59 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 60 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 61 let isIndirectBranch = 1 in { 62 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 63 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 64 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 65 Requires<[FeatureMiscellaneousExtensions2]>; 66 } 67 68 // Define AsmParser extended mnemonics for each general condition-code mask 69 // (integer or floating-point) 70 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 71 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 72 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 73 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 74 let isIndirectBranch = 1 in { 75 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 76 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 77 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 78 Requires<[FeatureMiscellaneousExtensions2]>; 79 } 80 } 81} 82 83// Unconditional branches. These are in fact simply variants of the 84// conditional branches with the condition mask set to "always". 85let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 86 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 87 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 88 let isIndirectBranch = 1 in { 89 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 90 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 91 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 92 Requires<[FeatureMiscellaneousExtensions2]>; 93 } 94} 95 96// NOPs. These are again variants of the conditional branches, 97// with the condition mask set to "never". 98def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 99def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 100 101// Fused compare-and-branch instructions. 102// 103// These instructions do not use or clobber the condition codes. 104// We nevertheless pretend that the relative compare-and-branch 105// instructions clobber CC, so that we can lower them to separate 106// comparisons and BRCLs if the branch ends up being out of range. 107let isBranch = 1, isTerminator = 1 in { 108 // As for normal branches, we handle these instructions internally in 109 // their raw CRJ-like form, but use assembly macros like CRJE when writing 110 // them out. Using the *Pair multiclasses, we also create the raw forms. 111 let Defs = [CC] in { 112 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 113 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 114 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 115 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 116 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 117 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 118 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 119 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 120 } 121 let isIndirectBranch = 1 in { 122 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 123 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 124 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 125 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 126 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 127 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 128 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 129 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 130 } 131 132 // Define AsmParser mnemonics for each integer condition-code mask. 133 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 134 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 135 let Defs = [CC] in { 136 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 137 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 138 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 139 imm32sx8>; 140 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 141 imm64sx8>; 142 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 143 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 144 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 145 imm32zx8>; 146 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 147 imm64zx8>; 148 } 149 let isIndirectBranch = 1 in { 150 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 151 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 152 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 153 imm32sx8>; 154 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 155 imm64sx8>; 156 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 157 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 158 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 159 imm32zx8>; 160 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 161 imm64zx8>; 162 } 163 } 164} 165 166// Decrement a register and branch if it is nonzero. These don't clobber CC, 167// but we might need to split long relative branches into sequences that do. 168let isBranch = 1, isTerminator = 1 in { 169 let Defs = [CC] in { 170 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 171 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 172 } 173 // This doesn't need to clobber CC since we never need to split it. 174 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 175 Requires<[FeatureHighWord]>; 176 177 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 178 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 179 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 180 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 181} 182 183let isBranch = 1, isTerminator = 1 in { 184 let Defs = [CC] in { 185 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 186 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 187 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 188 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 189 } 190 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 191 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 192 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 193 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 194} 195 196//===----------------------------------------------------------------------===// 197// Trap instructions 198//===----------------------------------------------------------------------===// 199 200// Unconditional trap. 201let hasCtrlDep = 1, hasSideEffects = 1 in 202 def Trap : Alias<4, (outs), (ins), [(trap)]>; 203 204// Conditional trap. 205let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 206 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 207 208// Fused compare-and-trap instructions. 209let hasCtrlDep = 1, hasSideEffects = 1 in { 210 // These patterns work the same way as for compare-and-branch. 211 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 212 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 213 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 214 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 215 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 216 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 217 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 218 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 219 let Predicates = [FeatureMiscellaneousExtensions] in { 220 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 221 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 222 } 223 224 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 225 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 226 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 227 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 228 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 229 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 230 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 231 imm32sx16>; 232 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 233 imm64sx16>; 234 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 235 imm32zx16>; 236 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 237 imm64zx16>; 238 let Predicates = [FeatureMiscellaneousExtensions] in { 239 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 240 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 241 } 242 } 243} 244 245//===----------------------------------------------------------------------===// 246// Call and return instructions 247//===----------------------------------------------------------------------===// 248 249// Define the general form of the call instructions for the asm parser. 250// These instructions don't hard-code %r14 as the return address register. 251let isCall = 1, Defs = [CC] in { 252 def BRAS : CallRI <"bras", 0xA75>; 253 def BRASL : CallRIL<"brasl", 0xC05>; 254 def BAS : CallRX <"bas", 0x4D>; 255 def BASR : CallRR <"basr", 0x0D>; 256} 257 258// Regular calls. 259let isCall = 1, Defs = [R14D, CC] in { 260 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 261 [(z_call pcrel32:$I2)]>; 262 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 263 [(z_call ADDR64:$R2)]>; 264} 265 266// TLS calls. These will be lowered into a call to __tls_get_offset, 267// with an extra relocation specifying the TLS symbol. 268let isCall = 1, Defs = [R14D, CC] in { 269 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 270 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 271 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 272 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 273} 274 275// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 276// are argument registers and since branching to R0 is a no-op. 277let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 278 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 279 [(z_sibcall pcrel32:$I2)]>; 280 let Uses = [R1D] in 281 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 282} 283 284// Conditional sibling calls. 285let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 286 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 287 pcrel32:$I2), []>; 288 let Uses = [R1D] in 289 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 290} 291 292// Fused compare and conditional sibling calls. 293let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 294 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 295 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 296 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 297 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 298 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 299 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 300 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 301 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 302} 303 304// A return instruction (br %r14). 305let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 306 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 307 308// A conditional return instruction (bcr <cond>, %r14). 309let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 310 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 311 312// Fused compare and conditional returns. 313let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 314 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 315 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 316 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 317 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 318 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 319 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 320 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 321 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 322} 323 324//===----------------------------------------------------------------------===// 325// Select instructions 326//===----------------------------------------------------------------------===// 327 328def Select32Mux : SelectWrapper<i32, GRX32>, Requires<[FeatureHighWord]>; 329def Select32 : SelectWrapper<i32, GR32>; 330def Select64 : SelectWrapper<i64, GR64>; 331 332// We don't define 32-bit Mux stores if we don't have STOCFH, because the 333// low-only STOC should then always be used if possible. 334defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 335 nonvolatile_anyextloadi8, bdxaddr20only>, 336 Requires<[FeatureHighWord]>; 337defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 338 nonvolatile_anyextloadi16, bdxaddr20only>, 339 Requires<[FeatureHighWord]>; 340defm CondStore32Mux : CondStores<GRX32, nonvolatile_store, 341 nonvolatile_load, bdxaddr20only>, 342 Requires<[FeatureLoadStoreOnCond2]>; 343defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 344 nonvolatile_anyextloadi8, bdxaddr20only>; 345defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 346 nonvolatile_anyextloadi16, bdxaddr20only>; 347defm CondStore32 : CondStores<GR32, nonvolatile_store, 348 nonvolatile_load, bdxaddr20only>; 349 350defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 351 nonvolatile_anyextloadi8, bdxaddr20only>; 352defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 353 nonvolatile_anyextloadi16, bdxaddr20only>; 354defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 355 nonvolatile_anyextloadi32, bdxaddr20only>; 356defm CondStore64 : CondStores<GR64, nonvolatile_store, 357 nonvolatile_load, bdxaddr20only>; 358 359//===----------------------------------------------------------------------===// 360// Move instructions 361//===----------------------------------------------------------------------===// 362 363// Register moves. 364// Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 365def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>, 366 Requires<[FeatureHighWord]>; 367def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 368def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 369 370let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 371 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 372 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 373} 374 375let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 376 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 377 378// Immediate moves. 379let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 380 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 381 // deopending on the choice of register. 382 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 383 Requires<[FeatureHighWord]>; 384 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 385 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 386 387 // Other 16-bit immediates. 388 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 389 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 390 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 391 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 392 393 // 32-bit immediates. 394 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 395 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 396 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 397} 398 399// Register loads. 400let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 401 // Expands to L, LY or LFH, depending on the choice of register. 402 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 403 Requires<[FeatureHighWord]>; 404 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 405 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 406 Requires<[FeatureHighWord]>; 407 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 408 409 // These instructions are split after register allocation, so we don't 410 // want a custom inserter. 411 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 412 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 413 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 414 } 415} 416let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 417 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 418 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 419} 420 421let canFoldAsLoad = 1 in { 422 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 423 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 424} 425 426// Load and zero rightmost byte. 427let Predicates = [FeatureLoadAndZeroRightmostByte] in { 428 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 429 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 430 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 431 (LZRF bdxaddr20only:$src)>; 432 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 433 (LZRG bdxaddr20only:$src)>; 434} 435 436// Load and trap. 437let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 438 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 439 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 440 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 441} 442 443// Register stores. 444let SimpleBDXStore = 1, mayStore = 1 in { 445 // Expands to ST, STY or STFH, depending on the choice of register. 446 def STMux : StoreRXYPseudo<store, GRX32, 4>, 447 Requires<[FeatureHighWord]>; 448 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 449 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 450 Requires<[FeatureHighWord]>; 451 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 452 453 // These instructions are split after register allocation, so we don't 454 // want a custom inserter. 455 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 456 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 457 [(store GR128:$src, bdxaddr20only128:$dst)]>; 458 } 459} 460def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 461def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 462 463// 8-bit immediate stores to 8-bit fields. 464defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 465 466// 16-bit immediate stores to 16-, 32- or 64-bit fields. 467def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 468def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 469def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 470 471// Memory-to-memory moves. 472let mayLoad = 1, mayStore = 1 in 473 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 474let mayLoad = 1, mayStore = 1, Defs = [CC] in { 475 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 476 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 477 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 478} 479 480// String moves. 481let mayLoad = 1, mayStore = 1, Defs = [CC] in 482 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 483 484//===----------------------------------------------------------------------===// 485// Conditional move instructions 486//===----------------------------------------------------------------------===// 487 488let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 489 // Load immediate on condition. Matched via DAG pattern and created 490 // by the PeepholeOptimizer via FoldImmediate. 491 492 // Expands to LOCHI or LOCHHI, depending on the choice of register. 493 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 494 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 495 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 496 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 497 498 // Move register on condition. Expanded from Select* pseudos and 499 // created by early if-conversion. 500 let isCommutable = 1 in { 501 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 502 // depending on the choice of registers. 503 def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>; 504 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 505 } 506 507 // Load on condition. Matched via DAG pattern. 508 // Expands to LOC or LOCFH, depending on the choice of register. 509 def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>; 510 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>; 511 512 // Store on condition. Expanded from CondStore* pseudos. 513 // Expands to STOC or STOCFH, depending on the choice of register. 514 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 515 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 516 517 // Define AsmParser extended mnemonics for each general condition-code mask. 518 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 519 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 520 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 521 imm32sx16>; 522 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 523 imm64sx16>; 524 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 525 imm32sx16>; 526 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 527 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 528 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 529 } 530} 531 532let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 533 // Move register on condition. Expanded from Select* pseudos and 534 // created by early if-conversion. 535 let isCommutable = 1 in { 536 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 537 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 538 } 539 540 // Load on condition. Matched via DAG pattern. 541 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 542 defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 543 544 // Store on condition. Expanded from CondStore* pseudos. 545 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 546 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 547 548 // Define AsmParser extended mnemonics for each general condition-code mask. 549 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 550 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 551 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 552 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 553 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 554 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 555 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 556 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 557 } 558} 559//===----------------------------------------------------------------------===// 560// Sign extensions 561//===----------------------------------------------------------------------===// 562// 563// Note that putting these before zero extensions mean that we will prefer 564// them for anyextload*. There's not really much to choose between the two 565// either way, but signed-extending loads have a short LH and a long LHY, 566// while zero-extending loads have only the long LLH. 567// 568//===----------------------------------------------------------------------===// 569 570// 32-bit extensions from registers. 571def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 572def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 573 574// 64-bit extensions from registers. 575def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 576def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 577def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 578 579let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 580 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 581 582// Match 32-to-64-bit sign extensions in which the source is already 583// in a 64-bit register. 584def : Pat<(sext_inreg GR64:$src, i32), 585 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 586 587// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 588// depending on the choice of register. 589def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 590 Requires<[FeatureHighWord]>; 591def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 592def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 593 Requires<[FeatureHighWord]>; 594 595// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 596// depending on the choice of register. 597def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 598 Requires<[FeatureHighWord]>; 599defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 600def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 601 Requires<[FeatureHighWord]>; 602def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 603 604// 64-bit extensions from memory. 605def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 606def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 607def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 608def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 609def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 610let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 611 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 612 613//===----------------------------------------------------------------------===// 614// Zero extensions 615//===----------------------------------------------------------------------===// 616 617// 32-bit extensions from registers. 618 619// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 620def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 621 Requires<[FeatureHighWord]>; 622def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 623// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 624def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 625 Requires<[FeatureHighWord]>; 626def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 627 628// 64-bit extensions from registers. 629def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 630def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 631def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 632 633// Match 32-to-64-bit zero extensions in which the source is already 634// in a 64-bit register. 635def : Pat<(and GR64:$src, 0xffffffff), 636 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 637 638// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 639// depending on the choice of register. 640def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 641 Requires<[FeatureHighWord]>; 642def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 643def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 644 Requires<[FeatureHighWord]>; 645 646// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 647// depending on the choice of register. 648def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 649 Requires<[FeatureHighWord]>; 650def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 651def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 652 Requires<[FeatureHighWord]>; 653def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 654 655// 64-bit extensions from memory. 656def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 657def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 658def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 659def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 660def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 661 662// 31-to-64-bit zero extensions. 663def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 664def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 665def : Pat<(and GR64:$src, 0x7fffffff), 666 (LLGTR GR64:$src)>; 667def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 668 (LLGT bdxaddr20only:$src)>; 669 670// Load and zero rightmost byte. 671let Predicates = [FeatureLoadAndZeroRightmostByte] in { 672 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 673 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 674 (LLZRGF bdxaddr20only:$src)>; 675} 676 677// Load and trap. 678let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 679 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 680 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 681} 682 683// Extend GR64s to GR128s. 684let usesCustomInserter = 1 in 685 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 686 687//===----------------------------------------------------------------------===// 688// "Any" extensions 689//===----------------------------------------------------------------------===// 690 691// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 692def : Pat<(i64 (anyext GR32:$src)), 693 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 694 695// Extend GR64s to GR128s. 696let usesCustomInserter = 1 in 697 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 698 699//===----------------------------------------------------------------------===// 700// Truncations 701//===----------------------------------------------------------------------===// 702 703// Truncations of 64-bit registers to 32-bit registers. 704def : Pat<(i32 (trunc GR64:$src)), 705 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 706 707// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 708// STC, STCY or STCH, depending on the choice of register. 709def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 710 Requires<[FeatureHighWord]>; 711defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 712def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 713 Requires<[FeatureHighWord]>; 714 715// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 716// STH, STHY or STHH, depending on the choice of register. 717def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 718 Requires<[FeatureHighWord]>; 719defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 720def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 721 Requires<[FeatureHighWord]>; 722def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 723 724// Truncations of 64-bit registers to memory. 725defm : StoreGR64Pair<STC, STCY, truncstorei8>; 726defm : StoreGR64Pair<STH, STHY, truncstorei16>; 727def : StoreGR64PC<STHRL, aligned_truncstorei16>; 728defm : StoreGR64Pair<ST, STY, truncstorei32>; 729def : StoreGR64PC<STRL, aligned_truncstorei32>; 730 731// Store characters under mask -- not (yet) used for codegen. 732defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 733def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 734 735//===----------------------------------------------------------------------===// 736// Multi-register moves 737//===----------------------------------------------------------------------===// 738 739// Multi-register loads. 740defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 741def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 742def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 743def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 744 745// Multi-register stores. 746defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 747def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 748def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 749 750//===----------------------------------------------------------------------===// 751// Byte swaps 752//===----------------------------------------------------------------------===// 753 754// Byte-swapping register moves. 755def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 756def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 757 758// Byte-swapping loads. Unlike normal loads, these instructions are 759// allowed to access storage more than once. 760def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 761def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 762def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 763 764// Likewise byte-swapping stores. 765def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 766def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 767def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 768 769// Byte-swapping memory-to-memory moves. 770let mayLoad = 1, mayStore = 1 in 771 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 772 773//===----------------------------------------------------------------------===// 774// Load address instructions 775//===----------------------------------------------------------------------===// 776 777// Load BDX-style addresses. 778let isAsCheapAsAMove = 1, isReMaterializable = 1 in 779 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 780 781// Load a PC-relative address. There's no version of this instruction 782// with a 16-bit offset, so there's no relaxation. 783let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 784 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 785 786// Load the Global Offset Table address. This will be lowered into a 787// larl $R1, _GLOBAL_OFFSET_TABLE_ 788// instruction. 789def GOT : Alias<6, (outs GR64:$R1), (ins), 790 [(set GR64:$R1, (global_offset_table))]>; 791 792//===----------------------------------------------------------------------===// 793// Absolute and Negation 794//===----------------------------------------------------------------------===// 795 796let Defs = [CC] in { 797 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 798 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 799 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 800 } 801 let CCValues = 0xE, CompareZeroCCMask = 0xE in 802 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 803} 804def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 805def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 806defm : SXU<z_iabs, LPGFR>; 807defm : SXU<z_iabs64, LPGFR>; 808 809let Defs = [CC] in { 810 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 811 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 812 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 813 } 814 let CCValues = 0xE, CompareZeroCCMask = 0xE in 815 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 816} 817def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 818def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 819defm : SXU<z_inegabs, LNGFR>; 820defm : SXU<z_inegabs64, LNGFR>; 821 822let Defs = [CC] in { 823 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 824 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 825 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 826 } 827 let CCValues = 0xE, CompareZeroCCMask = 0xE in 828 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 829} 830defm : SXU<ineg, LCGFR>; 831 832//===----------------------------------------------------------------------===// 833// Insertion 834//===----------------------------------------------------------------------===// 835 836let isCodeGenOnly = 1 in 837 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 838defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 839 840defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 841defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 842 843defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 844defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 845 846// Insert characters under mask -- not (yet) used for codegen. 847let Defs = [CC] in { 848 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 849 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 850} 851 852// Insertions of a 16-bit immediate, leaving other bits unaffected. 853// We don't have or_as_insert equivalents of these operations because 854// OI is available instead. 855// 856// IIxMux expands to II[LH]x, depending on the choice of register. 857def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 858 Requires<[FeatureHighWord]>; 859def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 860 Requires<[FeatureHighWord]>; 861def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 862def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 863def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 864def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 865def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 866def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 867def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 868def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 869 870// ...likewise for 32-bit immediates. For GR32s this is a general 871// full-width move. (We use IILF rather than something like LLILF 872// for 32-bit moves because IILF leaves the upper 32 bits of the 873// GR64 unchanged.) 874let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 875 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 876 Requires<[FeatureHighWord]>; 877 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 878 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 879} 880def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 881def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 882 883// An alternative model of inserthf, with the first operand being 884// a zero-extended value. 885def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 886 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 887 imm64hf32:$imm)>; 888 889//===----------------------------------------------------------------------===// 890// Addition 891//===----------------------------------------------------------------------===// 892 893// Plain addition. 894let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 895 // Addition of a register. 896 let isCommutable = 1 in { 897 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, add, GR32, GR32>; 898 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, add, GR64, GR64>; 899 } 900 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 901 902 // Addition to a high register. 903 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 904 Requires<[FeatureHighWord]>; 905 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 906 Requires<[FeatureHighWord]>; 907 908 // Addition of signed 16-bit immediates. 909 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 910 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 911 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 912 913 // Addition of signed 32-bit immediates. 914 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 915 Requires<[FeatureHighWord]>; 916 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 917 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 918 Requires<[FeatureHighWord]>; 919 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 920 921 // Addition of memory. 922 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 923 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 924 def AGH : BinaryRXY<"agh", 0xE338, add, GR64, asextloadi16, 2>, 925 Requires<[FeatureMiscellaneousExtensions2]>; 926 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 927 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 928 929 // Addition to memory. 930 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 931 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 932} 933defm : SXB<add, GR64, AGFR>; 934 935// Addition producing a carry. 936let Defs = [CC] in { 937 // Addition of a register. 938 let isCommutable = 1 in { 939 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, addc, GR32, GR32>; 940 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, addc, GR64, GR64>; 941 } 942 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 943 944 // Addition to a high register. 945 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 946 Requires<[FeatureHighWord]>; 947 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 948 Requires<[FeatureHighWord]>; 949 950 // Addition of signed 16-bit immediates. 951 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 952 Requires<[FeatureDistinctOps]>; 953 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 954 Requires<[FeatureDistinctOps]>; 955 956 // Addition of unsigned 32-bit immediates. 957 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 958 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 959 960 // Addition of signed 32-bit immediates. 961 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 962 Requires<[FeatureHighWord]>; 963 964 // Addition of memory. 965 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 966 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 967 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 968 969 // Addition to memory. 970 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 971 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 972} 973defm : ZXB<addc, GR64, ALGFR>; 974 975// Addition producing and using a carry. 976let Defs = [CC], Uses = [CC] in { 977 // Addition of a register. 978 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>; 979 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>; 980 981 // Addition of memory. 982 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 983 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 984} 985 986// Addition that does not modify the condition code. 987def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 988 Requires<[FeatureHighWord]>; 989 990//===----------------------------------------------------------------------===// 991// Subtraction 992//===----------------------------------------------------------------------===// 993 994// Plain subtraction. Although immediate forms exist, we use the 995// add-immediate instruction instead. 996let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 997 // Subtraction of a register. 998 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, sub, GR32, GR32>; 999 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1000 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, sub, GR64, GR64>; 1001 1002 // Subtraction from a high register. 1003 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1004 Requires<[FeatureHighWord]>; 1005 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1006 Requires<[FeatureHighWord]>; 1007 1008 // Subtraction of memory. 1009 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 1010 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 1011 def SGH : BinaryRXY<"sgh", 0xE339, sub, GR64, asextloadi16, 2>, 1012 Requires<[FeatureMiscellaneousExtensions2]>; 1013 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 1014 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 1015} 1016defm : SXB<sub, GR64, SGFR>; 1017 1018// Subtraction producing a carry. 1019let Defs = [CC] in { 1020 // Subtraction of a register. 1021 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, subc, GR32, GR32>; 1022 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1023 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, subc, GR64, GR64>; 1024 1025 // Subtraction from a high register. 1026 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1027 Requires<[FeatureHighWord]>; 1028 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1029 Requires<[FeatureHighWord]>; 1030 1031 // Subtraction of unsigned 32-bit immediates. These don't match 1032 // subc because we prefer addc for constants. 1033 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 1034 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 1035 1036 // Subtraction of memory. 1037 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 1038 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 1039 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 1040} 1041defm : ZXB<subc, GR64, SLGFR>; 1042 1043// Subtraction producing and using a carry. 1044let Defs = [CC], Uses = [CC] in { 1045 // Subtraction of a register. 1046 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>; 1047 def SLBGR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>; 1048 1049 // Subtraction of memory. 1050 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 1051 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 1052} 1053 1054//===----------------------------------------------------------------------===// 1055// AND 1056//===----------------------------------------------------------------------===// 1057 1058let Defs = [CC] in { 1059 // ANDs of a register. 1060 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1061 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1062 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1063 } 1064 1065 let isConvertibleToThreeAddress = 1 in { 1066 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1067 // The CC result only reflects the 16-bit field, not the full register. 1068 // 1069 // NIxMux expands to NI[LH]x, depending on the choice of register. 1070 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1071 Requires<[FeatureHighWord]>; 1072 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1073 Requires<[FeatureHighWord]>; 1074 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1075 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1076 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1077 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1078 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1079 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1080 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1081 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1082 1083 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1084 // The CC result only reflects the 32-bit field, which means we can 1085 // use it as a zero indicator for i32 operations but not otherwise. 1086 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1087 // Expands to NILF or NIHF, depending on the choice of register. 1088 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1089 Requires<[FeatureHighWord]>; 1090 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1091 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1092 } 1093 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1094 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1095 } 1096 1097 // ANDs of memory. 1098 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1099 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1100 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1101 } 1102 1103 // AND to memory 1104 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1105 1106 // Block AND. 1107 let mayLoad = 1, mayStore = 1 in 1108 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1109} 1110defm : RMWIByte<and, bdaddr12pair, NI>; 1111defm : RMWIByte<and, bdaddr20pair, NIY>; 1112 1113//===----------------------------------------------------------------------===// 1114// OR 1115//===----------------------------------------------------------------------===// 1116 1117let Defs = [CC] in { 1118 // ORs of a register. 1119 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1120 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1121 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1122 } 1123 1124 // ORs of a 16-bit immediate, leaving other bits unaffected. 1125 // The CC result only reflects the 16-bit field, not the full register. 1126 // 1127 // OIxMux expands to OI[LH]x, depending on the choice of register. 1128 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1129 Requires<[FeatureHighWord]>; 1130 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1131 Requires<[FeatureHighWord]>; 1132 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1133 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1134 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1135 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1136 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1137 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1138 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1139 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1140 1141 // ORs of a 32-bit immediate, leaving other bits unaffected. 1142 // The CC result only reflects the 32-bit field, which means we can 1143 // use it as a zero indicator for i32 operations but not otherwise. 1144 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1145 // Expands to OILF or OIHF, depending on the choice of register. 1146 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1147 Requires<[FeatureHighWord]>; 1148 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1149 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1150 } 1151 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1152 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1153 1154 // ORs of memory. 1155 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1156 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1157 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1158 } 1159 1160 // OR to memory 1161 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1162 1163 // Block OR. 1164 let mayLoad = 1, mayStore = 1 in 1165 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1166} 1167defm : RMWIByte<or, bdaddr12pair, OI>; 1168defm : RMWIByte<or, bdaddr20pair, OIY>; 1169 1170//===----------------------------------------------------------------------===// 1171// XOR 1172//===----------------------------------------------------------------------===// 1173 1174let Defs = [CC] in { 1175 // XORs of a register. 1176 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1177 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1178 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1179 } 1180 1181 // XORs of a 32-bit immediate, leaving other bits unaffected. 1182 // The CC result only reflects the 32-bit field, which means we can 1183 // use it as a zero indicator for i32 operations but not otherwise. 1184 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1185 // Expands to XILF or XIHF, depending on the choice of register. 1186 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1187 Requires<[FeatureHighWord]>; 1188 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1189 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1190 } 1191 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1192 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1193 1194 // XORs of memory. 1195 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1196 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1197 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1198 } 1199 1200 // XOR to memory 1201 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1202 1203 // Block XOR. 1204 let mayLoad = 1, mayStore = 1 in 1205 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1206} 1207defm : RMWIByte<xor, bdaddr12pair, XI>; 1208defm : RMWIByte<xor, bdaddr20pair, XIY>; 1209 1210//===----------------------------------------------------------------------===// 1211// Multiplication 1212//===----------------------------------------------------------------------===// 1213 1214// Multiplication of a register, setting the condition code. We prefer these 1215// over MS(G)R if available, even though we cannot use the condition code, 1216// since they are three-operand instructions. 1217let Predicates = [FeatureMiscellaneousExtensions2], 1218 Defs = [CC], isCommutable = 1 in { 1219 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1220 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1221} 1222 1223// Multiplication of a register. 1224let isCommutable = 1 in { 1225 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1226 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1227} 1228def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1229defm : SXB<mul, GR64, MSGFR>; 1230 1231// Multiplication of a signed 16-bit immediate. 1232def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1233def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1234 1235// Multiplication of a signed 32-bit immediate. 1236def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1237def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1238 1239// Multiplication of memory. 1240defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1241defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1242def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1243 Requires<[FeatureMiscellaneousExtensions2]>; 1244def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1245def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1246 1247// Multiplication of memory, setting the condition code. 1248let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1249 def MSC : BinaryRXY<"msc", 0xE353, null_frag, GR32, load, 4>; 1250 def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>; 1251} 1252 1253// Multiplication of a register, producing two results. 1254def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1255def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1256 Requires<[FeatureMiscellaneousExtensions2]>; 1257def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1258def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1259 1260def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1261 (MGRK GR64:$src1, GR64:$src2)>; 1262def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1263 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1264 1265// Multiplication of memory, producing two results. 1266def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1267def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1268def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1269 Requires<[FeatureMiscellaneousExtensions2]>; 1270def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1271def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1272 1273def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1274 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1275def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1276 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1277 1278//===----------------------------------------------------------------------===// 1279// Division and remainder 1280//===----------------------------------------------------------------------===// 1281 1282let hasSideEffects = 1 in { // Do not speculatively execute. 1283 // Division and remainder, from registers. 1284 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1285 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1286 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1287 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1288 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1289 1290 // Division and remainder, from memory. 1291 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1292 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1293 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1294 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1295 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1296} 1297def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1298 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1299def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1300 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1301def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1302 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1303def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1304 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1305 1306def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1307 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1308 subreg_l32)), GR32:$src2)>; 1309def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1310 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1311 subreg_l32)), bdxaddr20only:$src2)>; 1312def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1313 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1314def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1315 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1316 1317//===----------------------------------------------------------------------===// 1318// Shifts 1319//===----------------------------------------------------------------------===// 1320 1321// Logical shift left. 1322defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1323def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1324def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1325 1326// Arithmetic shift left. 1327let Defs = [CC] in { 1328 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1329 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1330 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1331} 1332 1333// Logical shift right. 1334defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1335def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1336def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1337 1338// Arithmetic shift right. 1339let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1340 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1341 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1342 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1343} 1344 1345// Rotate left. 1346def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1347def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1348 1349// Rotate second operand left and inserted selected bits into first operand. 1350// These can act like 32-bit operands provided that the constant start and 1351// end bits (operands 2 and 3) are in the range [32, 64). 1352let Defs = [CC] in { 1353 let isCodeGenOnly = 1 in 1354 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1355 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1356 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1357} 1358 1359// On zEC12 we have a variant of RISBG that does not set CC. 1360let Predicates = [FeatureMiscellaneousExtensions] in 1361 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1362 1363// Forms of RISBG that only affect one word of the destination register. 1364// They do not set CC. 1365let Predicates = [FeatureHighWord] in { 1366 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1367 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1368 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1369 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1370 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1371 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1372 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1373} 1374 1375// Rotate second operand left and perform a logical operation with selected 1376// bits of the first operand. The CC result only describes the selected bits, 1377// so isn't useful for a full comparison against zero. 1378let Defs = [CC] in { 1379 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1380 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1381 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1382} 1383 1384//===----------------------------------------------------------------------===// 1385// Comparison 1386//===----------------------------------------------------------------------===// 1387 1388// Signed comparisons. We put these before the unsigned comparisons because 1389// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1390// of the unsigned forms do. 1391let Defs = [CC], CCValues = 0xE in { 1392 // Comparison with a register. 1393 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1394 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1395 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1396 1397 // Comparison with a high register. 1398 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1399 Requires<[FeatureHighWord]>; 1400 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1401 Requires<[FeatureHighWord]>; 1402 1403 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1404 // depending on the choice of register. 1405 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1406 Requires<[FeatureHighWord]>; 1407 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1408 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1409 1410 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1411 // depending on the choice of register. 1412 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1413 Requires<[FeatureHighWord]>; 1414 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1415 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1416 Requires<[FeatureHighWord]>; 1417 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1418 1419 // Comparison with memory. 1420 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1421 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1422 Requires<[FeatureHighWord]>; 1423 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1424 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1425 Requires<[FeatureHighWord]>; 1426 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1427 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1428 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1429 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1430 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1431 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1432 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1433 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1434 1435 // Comparison between memory and a signed 16-bit immediate. 1436 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1437 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1438 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1439} 1440defm : SXB<z_scmp, GR64, CGFR>; 1441 1442// Unsigned comparisons. 1443let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1444 // Comparison with a register. 1445 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1446 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1447 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1448 1449 // Comparison with a high register. 1450 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1451 Requires<[FeatureHighWord]>; 1452 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1453 Requires<[FeatureHighWord]>; 1454 1455 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1456 // or CLIH, depending on the choice of register. 1457 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1458 Requires<[FeatureHighWord]>; 1459 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1460 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1461 Requires<[FeatureHighWord]>; 1462 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1463 1464 // Comparison with memory. 1465 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1466 Requires<[FeatureHighWord]>; 1467 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1468 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1469 Requires<[FeatureHighWord]>; 1470 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1471 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1472 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1473 aligned_azextloadi16>; 1474 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1475 aligned_load>; 1476 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1477 aligned_azextloadi16>; 1478 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1479 aligned_azextloadi32>; 1480 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1481 aligned_load>; 1482 1483 // Comparison between memory and an unsigned 8-bit immediate. 1484 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1485 1486 // Comparison between memory and an unsigned 16-bit immediate. 1487 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1488 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1489 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1490} 1491defm : ZXB<z_ucmp, GR64, CLGFR>; 1492 1493// Memory-to-memory comparison. 1494let mayLoad = 1, Defs = [CC] in { 1495 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1496 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1497 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1498 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1499} 1500 1501// String comparison. 1502let mayLoad = 1, Defs = [CC] in 1503 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1504 1505// Test under mask. 1506let Defs = [CC] in { 1507 // TMxMux expands to TM[LH]x, depending on the choice of register. 1508 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1509 Requires<[FeatureHighWord]>; 1510 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1511 Requires<[FeatureHighWord]>; 1512 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1513 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1514 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1515 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1516 1517 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1518 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1519 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1520 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1521 1522 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1523} 1524 1525def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1526def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1527 1528// Compare logical characters under mask -- not (yet) used for codegen. 1529let Defs = [CC] in { 1530 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1531 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1532} 1533 1534//===----------------------------------------------------------------------===// 1535// Prefetch and execution hint 1536//===----------------------------------------------------------------------===// 1537 1538let mayLoad = 1, mayStore = 1 in { 1539 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1540 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1541} 1542 1543let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1544 // Branch Prediction Preload 1545 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1546 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1547 1548 // Next Instruction Access Intent 1549 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1550} 1551 1552//===----------------------------------------------------------------------===// 1553// Atomic operations 1554//===----------------------------------------------------------------------===// 1555 1556// A serialization instruction that acts as a barrier for all memory 1557// accesses, which expands to "bcr 14, 0". 1558let hasSideEffects = 1 in 1559def Serialize : Alias<2, (outs), (ins), []>; 1560 1561// A pseudo instruction that serves as a compiler barrier. 1562let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1563def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1564 1565let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1566 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1567 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1568 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1569 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1570 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1571 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1572 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1573 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1574 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1575 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1576} 1577 1578def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1579def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1580def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1581 1582def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1583def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1584let Predicates = [FeatureNoInterlockedAccess1] in { 1585 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1586 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1587 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1588 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1589 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1590 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1591} 1592 1593def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1594def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1595def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1596 1597def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1598def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1599let Predicates = [FeatureNoInterlockedAccess1] in { 1600 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1601 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1602 imm32ll16c>; 1603 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1604 imm32lh16c>; 1605 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1606 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1607 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1608 imm64ll16c>; 1609 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1610 imm64lh16c>; 1611 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1612 imm64hl16c>; 1613 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1614 imm64hh16c>; 1615 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1616 imm64lf32c>; 1617 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1618 imm64hf32c>; 1619} 1620 1621def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1622def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1623let Predicates = [FeatureNoInterlockedAccess1] in { 1624 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1625 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1626 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1627 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1628 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1629 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1630 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1631 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1632 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1633 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1634 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1635} 1636 1637def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1638def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1639let Predicates = [FeatureNoInterlockedAccess1] in { 1640 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1641 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1642 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1643 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1644 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1645} 1646 1647def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1648def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1649 imm32lh16c>; 1650def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1651def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1652 imm32ll16c>; 1653def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1654 imm32lh16c>; 1655def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1656def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1657def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1658 imm64ll16c>; 1659def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1660 imm64lh16c>; 1661def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1662 imm64hl16c>; 1663def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1664 imm64hh16c>; 1665def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1666 imm64lf32c>; 1667def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1668 imm64hf32c>; 1669 1670def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1671def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1672def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1673 1674def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1675def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1676def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1677 1678def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1679def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1680def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1681 1682def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1683def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1684def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1685 1686def ATOMIC_CMP_SWAPW 1687 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1688 ADDR32:$bitshift, ADDR32:$negbitshift, 1689 uimm32:$bitsize), 1690 [(set GR32:$dst, 1691 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1692 ADDR32:$bitshift, ADDR32:$negbitshift, 1693 uimm32:$bitsize))]> { 1694 let Defs = [CC]; 1695 let mayLoad = 1; 1696 let mayStore = 1; 1697 let usesCustomInserter = 1; 1698 let hasNoSchedulingInfo = 1; 1699} 1700 1701// Test and set. 1702let mayLoad = 1, Defs = [CC] in 1703 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1704 1705// Compare and swap. 1706let Defs = [CC] in { 1707 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1708 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1709} 1710 1711// Compare double and swap. 1712let Defs = [CC] in { 1713 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1714 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1715} 1716 1717// Compare and swap and store. 1718let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1719 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1720 1721// Perform locked operation. 1722let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1723 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1724 1725// Load/store pair from/to quadword. 1726def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1727def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1728 1729// Load pair disjoint. 1730let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1731 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1732 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1733} 1734 1735//===----------------------------------------------------------------------===// 1736// Translate and convert 1737//===----------------------------------------------------------------------===// 1738 1739let mayLoad = 1, mayStore = 1 in 1740 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1741 1742let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1743 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1744 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1745} 1746 1747let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1748 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1749 1750let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1751 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1752 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1753} 1754 1755let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1756 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1757 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1758 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1759 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1760} 1761 1762let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1763 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1764 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1765 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1766 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1767 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1768 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1769 1770 let isAsmParserOnly = 1 in { 1771 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1772 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1773 } 1774} 1775 1776//===----------------------------------------------------------------------===// 1777// Message-security assist 1778//===----------------------------------------------------------------------===// 1779 1780let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1781 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1782 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1783 1784 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1785 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1786 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1787 1788 let Predicates = [FeatureMessageSecurityAssist4] in { 1789 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1790 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1791 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1792 GR128, GR128, GR128>; 1793 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1794 } 1795 1796 let Predicates = [FeatureMessageSecurityAssist5] in 1797 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1798 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1799 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1800 1801 let Predicates = [FeatureMessageSecurityAssist8] in 1802 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1803 GR128, GR128, GR128>; 1804} 1805 1806//===----------------------------------------------------------------------===// 1807// Guarded storage 1808//===----------------------------------------------------------------------===// 1809 1810// These instructions use and/or modify the guarded storage control 1811// registers, which we do not otherwise model, so they should have 1812// hasSideEffects. 1813let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1814 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1815 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1816 1817 let mayLoad = 1 in 1818 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1819 let mayStore = 1 in 1820 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1821} 1822 1823//===----------------------------------------------------------------------===// 1824// Decimal arithmetic 1825//===----------------------------------------------------------------------===// 1826 1827defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1828def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1829 1830defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1831def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1832 1833let mayLoad = 1, mayStore = 1 in { 1834 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1835 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1836 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1837 1838 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1839 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1840 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1841 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1842 let Defs = [CC] in { 1843 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1844 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1845 } 1846} 1847 1848let mayLoad = 1, mayStore = 1 in { 1849 let Defs = [CC] in { 1850 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1851 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1852 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1853 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1854 } 1855 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1856 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1857 let Defs = [CC] in { 1858 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1859 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1860 } 1861} 1862 1863let Defs = [CC] in { 1864 def CP : CompareSSb<"cp", 0xF9>; 1865 def TP : TestRSL<"tp", 0xEBC0>; 1866} 1867 1868//===----------------------------------------------------------------------===// 1869// Access registers 1870//===----------------------------------------------------------------------===// 1871 1872// Read a 32-bit access register into a GR32. As with all GR32 operations, 1873// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1874// when a 64-bit address is stored in a pair of access registers. 1875def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1876 1877// Set access register. 1878def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1879 1880// Copy access register. 1881def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1882 1883// Load address extended. 1884defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1885 1886// Load access multiple. 1887defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1888 1889// Store access multiple. 1890defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1891 1892//===----------------------------------------------------------------------===// 1893// Program mask and addressing mode 1894//===----------------------------------------------------------------------===// 1895 1896// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1897let Uses = [CC] in 1898 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1899 1900// Set CC and program mask from a register. 1901let hasSideEffects = 1, Defs = [CC] in 1902 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1903 1904// Branch and link - like BAS, but also extracts CC and program mask. 1905let isCall = 1, Uses = [CC], Defs = [CC] in { 1906 def BAL : CallRX<"bal", 0x45>; 1907 def BALR : CallRR<"balr", 0x05>; 1908} 1909 1910// Test addressing mode. 1911let Defs = [CC] in 1912 def TAM : SideEffectInherentE<"tam", 0x010B>; 1913 1914// Set addressing mode. 1915let hasSideEffects = 1 in { 1916 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 1917 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 1918 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 1919} 1920 1921// Branch and set mode. Not really a call, but also sets an output register. 1922let isBranch = 1, isTerminator = 1, isBarrier = 1 in 1923 def BSM : CallRR<"bsm", 0x0B>; 1924 1925// Branch and save and set mode. 1926let isCall = 1, Defs = [CC] in 1927 def BASSM : CallRR<"bassm", 0x0C>; 1928 1929//===----------------------------------------------------------------------===// 1930// Transactional execution 1931//===----------------------------------------------------------------------===// 1932 1933let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 1934 // Transaction Begin 1935 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 1936 def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 1937 def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 1938 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 1939 int_s390_tbeginc, imm32zx16>; 1940 } 1941 1942 // Transaction End 1943 let Defs = [CC] in 1944 def TEND : SideEffectInherentS<"tend", 0xB2F8, z_tend>; 1945 1946 // Transaction Abort 1947 let isTerminator = 1, isBarrier = 1, mayStore = 1, 1948 hasSideEffects = 1 in 1949 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 1950 1951 // Nontransactional Store 1952 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1953 1954 // Extract Transaction Nesting Depth 1955 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 1956} 1957 1958//===----------------------------------------------------------------------===// 1959// Processor assist 1960//===----------------------------------------------------------------------===// 1961 1962let Predicates = [FeatureProcessorAssist] in { 1963 let hasSideEffects = 1 in 1964 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 1965 def : Pat<(int_s390_ppa_txassist GR32:$src), 1966 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1967 0, 1)>; 1968} 1969 1970//===----------------------------------------------------------------------===// 1971// Miscellaneous Instructions. 1972//===----------------------------------------------------------------------===// 1973 1974// Find leftmost one, AKA count leading zeros. The instruction actually 1975// returns a pair of GR64s, the first giving the number of leading zeros 1976// and the second giving a copy of the source with the leftmost one bit 1977// cleared. We only use the first result here. 1978let Defs = [CC] in 1979 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 1980def : Pat<(ctlz GR64:$src), 1981 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1982 1983// Population count. Counts bits set per byte. 1984let Predicates = [FeaturePopulationCount], Defs = [CC] in 1985 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 1986 1987// Search a block of memory for a character. 1988let mayLoad = 1, Defs = [CC] in 1989 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 1990let mayLoad = 1, Defs = [CC], Uses = [R0L] in 1991 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 1992 1993// Compare until substring equal. 1994let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 1995 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 1996 1997// Compare and form codeword. 1998let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 1999 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2000 2001// Update tree. 2002let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2003 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2004 def UPT : SideEffectInherentE<"upt", 0x0102>; 2005 2006// Checksum. 2007let mayLoad = 1, Defs = [CC] in 2008 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2009 2010// Compression call. 2011let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2012 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2013 2014// Execute. 2015let hasSideEffects = 1 in { 2016 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2017 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2018} 2019 2020//===----------------------------------------------------------------------===// 2021// .insn directive instructions 2022//===----------------------------------------------------------------------===// 2023 2024let isCodeGenOnly = 1, hasSideEffects = 1 in { 2025 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2026 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2027 imm32sx16:$I2), 2028 ".insn ri,$enc,$R1,$I2", []>; 2029 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2030 AnyReg:$R3, brtarget16:$I2), 2031 ".insn rie,$enc,$R1,$R3,$I2", []>; 2032 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2033 brtarget32:$I2), 2034 ".insn ril,$enc,$R1,$I2", []>; 2035 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2036 uimm32:$I2), 2037 ".insn rilu,$enc,$R1,$I2", []>; 2038 def InsnRIS : DirectiveInsnRIS<(outs), 2039 (ins imm64zx48:$enc, AnyReg:$R1, 2040 imm32sx8:$I2, imm32zx4:$M3, 2041 bdaddr12only:$BD4), 2042 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2043 def InsnRR : DirectiveInsnRR<(outs), 2044 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2045 ".insn rr,$enc,$R1,$R2", []>; 2046 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2047 AnyReg:$R1, AnyReg:$R2), 2048 ".insn rre,$enc,$R1,$R2", []>; 2049 def InsnRRF : DirectiveInsnRRF<(outs), 2050 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2051 AnyReg:$R3, imm32zx4:$M4), 2052 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2053 def InsnRRS : DirectiveInsnRRS<(outs), 2054 (ins imm64zx48:$enc, AnyReg:$R1, 2055 AnyReg:$R2, imm32zx4:$M3, 2056 bdaddr12only:$BD4), 2057 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2058 def InsnRS : DirectiveInsnRS<(outs), 2059 (ins imm64zx32:$enc, AnyReg:$R1, 2060 AnyReg:$R3, bdaddr12only:$BD2), 2061 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2062 def InsnRSE : DirectiveInsnRSE<(outs), 2063 (ins imm64zx48:$enc, AnyReg:$R1, 2064 AnyReg:$R3, bdaddr12only:$BD2), 2065 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2066 def InsnRSI : DirectiveInsnRSI<(outs), 2067 (ins imm64zx48:$enc, AnyReg:$R1, 2068 AnyReg:$R3, brtarget16:$RI2), 2069 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2070 def InsnRSY : DirectiveInsnRSY<(outs), 2071 (ins imm64zx48:$enc, AnyReg:$R1, 2072 AnyReg:$R3, bdaddr20only:$BD2), 2073 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2074 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2075 bdxaddr12only:$XBD2), 2076 ".insn rx,$enc,$R1,$XBD2", []>; 2077 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2078 bdxaddr12only:$XBD2), 2079 ".insn rxe,$enc,$R1,$XBD2", []>; 2080 def InsnRXF : DirectiveInsnRXF<(outs), 2081 (ins imm64zx48:$enc, AnyReg:$R1, 2082 AnyReg:$R3, bdxaddr12only:$XBD2), 2083 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2084 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2085 bdxaddr20only:$XBD2), 2086 ".insn rxy,$enc,$R1,$XBD2", []>; 2087 def InsnS : DirectiveInsnS<(outs), 2088 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2089 ".insn s,$enc,$BD2", []>; 2090 def InsnSI : DirectiveInsnSI<(outs), 2091 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2092 imm32sx8:$I2), 2093 ".insn si,$enc,$BD1,$I2", []>; 2094 def InsnSIY : DirectiveInsnSIY<(outs), 2095 (ins imm64zx48:$enc, 2096 bdaddr20only:$BD1, imm32zx8:$I2), 2097 ".insn siy,$enc,$BD1,$I2", []>; 2098 def InsnSIL : DirectiveInsnSIL<(outs), 2099 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2100 imm32zx16:$I2), 2101 ".insn sil,$enc,$BD1,$I2", []>; 2102 def InsnSS : DirectiveInsnSS<(outs), 2103 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2104 bdaddr12only:$BD2, AnyReg:$R3), 2105 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2106 def InsnSSE : DirectiveInsnSSE<(outs), 2107 (ins imm64zx48:$enc, 2108 bdaddr12only:$BD1,bdaddr12only:$BD2), 2109 ".insn sse,$enc,$BD1,$BD2", []>; 2110 def InsnSSF : DirectiveInsnSSF<(outs), 2111 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2112 bdaddr12only:$BD2, AnyReg:$R3), 2113 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2114} 2115 2116//===----------------------------------------------------------------------===// 2117// Peepholes. 2118//===----------------------------------------------------------------------===// 2119 2120// Use AL* for GR64 additions of unsigned 32-bit values. 2121defm : ZXB<add, GR64, ALGFR>; 2122def : Pat<(add GR64:$src1, imm64zx32:$src2), 2123 (ALGFI GR64:$src1, imm64zx32:$src2)>; 2124def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2125 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 2126 2127// Use SL* for GR64 subtractions of unsigned 32-bit values. 2128defm : ZXB<sub, GR64, SLGFR>; 2129def : Pat<(add GR64:$src1, imm64zx32n:$src2), 2130 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 2131def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 2132 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 2133 2134// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2135// equivalent to (and (xor x, -1), y) 2136def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2137 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2138 2139// Shift/rotate instructions only use the last 6 bits of the second operand 2140// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2141// last 16 bits. 2142// Complexity is added so that we match this before we match NILF on the AND 2143// operation alone. 2144let AddedComplexity = 4 in { 2145 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2146 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2147 2148 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 2149 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2150 2151 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2152 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2153 2154 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2155 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2156 2157 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 2158 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2159 2160 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2161 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2162 2163 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2164 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2165 2166 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2167 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2168} 2169 2170// Peepholes for turning scalar operations into block operations. 2171defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2172 XCSequence, 1>; 2173defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2174 XCSequence, 2>; 2175defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2176 XCSequence, 4>; 2177defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2178 OCSequence, XCSequence, 1>; 2179defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2180 XCSequence, 2>; 2181defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2182 XCSequence, 4>; 2183defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2184 XCSequence, 8>; 2185