1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 15 [(callseq_start timm:$amt)]>; 16def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_end timm:$amt1, timm:$amt2)]>; 18 19let neverHasSideEffects = 1 in { 20 // Takes as input the value of the stack pointer after a dynamic allocation 21 // has been made. Sets the output to the address of the dynamically- 22 // allocated area itself, skipping the outgoing arguments. 23 // 24 // This expands to an LA or LAY instruction. We restrict the offset 25 // to the range of LA and keep the LAY range in reserve for when 26 // the size of the outgoing arguments is added. 27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 28 [(set GR64:$dst, dynalloc12only:$src)]>; 29} 30 31//===----------------------------------------------------------------------===// 32// Control flow instructions 33//===----------------------------------------------------------------------===// 34 35// A return instruction. R1 is the condition-code mask (all 1s) 36// and R2 is the target address, which is always stored in %r14. 37let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1, 38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in { 39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>; 40} 41 42// Unconditional branches. R1 is the condition-code mask (all 1s). 43let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in { 44 let isIndirectBranch = 1 in 45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), 46 "br\t$R2", [(brind ADDR64:$R2)]>; 47 48 // An assembler extended mnemonic for BRC. 49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", 50 [(br bb:$I2)]>; 51 52 // An assembler extended mnemonic for BRCL. (The extension is "G" 53 // rather than "L" because "JL" is "Jump if Less".) 54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>; 55} 56 57// Conditional branches. It's easier for LLVM to handle these branches 58// in their raw BRC/BRCL form, with the 4-bit condition-code mask being 59// the first operand. It seems friendlier to use mnemonic forms like 60// JE and JLH when writing out the assembly though. 61// 62// Using a custom inserter for BRC gives us a chance to convert the BRC 63// and a preceding compare into a single compare-and-branch instruction. 64// The inserter makes no change in cases where a separate branch really 65// is needed. 66multiclass CondBranches<Operand ccmask, string short, string long> { 67 let isBranch = 1, isTerminator = 1, Uses = [CC] in { 68 def "" : InstRI<0xA74, (outs), (ins ccmask:$R1, brtarget16:$I2), short, []>; 69 def L : InstRIL<0xC04, (outs), (ins ccmask:$R1, brtarget32:$I2), long, []>; 70 } 71} 72let isCodeGenOnly = 1, usesCustomInserter = 1 in 73 defm BRC : CondBranches<cond4, "j$R1\t$I2", "jg$R1\t$I2">; 74defm AsmBRC : CondBranches<uimm8zx4, "brc\t$R1, $I2", "brcl\t$R1, $I2">; 75 76def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRC cond4:$cond, bb:$dst)>; 77 78// Fused compare-and-branch instructions. As for normal branches, 79// we handle these instructions internally in their raw CRJ-like form, 80// but use assembly macros like CRJE when writing them out. 81// 82// These instructions do not use or clobber the condition codes. 83// We nevertheless pretend that they clobber CC, so that we can lower 84// them to separate comparisons and BRCLs if the branch ends up being 85// out of range. 86multiclass CompareBranches<Operand ccmask, string pos1, string pos2> { 87 let isBranch = 1, isTerminator = 1, Defs = [CC] in { 88 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3, 89 brtarget16:$RI4), 90 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 91 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3, 92 brtarget16:$RI4), 93 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>; 94 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3, 95 brtarget16:$RI4), 96 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 97 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3, 98 brtarget16:$RI4), 99 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>; 100 } 101} 102let isCodeGenOnly = 1 in 103 defm C : CompareBranches<cond4, "$M3", "">; 104defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">; 105 106// Define AsmParser mnemonics for each general condition-code mask 107// (integer or floating-point) 108multiclass CondExtendedMnemonic<bits<4> ccmask, string name> { 109 let R1 = ccmask in { 110 def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2), 111 "j"##name##"\t$I2", []>; 112 def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2), 113 "jg"##name##"\t$I2", []>; 114 } 115} 116defm AsmJO : CondExtendedMnemonic<1, "o">; 117defm AsmJH : CondExtendedMnemonic<2, "h">; 118defm AsmJNLE : CondExtendedMnemonic<3, "nle">; 119defm AsmJL : CondExtendedMnemonic<4, "l">; 120defm AsmJNHE : CondExtendedMnemonic<5, "nhe">; 121defm AsmJLH : CondExtendedMnemonic<6, "lh">; 122defm AsmJNE : CondExtendedMnemonic<7, "ne">; 123defm AsmJE : CondExtendedMnemonic<8, "e">; 124defm AsmJNLH : CondExtendedMnemonic<9, "nlh">; 125defm AsmJHE : CondExtendedMnemonic<10, "he">; 126defm AsmJNL : CondExtendedMnemonic<11, "nl">; 127defm AsmJLE : CondExtendedMnemonic<12, "le">; 128defm AsmJNH : CondExtendedMnemonic<13, "nh">; 129defm AsmJNO : CondExtendedMnemonic<14, "no">; 130 131// Define AsmParser mnemonics for each integer condition-code mask. 132// This is like the list above, except that condition 3 is not possible 133// and that the low bit of the mask is therefore always 0. This means 134// that each condition has two names. Conditions "o" and "no" are not used. 135// 136// We don't make one of the two names an alias of the other because 137// we need the custom parsing routines to select the correct register class. 138multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> { 139 let M3 = ccmask in { 140 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, 141 brtarget16:$RI4), 142 "crj"##name##"\t$R1, $R2, $RI4", []>; 143 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, 144 brtarget16:$RI4), 145 "cgrj"##name##"\t$R1, $R2, $RI4", []>; 146 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, 147 brtarget16:$RI4), 148 "cij"##name##"\t$R1, $I2, $RI4", []>; 149 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, 150 brtarget16:$RI4), 151 "cgij"##name##"\t$R1, $I2, $RI4", []>; 152 } 153} 154multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2> 155 : IntCondExtendedMnemonicA<ccmask, name1> { 156 let isAsmParserOnly = 1 in 157 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>; 158} 159defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">; 160defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">; 161defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">; 162defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">; 163defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">; 164defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">; 165 166def Select32 : SelectWrapper<GR32>; 167def Select64 : SelectWrapper<GR64>; 168 169//===----------------------------------------------------------------------===// 170// Call instructions 171//===----------------------------------------------------------------------===// 172 173// The definitions here are for the call-clobbered registers. 174let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D, 175 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D], 176 R1 = 14, isCodeGenOnly = 1 in { 177 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops), 178 "bras\t%r14, $I2", []>; 179 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops), 180 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>; 181 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops), 182 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>; 183} 184 185// Define the general form of the call instructions for the asm parser. 186// These instructions don't hard-code %r14 as the return address register. 187def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2), 188 "bras\t$R1, $I2", []>; 189def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2), 190 "brasl\t$R1, $I2", []>; 191def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2), 192 "basr\t$R1, $R2", []>; 193 194//===----------------------------------------------------------------------===// 195// Move instructions 196//===----------------------------------------------------------------------===// 197 198// Register moves. 199let neverHasSideEffects = 1 in { 200 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 201 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 202} 203 204// Immediate moves. 205let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 206 // 16-bit sign-extended immediates. 207 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 208 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 209 210 // Other 16-bit immediates. 211 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 212 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 213 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 214 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 215 216 // 32-bit immediates. 217 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 218 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 219 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 220} 221 222// Register loads. 223let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 224 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>; 225 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 226 227 def LG : UnaryRXY<"lg", 0xE304, load, GR64>; 228 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 229 230 // These instructions are split after register allocation, so we don't 231 // want a custom inserter. 232 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 233 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 234 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 235 } 236} 237 238// Register stores. 239let SimpleBDXStore = 1 in { 240 let isCodeGenOnly = 1 in { 241 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>; 242 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 243 } 244 245 def STG : StoreRXY<"stg", 0xE324, store, GR64>; 246 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 247 248 // These instructions are split after register allocation, so we don't 249 // want a custom inserter. 250 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 251 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 252 [(store GR128:$src, bdxaddr20only128:$dst)]>; 253 } 254} 255 256// 8-bit immediate stores to 8-bit fields. 257defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 258 259// 16-bit immediate stores to 16-, 32- or 64-bit fields. 260def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 261def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 262def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 263 264//===----------------------------------------------------------------------===// 265// Sign extensions 266//===----------------------------------------------------------------------===// 267 268// 32-bit extensions from registers. 269let neverHasSideEffects = 1 in { 270 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 271 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 272} 273 274// 64-bit extensions from registers. 275let neverHasSideEffects = 1 in { 276 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 277 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 278 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 279} 280 281// Match 32-to-64-bit sign extensions in which the source is already 282// in a 64-bit register. 283def : Pat<(sext_inreg GR64:$src, i32), 284 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 285 286// 32-bit extensions from memory. 287def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32>; 288defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32>; 289def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>; 290 291// 64-bit extensions from memory. 292def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64>; 293def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64>; 294def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64>; 295def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>; 296def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>; 297 298// If the sign of a load-extend operation doesn't matter, use the signed ones. 299// There's not really much to choose between the sign and zero extensions, 300// but LH is more compact than LLH for small offsets. 301def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>; 302def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>; 303def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>; 304 305def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>; 306def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>; 307def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>; 308 309//===----------------------------------------------------------------------===// 310// Zero extensions 311//===----------------------------------------------------------------------===// 312 313// 32-bit extensions from registers. 314let neverHasSideEffects = 1 in { 315 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 316 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 317} 318 319// 64-bit extensions from registers. 320let neverHasSideEffects = 1 in { 321 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 322 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 323 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 324} 325 326// Match 32-to-64-bit zero extensions in which the source is already 327// in a 64-bit register. 328def : Pat<(and GR64:$src, 0xffffffff), 329 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>; 330 331// 32-bit extensions from memory. 332def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32>; 333def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32>; 334def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>; 335 336// 64-bit extensions from memory. 337def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64>; 338def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64>; 339def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64>; 340def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>; 341def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>; 342 343//===----------------------------------------------------------------------===// 344// Truncations 345//===----------------------------------------------------------------------===// 346 347// Truncations of 64-bit registers to 32-bit registers. 348def : Pat<(i32 (trunc GR64:$src)), 349 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>; 350 351// Truncations of 32-bit registers to memory. 352let isCodeGenOnly = 1 in { 353 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32>; 354 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32>; 355 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 356} 357 358// Truncations of 64-bit registers to memory. 359defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64>; 360defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64>; 361def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>; 362defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64>; 363def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>; 364 365//===----------------------------------------------------------------------===// 366// Multi-register moves 367//===----------------------------------------------------------------------===// 368 369// Multi-register loads. 370def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 371 372// Multi-register stores. 373def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 374 375//===----------------------------------------------------------------------===// 376// Byte swaps 377//===----------------------------------------------------------------------===// 378 379// Byte-swapping register moves. 380let neverHasSideEffects = 1 in { 381 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 382 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 383} 384 385// Byte-swapping loads. Unlike normal loads, these instructions are 386// allowed to access storage more than once. 387def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32>; 388def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64>; 389 390// Likewise byte-swapping stores. 391def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32>; 392def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>, GR64>; 393 394//===----------------------------------------------------------------------===// 395// Load address instructions 396//===----------------------------------------------------------------------===// 397 398// Load BDX-style addresses. 399let neverHasSideEffects = 1, Function = "la" in { 400 let PairType = "12" in 401 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2), 402 "la\t$R1, $XBD2", 403 [(set GR64:$R1, laaddr12pair:$XBD2)]>; 404 let PairType = "20" in 405 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2), 406 "lay\t$R1, $XBD2", 407 [(set GR64:$R1, laaddr20pair:$XBD2)]>; 408} 409 410// Load a PC-relative address. There's no version of this instruction 411// with a 16-bit offset, so there's no relaxation. 412let neverHasSideEffects = 1 in { 413 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2), 414 "larl\t$R1, $I2", 415 [(set GR64:$R1, pcrel32:$I2)]>; 416} 417 418//===----------------------------------------------------------------------===// 419// Negation 420//===----------------------------------------------------------------------===// 421 422let Defs = [CC] in { 423 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 424 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 425 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 426} 427defm : SXU<ineg, LCGFR>; 428 429//===----------------------------------------------------------------------===// 430// Insertion 431//===----------------------------------------------------------------------===// 432 433let isCodeGenOnly = 1 in 434 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8>; 435defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8>; 436 437defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>; 438defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>; 439 440defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>; 441defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>; 442 443// Insertions of a 16-bit immediate, leaving other bits unaffected. 444// We don't have or_as_insert equivalents of these operations because 445// OI is available instead. 446let isCodeGenOnly = 1 in { 447 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 448 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 449} 450def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>; 451def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>; 452def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>; 453def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>; 454 455// ...likewise for 32-bit immediates. For GR32s this is a general 456// full-width move. (We use IILF rather than something like LLILF 457// for 32-bit moves because IILF leaves the upper 32 bits of the 458// GR64 unchanged.) 459let isCodeGenOnly = 1 in { 460 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 461} 462def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>; 463def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>; 464 465// An alternative model of inserthf, with the first operand being 466// a zero-extended value. 467def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 468 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit), 469 imm64hf32:$imm)>; 470 471//===----------------------------------------------------------------------===// 472// Addition 473//===----------------------------------------------------------------------===// 474 475// Plain addition. 476let Defs = [CC] in { 477 // Addition of a register. 478 let isCommutable = 1 in { 479 def AR : BinaryRR <"ar", 0x1A, add, GR32, GR32>; 480 def AGR : BinaryRRE<"agr", 0xB908, add, GR64, GR64>; 481 } 482 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 483 484 // Addition of signed 16-bit immediates. 485 def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>; 486 def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>; 487 488 // Addition of signed 32-bit immediates. 489 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 490 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 491 492 // Addition of memory. 493 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16>; 494 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load>; 495 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32>; 496 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load>; 497 498 // Addition to memory. 499 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 500 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 501} 502defm : SXB<add, GR64, AGFR>; 503 504// Addition producing a carry. 505let Defs = [CC] in { 506 // Addition of a register. 507 let isCommutable = 1 in { 508 def ALR : BinaryRR <"alr", 0x1E, addc, GR32, GR32>; 509 def ALGR : BinaryRRE<"algr", 0xB90A, addc, GR64, GR64>; 510 } 511 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 512 513 // Addition of unsigned 32-bit immediates. 514 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 515 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 516 517 // Addition of memory. 518 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load>; 519 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32>; 520 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load>; 521} 522defm : ZXB<addc, GR64, ALGFR>; 523 524// Addition producing and using a carry. 525let Defs = [CC], Uses = [CC] in { 526 // Addition of a register. 527 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>; 528 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>; 529 530 // Addition of memory. 531 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load>; 532 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load>; 533} 534 535//===----------------------------------------------------------------------===// 536// Subtraction 537//===----------------------------------------------------------------------===// 538 539// Plain substraction. Although immediate forms exist, we use the 540// add-immediate instruction instead. 541let Defs = [CC] in { 542 // Subtraction of a register. 543 def SR : BinaryRR <"sr", 0x1B, sub, GR32, GR32>; 544 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 545 def SGR : BinaryRRE<"sgr", 0xB909, sub, GR64, GR64>; 546 547 // Subtraction of memory. 548 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16>; 549 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load>; 550 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32>; 551 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load>; 552} 553defm : SXB<sub, GR64, SGFR>; 554 555// Subtraction producing a carry. 556let Defs = [CC] in { 557 // Subtraction of a register. 558 def SLR : BinaryRR <"slr", 0x1F, subc, GR32, GR32>; 559 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 560 def SLGR : BinaryRRE<"slgr", 0xB90B, subc, GR64, GR64>; 561 562 // Subtraction of unsigned 32-bit immediates. These don't match 563 // subc because we prefer addc for constants. 564 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 565 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 566 567 // Subtraction of memory. 568 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load>; 569 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32>; 570 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load>; 571} 572defm : ZXB<subc, GR64, SLGFR>; 573 574// Subtraction producing and using a carry. 575let Defs = [CC], Uses = [CC] in { 576 // Subtraction of a register. 577 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>; 578 def SLGBR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>; 579 580 // Subtraction of memory. 581 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load>; 582 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load>; 583} 584 585//===----------------------------------------------------------------------===// 586// AND 587//===----------------------------------------------------------------------===// 588 589let Defs = [CC] in { 590 // ANDs of a register. 591 let isCommutable = 1 in { 592 def NR : BinaryRR <"nr", 0x14, and, GR32, GR32>; 593 def NGR : BinaryRRE<"ngr", 0xB980, and, GR64, GR64>; 594 } 595 596 // ANDs of a 16-bit immediate, leaving other bits unaffected. 597 let isCodeGenOnly = 1 in { 598 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 599 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 600 } 601 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>; 602 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>; 603 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>; 604 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>; 605 606 // ANDs of a 32-bit immediate, leaving other bits unaffected. 607 let isCodeGenOnly = 1 in 608 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 609 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>; 610 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>; 611 612 // ANDs of memory. 613 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load>; 614 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load>; 615 616 // AND to memory 617 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>; 618} 619defm : RMWIByte<and, bdaddr12pair, NI>; 620defm : RMWIByte<and, bdaddr20pair, NIY>; 621 622//===----------------------------------------------------------------------===// 623// OR 624//===----------------------------------------------------------------------===// 625 626let Defs = [CC] in { 627 // ORs of a register. 628 let isCommutable = 1 in { 629 def OR : BinaryRR <"or", 0x16, or, GR32, GR32>; 630 def OGR : BinaryRRE<"ogr", 0xB981, or, GR64, GR64>; 631 } 632 633 // ORs of a 16-bit immediate, leaving other bits unaffected. 634 let isCodeGenOnly = 1 in { 635 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 636 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 637 } 638 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>; 639 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>; 640 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>; 641 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>; 642 643 // ORs of a 32-bit immediate, leaving other bits unaffected. 644 let isCodeGenOnly = 1 in 645 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 646 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>; 647 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>; 648 649 // ORs of memory. 650 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load>; 651 def OG : BinaryRXY<"og", 0xE381, or, GR64, load>; 652 653 // OR to memory 654 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>; 655} 656defm : RMWIByte<or, bdaddr12pair, OI>; 657defm : RMWIByte<or, bdaddr20pair, OIY>; 658 659//===----------------------------------------------------------------------===// 660// XOR 661//===----------------------------------------------------------------------===// 662 663let Defs = [CC] in { 664 // XORs of a register. 665 let isCommutable = 1 in { 666 def XR : BinaryRR <"xr", 0x17, xor, GR32, GR32>; 667 def XGR : BinaryRRE<"xgr", 0xB982, xor, GR64, GR64>; 668 } 669 670 // XORs of a 32-bit immediate, leaving other bits unaffected. 671 let isCodeGenOnly = 1 in 672 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 673 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>; 674 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>; 675 676 // XORs of memory. 677 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load>; 678 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load>; 679 680 // XOR to memory 681 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>; 682} 683defm : RMWIByte<xor, bdaddr12pair, XI>; 684defm : RMWIByte<xor, bdaddr20pair, XIY>; 685 686//===----------------------------------------------------------------------===// 687// Multiplication 688//===----------------------------------------------------------------------===// 689 690// Multiplication of a register. 691let isCommutable = 1 in { 692 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 693 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 694} 695def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 696defm : SXB<mul, GR64, MSGFR>; 697 698// Multiplication of a signed 16-bit immediate. 699def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 700def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 701 702// Multiplication of a signed 32-bit immediate. 703def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 704def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 705 706// Multiplication of memory. 707defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16>; 708defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load>; 709def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32>; 710def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load>; 711 712// Multiplication of a register, producing two results. 713def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>; 714 715// Multiplication of memory, producing two results. 716def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load>; 717 718//===----------------------------------------------------------------------===// 719// Division and remainder 720//===----------------------------------------------------------------------===// 721 722// Division and remainder, from registers. 723def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 724def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>; 725def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>; 726def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>; 727defm : SXB<z_sdivrem64, GR128, DSGFR>; 728 729// Division and remainder, from memory. 730def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem64, GR128, sextloadi32>; 731def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load>; 732def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load>; 733def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load>; 734 735//===----------------------------------------------------------------------===// 736// Shifts 737//===----------------------------------------------------------------------===// 738 739// Shift left. 740let neverHasSideEffects = 1 in { 741 def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>; 742 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>; 743} 744 745// Logical shift right. 746let neverHasSideEffects = 1 in { 747 def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>; 748 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>; 749} 750 751// Arithmetic shift right. 752let Defs = [CC] in { 753 def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>; 754 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>; 755} 756 757// Rotate left. 758let neverHasSideEffects = 1 in { 759 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>; 760 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>; 761} 762 763// Rotate second operand left and inserted selected bits into first operand. 764// These can act like 32-bit operands provided that the constant start and 765// end bits (operands 2 and 3) are in the range [32, 64) 766let Defs = [CC] in { 767 let isCodeGenOnly = 1 in 768 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 769 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 770} 771 772//===----------------------------------------------------------------------===// 773// Comparison 774//===----------------------------------------------------------------------===// 775 776// Signed comparisons. 777let Defs = [CC] in { 778 // Comparison with a register. 779 def CR : CompareRR <"cr", 0x19, z_cmp, GR32, GR32>; 780 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 781 def CGR : CompareRRE<"cgr", 0xB920, z_cmp, GR64, GR64>; 782 783 // Comparison with a signed 16-bit immediate. 784 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>; 785 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>; 786 787 // Comparison with a signed 32-bit immediate. 788 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>; 789 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>; 790 791 // Comparison with memory. 792 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16>; 793 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load>; 794 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16>; 795 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32>; 796 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load>; 797 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>; 798 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>; 799 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>; 800 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>; 801 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>; 802 803 // Comparison between memory and a signed 16-bit immediate. 804 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>; 805 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>; 806 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>; 807} 808defm : SXB<z_cmp, GR64, CGFR>; 809 810// Unsigned comparisons. 811let Defs = [CC] in { 812 // Comparison with a register. 813 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 814 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 815 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 816 817 // Comparison with a signed 32-bit immediate. 818 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 819 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 820 821 // Comparison with memory. 822 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load>; 823 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32>; 824 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load>; 825 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 826 aligned_zextloadi16>; 827 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 828 aligned_load>; 829 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 830 aligned_zextloadi16>; 831 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 832 aligned_zextloadi32>; 833 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 834 aligned_load>; 835 836 // Comparison between memory and an unsigned 8-bit immediate. 837 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>; 838 839 // Comparison between memory and an unsigned 16-bit immediate. 840 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>; 841 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 842 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 843} 844defm : ZXB<z_ucmp, GR64, CLGFR>; 845 846//===----------------------------------------------------------------------===// 847// Atomic operations 848//===----------------------------------------------------------------------===// 849 850def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 851def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 852def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 853 854def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 855def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 856def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 857def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 858def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 859def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 860def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 861def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 862 863def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 864def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 865def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 866 867def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 868def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 869def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 870def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>; 871def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>; 872def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 873def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 874def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>; 875def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>; 876def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>; 877def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>; 878def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>; 879def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>; 880 881def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 882def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 883def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 884def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 885def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 886def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 887def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 888def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 889def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 890def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 891def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 892def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 893def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 894 895def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 896def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 897def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 898def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 899def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 900def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 901def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 902 903def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 904def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 905 imm32lh16c>; 906def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 907def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 908 imm32ll16c>; 909def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32, 910 imm32lh16c>; 911def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 912def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 913def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 914 imm64ll16c>; 915def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 916 imm64lh16c>; 917def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64, 918 imm64hl16c>; 919def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64, 920 imm64hh16c>; 921def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 922 imm64lf32c>; 923def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64, 924 imm64hf32c>; 925 926def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 927def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 928def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 929 930def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 931def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 932def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 933 934def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 935def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 936def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 937 938def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 939def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 940def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 941 942def ATOMIC_CMP_SWAPW 943 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 944 ADDR32:$bitshift, ADDR32:$negbitshift, 945 uimm32:$bitsize), 946 [(set GR32:$dst, 947 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 948 ADDR32:$bitshift, ADDR32:$negbitshift, 949 uimm32:$bitsize))]> { 950 let Defs = [CC]; 951 let mayLoad = 1; 952 let mayStore = 1; 953 let usesCustomInserter = 1; 954} 955 956let Defs = [CC] in { 957 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 958 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 959} 960 961//===----------------------------------------------------------------------===// 962// Miscellaneous Instructions. 963//===----------------------------------------------------------------------===// 964 965// Read a 32-bit access register into a GR32. As with all GR32 operations, 966// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 967// when a 64-bit address is stored in a pair of access registers. 968def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2), 969 "ear\t$R1, $R2", 970 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>; 971 972// Find leftmost one, AKA count leading zeros. The instruction actually 973// returns a pair of GR64s, the first giving the number of leading zeros 974// and the second giving a copy of the source with the leftmost one bit 975// cleared. We only use the first result here. 976let Defs = [CC] in { 977 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 978} 979def : Pat<(ctlz GR64:$src), 980 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>; 981 982// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 983def : Pat<(i64 (anyext GR32:$src)), 984 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>; 985 986// There are no 32-bit equivalents of LLILL and LLILH, so use a full 987// 64-bit move followed by a subreg. This preserves the invariant that 988// all GR32 operations only modify the low 32 bits. 989def : Pat<(i32 imm32ll16:$src), 990 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>; 991def : Pat<(i32 imm32lh16:$src), 992 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>; 993 994// Extend GR32s and GR64s to GR128s. 995let usesCustomInserter = 1 in { 996 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 997 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 998 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 999} 1000 1001//===----------------------------------------------------------------------===// 1002// Peepholes. 1003//===----------------------------------------------------------------------===// 1004 1005// Use AL* for GR64 additions of unsigned 32-bit values. 1006defm : ZXB<add, GR64, ALGFR>; 1007def : Pat<(add GR64:$src1, imm64zx32:$src2), 1008 (ALGFI GR64:$src1, imm64zx32:$src2)>; 1009def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 1010 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 1011 1012// Use SL* for GR64 subtractions of unsigned 32-bit values. 1013defm : ZXB<sub, GR64, SLGFR>; 1014def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1015 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1016def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)), 1017 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 1018