1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14// The callseq_start node requires the hasSideEffects flag, even though these 15// instructions are noops on SystemZ. 16let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 17 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_start timm:$amt1, timm:$amt2)]>; 19 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_end timm:$amt1, timm:$amt2)]>; 21} 22 23// Takes as input the value of the stack pointer after a dynamic allocation 24// has been made. Sets the output to the address of the dynamically- 25// allocated area itself, skipping the outgoing arguments. 26// 27// This expands to an LA or LAY instruction. We restrict the offset 28// to the range of LA and keep the LAY range in reserve for when 29// the size of the outgoing arguments is added. 30def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 31 [(set GR64:$dst, dynalloc12only:$src)]>; 32 33 34//===----------------------------------------------------------------------===// 35// Branch instructions 36//===----------------------------------------------------------------------===// 37 38// Conditional branches. 39let isBranch = 1, isTerminator = 1, Uses = [CC] in { 40 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 41 // with the condition-code mask being the first operand. It seems friendlier 42 // to use mnemonic forms like JE and JLH when writing out the assembly though. 43 let isCodeGenOnly = 1 in { 44 // An assembler extended mnemonic for BRC. 45 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 46 // An assembler extended mnemonic for BRCL. (The extension is "G" 47 // rather than "L" because "JL" is "Jump if Less".) 48 def BRCL : CondBranchRIL<"jg#", 0xC04>; 49 let isIndirectBranch = 1 in { 50 def BC : CondBranchRX<"b#", 0x47>; 51 def BCR : CondBranchRR<"b#r", 0x07>; 52 def BIC : CondBranchRXY<"bi#", 0xe347>, 53 Requires<[FeatureMiscellaneousExtensions2]>; 54 } 55 } 56 57 // Allow using the raw forms directly from the assembler (and occasional 58 // special code generation needs) as well. 59 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 60 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 61 let isIndirectBranch = 1 in { 62 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 63 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 64 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 65 Requires<[FeatureMiscellaneousExtensions2]>; 66 } 67 68 // Define AsmParser extended mnemonics for each general condition-code mask 69 // (integer or floating-point) 70 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 71 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 72 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 73 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 74 let isIndirectBranch = 1 in { 75 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 76 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 77 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 78 Requires<[FeatureMiscellaneousExtensions2]>; 79 } 80 } 81} 82 83// Unconditional branches. These are in fact simply variants of the 84// conditional branches with the condition mask set to "always". 85let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 86 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 87 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 88 let isIndirectBranch = 1 in { 89 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 90 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 91 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 92 Requires<[FeatureMiscellaneousExtensions2]>; 93 } 94} 95 96// NOPs. These are again variants of the conditional branches, 97// with the condition mask set to "never". 98def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 99def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 100 101// Fused compare-and-branch instructions. 102// 103// These instructions do not use or clobber the condition codes. 104// We nevertheless pretend that the relative compare-and-branch 105// instructions clobber CC, so that we can lower them to separate 106// comparisons and BRCLs if the branch ends up being out of range. 107let isBranch = 1, isTerminator = 1 in { 108 // As for normal branches, we handle these instructions internally in 109 // their raw CRJ-like form, but use assembly macros like CRJE when writing 110 // them out. Using the *Pair multiclasses, we also create the raw forms. 111 let Defs = [CC] in { 112 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 113 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 114 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 115 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 116 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 117 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 118 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 119 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 120 } 121 let isIndirectBranch = 1 in { 122 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 123 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 124 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 125 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 126 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 127 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 128 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 129 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 130 } 131 132 // Define AsmParser mnemonics for each integer condition-code mask. 133 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 134 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 135 let Defs = [CC] in { 136 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 137 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 138 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 139 imm32sx8>; 140 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 141 imm64sx8>; 142 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 143 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 144 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 145 imm32zx8>; 146 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 147 imm64zx8>; 148 } 149 let isIndirectBranch = 1 in { 150 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 151 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 152 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 153 imm32sx8>; 154 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 155 imm64sx8>; 156 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 157 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 158 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 159 imm32zx8>; 160 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 161 imm64zx8>; 162 } 163 } 164} 165 166// Decrement a register and branch if it is nonzero. These don't clobber CC, 167// but we might need to split long relative branches into sequences that do. 168let isBranch = 1, isTerminator = 1 in { 169 let Defs = [CC] in { 170 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 171 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 172 } 173 // This doesn't need to clobber CC since we never need to split it. 174 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 175 Requires<[FeatureHighWord]>; 176 177 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 178 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 179 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 180 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 181} 182 183let isBranch = 1, isTerminator = 1 in { 184 let Defs = [CC] in { 185 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 186 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 187 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 188 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 189 } 190 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 191 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 192 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 193 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 194} 195 196//===----------------------------------------------------------------------===// 197// Trap instructions 198//===----------------------------------------------------------------------===// 199 200// Unconditional trap. 201let hasCtrlDep = 1, hasSideEffects = 1 in 202 def Trap : Alias<4, (outs), (ins), [(trap)]>; 203 204// Conditional trap. 205let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 206 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 207 208// Fused compare-and-trap instructions. 209let hasCtrlDep = 1, hasSideEffects = 1 in { 210 // These patterns work the same way as for compare-and-branch. 211 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 212 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 213 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 214 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 215 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 216 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 217 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 218 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 219 let Predicates = [FeatureMiscellaneousExtensions] in { 220 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 221 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 222 } 223 224 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 225 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 226 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 227 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 228 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 229 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 230 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 231 imm32sx16>; 232 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 233 imm64sx16>; 234 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 235 imm32zx16>; 236 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 237 imm64zx16>; 238 let Predicates = [FeatureMiscellaneousExtensions] in { 239 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 240 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 241 } 242 } 243} 244 245//===----------------------------------------------------------------------===// 246// Call and return instructions 247//===----------------------------------------------------------------------===// 248 249// Define the general form of the call instructions for the asm parser. 250// These instructions don't hard-code %r14 as the return address register. 251let isCall = 1, Defs = [CC] in { 252 def BRAS : CallRI <"bras", 0xA75>; 253 def BRASL : CallRIL<"brasl", 0xC05>; 254 def BAS : CallRX <"bas", 0x4D>; 255 def BASR : CallRR <"basr", 0x0D>; 256} 257 258// Regular calls. 259let isCall = 1, Defs = [R14D, CC] in { 260 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 261 [(z_call pcrel32:$I2)]>; 262 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 263 [(z_call ADDR64:$R2)]>; 264} 265 266// TLS calls. These will be lowered into a call to __tls_get_offset, 267// with an extra relocation specifying the TLS symbol. 268let isCall = 1, Defs = [R14D, CC] in { 269 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 270 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 271 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 272 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 273} 274 275// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 276// are argument registers and since branching to R0 is a no-op. 277let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 278 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 279 [(z_sibcall pcrel32:$I2)]>; 280 let Uses = [R1D] in 281 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 282} 283 284// Conditional sibling calls. 285let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 286 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 287 pcrel32:$I2), []>; 288 let Uses = [R1D] in 289 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 290} 291 292// Fused compare and conditional sibling calls. 293let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 294 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 295 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 296 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 297 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 298 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 299 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 300 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 301 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 302} 303 304// A return instruction (br %r14). 305let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 306 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 307 308// A conditional return instruction (bcr <cond>, %r14). 309let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 310 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 311 312// Fused compare and conditional returns. 313let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 314 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 315 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 316 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 317 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 318 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 319 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 320 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 321 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 322} 323 324//===----------------------------------------------------------------------===// 325// Select instructions 326//===----------------------------------------------------------------------===// 327 328def Select32 : SelectWrapper<i32, GR32>, 329 Requires<[FeatureNoLoadStoreOnCond]>; 330def Select64 : SelectWrapper<i64, GR64>, 331 Requires<[FeatureNoLoadStoreOnCond]>; 332 333// We don't define 32-bit Mux stores if we don't have STOCFH, because the 334// low-only STOC should then always be used if possible. 335defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 336 nonvolatile_anyextloadi8, bdxaddr20only>, 337 Requires<[FeatureHighWord]>; 338defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 339 nonvolatile_anyextloadi16, bdxaddr20only>, 340 Requires<[FeatureHighWord]>; 341defm CondStore32Mux : CondStores<GRX32, nonvolatile_store, 342 nonvolatile_load, bdxaddr20only>, 343 Requires<[FeatureLoadStoreOnCond2]>; 344defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 345 nonvolatile_anyextloadi8, bdxaddr20only>; 346defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 347 nonvolatile_anyextloadi16, bdxaddr20only>; 348defm CondStore32 : CondStores<GR32, nonvolatile_store, 349 nonvolatile_load, bdxaddr20only>; 350 351defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 352 nonvolatile_anyextloadi8, bdxaddr20only>; 353defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 354 nonvolatile_anyextloadi16, bdxaddr20only>; 355defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 356 nonvolatile_anyextloadi32, bdxaddr20only>; 357defm CondStore64 : CondStores<GR64, nonvolatile_store, 358 nonvolatile_load, bdxaddr20only>; 359 360//===----------------------------------------------------------------------===// 361// Move instructions 362//===----------------------------------------------------------------------===// 363 364// Register moves. 365// Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 366def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>, 367 Requires<[FeatureHighWord]>; 368def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 369def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 370 371let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 372 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 373 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 374} 375 376let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 377 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 378 379// Immediate moves. 380let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 381 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 382 // deopending on the choice of register. 383 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 384 Requires<[FeatureHighWord]>; 385 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 386 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 387 388 // Other 16-bit immediates. 389 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 390 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 391 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 392 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 393 394 // 32-bit immediates. 395 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 396 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 397 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 398} 399 400// Register loads. 401let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 402 // Expands to L, LY or LFH, depending on the choice of register. 403 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 404 Requires<[FeatureHighWord]>; 405 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 406 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 407 Requires<[FeatureHighWord]>; 408 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 409 410 // These instructions are split after register allocation, so we don't 411 // want a custom inserter. 412 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 413 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 414 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 415 } 416} 417let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 418 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 419 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 420} 421 422let canFoldAsLoad = 1 in { 423 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 424 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 425} 426 427// Load and zero rightmost byte. 428let Predicates = [FeatureLoadAndZeroRightmostByte] in { 429 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 430 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 431 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 432 (LZRF bdxaddr20only:$src)>; 433 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 434 (LZRG bdxaddr20only:$src)>; 435} 436 437// Load and trap. 438let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 439 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 440 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 441 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 442} 443 444// Register stores. 445let SimpleBDXStore = 1, mayStore = 1 in { 446 // Expands to ST, STY or STFH, depending on the choice of register. 447 def STMux : StoreRXYPseudo<store, GRX32, 4>, 448 Requires<[FeatureHighWord]>; 449 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 450 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 451 Requires<[FeatureHighWord]>; 452 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 453 454 // These instructions are split after register allocation, so we don't 455 // want a custom inserter. 456 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 457 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 458 [(store GR128:$src, bdxaddr20only128:$dst)]>; 459 } 460} 461def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 462def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 463 464// 8-bit immediate stores to 8-bit fields. 465defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 466 467// 16-bit immediate stores to 16-, 32- or 64-bit fields. 468def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 469def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 470def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 471 472// Memory-to-memory moves. 473let mayLoad = 1, mayStore = 1 in 474 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 475let mayLoad = 1, mayStore = 1, Defs = [CC] in { 476 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 477 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 478 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 479} 480 481// String moves. 482let mayLoad = 1, mayStore = 1, Defs = [CC] in 483 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 484 485//===----------------------------------------------------------------------===// 486// Conditional move instructions 487//===----------------------------------------------------------------------===// 488 489let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 490 // Load immediate on condition. Matched via DAG pattern and created 491 // by the PeepholeOptimizer via FoldImmediate. 492 493 // Expands to LOCHI or LOCHHI, depending on the choice of register. 494 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 495 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 496 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 497 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 498 499 // Move register on condition. Matched via DAG pattern and 500 // created by early if-conversion. 501 let isCommutable = 1 in { 502 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 503 // depending on the choice of registers. 504 def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>; 505 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 506 } 507 508 // Load on condition. Matched via DAG pattern. 509 // Expands to LOC or LOCFH, depending on the choice of register. 510 def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>; 511 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>; 512 513 // Store on condition. Expanded from CondStore* pseudos. 514 // Expands to STOC or STOCFH, depending on the choice of register. 515 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 516 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 517 518 // Define AsmParser extended mnemonics for each general condition-code mask. 519 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 520 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 521 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 522 imm32sx16>; 523 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 524 imm64sx16>; 525 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 526 imm32sx16>; 527 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 528 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 529 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 530 } 531} 532 533let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 534 // Move register on condition. Matched via DAG pattern and 535 // created by early if-conversion. 536 let isCommutable = 1 in { 537 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 538 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 539 } 540 541 // Load on condition. Matched via DAG pattern. 542 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 543 defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 544 545 // Store on condition. Expanded from CondStore* pseudos. 546 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 547 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 548 549 // Define AsmParser extended mnemonics for each general condition-code mask. 550 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 551 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 552 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 553 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 554 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 555 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 556 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 557 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 558 } 559} 560//===----------------------------------------------------------------------===// 561// Sign extensions 562//===----------------------------------------------------------------------===// 563// 564// Note that putting these before zero extensions mean that we will prefer 565// them for anyextload*. There's not really much to choose between the two 566// either way, but signed-extending loads have a short LH and a long LHY, 567// while zero-extending loads have only the long LLH. 568// 569//===----------------------------------------------------------------------===// 570 571// 32-bit extensions from registers. 572def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 573def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 574 575// 64-bit extensions from registers. 576def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 577def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 578def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 579 580let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 581 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 582 583// Match 32-to-64-bit sign extensions in which the source is already 584// in a 64-bit register. 585def : Pat<(sext_inreg GR64:$src, i32), 586 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 587 588// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 589// depending on the choice of register. 590def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 591 Requires<[FeatureHighWord]>; 592def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 593def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 594 Requires<[FeatureHighWord]>; 595 596// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 597// depending on the choice of register. 598def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 599 Requires<[FeatureHighWord]>; 600defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 601def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 602 Requires<[FeatureHighWord]>; 603def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 604 605// 64-bit extensions from memory. 606def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 607def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 608def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 609def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 610def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 611let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 612 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 613 614//===----------------------------------------------------------------------===// 615// Zero extensions 616//===----------------------------------------------------------------------===// 617 618// 32-bit extensions from registers. 619 620// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 621def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 622 Requires<[FeatureHighWord]>; 623def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 624// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 625def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 626 Requires<[FeatureHighWord]>; 627def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 628 629// 64-bit extensions from registers. 630def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 631def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 632def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 633 634// Match 32-to-64-bit zero extensions in which the source is already 635// in a 64-bit register. 636def : Pat<(and GR64:$src, 0xffffffff), 637 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 638 639// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 640// depending on the choice of register. 641def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 642 Requires<[FeatureHighWord]>; 643def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 644def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 645 Requires<[FeatureHighWord]>; 646 647// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 648// depending on the choice of register. 649def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 650 Requires<[FeatureHighWord]>; 651def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 652def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 653 Requires<[FeatureHighWord]>; 654def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 655 656// 64-bit extensions from memory. 657def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 658def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 659def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 660def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 661def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 662 663// 31-to-64-bit zero extensions. 664def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 665def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 666def : Pat<(and GR64:$src, 0x7fffffff), 667 (LLGTR GR64:$src)>; 668def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 669 (LLGT bdxaddr20only:$src)>; 670 671// Load and zero rightmost byte. 672let Predicates = [FeatureLoadAndZeroRightmostByte] in { 673 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 674 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 675 (LLZRGF bdxaddr20only:$src)>; 676} 677 678// Load and trap. 679let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 680 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 681 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 682} 683 684// Extend GR64s to GR128s. 685let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 686 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 687 688//===----------------------------------------------------------------------===// 689// "Any" extensions 690//===----------------------------------------------------------------------===// 691 692// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 693def : Pat<(i64 (anyext GR32:$src)), 694 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 695 696// Extend GR64s to GR128s. 697let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 698 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 699 700//===----------------------------------------------------------------------===// 701// Truncations 702//===----------------------------------------------------------------------===// 703 704// Truncations of 64-bit registers to 32-bit registers. 705def : Pat<(i32 (trunc GR64:$src)), 706 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 707 708// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 709// STC, STCY or STCH, depending on the choice of register. 710def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 711 Requires<[FeatureHighWord]>; 712defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 713def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 714 Requires<[FeatureHighWord]>; 715 716// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 717// STH, STHY or STHH, depending on the choice of register. 718def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 719 Requires<[FeatureHighWord]>; 720defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 721def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 722 Requires<[FeatureHighWord]>; 723def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 724 725// Truncations of 64-bit registers to memory. 726defm : StoreGR64Pair<STC, STCY, truncstorei8>; 727defm : StoreGR64Pair<STH, STHY, truncstorei16>; 728def : StoreGR64PC<STHRL, aligned_truncstorei16>; 729defm : StoreGR64Pair<ST, STY, truncstorei32>; 730def : StoreGR64PC<STRL, aligned_truncstorei32>; 731 732// Store characters under mask -- not (yet) used for codegen. 733defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 734def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 735 736//===----------------------------------------------------------------------===// 737// Multi-register moves 738//===----------------------------------------------------------------------===// 739 740// Multi-register loads. 741defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 742def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 743def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 744def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 745 746// Multi-register stores. 747defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 748def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 749def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 750 751//===----------------------------------------------------------------------===// 752// Byte swaps 753//===----------------------------------------------------------------------===// 754 755// Byte-swapping register moves. 756def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 757def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 758 759// Byte-swapping loads. Unlike normal loads, these instructions are 760// allowed to access storage more than once. 761def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 762def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 763def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 764 765// Likewise byte-swapping stores. 766def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 767def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 768def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 769 770// Byte-swapping memory-to-memory moves. 771let mayLoad = 1, mayStore = 1 in 772 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 773 774//===----------------------------------------------------------------------===// 775// Load address instructions 776//===----------------------------------------------------------------------===// 777 778// Load BDX-style addresses. 779let isAsCheapAsAMove = 1, isReMaterializable = 1 in 780 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 781 782// Load a PC-relative address. There's no version of this instruction 783// with a 16-bit offset, so there's no relaxation. 784let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 785 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 786 787// Load the Global Offset Table address. This will be lowered into a 788// larl $R1, _GLOBAL_OFFSET_TABLE_ 789// instruction. 790def GOT : Alias<6, (outs GR64:$R1), (ins), 791 [(set GR64:$R1, (global_offset_table))]>; 792 793//===----------------------------------------------------------------------===// 794// Absolute and Negation 795//===----------------------------------------------------------------------===// 796 797let Defs = [CC] in { 798 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 799 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 800 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 801 } 802 let CCValues = 0xE, CompareZeroCCMask = 0xE in 803 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 804} 805def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 806def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 807defm : SXU<z_iabs, LPGFR>; 808defm : SXU<z_iabs64, LPGFR>; 809 810let Defs = [CC] in { 811 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 812 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 813 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 814 } 815 let CCValues = 0xE, CompareZeroCCMask = 0xE in 816 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 817} 818def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 819def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 820defm : SXU<z_inegabs, LNGFR>; 821defm : SXU<z_inegabs64, LNGFR>; 822 823let Defs = [CC] in { 824 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 825 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 826 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 827 } 828 let CCValues = 0xE, CompareZeroCCMask = 0xE in 829 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 830} 831defm : SXU<ineg, LCGFR>; 832 833//===----------------------------------------------------------------------===// 834// Insertion 835//===----------------------------------------------------------------------===// 836 837let isCodeGenOnly = 1 in 838 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 839defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 840 841defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 842defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 843 844defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 845defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 846 847// Insert characters under mask -- not (yet) used for codegen. 848let Defs = [CC] in { 849 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 850 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 851} 852 853// Insertions of a 16-bit immediate, leaving other bits unaffected. 854// We don't have or_as_insert equivalents of these operations because 855// OI is available instead. 856// 857// IIxMux expands to II[LH]x, depending on the choice of register. 858def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 859 Requires<[FeatureHighWord]>; 860def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 861 Requires<[FeatureHighWord]>; 862def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 863def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 864def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 865def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 866def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 867def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 868def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 869def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 870 871// ...likewise for 32-bit immediates. For GR32s this is a general 872// full-width move. (We use IILF rather than something like LLILF 873// for 32-bit moves because IILF leaves the upper 32 bits of the 874// GR64 unchanged.) 875let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 876 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 877 Requires<[FeatureHighWord]>; 878 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 879 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 880} 881def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 882def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 883 884// An alternative model of inserthf, with the first operand being 885// a zero-extended value. 886def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 887 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 888 imm64hf32:$imm)>; 889 890//===----------------------------------------------------------------------===// 891// Addition 892//===----------------------------------------------------------------------===// 893 894// Addition producing a signed overflow flag. 895let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 896 // Addition of a register. 897 let isCommutable = 1 in { 898 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 899 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 900 } 901 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 902 903 // Addition to a high register. 904 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 905 Requires<[FeatureHighWord]>; 906 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 907 Requires<[FeatureHighWord]>; 908 909 // Addition of signed 16-bit immediates. 910 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 911 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 912 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 913 914 // Addition of signed 32-bit immediates. 915 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 916 Requires<[FeatureHighWord]>; 917 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 918 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 919 Requires<[FeatureHighWord]>; 920 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 921 922 // Addition of memory. 923 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 924 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 925 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 926 Requires<[FeatureMiscellaneousExtensions2]>; 927 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 928 def AG : BinaryRXY<"ag", 0xE308, z_sadd, GR64, load, 8>; 929 930 // Addition to memory. 931 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 932 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 933} 934defm : SXB<z_sadd, GR64, AGFR>; 935 936// Addition producing a carry. 937let Defs = [CC] in { 938 // Addition of a register. 939 let isCommutable = 1 in { 940 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 941 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 942 } 943 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 944 945 // Addition to a high register. 946 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 947 Requires<[FeatureHighWord]>; 948 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 949 Requires<[FeatureHighWord]>; 950 951 // Addition of signed 16-bit immediates. 952 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 953 Requires<[FeatureDistinctOps]>; 954 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 955 Requires<[FeatureDistinctOps]>; 956 957 // Addition of unsigned 32-bit immediates. 958 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 959 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 960 961 // Addition of signed 32-bit immediates. 962 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 963 Requires<[FeatureHighWord]>; 964 965 // Addition of memory. 966 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 967 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 968 def ALG : BinaryRXY<"alg", 0xE30A, z_uadd, GR64, load, 8>; 969 970 // Addition to memory. 971 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 972 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 973} 974defm : ZXB<z_uadd, GR64, ALGFR>; 975 976// Addition producing and using a carry. 977let Defs = [CC], Uses = [CC] in { 978 // Addition of a register. 979 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 980 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 981 982 // Addition of memory. 983 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 984 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 985} 986 987// Addition that does not modify the condition code. 988def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 989 Requires<[FeatureHighWord]>; 990 991 992//===----------------------------------------------------------------------===// 993// Subtraction 994//===----------------------------------------------------------------------===// 995 996// Subtraction producing a signed overflow flag. 997let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 998 // Subtraction of a register. 999 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1000 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1001 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1002 1003 // Subtraction from a high register. 1004 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1005 Requires<[FeatureHighWord]>; 1006 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1007 Requires<[FeatureHighWord]>; 1008 1009 // Subtraction of memory. 1010 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1011 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1012 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1013 Requires<[FeatureMiscellaneousExtensions2]>; 1014 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1015 def SG : BinaryRXY<"sg", 0xE309, z_ssub, GR64, load, 8>; 1016} 1017defm : SXB<z_ssub, GR64, SGFR>; 1018 1019// Subtracting an immediate is the same as adding the negated immediate. 1020let AddedComplexity = 1 in { 1021 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1022 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1023 Requires<[FeatureHighWord]>; 1024 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1025 (AFIMux GR32:$src1, simm32n:$src2)>, 1026 Requires<[FeatureHighWord]>; 1027 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1028 (AHI GR32:$src1, imm32sx16n:$src2)>; 1029 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1030 (AFI GR32:$src1, simm32n:$src2)>; 1031 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1032 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1033 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1034 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1035} 1036 1037// Subtraction producing a carry. 1038let Defs = [CC] in { 1039 // Subtraction of a register. 1040 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1041 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1042 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1043 1044 // Subtraction from a high register. 1045 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1046 Requires<[FeatureHighWord]>; 1047 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1048 Requires<[FeatureHighWord]>; 1049 1050 // Subtraction of unsigned 32-bit immediates. 1051 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1052 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1053 1054 // Subtraction of memory. 1055 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1056 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1057 def SLG : BinaryRXY<"slg", 0xE30B, z_usub, GR64, load, 8>; 1058} 1059defm : ZXB<z_usub, GR64, SLGFR>; 1060 1061// Subtracting an immediate is the same as adding the negated immediate. 1062let AddedComplexity = 1 in { 1063 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1064 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1065 Requires<[FeatureDistinctOps]>; 1066 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1067 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1068 Requires<[FeatureDistinctOps]>; 1069} 1070 1071// And vice versa in one special case (but we prefer addition). 1072def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1073 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1074 1075// Subtraction producing and using a carry. 1076let Defs = [CC], Uses = [CC] in { 1077 // Subtraction of a register. 1078 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1079 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1080 1081 // Subtraction of memory. 1082 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1083 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1084} 1085 1086 1087//===----------------------------------------------------------------------===// 1088// AND 1089//===----------------------------------------------------------------------===// 1090 1091let Defs = [CC] in { 1092 // ANDs of a register. 1093 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1094 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1095 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1096 } 1097 1098 let isConvertibleToThreeAddress = 1 in { 1099 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1100 // The CC result only reflects the 16-bit field, not the full register. 1101 // 1102 // NIxMux expands to NI[LH]x, depending on the choice of register. 1103 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1104 Requires<[FeatureHighWord]>; 1105 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1106 Requires<[FeatureHighWord]>; 1107 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1108 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1109 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1110 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1111 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1112 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1113 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1114 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1115 1116 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1117 // The CC result only reflects the 32-bit field, which means we can 1118 // use it as a zero indicator for i32 operations but not otherwise. 1119 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1120 // Expands to NILF or NIHF, depending on the choice of register. 1121 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1122 Requires<[FeatureHighWord]>; 1123 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1124 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1125 } 1126 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1127 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1128 } 1129 1130 // ANDs of memory. 1131 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1132 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1133 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1134 } 1135 1136 // AND to memory 1137 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1138 1139 // Block AND. 1140 let mayLoad = 1, mayStore = 1 in 1141 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1142} 1143defm : RMWIByte<and, bdaddr12pair, NI>; 1144defm : RMWIByte<and, bdaddr20pair, NIY>; 1145 1146//===----------------------------------------------------------------------===// 1147// OR 1148//===----------------------------------------------------------------------===// 1149 1150let Defs = [CC] in { 1151 // ORs of a register. 1152 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1153 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1154 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1155 } 1156 1157 // ORs of a 16-bit immediate, leaving other bits unaffected. 1158 // The CC result only reflects the 16-bit field, not the full register. 1159 // 1160 // OIxMux expands to OI[LH]x, depending on the choice of register. 1161 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1162 Requires<[FeatureHighWord]>; 1163 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1164 Requires<[FeatureHighWord]>; 1165 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1166 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1167 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1168 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1169 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1170 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1171 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1172 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1173 1174 // ORs of a 32-bit immediate, leaving other bits unaffected. 1175 // The CC result only reflects the 32-bit field, which means we can 1176 // use it as a zero indicator for i32 operations but not otherwise. 1177 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1178 // Expands to OILF or OIHF, depending on the choice of register. 1179 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1180 Requires<[FeatureHighWord]>; 1181 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1182 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1183 } 1184 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1185 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1186 1187 // ORs of memory. 1188 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1189 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1190 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1191 } 1192 1193 // OR to memory 1194 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1195 1196 // Block OR. 1197 let mayLoad = 1, mayStore = 1 in 1198 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1199} 1200defm : RMWIByte<or, bdaddr12pair, OI>; 1201defm : RMWIByte<or, bdaddr20pair, OIY>; 1202 1203//===----------------------------------------------------------------------===// 1204// XOR 1205//===----------------------------------------------------------------------===// 1206 1207let Defs = [CC] in { 1208 // XORs of a register. 1209 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1210 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1211 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1212 } 1213 1214 // XORs of a 32-bit immediate, leaving other bits unaffected. 1215 // The CC result only reflects the 32-bit field, which means we can 1216 // use it as a zero indicator for i32 operations but not otherwise. 1217 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1218 // Expands to XILF or XIHF, depending on the choice of register. 1219 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1220 Requires<[FeatureHighWord]>; 1221 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1222 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1223 } 1224 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1225 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1226 1227 // XORs of memory. 1228 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1229 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1230 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1231 } 1232 1233 // XOR to memory 1234 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1235 1236 // Block XOR. 1237 let mayLoad = 1, mayStore = 1 in 1238 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1239} 1240defm : RMWIByte<xor, bdaddr12pair, XI>; 1241defm : RMWIByte<xor, bdaddr20pair, XIY>; 1242 1243//===----------------------------------------------------------------------===// 1244// Multiplication 1245//===----------------------------------------------------------------------===// 1246 1247// Multiplication of a register, setting the condition code. We prefer these 1248// over MS(G)R if available, even though we cannot use the condition code, 1249// since they are three-operand instructions. 1250let Predicates = [FeatureMiscellaneousExtensions2], 1251 Defs = [CC], isCommutable = 1 in { 1252 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1253 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1254} 1255 1256// Multiplication of a register. 1257let isCommutable = 1 in { 1258 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1259 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1260} 1261def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1262defm : SXB<mul, GR64, MSGFR>; 1263 1264// Multiplication of a signed 16-bit immediate. 1265def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1266def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1267 1268// Multiplication of a signed 32-bit immediate. 1269def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1270def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1271 1272// Multiplication of memory. 1273defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1274defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1275def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1276 Requires<[FeatureMiscellaneousExtensions2]>; 1277def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1278def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1279 1280// Multiplication of memory, setting the condition code. 1281let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1282 def MSC : BinaryRXY<"msc", 0xE353, null_frag, GR32, load, 4>; 1283 def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>; 1284} 1285 1286// Multiplication of a register, producing two results. 1287def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1288def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1289 Requires<[FeatureMiscellaneousExtensions2]>; 1290def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1291def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1292 1293def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1294 (MGRK GR64:$src1, GR64:$src2)>; 1295def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1296 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1297 1298// Multiplication of memory, producing two results. 1299def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1300def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1301def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1302 Requires<[FeatureMiscellaneousExtensions2]>; 1303def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1304def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1305 1306def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1307 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1308def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1309 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1310 1311//===----------------------------------------------------------------------===// 1312// Division and remainder 1313//===----------------------------------------------------------------------===// 1314 1315let hasSideEffects = 1 in { // Do not speculatively execute. 1316 // Division and remainder, from registers. 1317 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1318 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1319 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1320 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1321 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1322 1323 // Division and remainder, from memory. 1324 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1325 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1326 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1327 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1328 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1329} 1330def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1331 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1332def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1333 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1334def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1335 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1336def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1337 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1338 1339def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1340 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1341 subreg_l32)), GR32:$src2)>; 1342def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1343 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1344 subreg_l32)), bdxaddr20only:$src2)>; 1345def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1346 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1347def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1348 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1349 1350//===----------------------------------------------------------------------===// 1351// Shifts 1352//===----------------------------------------------------------------------===// 1353 1354// Logical shift left. 1355defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1356def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1357def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1358 1359// Arithmetic shift left. 1360let Defs = [CC] in { 1361 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1362 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1363 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1364} 1365 1366// Logical shift right. 1367defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1368def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1369def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1370 1371// Arithmetic shift right. 1372let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1373 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1374 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1375 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1376} 1377 1378// Rotate left. 1379def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1380def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1381 1382// Rotate second operand left and inserted selected bits into first operand. 1383// These can act like 32-bit operands provided that the constant start and 1384// end bits (operands 2 and 3) are in the range [32, 64). 1385let Defs = [CC] in { 1386 let isCodeGenOnly = 1 in 1387 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1388 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1389 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1390} 1391 1392// On zEC12 we have a variant of RISBG that does not set CC. 1393let Predicates = [FeatureMiscellaneousExtensions] in 1394 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1395 1396// Forms of RISBG that only affect one word of the destination register. 1397// They do not set CC. 1398let Predicates = [FeatureHighWord] in { 1399 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1400 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1401 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1402 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1403 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1404 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1405 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1406} 1407 1408// Rotate second operand left and perform a logical operation with selected 1409// bits of the first operand. The CC result only describes the selected bits, 1410// so isn't useful for a full comparison against zero. 1411let Defs = [CC] in { 1412 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1413 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1414 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1415} 1416 1417//===----------------------------------------------------------------------===// 1418// Comparison 1419//===----------------------------------------------------------------------===// 1420 1421// Signed comparisons. We put these before the unsigned comparisons because 1422// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1423// of the unsigned forms do. 1424let Defs = [CC], CCValues = 0xE in { 1425 // Comparison with a register. 1426 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1427 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1428 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1429 1430 // Comparison with a high register. 1431 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1432 Requires<[FeatureHighWord]>; 1433 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1434 Requires<[FeatureHighWord]>; 1435 1436 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1437 // depending on the choice of register. 1438 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1439 Requires<[FeatureHighWord]>; 1440 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1441 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1442 1443 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1444 // depending on the choice of register. 1445 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1446 Requires<[FeatureHighWord]>; 1447 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1448 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1449 Requires<[FeatureHighWord]>; 1450 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1451 1452 // Comparison with memory. 1453 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1454 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1455 Requires<[FeatureHighWord]>; 1456 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1457 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1458 Requires<[FeatureHighWord]>; 1459 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1460 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1461 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1462 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1463 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1464 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1465 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1466 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1467 1468 // Comparison between memory and a signed 16-bit immediate. 1469 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1470 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1471 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1472} 1473defm : SXB<z_scmp, GR64, CGFR>; 1474 1475// Unsigned comparisons. 1476let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1477 // Comparison with a register. 1478 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1479 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1480 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1481 1482 // Comparison with a high register. 1483 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1484 Requires<[FeatureHighWord]>; 1485 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1486 Requires<[FeatureHighWord]>; 1487 1488 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1489 // or CLIH, depending on the choice of register. 1490 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1491 Requires<[FeatureHighWord]>; 1492 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1493 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1494 Requires<[FeatureHighWord]>; 1495 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1496 1497 // Comparison with memory. 1498 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1499 Requires<[FeatureHighWord]>; 1500 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1501 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1502 Requires<[FeatureHighWord]>; 1503 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1504 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1505 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1506 aligned_azextloadi16>; 1507 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1508 aligned_load>; 1509 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1510 aligned_azextloadi16>; 1511 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1512 aligned_azextloadi32>; 1513 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1514 aligned_load>; 1515 1516 // Comparison between memory and an unsigned 8-bit immediate. 1517 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1518 1519 // Comparison between memory and an unsigned 16-bit immediate. 1520 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1521 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1522 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1523} 1524defm : ZXB<z_ucmp, GR64, CLGFR>; 1525 1526// Memory-to-memory comparison. 1527let mayLoad = 1, Defs = [CC] in { 1528 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1529 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1530 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1531 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1532} 1533 1534// String comparison. 1535let mayLoad = 1, Defs = [CC] in 1536 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1537 1538// Test under mask. 1539let Defs = [CC] in { 1540 // TMxMux expands to TM[LH]x, depending on the choice of register. 1541 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1542 Requires<[FeatureHighWord]>; 1543 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1544 Requires<[FeatureHighWord]>; 1545 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1546 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1547 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1548 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1549 1550 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1551 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1552 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1553 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1554 1555 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1556} 1557 1558def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1559def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1560 1561// Compare logical characters under mask -- not (yet) used for codegen. 1562let Defs = [CC] in { 1563 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1564 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1565} 1566 1567//===----------------------------------------------------------------------===// 1568// Prefetch and execution hint 1569//===----------------------------------------------------------------------===// 1570 1571let mayLoad = 1, mayStore = 1 in { 1572 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1573 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1574} 1575 1576let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1577 // Branch Prediction Preload 1578 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1579 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1580 1581 // Next Instruction Access Intent 1582 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1583} 1584 1585//===----------------------------------------------------------------------===// 1586// Atomic operations 1587//===----------------------------------------------------------------------===// 1588 1589// A serialization instruction that acts as a barrier for all memory 1590// accesses, which expands to "bcr 14, 0". 1591let hasSideEffects = 1 in 1592def Serialize : Alias<2, (outs), (ins), []>; 1593 1594// A pseudo instruction that serves as a compiler barrier. 1595let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1596def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1597 1598let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1599 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1600 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1601 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1602 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1603 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1604 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1605 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1606 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1607 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1608 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1609} 1610 1611def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1612def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1613def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1614 1615def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1616def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1617let Predicates = [FeatureNoInterlockedAccess1] in { 1618 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1619 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1620 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1621 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1622 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1623 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1624} 1625 1626def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1627def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1628def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1629 1630def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1631def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1632let Predicates = [FeatureNoInterlockedAccess1] in { 1633 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1634 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1635 imm32ll16c>; 1636 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1637 imm32lh16c>; 1638 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1639 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1640 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1641 imm64ll16c>; 1642 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1643 imm64lh16c>; 1644 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1645 imm64hl16c>; 1646 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1647 imm64hh16c>; 1648 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1649 imm64lf32c>; 1650 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1651 imm64hf32c>; 1652} 1653 1654def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1655def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1656let Predicates = [FeatureNoInterlockedAccess1] in { 1657 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1658 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1659 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1660 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1661 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1662 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1663 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1664 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1665 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1666 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1667 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1668} 1669 1670def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1671def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1672let Predicates = [FeatureNoInterlockedAccess1] in { 1673 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1674 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1675 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1676 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1677 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1678} 1679 1680def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1681def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1682 imm32lh16c>; 1683def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1684def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1685 imm32ll16c>; 1686def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1687 imm32lh16c>; 1688def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1689def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1690def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1691 imm64ll16c>; 1692def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1693 imm64lh16c>; 1694def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1695 imm64hl16c>; 1696def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1697 imm64hh16c>; 1698def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1699 imm64lf32c>; 1700def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1701 imm64hf32c>; 1702 1703def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1704def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1705def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1706 1707def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1708def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1709def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1710 1711def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1712def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1713def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1714 1715def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1716def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1717def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1718 1719def ATOMIC_CMP_SWAPW 1720 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1721 ADDR32:$bitshift, ADDR32:$negbitshift, 1722 uimm32:$bitsize), 1723 [(set GR32:$dst, 1724 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1725 ADDR32:$bitshift, ADDR32:$negbitshift, 1726 uimm32:$bitsize))]> { 1727 let Defs = [CC]; 1728 let mayLoad = 1; 1729 let mayStore = 1; 1730 let usesCustomInserter = 1; 1731 let hasNoSchedulingInfo = 1; 1732} 1733 1734// Test and set. 1735let mayLoad = 1, Defs = [CC] in 1736 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1737 1738// Compare and swap. 1739let Defs = [CC] in { 1740 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1741 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1742} 1743 1744// Compare double and swap. 1745let Defs = [CC] in { 1746 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1747 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1748} 1749 1750// Compare and swap and store. 1751let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1752 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1753 1754// Perform locked operation. 1755let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1756 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1757 1758// Load/store pair from/to quadword. 1759def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1760def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1761 1762// Load pair disjoint. 1763let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1764 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1765 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1766} 1767 1768//===----------------------------------------------------------------------===// 1769// Translate and convert 1770//===----------------------------------------------------------------------===// 1771 1772let mayLoad = 1, mayStore = 1 in 1773 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1774 1775let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1776 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1777 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1778} 1779 1780let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1781 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1782 1783let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1784 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1785 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1786} 1787 1788let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1789 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1790 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1791 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1792 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1793} 1794 1795let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1796 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1797 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1798 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1799 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1800 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1801 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1802 1803 let isAsmParserOnly = 1 in { 1804 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1805 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1806 } 1807} 1808 1809//===----------------------------------------------------------------------===// 1810// Message-security assist 1811//===----------------------------------------------------------------------===// 1812 1813let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1814 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1815 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1816 1817 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1818 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1819 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1820 1821 let Predicates = [FeatureMessageSecurityAssist4] in { 1822 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1823 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1824 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1825 GR128, GR128, GR128>; 1826 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1827 } 1828 1829 let Predicates = [FeatureMessageSecurityAssist5] in 1830 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1831 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1832 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1833 1834 let Predicates = [FeatureMessageSecurityAssist8] in 1835 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1836 GR128, GR128, GR128>; 1837} 1838 1839//===----------------------------------------------------------------------===// 1840// Guarded storage 1841//===----------------------------------------------------------------------===// 1842 1843// These instructions use and/or modify the guarded storage control 1844// registers, which we do not otherwise model, so they should have 1845// hasSideEffects. 1846let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1847 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1848 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1849 1850 let mayLoad = 1 in 1851 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1852 let mayStore = 1 in 1853 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1854} 1855 1856//===----------------------------------------------------------------------===// 1857// Decimal arithmetic 1858//===----------------------------------------------------------------------===// 1859 1860defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1861def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1862 1863defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1864def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1865 1866let mayLoad = 1, mayStore = 1 in { 1867 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1868 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1869 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1870 1871 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1872 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1873 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1874 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1875 let Defs = [CC] in { 1876 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1877 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1878 } 1879} 1880 1881let mayLoad = 1, mayStore = 1 in { 1882 let Defs = [CC] in { 1883 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1884 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1885 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1886 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1887 } 1888 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1889 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1890 let Defs = [CC] in { 1891 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1892 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1893 } 1894} 1895 1896let Defs = [CC] in { 1897 def CP : CompareSSb<"cp", 0xF9>; 1898 def TP : TestRSL<"tp", 0xEBC0>; 1899} 1900 1901//===----------------------------------------------------------------------===// 1902// Access registers 1903//===----------------------------------------------------------------------===// 1904 1905// Read a 32-bit access register into a GR32. As with all GR32 operations, 1906// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1907// when a 64-bit address is stored in a pair of access registers. 1908def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1909 1910// Set access register. 1911def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1912 1913// Copy access register. 1914def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1915 1916// Load address extended. 1917defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1918 1919// Load access multiple. 1920defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1921 1922// Store access multiple. 1923defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1924 1925//===----------------------------------------------------------------------===// 1926// Program mask and addressing mode 1927//===----------------------------------------------------------------------===// 1928 1929// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1930let Uses = [CC] in 1931 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1932 1933// Set CC and program mask from a register. 1934let hasSideEffects = 1, Defs = [CC] in 1935 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1936 1937// Branch and link - like BAS, but also extracts CC and program mask. 1938let isCall = 1, Uses = [CC], Defs = [CC] in { 1939 def BAL : CallRX<"bal", 0x45>; 1940 def BALR : CallRR<"balr", 0x05>; 1941} 1942 1943// Test addressing mode. 1944let Defs = [CC] in 1945 def TAM : SideEffectInherentE<"tam", 0x010B>; 1946 1947// Set addressing mode. 1948let hasSideEffects = 1 in { 1949 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 1950 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 1951 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 1952} 1953 1954// Branch and set mode. Not really a call, but also sets an output register. 1955let isBranch = 1, isTerminator = 1, isBarrier = 1 in 1956 def BSM : CallRR<"bsm", 0x0B>; 1957 1958// Branch and save and set mode. 1959let isCall = 1, Defs = [CC] in 1960 def BASSM : CallRR<"bassm", 0x0C>; 1961 1962//===----------------------------------------------------------------------===// 1963// Transactional execution 1964//===----------------------------------------------------------------------===// 1965 1966let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 1967 // Transaction Begin 1968 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 1969 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 1970 let hasNoSchedulingInfo = 1 in 1971 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 1972 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 1973 int_s390_tbeginc, imm32zx16>; 1974 } 1975 1976 // Transaction End 1977 let Defs = [CC] in 1978 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 1979 1980 // Transaction Abort 1981 let isTerminator = 1, isBarrier = 1, mayStore = 1, 1982 hasSideEffects = 1 in 1983 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 1984 1985 // Nontransactional Store 1986 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1987 1988 // Extract Transaction Nesting Depth 1989 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 1990} 1991 1992//===----------------------------------------------------------------------===// 1993// Processor assist 1994//===----------------------------------------------------------------------===// 1995 1996let Predicates = [FeatureProcessorAssist] in { 1997 let hasSideEffects = 1 in 1998 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 1999 def : Pat<(int_s390_ppa_txassist GR32:$src), 2000 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2001 0, 1)>; 2002} 2003 2004//===----------------------------------------------------------------------===// 2005// Miscellaneous Instructions. 2006//===----------------------------------------------------------------------===// 2007 2008// Find leftmost one, AKA count leading zeros. The instruction actually 2009// returns a pair of GR64s, the first giving the number of leading zeros 2010// and the second giving a copy of the source with the leftmost one bit 2011// cleared. We only use the first result here. 2012let Defs = [CC] in 2013 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2014def : Pat<(ctlz GR64:$src), 2015 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2016 2017// Population count. Counts bits set per byte. 2018let Predicates = [FeaturePopulationCount], Defs = [CC] in 2019 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2020 2021// Search a block of memory for a character. 2022let mayLoad = 1, Defs = [CC] in 2023 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2024let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2025 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2026 2027// Compare until substring equal. 2028let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2029 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2030 2031// Compare and form codeword. 2032let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2033 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2034 2035// Update tree. 2036let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2037 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2038 def UPT : SideEffectInherentE<"upt", 0x0102>; 2039 2040// Checksum. 2041let mayLoad = 1, Defs = [CC] in 2042 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2043 2044// Compression call. 2045let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2046 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2047 2048// Execute. 2049let hasSideEffects = 1 in { 2050 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2051 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2052} 2053 2054//===----------------------------------------------------------------------===// 2055// .insn directive instructions 2056//===----------------------------------------------------------------------===// 2057 2058let isCodeGenOnly = 1, hasSideEffects = 1 in { 2059 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2060 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2061 imm32sx16:$I2), 2062 ".insn ri,$enc,$R1,$I2", []>; 2063 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2064 AnyReg:$R3, brtarget16:$I2), 2065 ".insn rie,$enc,$R1,$R3,$I2", []>; 2066 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2067 brtarget32:$I2), 2068 ".insn ril,$enc,$R1,$I2", []>; 2069 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2070 uimm32:$I2), 2071 ".insn rilu,$enc,$R1,$I2", []>; 2072 def InsnRIS : DirectiveInsnRIS<(outs), 2073 (ins imm64zx48:$enc, AnyReg:$R1, 2074 imm32sx8:$I2, imm32zx4:$M3, 2075 bdaddr12only:$BD4), 2076 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2077 def InsnRR : DirectiveInsnRR<(outs), 2078 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2079 ".insn rr,$enc,$R1,$R2", []>; 2080 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2081 AnyReg:$R1, AnyReg:$R2), 2082 ".insn rre,$enc,$R1,$R2", []>; 2083 def InsnRRF : DirectiveInsnRRF<(outs), 2084 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2085 AnyReg:$R3, imm32zx4:$M4), 2086 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2087 def InsnRRS : DirectiveInsnRRS<(outs), 2088 (ins imm64zx48:$enc, AnyReg:$R1, 2089 AnyReg:$R2, imm32zx4:$M3, 2090 bdaddr12only:$BD4), 2091 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2092 def InsnRS : DirectiveInsnRS<(outs), 2093 (ins imm64zx32:$enc, AnyReg:$R1, 2094 AnyReg:$R3, bdaddr12only:$BD2), 2095 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2096 def InsnRSE : DirectiveInsnRSE<(outs), 2097 (ins imm64zx48:$enc, AnyReg:$R1, 2098 AnyReg:$R3, bdaddr12only:$BD2), 2099 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2100 def InsnRSI : DirectiveInsnRSI<(outs), 2101 (ins imm64zx48:$enc, AnyReg:$R1, 2102 AnyReg:$R3, brtarget16:$RI2), 2103 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2104 def InsnRSY : DirectiveInsnRSY<(outs), 2105 (ins imm64zx48:$enc, AnyReg:$R1, 2106 AnyReg:$R3, bdaddr20only:$BD2), 2107 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2108 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2109 bdxaddr12only:$XBD2), 2110 ".insn rx,$enc,$R1,$XBD2", []>; 2111 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2112 bdxaddr12only:$XBD2), 2113 ".insn rxe,$enc,$R1,$XBD2", []>; 2114 def InsnRXF : DirectiveInsnRXF<(outs), 2115 (ins imm64zx48:$enc, AnyReg:$R1, 2116 AnyReg:$R3, bdxaddr12only:$XBD2), 2117 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2118 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2119 bdxaddr20only:$XBD2), 2120 ".insn rxy,$enc,$R1,$XBD2", []>; 2121 def InsnS : DirectiveInsnS<(outs), 2122 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2123 ".insn s,$enc,$BD2", []>; 2124 def InsnSI : DirectiveInsnSI<(outs), 2125 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2126 imm32sx8:$I2), 2127 ".insn si,$enc,$BD1,$I2", []>; 2128 def InsnSIY : DirectiveInsnSIY<(outs), 2129 (ins imm64zx48:$enc, 2130 bdaddr20only:$BD1, imm32zx8:$I2), 2131 ".insn siy,$enc,$BD1,$I2", []>; 2132 def InsnSIL : DirectiveInsnSIL<(outs), 2133 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2134 imm32zx16:$I2), 2135 ".insn sil,$enc,$BD1,$I2", []>; 2136 def InsnSS : DirectiveInsnSS<(outs), 2137 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2138 bdaddr12only:$BD2, AnyReg:$R3), 2139 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2140 def InsnSSE : DirectiveInsnSSE<(outs), 2141 (ins imm64zx48:$enc, 2142 bdaddr12only:$BD1,bdaddr12only:$BD2), 2143 ".insn sse,$enc,$BD1,$BD2", []>; 2144 def InsnSSF : DirectiveInsnSSF<(outs), 2145 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2146 bdaddr12only:$BD2, AnyReg:$R3), 2147 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2148} 2149 2150//===----------------------------------------------------------------------===// 2151// Peepholes. 2152//===----------------------------------------------------------------------===// 2153 2154// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2155// equivalent to (and (xor x, -1), y) 2156def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2157 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2158 2159// Shift/rotate instructions only use the last 6 bits of the second operand 2160// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2161// last 16 bits. 2162// Complexity is added so that we match this before we match NILF on the AND 2163// operation alone. 2164let AddedComplexity = 4 in { 2165 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2166 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2167 2168 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 2169 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2170 2171 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2172 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2173 2174 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2175 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2176 2177 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 2178 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2179 2180 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2181 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2182 2183 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 2184 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2185 2186 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 2187 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 2188} 2189 2190// Peepholes for turning scalar operations into block operations. 2191defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2192 XCSequence, 1>; 2193defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2194 XCSequence, 2>; 2195defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2196 XCSequence, 4>; 2197defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2198 OCSequence, XCSequence, 1>; 2199defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2200 XCSequence, 2>; 2201defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2202 XCSequence, 4>; 2203defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2204 XCSequence, 8>; 2205