1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// The callseq_start node requires the hasSideEffects flag, even though these 17// instructions are noops on SystemZ. 18let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45//===----------------------------------------------------------------------===// 46// Branch instructions 47//===----------------------------------------------------------------------===// 48 49// Conditional branches. 50let isBranch = 1, isTerminator = 1, Uses = [CC] in { 51 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 52 // with the condition-code mask being the first operand. It seems friendlier 53 // to use mnemonic forms like JE and JLH when writing out the assembly though. 54 let isCodeGenOnly = 1 in { 55 // An assembler extended mnemonic for BRC. 56 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 57 // An assembler extended mnemonic for BRCL. (The extension is "G" 58 // rather than "L" because "JL" is "Jump if Less".) 59 def BRCL : CondBranchRIL<"jg#", 0xC04>; 60 let isIndirectBranch = 1 in { 61 def BC : CondBranchRX<"b#", 0x47>; 62 def BCR : CondBranchRR<"b#r", 0x07>; 63 def BIC : CondBranchRXY<"bi#", 0xe347>, 64 Requires<[FeatureMiscellaneousExtensions2]>; 65 } 66 } 67 68 // Allow using the raw forms directly from the assembler (and occasional 69 // special code generation needs) as well. 70 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 71 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 72 let isIndirectBranch = 1 in { 73 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 74 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 75 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 76 Requires<[FeatureMiscellaneousExtensions2]>; 77 } 78 79 // Define AsmParser extended mnemonics for each general condition-code mask 80 // (integer or floating-point) 81 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 82 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 83 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 84 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 85 let isIndirectBranch = 1 in { 86 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 87 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 88 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 89 Requires<[FeatureMiscellaneousExtensions2]>; 90 } 91 } 92} 93 94// Unconditional branches. These are in fact simply variants of the 95// conditional branches with the condition mask set to "always". 96let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 97 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 98 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 99 let isIndirectBranch = 1 in { 100 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 101 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 102 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 103 Requires<[FeatureMiscellaneousExtensions2]>; 104 } 105} 106 107// NOPs. These are again variants of the conditional branches, with the 108// condition mask set to "never". NOP_bare can't be an InstAlias since it 109// would need R0D hard coded which is not part of ADDR64BitRegClass. 110def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 111let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 112 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 113def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 114def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 115 116// An alias of BRC 0, label 117def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 118 119// An alias of BRCL 0, label 120def JGNOP : InstAlias<"jgnop\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 121 122// Fused compare-and-branch instructions. 123// 124// These instructions do not use or clobber the condition codes. 125// We nevertheless pretend that the relative compare-and-branch 126// instructions clobber CC, so that we can lower them to separate 127// comparisons and BRCLs if the branch ends up being out of range. 128let isBranch = 1, isTerminator = 1 in { 129 // As for normal branches, we handle these instructions internally in 130 // their raw CRJ-like form, but use assembly macros like CRJE when writing 131 // them out. Using the *Pair multiclasses, we also create the raw forms. 132 let Defs = [CC] in { 133 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 134 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 135 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 136 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 137 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 138 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 139 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 140 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 141 } 142 let isIndirectBranch = 1 in { 143 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 144 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 145 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 146 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 147 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 148 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 149 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 150 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 151 } 152 153 // Define AsmParser mnemonics for each integer condition-code mask. 154 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 155 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 156 let Defs = [CC] in { 157 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 158 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 159 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 160 imm32sx8>; 161 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 162 imm64sx8>; 163 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 164 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 165 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 166 imm32zx8>; 167 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 168 imm64zx8>; 169 } 170 let isIndirectBranch = 1 in { 171 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 172 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 173 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 174 imm32sx8>; 175 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 176 imm64sx8>; 177 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 178 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 179 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 180 imm32zx8>; 181 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 182 imm64zx8>; 183 } 184 } 185} 186 187// Decrement a register and branch if it is nonzero. These don't clobber CC, 188// but we might need to split long relative branches into sequences that do. 189let isBranch = 1, isTerminator = 1 in { 190 let Defs = [CC] in { 191 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 192 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 193 } 194 // This doesn't need to clobber CC since we never need to split it. 195 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 196 Requires<[FeatureHighWord]>; 197 198 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 199 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 200 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 201 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 202} 203 204let isBranch = 1, isTerminator = 1 in { 205 let Defs = [CC] in { 206 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 207 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 208 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 209 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 210 } 211 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 212 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 213 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 214 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 215} 216 217//===----------------------------------------------------------------------===// 218// Trap instructions 219//===----------------------------------------------------------------------===// 220 221// Unconditional trap. 222let hasCtrlDep = 1, hasSideEffects = 1 in 223 def Trap : Alias<4, (outs), (ins), [(trap)]>; 224 225// Conditional trap. 226let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 227 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 228 229// Fused compare-and-trap instructions. 230let hasCtrlDep = 1, hasSideEffects = 1 in { 231 // These patterns work the same way as for compare-and-branch. 232 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 233 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 234 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 235 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 236 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 237 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 238 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 239 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 240 let Predicates = [FeatureMiscellaneousExtensions] in { 241 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 242 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 243 } 244 245 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 246 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 247 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 248 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 249 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 250 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 251 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 252 imm32sx16>; 253 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 254 imm64sx16>; 255 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 256 imm32zx16>; 257 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 258 imm64zx16>; 259 let Predicates = [FeatureMiscellaneousExtensions] in { 260 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 261 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 262 } 263 } 264} 265 266//===----------------------------------------------------------------------===// 267// Call and return instructions 268//===----------------------------------------------------------------------===// 269 270// Define the general form of the call instructions for the asm parser. 271// These instructions don't hard-code %r14 as the return address register. 272let isCall = 1, Defs = [CC] in { 273 def BRAS : CallRI <"bras", 0xA75>; 274 def BRASL : CallRIL<"brasl", 0xC05>; 275 def BAS : CallRX <"bas", 0x4D>; 276 def BASR : CallRR <"basr", 0x0D>; 277} 278 279// z/OS XPLINK 280let Predicates = [IsTargetXPLINK64] in { 281 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 282 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 283 [(z_call pcrel32:$I2)]>; 284 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 285 [(z_call ADDR64:$R2)]>; 286 } 287} 288 289// Regular calls. 290// z/Linux ELF 291let Predicates = [IsTargetELF] in { 292 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 293 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 294 [(z_call pcrel32:$I2)]>; 295 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 296 [(z_call ADDR64:$R2)]>; 297 } 298 299 // TLS calls. These will be lowered into a call to __tls_get_offset, 300 // with an extra relocation specifying the TLS symbol. 301 let isCall = 1, Defs = [R14D, CC] in { 302 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 303 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 304 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 305 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 306 } 307} 308 309// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 310// R1 used for ELF 311let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 312 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 313 [(z_sibcall pcrel32:$I2)]>; 314 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 315 [(z_sibcall ADDR64:$R2)]>; 316} 317 318// Conditional sibling calls. 319let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 320 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 321 pcrel32:$I2), []>; 322 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 323 ADDR64:$R2), []>; 324} 325 326// Fused compare and conditional sibling calls. 327let isCall = 1, isTerminator = 1, isReturn = 1 in { 328 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 329 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 330 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 331 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 332 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 333 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 334 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 335 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 336} 337 338// A return instruction (br %r14) for ELF and (b 2 %r7) for XPLink. 339let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 340 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 341 342// A conditional return instruction (bcr <cond>, %r14). 343let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 344 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 345 346// Fused compare and conditional returns. 347let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 348 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 349 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 350 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 351 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 352 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 353 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 354 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 355 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 356} 357 358//===----------------------------------------------------------------------===// 359// Select instructions 360//===----------------------------------------------------------------------===// 361 362def Select32 : SelectWrapper<i32, GR32>, 363 Requires<[FeatureNoLoadStoreOnCond]>; 364def Select64 : SelectWrapper<i64, GR64>, 365 Requires<[FeatureNoLoadStoreOnCond]>; 366 367// We don't define 32-bit Mux stores if we don't have STOCFH, because the 368// low-only STOC should then always be used if possible. 369defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 370 nonvolatile_anyextloadi8, bdxaddr20only>, 371 Requires<[FeatureHighWord]>; 372defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 373 nonvolatile_anyextloadi16, bdxaddr20only>, 374 Requires<[FeatureHighWord]>; 375defm CondStore32Mux : CondStores<GRX32, simple_store, 376 simple_load, bdxaddr20only>, 377 Requires<[FeatureLoadStoreOnCond2]>; 378defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 379 nonvolatile_anyextloadi8, bdxaddr20only>; 380defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 381 nonvolatile_anyextloadi16, bdxaddr20only>; 382defm CondStore32 : CondStores<GR32, simple_store, 383 simple_load, bdxaddr20only>; 384 385defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 386 nonvolatile_anyextloadi8, bdxaddr20only>; 387defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 388 nonvolatile_anyextloadi16, bdxaddr20only>; 389defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 390 nonvolatile_anyextloadi32, bdxaddr20only>; 391defm CondStore64 : CondStores<GR64, simple_store, 392 simple_load, bdxaddr20only>; 393 394//===----------------------------------------------------------------------===// 395// Move instructions 396//===----------------------------------------------------------------------===// 397 398// Register moves. 399def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 400def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 401 402let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 403 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 404 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 405} 406 407let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 408 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 409 410// Immediate moves. 411let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 412 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 413 // deopending on the choice of register. 414 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 415 Requires<[FeatureHighWord]>; 416 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 417 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 418 419 // Other 16-bit immediates. 420 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 421 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 422 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 423 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 424 425 // 32-bit immediates. 426 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 427 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 428 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 429} 430 431// Register loads. 432let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 433 // Expands to L, LY or LFH, depending on the choice of register. 434 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 435 Requires<[FeatureHighWord]>; 436 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 437 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 438 Requires<[FeatureHighWord]>; 439 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 440 441 // These instructions are split after register allocation, so we don't 442 // want a custom inserter. 443 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 444 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 445 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 446 } 447} 448let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 449 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 450 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 451} 452 453let canFoldAsLoad = 1 in { 454 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 455 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 456} 457 458// Load and zero rightmost byte. 459let Predicates = [FeatureLoadAndZeroRightmostByte] in { 460 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 461 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 462 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 463 (LZRF bdxaddr20only:$src)>; 464 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 465 (LZRG bdxaddr20only:$src)>; 466} 467 468// Load and trap. 469let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 470 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 471 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 472 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 473} 474 475// Register stores. 476let SimpleBDXStore = 1, mayStore = 1 in { 477 // Expands to ST, STY or STFH, depending on the choice of register. 478 def STMux : StoreRXYPseudo<store, GRX32, 4>, 479 Requires<[FeatureHighWord]>; 480 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 481 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 482 Requires<[FeatureHighWord]>; 483 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 484 485 // These instructions are split after register allocation, so we don't 486 // want a custom inserter. 487 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 488 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 489 [(store GR128:$src, bdxaddr20only128:$dst)]>; 490 } 491} 492def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 493def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 494 495// 8-bit immediate stores to 8-bit fields. 496defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 497 498// 16-bit immediate stores to 16-, 32- or 64-bit fields. 499def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 500def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 501def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 502 503// Memory-to-memory moves. 504let mayLoad = 1, mayStore = 1 in 505 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 506let mayLoad = 1, mayStore = 1, Defs = [CC] in { 507 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 508 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 509 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 510} 511 512// Move right. 513let Predicates = [FeatureMiscellaneousExtensions3], 514 mayLoad = 1, mayStore = 1, Uses = [R0L] in 515 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 516 517// String moves. 518let mayLoad = 1, mayStore = 1, Defs = [CC] in 519 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 520 521//===----------------------------------------------------------------------===// 522// Conditional move instructions 523//===----------------------------------------------------------------------===// 524 525let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 526 // Select. 527 let isCommutable = 1 in { 528 // Expands to SELR or SELFHR or a branch-and-move sequence, 529 // depending on the choice of registers. 530 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 531 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 532 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 533 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 534 } 535 536 // Define AsmParser extended mnemonics for each general condition-code mask. 537 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 538 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 539 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 540 GR32, GR32, GR32>; 541 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 542 GRH32, GRH32, GRH32>; 543 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 544 GR64, GR64, GR64>; 545 } 546} 547 548let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 549 // Load immediate on condition. Matched via DAG pattern and created 550 // by the PeepholeOptimizer via FoldImmediate. 551 552 // Expands to LOCHI or LOCHHI, depending on the choice of register. 553 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 554 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 555 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 556 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 557 558 // Move register on condition. Matched via DAG pattern and 559 // created by early if-conversion. 560 let isCommutable = 1 in { 561 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 562 // depending on the choice of registers. 563 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 564 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 565 } 566 567 // Load on condition. Matched via DAG pattern. 568 // Expands to LOC or LOCFH, depending on the choice of register. 569 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 570 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 571 572 // Store on condition. Expanded from CondStore* pseudos. 573 // Expands to STOC or STOCFH, depending on the choice of register. 574 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 575 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 576 577 // Define AsmParser extended mnemonics for each general condition-code mask. 578 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 579 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 580 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 581 imm32sx16>; 582 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 583 imm64sx16>; 584 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 585 imm32sx16>; 586 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 587 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 588 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 589 } 590} 591 592let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 593 // Move register on condition. Matched via DAG pattern and 594 // created by early if-conversion. 595 let isCommutable = 1 in { 596 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 597 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 598 } 599 600 // Load on condition. Matched via DAG pattern. 601 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 602 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 603 604 // Store on condition. Expanded from CondStore* pseudos. 605 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 606 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 607 608 // Define AsmParser extended mnemonics for each general condition-code mask. 609 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 610 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 611 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 612 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 613 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 614 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 615 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 616 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 617 } 618} 619//===----------------------------------------------------------------------===// 620// Sign extensions 621//===----------------------------------------------------------------------===// 622// 623// Note that putting these before zero extensions mean that we will prefer 624// them for anyextload*. There's not really much to choose between the two 625// either way, but signed-extending loads have a short LH and a long LHY, 626// while zero-extending loads have only the long LLH. 627// 628//===----------------------------------------------------------------------===// 629 630// 32-bit extensions from registers. 631def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 632def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 633 634// 64-bit extensions from registers. 635def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 636def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 637def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 638 639let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 640 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 641 642// Match 32-to-64-bit sign extensions in which the source is already 643// in a 64-bit register. 644def : Pat<(sext_inreg GR64:$src, i32), 645 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 646 647// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 648// depending on the choice of register. 649def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 650 Requires<[FeatureHighWord]>; 651def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 652def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 653 Requires<[FeatureHighWord]>; 654 655// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 656// depending on the choice of register. 657def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 658 Requires<[FeatureHighWord]>; 659defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 660def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 661 Requires<[FeatureHighWord]>; 662def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 663 664// 64-bit extensions from memory. 665def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 666def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 667def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 668def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 669def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 670let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 671 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 672 673//===----------------------------------------------------------------------===// 674// Zero extensions 675//===----------------------------------------------------------------------===// 676 677// 32-bit extensions from registers. 678 679// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 680def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 681 Requires<[FeatureHighWord]>; 682def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 683// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 684def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 685 Requires<[FeatureHighWord]>; 686def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 687 688// 64-bit extensions from registers. 689def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 690def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 691def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 692 693// Match 32-to-64-bit zero extensions in which the source is already 694// in a 64-bit register. 695def : Pat<(and GR64:$src, 0xffffffff), 696 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 697 698// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 699// depending on the choice of register. 700def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 701 Requires<[FeatureHighWord]>; 702def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 703def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 704 Requires<[FeatureHighWord]>; 705 706// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 707// depending on the choice of register. 708def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 709 Requires<[FeatureHighWord]>; 710def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 711def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 712 Requires<[FeatureHighWord]>; 713def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 714 715// 64-bit extensions from memory. 716def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 717def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 718def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 719def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 720def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 721 722// 31-to-64-bit zero extensions. 723def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 724def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 725def : Pat<(and GR64:$src, 0x7fffffff), 726 (LLGTR GR64:$src)>; 727def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 728 (LLGT bdxaddr20only:$src)>; 729 730// Load and zero rightmost byte. 731let Predicates = [FeatureLoadAndZeroRightmostByte] in { 732 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 733 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 734 (LLZRGF bdxaddr20only:$src)>; 735} 736 737// Load and trap. 738let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 739 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 740 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 741} 742 743// Extend GR64s to GR128s. 744let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 745 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 746 747//===----------------------------------------------------------------------===// 748// "Any" extensions 749//===----------------------------------------------------------------------===// 750 751// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 752def : Pat<(i64 (anyext GR32:$src)), 753 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 754 755// Extend GR64s to GR128s. 756let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 757 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 758 759//===----------------------------------------------------------------------===// 760// Truncations 761//===----------------------------------------------------------------------===// 762 763// Truncations of 64-bit registers to 32-bit registers. 764def : Pat<(i32 (trunc GR64:$src)), 765 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 766 767// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 768// STC, STCY or STCH, depending on the choice of register. 769def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 770 Requires<[FeatureHighWord]>; 771defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 772def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 773 Requires<[FeatureHighWord]>; 774 775// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 776// STH, STHY or STHH, depending on the choice of register. 777def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 778 Requires<[FeatureHighWord]>; 779defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 780def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 781 Requires<[FeatureHighWord]>; 782def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 783 784// Truncations of 64-bit registers to memory. 785defm : StoreGR64Pair<STC, STCY, truncstorei8>; 786defm : StoreGR64Pair<STH, STHY, truncstorei16>; 787def : StoreGR64PC<STHRL, aligned_truncstorei16>; 788defm : StoreGR64Pair<ST, STY, truncstorei32>; 789def : StoreGR64PC<STRL, aligned_truncstorei32>; 790 791// Store characters under mask -- not (yet) used for codegen. 792defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 793def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 794 795//===----------------------------------------------------------------------===// 796// Multi-register moves 797//===----------------------------------------------------------------------===// 798 799// Multi-register loads. 800defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 801def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 802def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 803def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 804 805// Multi-register stores. 806defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 807def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 808def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 809 810//===----------------------------------------------------------------------===// 811// Byte swaps 812//===----------------------------------------------------------------------===// 813 814// Byte-swapping register moves. 815def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 816def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 817 818// Byte-swapping loads. 819def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 820def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 821def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 822 823// Byte-swapping stores. 824def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 825def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 826def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 827 828// Byte-swapping memory-to-memory moves. 829let mayLoad = 1, mayStore = 1 in 830 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 831 832//===----------------------------------------------------------------------===// 833// Load address instructions 834//===----------------------------------------------------------------------===// 835 836// Load BDX-style addresses. 837let isAsCheapAsAMove = 1, isReMaterializable = 1 in 838 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 839 840// Load a PC-relative address. There's no version of this instruction 841// with a 16-bit offset, so there's no relaxation. 842let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 843 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 844 845// Load the Global Offset Table address. This will be lowered into a 846// larl $R1, _GLOBAL_OFFSET_TABLE_ 847// instruction. 848def GOT : Alias<6, (outs GR64:$R1), (ins), 849 [(set GR64:$R1, (global_offset_table))]>; 850 851//===----------------------------------------------------------------------===// 852// Absolute and Negation 853//===----------------------------------------------------------------------===// 854 855let Defs = [CC] in { 856 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 857 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 858 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 859 } 860 let CCValues = 0xE, CompareZeroCCMask = 0xE in 861 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 862} 863defm : SXU<abs, LPGFR>; 864 865let Defs = [CC] in { 866 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 867 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 868 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 869 } 870 let CCValues = 0xE, CompareZeroCCMask = 0xE in 871 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 872} 873defm : SXU<z_inegabs, LNGFR>; 874 875let Defs = [CC] in { 876 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 877 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 878 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 879 } 880 let CCValues = 0xE, CompareZeroCCMask = 0xE in 881 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 882} 883defm : SXU<ineg, LCGFR>; 884 885//===----------------------------------------------------------------------===// 886// Insertion 887//===----------------------------------------------------------------------===// 888 889let isCodeGenOnly = 1 in 890 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 891defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 892 893defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 894defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 895 896defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 897defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 898 899// Insert characters under mask -- not (yet) used for codegen. 900let Defs = [CC] in { 901 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 902 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 903} 904 905// Insertions of a 16-bit immediate, leaving other bits unaffected. 906// We don't have or_as_insert equivalents of these operations because 907// OI is available instead. 908// 909// IIxMux expands to II[LH]x, depending on the choice of register. 910def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 911 Requires<[FeatureHighWord]>; 912def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 913 Requires<[FeatureHighWord]>; 914def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 915def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 916def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 917def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 918def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 919def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 920def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 921def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 922 923// ...likewise for 32-bit immediates. For GR32s this is a general 924// full-width move. (We use IILF rather than something like LLILF 925// for 32-bit moves because IILF leaves the upper 32 bits of the 926// GR64 unchanged.) 927let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 928 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 929 Requires<[FeatureHighWord]>; 930 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 931 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 932} 933def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 934def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 935 936// An alternative model of inserthf, with the first operand being 937// a zero-extended value. 938def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 939 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 940 imm64hf32:$imm)>; 941 942//===----------------------------------------------------------------------===// 943// Addition 944//===----------------------------------------------------------------------===// 945 946// Addition producing a signed overflow flag. 947let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 948 // Addition of a register. 949 let isCommutable = 1 in { 950 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 951 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 952 } 953 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 954 955 // Addition to a high register. 956 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 957 Requires<[FeatureHighWord]>; 958 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 959 Requires<[FeatureHighWord]>; 960 961 // Addition of signed 16-bit immediates. 962 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 963 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 964 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 965 966 // Addition of signed 32-bit immediates. 967 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 968 Requires<[FeatureHighWord]>; 969 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 970 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 971 Requires<[FeatureHighWord]>; 972 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 973 974 // Addition of memory. 975 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 976 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 977 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 978 Requires<[FeatureMiscellaneousExtensions2]>; 979 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 980 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 981 982 // Addition to memory. 983 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 984 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 985} 986defm : SXB<z_sadd, GR64, AGFR>; 987 988// Addition producing a carry. 989let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 990 // Addition of a register. 991 let isCommutable = 1 in { 992 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 993 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 994 } 995 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 996 997 // Addition to a high register. 998 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 999 Requires<[FeatureHighWord]>; 1000 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1001 Requires<[FeatureHighWord]>; 1002 1003 // Addition of signed 16-bit immediates. 1004 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1005 Requires<[FeatureDistinctOps]>; 1006 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1007 Requires<[FeatureDistinctOps]>; 1008 1009 // Addition of unsigned 32-bit immediates. 1010 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1011 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1012 1013 // Addition of signed 32-bit immediates. 1014 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1015 Requires<[FeatureHighWord]>; 1016 1017 // Addition of memory. 1018 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1019 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1020 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1021 1022 // Addition to memory. 1023 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1024 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1025} 1026defm : ZXB<z_uadd, GR64, ALGFR>; 1027 1028// Addition producing and using a carry. 1029let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1030 // Addition of a register. 1031 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1032 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1033 1034 // Addition of memory. 1035 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1036 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1037} 1038 1039// Addition that does not modify the condition code. 1040def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1041 Requires<[FeatureHighWord]>; 1042 1043 1044//===----------------------------------------------------------------------===// 1045// Subtraction 1046//===----------------------------------------------------------------------===// 1047 1048// Subtraction producing a signed overflow flag. 1049let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1050 CCIfNoSignedWrap = 1 in { 1051 // Subtraction of a register. 1052 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1053 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1054 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1055 1056 // Subtraction from a high register. 1057 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1058 Requires<[FeatureHighWord]>; 1059 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1060 Requires<[FeatureHighWord]>; 1061 1062 // Subtraction of memory. 1063 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1064 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1065 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1066 Requires<[FeatureMiscellaneousExtensions2]>; 1067 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1068 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1069} 1070defm : SXB<z_ssub, GR64, SGFR>; 1071 1072// Subtracting an immediate is the same as adding the negated immediate. 1073let AddedComplexity = 1 in { 1074 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1075 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1076 Requires<[FeatureHighWord]>; 1077 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1078 (AFIMux GR32:$src1, simm32n:$src2)>, 1079 Requires<[FeatureHighWord]>; 1080 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1081 (AHI GR32:$src1, imm32sx16n:$src2)>; 1082 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1083 (AFI GR32:$src1, simm32n:$src2)>; 1084 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1085 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1086 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1087 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1088} 1089 1090// And vice versa in one special case, where we need to load a 1091// constant into a register in any case, but the negated constant 1092// requires fewer instructions to load. 1093def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1094 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1095def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1096 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1097 1098// Subtraction producing a carry. 1099let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1100 // Subtraction of a register. 1101 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1102 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1103 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1104 1105 // Subtraction from a high register. 1106 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1107 Requires<[FeatureHighWord]>; 1108 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1109 Requires<[FeatureHighWord]>; 1110 1111 // Subtraction of unsigned 32-bit immediates. 1112 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1113 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1114 1115 // Subtraction of memory. 1116 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1117 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1118 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1119} 1120defm : ZXB<z_usub, GR64, SLGFR>; 1121 1122// Subtracting an immediate is the same as adding the negated immediate. 1123let AddedComplexity = 1 in { 1124 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1125 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1126 Requires<[FeatureDistinctOps]>; 1127 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1128 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1129 Requires<[FeatureDistinctOps]>; 1130} 1131 1132// And vice versa in one special case (but we prefer addition). 1133def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1134 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1135 1136// Subtraction producing and using a carry. 1137let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1138 // Subtraction of a register. 1139 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1140 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1141 1142 // Subtraction of memory. 1143 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1144 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1145} 1146 1147 1148//===----------------------------------------------------------------------===// 1149// AND 1150//===----------------------------------------------------------------------===// 1151 1152let Defs = [CC] in { 1153 // ANDs of a register. 1154 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1155 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1156 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1157 } 1158 1159 let isConvertibleToThreeAddress = 1 in { 1160 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1161 // The CC result only reflects the 16-bit field, not the full register. 1162 // 1163 // NIxMux expands to NI[LH]x, depending on the choice of register. 1164 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1165 Requires<[FeatureHighWord]>; 1166 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1167 Requires<[FeatureHighWord]>; 1168 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1169 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1170 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1171 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1172 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1173 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1174 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1175 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1176 1177 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1178 // The CC result only reflects the 32-bit field, which means we can 1179 // use it as a zero indicator for i32 operations but not otherwise. 1180 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1181 // Expands to NILF or NIHF, depending on the choice of register. 1182 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1183 Requires<[FeatureHighWord]>; 1184 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1185 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1186 } 1187 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1188 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1189 } 1190 1191 // ANDs of memory. 1192 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1193 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1194 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1195 } 1196 1197 // AND to memory 1198 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1199 1200 // Block AND. 1201 let mayLoad = 1, mayStore = 1 in 1202 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1203} 1204defm : RMWIByte<and, bdaddr12pair, NI>; 1205defm : RMWIByte<and, bdaddr20pair, NIY>; 1206 1207//===----------------------------------------------------------------------===// 1208// OR 1209//===----------------------------------------------------------------------===// 1210 1211let Defs = [CC] in { 1212 // ORs of a register. 1213 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1214 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1215 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1216 } 1217 1218 // ORs of a 16-bit immediate, leaving other bits unaffected. 1219 // The CC result only reflects the 16-bit field, not the full register. 1220 // 1221 // OIxMux expands to OI[LH]x, depending on the choice of register. 1222 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1223 Requires<[FeatureHighWord]>; 1224 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1225 Requires<[FeatureHighWord]>; 1226 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1227 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1228 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1229 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1230 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1231 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1232 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1233 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1234 1235 // ORs of a 32-bit immediate, leaving other bits unaffected. 1236 // The CC result only reflects the 32-bit field, which means we can 1237 // use it as a zero indicator for i32 operations but not otherwise. 1238 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1239 // Expands to OILF or OIHF, depending on the choice of register. 1240 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1241 Requires<[FeatureHighWord]>; 1242 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1243 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1244 } 1245 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1246 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1247 1248 // ORs of memory. 1249 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1250 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1251 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1252 } 1253 1254 // OR to memory 1255 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1256 1257 // Block OR. 1258 let mayLoad = 1, mayStore = 1 in 1259 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1260} 1261defm : RMWIByte<or, bdaddr12pair, OI>; 1262defm : RMWIByte<or, bdaddr20pair, OIY>; 1263 1264//===----------------------------------------------------------------------===// 1265// XOR 1266//===----------------------------------------------------------------------===// 1267 1268let Defs = [CC] in { 1269 // XORs of a register. 1270 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1271 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1272 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1273 } 1274 1275 // XORs of a 32-bit immediate, leaving other bits unaffected. 1276 // The CC result only reflects the 32-bit field, which means we can 1277 // use it as a zero indicator for i32 operations but not otherwise. 1278 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1279 // Expands to XILF or XIHF, depending on the choice of register. 1280 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1281 Requires<[FeatureHighWord]>; 1282 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1283 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1284 } 1285 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1286 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1287 1288 // XORs of memory. 1289 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1290 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1291 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1292 } 1293 1294 // XOR to memory 1295 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1296 1297 // Block XOR. 1298 let mayLoad = 1, mayStore = 1 in 1299 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1300} 1301defm : RMWIByte<xor, bdaddr12pair, XI>; 1302defm : RMWIByte<xor, bdaddr20pair, XIY>; 1303 1304//===----------------------------------------------------------------------===// 1305// Combined logical operations 1306//===----------------------------------------------------------------------===// 1307 1308let Predicates = [FeatureMiscellaneousExtensions3], 1309 Defs = [CC] in { 1310 // AND with complement. 1311 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1312 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1313 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1314 } 1315 1316 // OR with complement. 1317 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1318 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1319 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1320 } 1321 1322 // NAND. 1323 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1324 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1325 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1326 } 1327 1328 // NOR. 1329 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1330 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1331 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1332 } 1333 1334 // NXOR. 1335 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1336 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1337 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1338 } 1339} 1340 1341//===----------------------------------------------------------------------===// 1342// Multiplication 1343//===----------------------------------------------------------------------===// 1344 1345// Multiplication of a register, setting the condition code. We prefer these 1346// over MS(G)R if available, even though we cannot use the condition code, 1347// since they are three-operand instructions. 1348let Predicates = [FeatureMiscellaneousExtensions2], 1349 Defs = [CC], isCommutable = 1 in { 1350 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1351 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1352} 1353 1354// Multiplication of a register. 1355let isCommutable = 1 in { 1356 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1357 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1358} 1359def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1360defm : SXB<mul, GR64, MSGFR>; 1361 1362// Multiplication of a signed 16-bit immediate. 1363def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1364def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1365 1366// Multiplication of a signed 32-bit immediate. 1367def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1368def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1369 1370// Multiplication of memory. 1371defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1372defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1373def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1374 Requires<[FeatureMiscellaneousExtensions2]>; 1375def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1376def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1377 1378// Multiplication of memory, setting the condition code. 1379let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1380 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1381 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1382} 1383 1384// Multiplication of a register, producing two results. 1385def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1386def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1387 Requires<[FeatureMiscellaneousExtensions2]>; 1388def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1389def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1390 1391def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1392 (MGRK GR64:$src1, GR64:$src2)>; 1393def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1394 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1395 1396// Multiplication of memory, producing two results. 1397def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1398def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1399def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1400 Requires<[FeatureMiscellaneousExtensions2]>; 1401def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1402def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1403 1404def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1405 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1406def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1407 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1408 1409//===----------------------------------------------------------------------===// 1410// Division and remainder 1411//===----------------------------------------------------------------------===// 1412 1413let hasSideEffects = 1 in { // Do not speculatively execute. 1414 // Division and remainder, from registers. 1415 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1416 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1417 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1418 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1419 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1420 1421 // Division and remainder, from memory. 1422 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1423 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1424 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1425 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1426 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1427} 1428def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1429 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1430def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1431 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1432def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1433 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1434def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1435 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1436 1437def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1438 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1439 subreg_l32)), GR32:$src2)>; 1440def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1441 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1442 subreg_l32)), bdxaddr20only:$src2)>; 1443def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1444 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1445def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1446 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1447 1448//===----------------------------------------------------------------------===// 1449// Shifts 1450//===----------------------------------------------------------------------===// 1451 1452// Logical shift left. 1453defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1454def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1455def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1456 1457// Arithmetic shift left. 1458let Defs = [CC] in { 1459 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1460 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1461 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1462} 1463 1464// Logical shift right. 1465defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1466def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1467def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1468 1469// Arithmetic shift right. 1470let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1471 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1472 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1473 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1474} 1475 1476// Rotate left. 1477def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1478def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1479 1480// Rotate second operand left and inserted selected bits into first operand. 1481// These can act like 32-bit operands provided that the constant start and 1482// end bits (operands 2 and 3) are in the range [32, 64). 1483let Defs = [CC] in { 1484 let isCodeGenOnly = 1 in 1485 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1486 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1487 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1488} 1489 1490// On zEC12 we have a variant of RISBG that does not set CC. 1491let Predicates = [FeatureMiscellaneousExtensions] in 1492 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1493 1494// Forms of RISBG that only affect one word of the destination register. 1495// They do not set CC. 1496let Predicates = [FeatureHighWord] in { 1497 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1498 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1499 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1500 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1501 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1502 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1503 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1504} 1505 1506// Rotate second operand left and perform a logical operation with selected 1507// bits of the first operand. The CC result only describes the selected bits, 1508// so isn't useful for a full comparison against zero. 1509let Defs = [CC] in { 1510 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1511 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1512 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1513} 1514 1515//===----------------------------------------------------------------------===// 1516// Comparison 1517//===----------------------------------------------------------------------===// 1518 1519// Signed comparisons. We put these before the unsigned comparisons because 1520// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1521// of the unsigned forms do. 1522let Defs = [CC], CCValues = 0xE in { 1523 // Comparison with a register. 1524 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1525 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1526 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1527 1528 // Comparison with a high register. 1529 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1530 Requires<[FeatureHighWord]>; 1531 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1532 Requires<[FeatureHighWord]>; 1533 1534 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1535 // depending on the choice of register. 1536 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1537 Requires<[FeatureHighWord]>; 1538 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1539 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1540 1541 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1542 // depending on the choice of register. 1543 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1544 Requires<[FeatureHighWord]>; 1545 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1546 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1547 Requires<[FeatureHighWord]>; 1548 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1549 1550 // Comparison with memory. 1551 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1552 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1553 Requires<[FeatureHighWord]>; 1554 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1555 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1556 Requires<[FeatureHighWord]>; 1557 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1558 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1559 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1560 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1561 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1562 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1563 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1564 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1565 1566 // Comparison between memory and a signed 16-bit immediate. 1567 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1568 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1569 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1570} 1571defm : SXB<z_scmp, GR64, CGFR>; 1572 1573// Unsigned comparisons. 1574let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1575 // Comparison with a register. 1576 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1577 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1578 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1579 1580 // Comparison with a high register. 1581 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1582 Requires<[FeatureHighWord]>; 1583 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1584 Requires<[FeatureHighWord]>; 1585 1586 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1587 // or CLIH, depending on the choice of register. 1588 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1589 Requires<[FeatureHighWord]>; 1590 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1591 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1592 Requires<[FeatureHighWord]>; 1593 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1594 1595 // Comparison with memory. 1596 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1597 Requires<[FeatureHighWord]>; 1598 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1599 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1600 Requires<[FeatureHighWord]>; 1601 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1602 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1603 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1604 aligned_azextloadi16>; 1605 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1606 aligned_load>; 1607 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1608 aligned_azextloadi16>; 1609 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1610 aligned_azextloadi32>; 1611 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1612 aligned_load>; 1613 1614 // Comparison between memory and an unsigned 8-bit immediate. 1615 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1616 1617 // Comparison between memory and an unsigned 16-bit immediate. 1618 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1619 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1620 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1621} 1622defm : ZXB<z_ucmp, GR64, CLGFR>; 1623 1624// Memory-to-memory comparison. 1625let mayLoad = 1, Defs = [CC] in { 1626 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1627 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1628 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1629 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1630} 1631 1632// String comparison. 1633let mayLoad = 1, Defs = [CC] in 1634 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1635 1636// Test under mask. 1637let Defs = [CC] in { 1638 // TMxMux expands to TM[LH]x, depending on the choice of register. 1639 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1640 Requires<[FeatureHighWord]>; 1641 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1642 Requires<[FeatureHighWord]>; 1643 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1644 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1645 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1646 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1647 1648 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1649 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1650 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1651 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1652 1653 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1654} 1655 1656def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1657def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1658 1659// Compare logical characters under mask -- not (yet) used for codegen. 1660let Defs = [CC] in { 1661 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1662 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1663} 1664 1665//===----------------------------------------------------------------------===// 1666// Prefetch and execution hint 1667//===----------------------------------------------------------------------===// 1668 1669let mayLoad = 1, mayStore = 1 in { 1670 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1671 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1672} 1673 1674let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1675 // Branch Prediction Preload 1676 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1677 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1678 1679 // Next Instruction Access Intent 1680 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1681} 1682 1683//===----------------------------------------------------------------------===// 1684// Atomic operations 1685//===----------------------------------------------------------------------===// 1686 1687// A serialization instruction that acts as a barrier for all memory 1688// accesses, which expands to "bcr 14, 0". 1689let hasSideEffects = 1 in 1690def Serialize : Alias<2, (outs), (ins), []>; 1691 1692// A pseudo instruction that serves as a compiler barrier. 1693let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1694def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1695 1696let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1697 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1698 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1699 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1700 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1701 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1702 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1703 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1704 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1705 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1706 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1707} 1708 1709def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1710def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1711def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1712 1713def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1714def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1715let Predicates = [FeatureNoInterlockedAccess1] in { 1716 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1717 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1718 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1719 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1720 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1721 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1722} 1723 1724def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1725def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1726def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1727 1728def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1729def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1730let Predicates = [FeatureNoInterlockedAccess1] in { 1731 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1732 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1733 imm32ll16c>; 1734 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1735 imm32lh16c>; 1736 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1737 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1738 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1739 imm64ll16c>; 1740 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1741 imm64lh16c>; 1742 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1743 imm64hl16c>; 1744 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1745 imm64hh16c>; 1746 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1747 imm64lf32c>; 1748 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1749 imm64hf32c>; 1750} 1751 1752def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1753def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1754let Predicates = [FeatureNoInterlockedAccess1] in { 1755 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1756 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1757 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1758 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1759 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1760 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1761 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1762 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1763 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1764 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1765 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1766} 1767 1768def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1769def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1770let Predicates = [FeatureNoInterlockedAccess1] in { 1771 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1772 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1773 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1774 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1775 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1776} 1777 1778def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1779def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1780 imm32lh16c>; 1781def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1782def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1783 imm32ll16c>; 1784def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1785 imm32lh16c>; 1786def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1787def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1788def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1789 imm64ll16c>; 1790def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1791 imm64lh16c>; 1792def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1793 imm64hl16c>; 1794def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1795 imm64hh16c>; 1796def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1797 imm64lf32c>; 1798def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1799 imm64hf32c>; 1800 1801def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1802def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1803def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1804 1805def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1806def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1807def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1808 1809def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1810def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1811def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1812 1813def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1814def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1815def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1816 1817def ATOMIC_CMP_SWAPW 1818 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1819 ADDR32:$bitshift, ADDR32:$negbitshift, 1820 uimm32:$bitsize), 1821 [(set GR32:$dst, 1822 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1823 ADDR32:$bitshift, ADDR32:$negbitshift, 1824 uimm32:$bitsize))]> { 1825 let Defs = [CC]; 1826 let mayLoad = 1; 1827 let mayStore = 1; 1828 let usesCustomInserter = 1; 1829 let hasNoSchedulingInfo = 1; 1830} 1831 1832// Test and set. 1833let mayLoad = 1, Defs = [CC] in 1834 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1835 1836// Compare and swap. 1837let Defs = [CC] in { 1838 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1839 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1840} 1841 1842// Compare double and swap. 1843let Defs = [CC] in { 1844 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1845 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1846} 1847 1848// Compare and swap and store. 1849let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1850 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1851 1852// Perform locked operation. 1853let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1854 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1855 1856// Load/store pair from/to quadword. 1857def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1858def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1859 1860// Load pair disjoint. 1861let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1862 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1863 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1864} 1865 1866//===----------------------------------------------------------------------===// 1867// Translate and convert 1868//===----------------------------------------------------------------------===// 1869 1870let mayLoad = 1, mayStore = 1 in 1871 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1872 1873let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1874 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1875 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1876} 1877 1878let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1879 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1880 1881let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1882 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1883 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1884} 1885 1886let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1887 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1888 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1889 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1890 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1891} 1892 1893let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1894 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1895 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1896 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1897 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1898 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1899 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1900 1901 let isAsmParserOnly = 1 in { 1902 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1903 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1904 } 1905} 1906 1907//===----------------------------------------------------------------------===// 1908// Message-security assist 1909//===----------------------------------------------------------------------===// 1910 1911let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1912 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1913 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1914 1915 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1916 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1917 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1918 1919 let Predicates = [FeatureMessageSecurityAssist4] in { 1920 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1921 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1922 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1923 GR128, GR128, GR128>; 1924 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1925 } 1926 1927 let Predicates = [FeatureMessageSecurityAssist5] in 1928 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1929 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1930 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1931 1932 let Predicates = [FeatureMessageSecurityAssist8] in 1933 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1934 GR128, GR128, GR128>; 1935 1936 let Predicates = [FeatureMessageSecurityAssist9] in 1937 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1938} 1939 1940//===----------------------------------------------------------------------===// 1941// Guarded storage 1942//===----------------------------------------------------------------------===// 1943 1944// These instructions use and/or modify the guarded storage control 1945// registers, which we do not otherwise model, so they should have 1946// hasSideEffects. 1947let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1948 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1949 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1950 1951 let mayLoad = 1 in 1952 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1953 let mayStore = 1 in 1954 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1955} 1956 1957//===----------------------------------------------------------------------===// 1958// Decimal arithmetic 1959//===----------------------------------------------------------------------===// 1960 1961defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1962def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1963 1964defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1965def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1966 1967let mayLoad = 1, mayStore = 1 in { 1968 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1969 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1970 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1971 1972 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1973 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1974 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1975 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1976 let Defs = [CC] in { 1977 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1978 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1979 } 1980} 1981 1982let mayLoad = 1, mayStore = 1 in { 1983 let Defs = [CC] in { 1984 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1985 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1986 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1987 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1988 } 1989 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1990 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1991 let Defs = [CC] in { 1992 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1993 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1994 } 1995} 1996 1997let Defs = [CC] in { 1998 def CP : CompareSSb<"cp", 0xF9>; 1999 def TP : TestRSL<"tp", 0xEBC0>; 2000} 2001 2002//===----------------------------------------------------------------------===// 2003// Access registers 2004//===----------------------------------------------------------------------===// 2005 2006// Read a 32-bit access register into a GR32. As with all GR32 operations, 2007// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 2008// when a 64-bit address is stored in a pair of access registers. 2009def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 2010 2011// Set access register. 2012def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 2013 2014// Copy access register. 2015def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2016 2017// Load address extended. 2018defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2019 2020// Load access multiple. 2021defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2022 2023// Store access multiple. 2024defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2025 2026//===----------------------------------------------------------------------===// 2027// Program mask and addressing mode 2028//===----------------------------------------------------------------------===// 2029 2030// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2031let Uses = [CC] in 2032 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2033 2034// Set CC and program mask from a register. 2035let hasSideEffects = 1, Defs = [CC] in 2036 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2037 2038// Branch and link - like BAS, but also extracts CC and program mask. 2039let isCall = 1, Uses = [CC], Defs = [CC] in { 2040 def BAL : CallRX<"bal", 0x45>; 2041 def BALR : CallRR<"balr", 0x05>; 2042} 2043 2044// Test addressing mode. 2045let Defs = [CC] in 2046 def TAM : SideEffectInherentE<"tam", 0x010B>; 2047 2048// Set addressing mode. 2049let hasSideEffects = 1 in { 2050 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2051 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2052 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2053} 2054 2055// Branch and set mode. Not really a call, but also sets an output register. 2056let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2057 def BSM : CallRR<"bsm", 0x0B>; 2058 2059// Branch and save and set mode. 2060let isCall = 1, Defs = [CC] in 2061 def BASSM : CallRR<"bassm", 0x0C>; 2062 2063//===----------------------------------------------------------------------===// 2064// Transactional execution 2065//===----------------------------------------------------------------------===// 2066 2067let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2068 // Transaction Begin 2069 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2070 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2071 let hasNoSchedulingInfo = 1 in 2072 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2073 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2074 int_s390_tbeginc, imm32zx16>; 2075 } 2076 2077 // Transaction End 2078 let Defs = [CC] in 2079 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2080 2081 // Transaction Abort 2082 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2083 hasSideEffects = 1 in 2084 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2085 2086 // Nontransactional Store 2087 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2088 2089 // Extract Transaction Nesting Depth 2090 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2091} 2092 2093//===----------------------------------------------------------------------===// 2094// Processor assist 2095//===----------------------------------------------------------------------===// 2096 2097let Predicates = [FeatureProcessorAssist] in { 2098 let hasSideEffects = 1 in 2099 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2100 def : Pat<(int_s390_ppa_txassist GR32:$src), 2101 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2102 zero_reg, 1)>; 2103} 2104 2105//===----------------------------------------------------------------------===// 2106// Miscellaneous Instructions. 2107//===----------------------------------------------------------------------===// 2108 2109// Find leftmost one, AKA count leading zeros. The instruction actually 2110// returns a pair of GR64s, the first giving the number of leading zeros 2111// and the second giving a copy of the source with the leftmost one bit 2112// cleared. We only use the first result here. 2113let Defs = [CC] in 2114 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2115def : Pat<(i64 (ctlz GR64:$src)), 2116 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2117 2118// Population count. Counts bits set per byte or doubleword. 2119let Predicates = [FeatureMiscellaneousExtensions3] in { 2120 let Defs = [CC] in 2121 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2122 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2123} 2124let Predicates = [FeaturePopulationCount], Defs = [CC] in 2125 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2126 2127// Search a block of memory for a character. 2128let mayLoad = 1, Defs = [CC] in 2129 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2130let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2131 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2132 2133// Compare until substring equal. 2134let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2135 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2136 2137// Compare and form codeword. 2138let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2139 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2140 2141// Update tree. 2142let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2143 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2144 def UPT : SideEffectInherentE<"upt", 0x0102>; 2145 2146// Checksum. 2147let mayLoad = 1, Defs = [CC] in 2148 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2149 2150// Compression call. 2151let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2152 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2153 2154// Sort lists. 2155let Predicates = [FeatureEnhancedSort], 2156 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2157 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2158 2159// Deflate conversion call. 2160let Predicates = [FeatureDeflateConversion], 2161 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2162 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2163 GR128, GR128, GR64>; 2164 2165// Execute. 2166let hasSideEffects = 1 in { 2167 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2168 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2169} 2170 2171//===----------------------------------------------------------------------===// 2172// .insn directive instructions 2173//===----------------------------------------------------------------------===// 2174 2175let isCodeGenOnly = 1, hasSideEffects = 1 in { 2176 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2177 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2178 imm32sx16:$I2), 2179 ".insn ri,$enc,$R1,$I2", []>; 2180 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2181 AnyReg:$R3, brtarget16:$I2), 2182 ".insn rie,$enc,$R1,$R3,$I2", []>; 2183 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2184 brtarget32:$I2), 2185 ".insn ril,$enc,$R1,$I2", []>; 2186 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2187 uimm32:$I2), 2188 ".insn rilu,$enc,$R1,$I2", []>; 2189 def InsnRIS : DirectiveInsnRIS<(outs), 2190 (ins imm64zx48:$enc, AnyReg:$R1, 2191 imm32sx8:$I2, imm32zx4:$M3, 2192 bdaddr12only:$BD4), 2193 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2194 def InsnRR : DirectiveInsnRR<(outs), 2195 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2196 ".insn rr,$enc,$R1,$R2", []>; 2197 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2198 AnyReg:$R1, AnyReg:$R2), 2199 ".insn rre,$enc,$R1,$R2", []>; 2200 def InsnRRF : DirectiveInsnRRF<(outs), 2201 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2202 AnyReg:$R3, imm32zx4:$M4), 2203 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2204 def InsnRRS : DirectiveInsnRRS<(outs), 2205 (ins imm64zx48:$enc, AnyReg:$R1, 2206 AnyReg:$R2, imm32zx4:$M3, 2207 bdaddr12only:$BD4), 2208 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2209 def InsnRS : DirectiveInsnRS<(outs), 2210 (ins imm64zx32:$enc, AnyReg:$R1, 2211 AnyReg:$R3, bdaddr12only:$BD2), 2212 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2213 def InsnRSE : DirectiveInsnRSE<(outs), 2214 (ins imm64zx48:$enc, AnyReg:$R1, 2215 AnyReg:$R3, bdaddr12only:$BD2), 2216 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2217 def InsnRSI : DirectiveInsnRSI<(outs), 2218 (ins imm64zx48:$enc, AnyReg:$R1, 2219 AnyReg:$R3, brtarget16:$RI2), 2220 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2221 def InsnRSY : DirectiveInsnRSY<(outs), 2222 (ins imm64zx48:$enc, AnyReg:$R1, 2223 AnyReg:$R3, bdaddr20only:$BD2), 2224 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2225 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2226 bdxaddr12only:$XBD2), 2227 ".insn rx,$enc,$R1,$XBD2", []>; 2228 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2229 bdxaddr12only:$XBD2), 2230 ".insn rxe,$enc,$R1,$XBD2", []>; 2231 def InsnRXF : DirectiveInsnRXF<(outs), 2232 (ins imm64zx48:$enc, AnyReg:$R1, 2233 AnyReg:$R3, bdxaddr12only:$XBD2), 2234 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2235 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2236 bdxaddr20only:$XBD2), 2237 ".insn rxy,$enc,$R1,$XBD2", []>; 2238 def InsnS : DirectiveInsnS<(outs), 2239 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2240 ".insn s,$enc,$BD2", []>; 2241 def InsnSI : DirectiveInsnSI<(outs), 2242 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2243 imm32sx8:$I2), 2244 ".insn si,$enc,$BD1,$I2", []>; 2245 def InsnSIY : DirectiveInsnSIY<(outs), 2246 (ins imm64zx48:$enc, 2247 bdaddr20only:$BD1, imm32zx8:$I2), 2248 ".insn siy,$enc,$BD1,$I2", []>; 2249 def InsnSIL : DirectiveInsnSIL<(outs), 2250 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2251 imm32zx16:$I2), 2252 ".insn sil,$enc,$BD1,$I2", []>; 2253 def InsnSS : DirectiveInsnSS<(outs), 2254 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2255 bdaddr12only:$BD2, AnyReg:$R3), 2256 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2257 def InsnSSE : DirectiveInsnSSE<(outs), 2258 (ins imm64zx48:$enc, 2259 bdaddr12only:$BD1,bdaddr12only:$BD2), 2260 ".insn sse,$enc,$BD1,$BD2", []>; 2261 def InsnSSF : DirectiveInsnSSF<(outs), 2262 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2263 bdaddr12only:$BD2, AnyReg:$R3), 2264 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2265 def InsnVRI : DirectiveInsnVRI<(outs), 2266 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2267 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2268 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2269 def InsnVRR : DirectiveInsnVRR<(outs), 2270 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2271 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2272 imm32zx4:$M6), 2273 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2274 def InsnVRS : DirectiveInsnVRS<(outs), 2275 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2276 bdaddr12only:$BD2, imm32zx4:$M4), 2277 ".insn vrs,$enc,$BD2,$M4", []>; 2278 def InsnVRV : DirectiveInsnVRV<(outs), 2279 (ins imm64zx48:$enc, VR128:$V1, 2280 bdvaddr12only:$VBD2, imm32zx4:$M3), 2281 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2282 def InsnVRX : DirectiveInsnVRX<(outs), 2283 (ins imm64zx48:$enc, VR128:$V1, 2284 bdxaddr12only:$XBD2, imm32zx4:$M3), 2285 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2286 def InsnVSI : DirectiveInsnVSI<(outs), 2287 (ins imm64zx48:$enc, VR128:$V1, 2288 bdaddr12only:$BD2, imm32zx8:$I3), 2289 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2290} 2291 2292//===----------------------------------------------------------------------===// 2293// Peepholes. 2294//===----------------------------------------------------------------------===// 2295 2296// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2297// equivalent to (and (xor x, -1), y) 2298def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2299 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2300 2301// Shift/rotate instructions only use the last 6 bits of the second operand 2302// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2303// last 16 bits. 2304// Complexity is added so that we match this before we match NILF on the AND 2305// operation alone. 2306let AddedComplexity = 4 in { 2307 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2308 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2309 2310 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2311 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2312 2313 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2314 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2315 2316 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2317 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2318 2319 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2320 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2321 2322 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2323 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2324 2325 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2326 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2327 2328 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2329 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2330} 2331 2332// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2333// use the last 6 bits of the second operand register (making it modulo 64). 2334let AddedComplexity = 4 in { 2335 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2336 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2337 2338 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2339 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2340 2341 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2342 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2343 2344 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2345 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2346} 2347 2348// Peepholes for turning scalar operations into block operations. 2349defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2350 XCSequence, 1>; 2351defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2352 XCSequence, 2>; 2353defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2354 XCSequence, 4>; 2355defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2356 OCSequence, XCSequence, 1>; 2357defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2358 XCSequence, 2>; 2359defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2360 XCSequence, 4>; 2361defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2362 XCSequence, 8>; 2363 2364//===----------------------------------------------------------------------===// 2365// Mnemonic Aliases 2366//===----------------------------------------------------------------------===// 2367 2368def JCT : MnemonicAlias<"jct", "brct">; 2369def JCTG : MnemonicAlias<"jctg", "brctg">; 2370def JAS : MnemonicAlias<"jas", "bras">; 2371def JASL : MnemonicAlias<"jasl", "brasl">; 2372def JXH : MnemonicAlias<"jxh", "brxh">; 2373def JXLE : MnemonicAlias<"jxle", "brxle">; 2374def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2375def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2376 2377def BRU : MnemonicAlias<"bru", "j">; 2378def BRUL : MnemonicAlias<"brul", "jg">; 2379 2380foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2381 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2382 def BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2383 def BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#">; 2384} 2385