1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Stack allocation 11//===----------------------------------------------------------------------===// 12 13// The callseq_start node requires the hasSideEffects flag, even though these 14// instructions are noops on SystemZ. 15let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 16 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_start timm:$amt1, timm:$amt2)]>; 18 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 19 [(callseq_end timm:$amt1, timm:$amt2)]>; 20} 21 22// Takes as input the value of the stack pointer after a dynamic allocation 23// has been made. Sets the output to the address of the dynamically- 24// allocated area itself, skipping the outgoing arguments. 25// 26// This expands to an LA or LAY instruction. We restrict the offset 27// to the range of LA and keep the LAY range in reserve for when 28// the size of the outgoing arguments is added. 29def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31 32let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 33 usesCustomInserter = 1 in 34 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 35 (ins GR64:$oldSP, GR64:$space), 36 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 37 38let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 39 hasSideEffects = 1 in 40 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 41 42//===----------------------------------------------------------------------===// 43// Branch instructions 44//===----------------------------------------------------------------------===// 45 46// Conditional branches. 47let isBranch = 1, isTerminator = 1, Uses = [CC] in { 48 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 49 // with the condition-code mask being the first operand. It seems friendlier 50 // to use mnemonic forms like JE and JLH when writing out the assembly though. 51 let isCodeGenOnly = 1 in { 52 // An assembler extended mnemonic for BRC. 53 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 54 // An assembler extended mnemonic for BRCL. (The extension is "G" 55 // rather than "L" because "JL" is "Jump if Less".) 56 def BRCL : CondBranchRIL<"jg#", 0xC04>; 57 let isIndirectBranch = 1 in { 58 def BC : CondBranchRX<"b#", 0x47>; 59 def BCR : CondBranchRR<"b#r", 0x07>; 60 def BIC : CondBranchRXY<"bi#", 0xe347>, 61 Requires<[FeatureMiscellaneousExtensions2]>; 62 } 63 } 64 65 // Allow using the raw forms directly from the assembler (and occasional 66 // special code generation needs) as well. 67 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 68 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 69 let isIndirectBranch = 1 in { 70 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 71 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 72 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 73 Requires<[FeatureMiscellaneousExtensions2]>; 74 } 75 76 // Define AsmParser extended mnemonics for each general condition-code mask 77 // (integer or floating-point) 78 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 79 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 80 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 81 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 82 let isIndirectBranch = 1 in { 83 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 84 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 85 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 86 Requires<[FeatureMiscellaneousExtensions2]>; 87 } 88 } 89} 90 91// Unconditional branches. These are in fact simply variants of the 92// conditional branches with the condition mask set to "always". 93let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 94 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 95 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 96 let isIndirectBranch = 1 in { 97 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 98 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 99 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 100 Requires<[FeatureMiscellaneousExtensions2]>; 101 } 102} 103 104// NOPs. These are again variants of the conditional branches, with the 105// condition mask set to "never". NOP_bare can't be an InstAlias since it 106// would need R0D hard coded which is not part of ADDR64BitRegClass. 107def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 108let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 109 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 110def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 111def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 112 113// Fused compare-and-branch instructions. 114// 115// These instructions do not use or clobber the condition codes. 116// We nevertheless pretend that the relative compare-and-branch 117// instructions clobber CC, so that we can lower them to separate 118// comparisons and BRCLs if the branch ends up being out of range. 119let isBranch = 1, isTerminator = 1 in { 120 // As for normal branches, we handle these instructions internally in 121 // their raw CRJ-like form, but use assembly macros like CRJE when writing 122 // them out. Using the *Pair multiclasses, we also create the raw forms. 123 let Defs = [CC] in { 124 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 125 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 126 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 127 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 128 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 129 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 130 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 131 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 132 } 133 let isIndirectBranch = 1 in { 134 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 135 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 136 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 137 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 138 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 139 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 140 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 141 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 142 } 143 144 // Define AsmParser mnemonics for each integer condition-code mask. 145 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 146 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 147 let Defs = [CC] in { 148 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 149 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 150 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 151 imm32sx8>; 152 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 153 imm64sx8>; 154 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 155 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 156 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 157 imm32zx8>; 158 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 159 imm64zx8>; 160 } 161 let isIndirectBranch = 1 in { 162 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 163 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 164 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 165 imm32sx8>; 166 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 167 imm64sx8>; 168 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 169 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 170 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 171 imm32zx8>; 172 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 173 imm64zx8>; 174 } 175 } 176} 177 178// Decrement a register and branch if it is nonzero. These don't clobber CC, 179// but we might need to split long relative branches into sequences that do. 180let isBranch = 1, isTerminator = 1 in { 181 let Defs = [CC] in { 182 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 183 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 184 } 185 // This doesn't need to clobber CC since we never need to split it. 186 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 187 Requires<[FeatureHighWord]>; 188 189 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 190 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 191 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 192 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 193} 194 195let isBranch = 1, isTerminator = 1 in { 196 let Defs = [CC] in { 197 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 198 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 199 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 200 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 201 } 202 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 203 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 204 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 205 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 206} 207 208//===----------------------------------------------------------------------===// 209// Trap instructions 210//===----------------------------------------------------------------------===// 211 212// Unconditional trap. 213let hasCtrlDep = 1, hasSideEffects = 1 in 214 def Trap : Alias<4, (outs), (ins), [(trap)]>; 215 216// Conditional trap. 217let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 218 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 219 220// Fused compare-and-trap instructions. 221let hasCtrlDep = 1, hasSideEffects = 1 in { 222 // These patterns work the same way as for compare-and-branch. 223 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 224 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 225 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 226 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 227 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 228 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 229 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 230 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 231 let Predicates = [FeatureMiscellaneousExtensions] in { 232 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 233 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 234 } 235 236 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 237 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 238 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 239 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 240 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 241 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 242 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 243 imm32sx16>; 244 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 245 imm64sx16>; 246 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 247 imm32zx16>; 248 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 249 imm64zx16>; 250 let Predicates = [FeatureMiscellaneousExtensions] in { 251 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 252 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 253 } 254 } 255} 256 257//===----------------------------------------------------------------------===// 258// Call and return instructions 259//===----------------------------------------------------------------------===// 260 261// Define the general form of the call instructions for the asm parser. 262// These instructions don't hard-code %r14 as the return address register. 263let isCall = 1, Defs = [CC] in { 264 def BRAS : CallRI <"bras", 0xA75>; 265 def BRASL : CallRIL<"brasl", 0xC05>; 266 def BAS : CallRX <"bas", 0x4D>; 267 def BASR : CallRR <"basr", 0x0D>; 268} 269 270// Regular calls. 271let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 272 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 273 [(z_call pcrel32:$I2)]>; 274 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 275 [(z_call ADDR64:$R2)]>; 276} 277 278// TLS calls. These will be lowered into a call to __tls_get_offset, 279// with an extra relocation specifying the TLS symbol. 280let isCall = 1, Defs = [R14D, CC] in { 281 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 282 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 283 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 284 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 285} 286 287// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 288// are argument registers and since branching to R0 is a no-op. 289let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 290 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 291 [(z_sibcall pcrel32:$I2)]>; 292 let Uses = [R1D] in 293 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 294} 295 296// Conditional sibling calls. 297let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 298 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 299 pcrel32:$I2), []>; 300 let Uses = [R1D] in 301 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 302} 303 304// Fused compare and conditional sibling calls. 305let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 306 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 307 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 308 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 309 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 310 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 311 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 312 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 313 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 314} 315 316// A return instruction (br %r14). 317let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 318 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 319 320// A conditional return instruction (bcr <cond>, %r14). 321let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 322 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 323 324// Fused compare and conditional returns. 325let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 326 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 327 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 328 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 329 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 330 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 331 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 332 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 333 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 334} 335 336//===----------------------------------------------------------------------===// 337// Select instructions 338//===----------------------------------------------------------------------===// 339 340def Select32 : SelectWrapper<i32, GR32>, 341 Requires<[FeatureNoLoadStoreOnCond]>; 342def Select64 : SelectWrapper<i64, GR64>, 343 Requires<[FeatureNoLoadStoreOnCond]>; 344 345// We don't define 32-bit Mux stores if we don't have STOCFH, because the 346// low-only STOC should then always be used if possible. 347defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 348 nonvolatile_anyextloadi8, bdxaddr20only>, 349 Requires<[FeatureHighWord]>; 350defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 351 nonvolatile_anyextloadi16, bdxaddr20only>, 352 Requires<[FeatureHighWord]>; 353defm CondStore32Mux : CondStores<GRX32, simple_store, 354 simple_load, bdxaddr20only>, 355 Requires<[FeatureLoadStoreOnCond2]>; 356defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 357 nonvolatile_anyextloadi8, bdxaddr20only>; 358defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 359 nonvolatile_anyextloadi16, bdxaddr20only>; 360defm CondStore32 : CondStores<GR32, simple_store, 361 simple_load, bdxaddr20only>; 362 363defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 364 nonvolatile_anyextloadi8, bdxaddr20only>; 365defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 366 nonvolatile_anyextloadi16, bdxaddr20only>; 367defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 368 nonvolatile_anyextloadi32, bdxaddr20only>; 369defm CondStore64 : CondStores<GR64, simple_store, 370 simple_load, bdxaddr20only>; 371 372//===----------------------------------------------------------------------===// 373// Move instructions 374//===----------------------------------------------------------------------===// 375 376// Register moves. 377def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 378def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 379 380let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 381 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 382 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 383} 384 385let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 386 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 387 388// Immediate moves. 389let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 390 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 391 // deopending on the choice of register. 392 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 393 Requires<[FeatureHighWord]>; 394 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 395 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 396 397 // Other 16-bit immediates. 398 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 399 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 400 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 401 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 402 403 // 32-bit immediates. 404 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 405 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 406 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 407} 408 409// Register loads. 410let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 411 // Expands to L, LY or LFH, depending on the choice of register. 412 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 413 Requires<[FeatureHighWord]>; 414 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 415 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 416 Requires<[FeatureHighWord]>; 417 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 418 419 // These instructions are split after register allocation, so we don't 420 // want a custom inserter. 421 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 422 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 423 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 424 } 425} 426let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 427 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 428 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 429} 430 431let canFoldAsLoad = 1 in { 432 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 433 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 434} 435 436// Load and zero rightmost byte. 437let Predicates = [FeatureLoadAndZeroRightmostByte] in { 438 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 439 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 440 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 441 (LZRF bdxaddr20only:$src)>; 442 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 443 (LZRG bdxaddr20only:$src)>; 444} 445 446// Load and trap. 447let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 448 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 449 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 450 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 451} 452 453// Register stores. 454let SimpleBDXStore = 1, mayStore = 1 in { 455 // Expands to ST, STY or STFH, depending on the choice of register. 456 def STMux : StoreRXYPseudo<store, GRX32, 4>, 457 Requires<[FeatureHighWord]>; 458 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 459 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 460 Requires<[FeatureHighWord]>; 461 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 462 463 // These instructions are split after register allocation, so we don't 464 // want a custom inserter. 465 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 466 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 467 [(store GR128:$src, bdxaddr20only128:$dst)]>; 468 } 469} 470def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 471def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 472 473// 8-bit immediate stores to 8-bit fields. 474defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 475 476// 16-bit immediate stores to 16-, 32- or 64-bit fields. 477def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 478def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 479def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 480 481// Memory-to-memory moves. 482let mayLoad = 1, mayStore = 1 in 483 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 484let mayLoad = 1, mayStore = 1, Defs = [CC] in { 485 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 486 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 487 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 488} 489 490// Move right. 491let Predicates = [FeatureMiscellaneousExtensions3], 492 mayLoad = 1, mayStore = 1, Uses = [R0L] in 493 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 494 495// String moves. 496let mayLoad = 1, mayStore = 1, Defs = [CC] in 497 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 498 499//===----------------------------------------------------------------------===// 500// Conditional move instructions 501//===----------------------------------------------------------------------===// 502 503let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 504 // Select. 505 let isCommutable = 1 in { 506 // Expands to SELR or SELFHR or a branch-and-move sequence, 507 // depending on the choice of registers. 508 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 509 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 510 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 511 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 512 } 513 514 // Define AsmParser extended mnemonics for each general condition-code mask. 515 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 516 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 517 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 518 GR32, GR32, GR32>; 519 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 520 GRH32, GRH32, GRH32>; 521 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 522 GR64, GR64, GR64>; 523 } 524} 525 526let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 527 // Load immediate on condition. Matched via DAG pattern and created 528 // by the PeepholeOptimizer via FoldImmediate. 529 530 // Expands to LOCHI or LOCHHI, depending on the choice of register. 531 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 532 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 533 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 534 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 535 536 // Move register on condition. Matched via DAG pattern and 537 // created by early if-conversion. 538 let isCommutable = 1 in { 539 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 540 // depending on the choice of registers. 541 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 542 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 543 } 544 545 // Load on condition. Matched via DAG pattern. 546 // Expands to LOC or LOCFH, depending on the choice of register. 547 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 548 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 549 550 // Store on condition. Expanded from CondStore* pseudos. 551 // Expands to STOC or STOCFH, depending on the choice of register. 552 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 553 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 554 555 // Define AsmParser extended mnemonics for each general condition-code mask. 556 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 557 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 558 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 559 imm32sx16>; 560 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 561 imm64sx16>; 562 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 563 imm32sx16>; 564 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 565 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 566 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 567 } 568} 569 570let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 571 // Move register on condition. Matched via DAG pattern and 572 // created by early if-conversion. 573 let isCommutable = 1 in { 574 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 575 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 576 } 577 578 // Load on condition. Matched via DAG pattern. 579 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 580 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 581 582 // Store on condition. Expanded from CondStore* pseudos. 583 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 584 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 585 586 // Define AsmParser extended mnemonics for each general condition-code mask. 587 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 588 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 589 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 590 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 591 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 592 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 593 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 594 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 595 } 596} 597//===----------------------------------------------------------------------===// 598// Sign extensions 599//===----------------------------------------------------------------------===// 600// 601// Note that putting these before zero extensions mean that we will prefer 602// them for anyextload*. There's not really much to choose between the two 603// either way, but signed-extending loads have a short LH and a long LHY, 604// while zero-extending loads have only the long LLH. 605// 606//===----------------------------------------------------------------------===// 607 608// 32-bit extensions from registers. 609def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 610def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 611 612// 64-bit extensions from registers. 613def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 614def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 615def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 616 617let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 618 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 619 620// Match 32-to-64-bit sign extensions in which the source is already 621// in a 64-bit register. 622def : Pat<(sext_inreg GR64:$src, i32), 623 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 624 625// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 626// depending on the choice of register. 627def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 628 Requires<[FeatureHighWord]>; 629def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 630def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 631 Requires<[FeatureHighWord]>; 632 633// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 634// depending on the choice of register. 635def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 636 Requires<[FeatureHighWord]>; 637defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 638def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 639 Requires<[FeatureHighWord]>; 640def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 641 642// 64-bit extensions from memory. 643def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 644def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 645def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 646def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 647def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 648let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 649 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 650 651//===----------------------------------------------------------------------===// 652// Zero extensions 653//===----------------------------------------------------------------------===// 654 655// 32-bit extensions from registers. 656 657// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 658def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 659 Requires<[FeatureHighWord]>; 660def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 661// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 662def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 663 Requires<[FeatureHighWord]>; 664def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 665 666// 64-bit extensions from registers. 667def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 668def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 669def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 670 671// Match 32-to-64-bit zero extensions in which the source is already 672// in a 64-bit register. 673def : Pat<(and GR64:$src, 0xffffffff), 674 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 675 676// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 677// depending on the choice of register. 678def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 679 Requires<[FeatureHighWord]>; 680def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 681def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 682 Requires<[FeatureHighWord]>; 683 684// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 685// depending on the choice of register. 686def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 687 Requires<[FeatureHighWord]>; 688def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 689def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 690 Requires<[FeatureHighWord]>; 691def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 692 693// 64-bit extensions from memory. 694def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 695def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 696def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 697def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 698def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 699 700// 31-to-64-bit zero extensions. 701def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 702def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 703def : Pat<(and GR64:$src, 0x7fffffff), 704 (LLGTR GR64:$src)>; 705def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 706 (LLGT bdxaddr20only:$src)>; 707 708// Load and zero rightmost byte. 709let Predicates = [FeatureLoadAndZeroRightmostByte] in { 710 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 711 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 712 (LLZRGF bdxaddr20only:$src)>; 713} 714 715// Load and trap. 716let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 717 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 718 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 719} 720 721// Extend GR64s to GR128s. 722let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 723 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 724 725//===----------------------------------------------------------------------===// 726// "Any" extensions 727//===----------------------------------------------------------------------===// 728 729// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 730def : Pat<(i64 (anyext GR32:$src)), 731 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 732 733// Extend GR64s to GR128s. 734let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 735 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 736 737//===----------------------------------------------------------------------===// 738// Truncations 739//===----------------------------------------------------------------------===// 740 741// Truncations of 64-bit registers to 32-bit registers. 742def : Pat<(i32 (trunc GR64:$src)), 743 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 744 745// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 746// STC, STCY or STCH, depending on the choice of register. 747def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 748 Requires<[FeatureHighWord]>; 749defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 750def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 751 Requires<[FeatureHighWord]>; 752 753// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 754// STH, STHY or STHH, depending on the choice of register. 755def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 756 Requires<[FeatureHighWord]>; 757defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 758def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 759 Requires<[FeatureHighWord]>; 760def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 761 762// Truncations of 64-bit registers to memory. 763defm : StoreGR64Pair<STC, STCY, truncstorei8>; 764defm : StoreGR64Pair<STH, STHY, truncstorei16>; 765def : StoreGR64PC<STHRL, aligned_truncstorei16>; 766defm : StoreGR64Pair<ST, STY, truncstorei32>; 767def : StoreGR64PC<STRL, aligned_truncstorei32>; 768 769// Store characters under mask -- not (yet) used for codegen. 770defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 771def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 772 773//===----------------------------------------------------------------------===// 774// Multi-register moves 775//===----------------------------------------------------------------------===// 776 777// Multi-register loads. 778defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 779def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 780def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 781def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 782 783// Multi-register stores. 784defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 785def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 786def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 787 788//===----------------------------------------------------------------------===// 789// Byte swaps 790//===----------------------------------------------------------------------===// 791 792// Byte-swapping register moves. 793def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 794def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 795 796// Byte-swapping loads. 797def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 798def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 799def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 800 801// Byte-swapping stores. 802def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 803def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 804def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 805 806// Byte-swapping memory-to-memory moves. 807let mayLoad = 1, mayStore = 1 in 808 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 809 810//===----------------------------------------------------------------------===// 811// Load address instructions 812//===----------------------------------------------------------------------===// 813 814// Load BDX-style addresses. 815let isAsCheapAsAMove = 1, isReMaterializable = 1 in 816 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 817 818// Load a PC-relative address. There's no version of this instruction 819// with a 16-bit offset, so there's no relaxation. 820let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 821 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 822 823// Load the Global Offset Table address. This will be lowered into a 824// larl $R1, _GLOBAL_OFFSET_TABLE_ 825// instruction. 826def GOT : Alias<6, (outs GR64:$R1), (ins), 827 [(set GR64:$R1, (global_offset_table))]>; 828 829//===----------------------------------------------------------------------===// 830// Absolute and Negation 831//===----------------------------------------------------------------------===// 832 833let Defs = [CC] in { 834 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 835 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 836 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 837 } 838 let CCValues = 0xE, CompareZeroCCMask = 0xE in 839 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 840} 841defm : SXU<abs, LPGFR>; 842 843let Defs = [CC] in { 844 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 845 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 846 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 847 } 848 let CCValues = 0xE, CompareZeroCCMask = 0xE in 849 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 850} 851defm : SXU<z_inegabs, LNGFR>; 852 853let Defs = [CC] in { 854 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 855 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 856 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 857 } 858 let CCValues = 0xE, CompareZeroCCMask = 0xE in 859 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 860} 861defm : SXU<ineg, LCGFR>; 862 863//===----------------------------------------------------------------------===// 864// Insertion 865//===----------------------------------------------------------------------===// 866 867let isCodeGenOnly = 1 in 868 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 869defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 870 871defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 872defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 873 874defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 875defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 876 877// Insert characters under mask -- not (yet) used for codegen. 878let Defs = [CC] in { 879 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 880 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 881} 882 883// Insertions of a 16-bit immediate, leaving other bits unaffected. 884// We don't have or_as_insert equivalents of these operations because 885// OI is available instead. 886// 887// IIxMux expands to II[LH]x, depending on the choice of register. 888def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 889 Requires<[FeatureHighWord]>; 890def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 891 Requires<[FeatureHighWord]>; 892def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 893def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 894def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 895def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 896def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 897def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 898def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 899def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 900 901// ...likewise for 32-bit immediates. For GR32s this is a general 902// full-width move. (We use IILF rather than something like LLILF 903// for 32-bit moves because IILF leaves the upper 32 bits of the 904// GR64 unchanged.) 905let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 906 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 907 Requires<[FeatureHighWord]>; 908 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 909 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 910} 911def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 912def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 913 914// An alternative model of inserthf, with the first operand being 915// a zero-extended value. 916def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 917 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 918 imm64hf32:$imm)>; 919 920//===----------------------------------------------------------------------===// 921// Addition 922//===----------------------------------------------------------------------===// 923 924// Addition producing a signed overflow flag. 925let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 926 // Addition of a register. 927 let isCommutable = 1 in { 928 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 929 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 930 } 931 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 932 933 // Addition to a high register. 934 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 935 Requires<[FeatureHighWord]>; 936 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 937 Requires<[FeatureHighWord]>; 938 939 // Addition of signed 16-bit immediates. 940 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 941 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 942 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 943 944 // Addition of signed 32-bit immediates. 945 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 946 Requires<[FeatureHighWord]>; 947 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 948 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 949 Requires<[FeatureHighWord]>; 950 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 951 952 // Addition of memory. 953 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 954 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 955 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 956 Requires<[FeatureMiscellaneousExtensions2]>; 957 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 958 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 959 960 // Addition to memory. 961 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 962 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 963} 964defm : SXB<z_sadd, GR64, AGFR>; 965 966// Addition producing a carry. 967let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 968 // Addition of a register. 969 let isCommutable = 1 in { 970 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 971 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 972 } 973 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 974 975 // Addition to a high register. 976 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 977 Requires<[FeatureHighWord]>; 978 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 979 Requires<[FeatureHighWord]>; 980 981 // Addition of signed 16-bit immediates. 982 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 983 Requires<[FeatureDistinctOps]>; 984 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 985 Requires<[FeatureDistinctOps]>; 986 987 // Addition of unsigned 32-bit immediates. 988 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 989 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 990 991 // Addition of signed 32-bit immediates. 992 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 993 Requires<[FeatureHighWord]>; 994 995 // Addition of memory. 996 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 997 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 998 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 999 1000 // Addition to memory. 1001 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1002 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1003} 1004defm : ZXB<z_uadd, GR64, ALGFR>; 1005 1006// Addition producing and using a carry. 1007let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1008 // Addition of a register. 1009 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1010 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1011 1012 // Addition of memory. 1013 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1014 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1015} 1016 1017// Addition that does not modify the condition code. 1018def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1019 Requires<[FeatureHighWord]>; 1020 1021 1022//===----------------------------------------------------------------------===// 1023// Subtraction 1024//===----------------------------------------------------------------------===// 1025 1026// Subtraction producing a signed overflow flag. 1027let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1028 CCIfNoSignedWrap = 1 in { 1029 // Subtraction of a register. 1030 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1031 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1032 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1033 1034 // Subtraction from a high register. 1035 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1036 Requires<[FeatureHighWord]>; 1037 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1038 Requires<[FeatureHighWord]>; 1039 1040 // Subtraction of memory. 1041 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1042 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1043 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1044 Requires<[FeatureMiscellaneousExtensions2]>; 1045 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1046 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1047} 1048defm : SXB<z_ssub, GR64, SGFR>; 1049 1050// Subtracting an immediate is the same as adding the negated immediate. 1051let AddedComplexity = 1 in { 1052 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1053 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1054 Requires<[FeatureHighWord]>; 1055 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1056 (AFIMux GR32:$src1, simm32n:$src2)>, 1057 Requires<[FeatureHighWord]>; 1058 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1059 (AHI GR32:$src1, imm32sx16n:$src2)>; 1060 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1061 (AFI GR32:$src1, simm32n:$src2)>; 1062 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1063 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1064 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1065 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1066} 1067 1068// And vice versa in one special case, where we need to load a 1069// constant into a register in any case, but the negated constant 1070// requires fewer instructions to load. 1071def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1072 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1073def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1074 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1075 1076// Subtraction producing a carry. 1077let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1078 // Subtraction of a register. 1079 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1080 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1081 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1082 1083 // Subtraction from a high register. 1084 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1085 Requires<[FeatureHighWord]>; 1086 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1087 Requires<[FeatureHighWord]>; 1088 1089 // Subtraction of unsigned 32-bit immediates. 1090 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1091 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1092 1093 // Subtraction of memory. 1094 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1095 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1096 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1097} 1098defm : ZXB<z_usub, GR64, SLGFR>; 1099 1100// Subtracting an immediate is the same as adding the negated immediate. 1101let AddedComplexity = 1 in { 1102 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1103 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1104 Requires<[FeatureDistinctOps]>; 1105 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1106 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1107 Requires<[FeatureDistinctOps]>; 1108} 1109 1110// And vice versa in one special case (but we prefer addition). 1111def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1112 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1113 1114// Subtraction producing and using a carry. 1115let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1116 // Subtraction of a register. 1117 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1118 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1119 1120 // Subtraction of memory. 1121 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1122 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1123} 1124 1125 1126//===----------------------------------------------------------------------===// 1127// AND 1128//===----------------------------------------------------------------------===// 1129 1130let Defs = [CC] in { 1131 // ANDs of a register. 1132 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1133 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1134 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1135 } 1136 1137 let isConvertibleToThreeAddress = 1 in { 1138 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1139 // The CC result only reflects the 16-bit field, not the full register. 1140 // 1141 // NIxMux expands to NI[LH]x, depending on the choice of register. 1142 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1143 Requires<[FeatureHighWord]>; 1144 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1145 Requires<[FeatureHighWord]>; 1146 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1147 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1148 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1149 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1150 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1151 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1152 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1153 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1154 1155 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1156 // The CC result only reflects the 32-bit field, which means we can 1157 // use it as a zero indicator for i32 operations but not otherwise. 1158 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1159 // Expands to NILF or NIHF, depending on the choice of register. 1160 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1161 Requires<[FeatureHighWord]>; 1162 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1163 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1164 } 1165 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1166 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1167 } 1168 1169 // ANDs of memory. 1170 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1171 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1172 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1173 } 1174 1175 // AND to memory 1176 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1177 1178 // Block AND. 1179 let mayLoad = 1, mayStore = 1 in 1180 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1181} 1182defm : RMWIByte<and, bdaddr12pair, NI>; 1183defm : RMWIByte<and, bdaddr20pair, NIY>; 1184 1185//===----------------------------------------------------------------------===// 1186// OR 1187//===----------------------------------------------------------------------===// 1188 1189let Defs = [CC] in { 1190 // ORs of a register. 1191 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1192 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1193 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1194 } 1195 1196 // ORs of a 16-bit immediate, leaving other bits unaffected. 1197 // The CC result only reflects the 16-bit field, not the full register. 1198 // 1199 // OIxMux expands to OI[LH]x, depending on the choice of register. 1200 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1201 Requires<[FeatureHighWord]>; 1202 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1203 Requires<[FeatureHighWord]>; 1204 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1205 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1206 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1207 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1208 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1209 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1210 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1211 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1212 1213 // ORs of a 32-bit immediate, leaving other bits unaffected. 1214 // The CC result only reflects the 32-bit field, which means we can 1215 // use it as a zero indicator for i32 operations but not otherwise. 1216 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1217 // Expands to OILF or OIHF, depending on the choice of register. 1218 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1219 Requires<[FeatureHighWord]>; 1220 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1221 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1222 } 1223 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1224 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1225 1226 // ORs of memory. 1227 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1228 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1229 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1230 } 1231 1232 // OR to memory 1233 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1234 1235 // Block OR. 1236 let mayLoad = 1, mayStore = 1 in 1237 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1238} 1239defm : RMWIByte<or, bdaddr12pair, OI>; 1240defm : RMWIByte<or, bdaddr20pair, OIY>; 1241 1242//===----------------------------------------------------------------------===// 1243// XOR 1244//===----------------------------------------------------------------------===// 1245 1246let Defs = [CC] in { 1247 // XORs of a register. 1248 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1249 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1250 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1251 } 1252 1253 // XORs of a 32-bit immediate, leaving other bits unaffected. 1254 // The CC result only reflects the 32-bit field, which means we can 1255 // use it as a zero indicator for i32 operations but not otherwise. 1256 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1257 // Expands to XILF or XIHF, depending on the choice of register. 1258 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1259 Requires<[FeatureHighWord]>; 1260 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1261 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1262 } 1263 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1264 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1265 1266 // XORs of memory. 1267 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1268 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1269 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1270 } 1271 1272 // XOR to memory 1273 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1274 1275 // Block XOR. 1276 let mayLoad = 1, mayStore = 1 in 1277 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1278} 1279defm : RMWIByte<xor, bdaddr12pair, XI>; 1280defm : RMWIByte<xor, bdaddr20pair, XIY>; 1281 1282//===----------------------------------------------------------------------===// 1283// Combined logical operations 1284//===----------------------------------------------------------------------===// 1285 1286let Predicates = [FeatureMiscellaneousExtensions3], 1287 Defs = [CC] in { 1288 // AND with complement. 1289 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1290 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1291 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1292 } 1293 1294 // OR with complement. 1295 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1296 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1297 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1298 } 1299 1300 // NAND. 1301 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1302 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1303 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1304 } 1305 1306 // NOR. 1307 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1308 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1309 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1310 } 1311 1312 // NXOR. 1313 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1314 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1315 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1316 } 1317} 1318 1319//===----------------------------------------------------------------------===// 1320// Multiplication 1321//===----------------------------------------------------------------------===// 1322 1323// Multiplication of a register, setting the condition code. We prefer these 1324// over MS(G)R if available, even though we cannot use the condition code, 1325// since they are three-operand instructions. 1326let Predicates = [FeatureMiscellaneousExtensions2], 1327 Defs = [CC], isCommutable = 1 in { 1328 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1329 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1330} 1331 1332// Multiplication of a register. 1333let isCommutable = 1 in { 1334 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1335 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1336} 1337def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1338defm : SXB<mul, GR64, MSGFR>; 1339 1340// Multiplication of a signed 16-bit immediate. 1341def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1342def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1343 1344// Multiplication of a signed 32-bit immediate. 1345def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1346def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1347 1348// Multiplication of memory. 1349defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1350defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1351def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1352 Requires<[FeatureMiscellaneousExtensions2]>; 1353def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1354def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1355 1356// Multiplication of memory, setting the condition code. 1357let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1358 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1359 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1360} 1361 1362// Multiplication of a register, producing two results. 1363def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1364def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1365 Requires<[FeatureMiscellaneousExtensions2]>; 1366def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1367def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1368 1369def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1370 (MGRK GR64:$src1, GR64:$src2)>; 1371def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1372 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1373 1374// Multiplication of memory, producing two results. 1375def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1376def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1377def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1378 Requires<[FeatureMiscellaneousExtensions2]>; 1379def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1380def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1381 1382def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1383 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1384def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1385 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1386 1387//===----------------------------------------------------------------------===// 1388// Division and remainder 1389//===----------------------------------------------------------------------===// 1390 1391let hasSideEffects = 1 in { // Do not speculatively execute. 1392 // Division and remainder, from registers. 1393 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1394 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1395 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1396 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1397 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1398 1399 // Division and remainder, from memory. 1400 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1401 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1402 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1403 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1404 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1405} 1406def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1407 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1408def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1409 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1410def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1411 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1412def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1413 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1414 1415def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1416 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1417 subreg_l32)), GR32:$src2)>; 1418def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1419 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1420 subreg_l32)), bdxaddr20only:$src2)>; 1421def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1422 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1423def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1424 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1425 1426//===----------------------------------------------------------------------===// 1427// Shifts 1428//===----------------------------------------------------------------------===// 1429 1430// Logical shift left. 1431defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1432def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1433def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1434 1435// Arithmetic shift left. 1436let Defs = [CC] in { 1437 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1438 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1439 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1440} 1441 1442// Logical shift right. 1443defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1444def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1445def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1446 1447// Arithmetic shift right. 1448let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1449 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1450 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1451 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1452} 1453 1454// Rotate left. 1455def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1456def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1457 1458// Rotate second operand left and inserted selected bits into first operand. 1459// These can act like 32-bit operands provided that the constant start and 1460// end bits (operands 2 and 3) are in the range [32, 64). 1461let Defs = [CC] in { 1462 let isCodeGenOnly = 1 in 1463 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1464 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1465 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1466} 1467 1468// On zEC12 we have a variant of RISBG that does not set CC. 1469let Predicates = [FeatureMiscellaneousExtensions] in 1470 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1471 1472// Forms of RISBG that only affect one word of the destination register. 1473// They do not set CC. 1474let Predicates = [FeatureHighWord] in { 1475 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1476 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1477 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1478 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1479 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1480 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1481 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1482} 1483 1484// Rotate second operand left and perform a logical operation with selected 1485// bits of the first operand. The CC result only describes the selected bits, 1486// so isn't useful for a full comparison against zero. 1487let Defs = [CC] in { 1488 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1489 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1490 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1491} 1492 1493//===----------------------------------------------------------------------===// 1494// Comparison 1495//===----------------------------------------------------------------------===// 1496 1497// Signed comparisons. We put these before the unsigned comparisons because 1498// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1499// of the unsigned forms do. 1500let Defs = [CC], CCValues = 0xE in { 1501 // Comparison with a register. 1502 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1503 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1504 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1505 1506 // Comparison with a high register. 1507 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1508 Requires<[FeatureHighWord]>; 1509 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1510 Requires<[FeatureHighWord]>; 1511 1512 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1513 // depending on the choice of register. 1514 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1515 Requires<[FeatureHighWord]>; 1516 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1517 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1518 1519 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1520 // depending on the choice of register. 1521 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1522 Requires<[FeatureHighWord]>; 1523 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1524 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1525 Requires<[FeatureHighWord]>; 1526 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1527 1528 // Comparison with memory. 1529 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1530 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1531 Requires<[FeatureHighWord]>; 1532 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1533 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1534 Requires<[FeatureHighWord]>; 1535 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1536 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1537 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1538 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1539 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1540 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1541 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1542 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1543 1544 // Comparison between memory and a signed 16-bit immediate. 1545 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1546 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1547 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1548} 1549defm : SXB<z_scmp, GR64, CGFR>; 1550 1551// Unsigned comparisons. 1552let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1553 // Comparison with a register. 1554 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1555 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1556 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1557 1558 // Comparison with a high register. 1559 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1560 Requires<[FeatureHighWord]>; 1561 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1562 Requires<[FeatureHighWord]>; 1563 1564 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1565 // or CLIH, depending on the choice of register. 1566 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1567 Requires<[FeatureHighWord]>; 1568 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1569 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1570 Requires<[FeatureHighWord]>; 1571 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1572 1573 // Comparison with memory. 1574 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1575 Requires<[FeatureHighWord]>; 1576 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1577 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1578 Requires<[FeatureHighWord]>; 1579 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1580 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1581 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1582 aligned_azextloadi16>; 1583 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1584 aligned_load>; 1585 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1586 aligned_azextloadi16>; 1587 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1588 aligned_azextloadi32>; 1589 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1590 aligned_load>; 1591 1592 // Comparison between memory and an unsigned 8-bit immediate. 1593 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1594 1595 // Comparison between memory and an unsigned 16-bit immediate. 1596 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1597 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1598 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1599} 1600defm : ZXB<z_ucmp, GR64, CLGFR>; 1601 1602// Memory-to-memory comparison. 1603let mayLoad = 1, Defs = [CC] in { 1604 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1605 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1606 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1607 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1608} 1609 1610// String comparison. 1611let mayLoad = 1, Defs = [CC] in 1612 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1613 1614// Test under mask. 1615let Defs = [CC] in { 1616 // TMxMux expands to TM[LH]x, depending on the choice of register. 1617 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1618 Requires<[FeatureHighWord]>; 1619 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1620 Requires<[FeatureHighWord]>; 1621 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1622 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1623 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1624 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1625 1626 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1627 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1628 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1629 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1630 1631 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1632} 1633 1634def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1635def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1636 1637// Compare logical characters under mask -- not (yet) used for codegen. 1638let Defs = [CC] in { 1639 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1640 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1641} 1642 1643//===----------------------------------------------------------------------===// 1644// Prefetch and execution hint 1645//===----------------------------------------------------------------------===// 1646 1647let mayLoad = 1, mayStore = 1 in { 1648 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1649 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1650} 1651 1652let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1653 // Branch Prediction Preload 1654 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1655 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1656 1657 // Next Instruction Access Intent 1658 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1659} 1660 1661//===----------------------------------------------------------------------===// 1662// Atomic operations 1663//===----------------------------------------------------------------------===// 1664 1665// A serialization instruction that acts as a barrier for all memory 1666// accesses, which expands to "bcr 14, 0". 1667let hasSideEffects = 1 in 1668def Serialize : Alias<2, (outs), (ins), []>; 1669 1670// A pseudo instruction that serves as a compiler barrier. 1671let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1672def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1673 1674let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1675 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1676 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1677 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1678 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1679 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1680 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1681 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1682 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1683 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1684 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1685} 1686 1687def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1688def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1689def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1690 1691def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1692def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1693let Predicates = [FeatureNoInterlockedAccess1] in { 1694 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1695 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1696 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1697 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1698 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1699 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1700} 1701 1702def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1703def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1704def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1705 1706def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1707def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1708let Predicates = [FeatureNoInterlockedAccess1] in { 1709 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1710 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1711 imm32ll16c>; 1712 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1713 imm32lh16c>; 1714 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1715 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1716 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1717 imm64ll16c>; 1718 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1719 imm64lh16c>; 1720 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1721 imm64hl16c>; 1722 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1723 imm64hh16c>; 1724 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1725 imm64lf32c>; 1726 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1727 imm64hf32c>; 1728} 1729 1730def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1731def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1732let Predicates = [FeatureNoInterlockedAccess1] in { 1733 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1734 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1735 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1736 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1737 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1738 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1739 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1740 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1741 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1742 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1743 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1744} 1745 1746def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1747def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1748let Predicates = [FeatureNoInterlockedAccess1] in { 1749 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1750 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1751 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1752 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1753 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1754} 1755 1756def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1757def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1758 imm32lh16c>; 1759def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1760def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1761 imm32ll16c>; 1762def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1763 imm32lh16c>; 1764def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1765def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1766def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1767 imm64ll16c>; 1768def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1769 imm64lh16c>; 1770def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1771 imm64hl16c>; 1772def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1773 imm64hh16c>; 1774def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1775 imm64lf32c>; 1776def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1777 imm64hf32c>; 1778 1779def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1780def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1781def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1782 1783def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1784def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1785def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1786 1787def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1788def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1789def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1790 1791def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1792def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1793def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1794 1795def ATOMIC_CMP_SWAPW 1796 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1797 ADDR32:$bitshift, ADDR32:$negbitshift, 1798 uimm32:$bitsize), 1799 [(set GR32:$dst, 1800 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1801 ADDR32:$bitshift, ADDR32:$negbitshift, 1802 uimm32:$bitsize))]> { 1803 let Defs = [CC]; 1804 let mayLoad = 1; 1805 let mayStore = 1; 1806 let usesCustomInserter = 1; 1807 let hasNoSchedulingInfo = 1; 1808} 1809 1810// Test and set. 1811let mayLoad = 1, Defs = [CC] in 1812 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1813 1814// Compare and swap. 1815let Defs = [CC] in { 1816 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1817 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1818} 1819 1820// Compare double and swap. 1821let Defs = [CC] in { 1822 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1823 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1824} 1825 1826// Compare and swap and store. 1827let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1828 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1829 1830// Perform locked operation. 1831let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1832 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1833 1834// Load/store pair from/to quadword. 1835def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1836def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1837 1838// Load pair disjoint. 1839let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1840 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1841 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1842} 1843 1844//===----------------------------------------------------------------------===// 1845// Translate and convert 1846//===----------------------------------------------------------------------===// 1847 1848let mayLoad = 1, mayStore = 1 in 1849 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1850 1851let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1852 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1853 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1854} 1855 1856let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1857 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1858 1859let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1860 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1861 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1862} 1863 1864let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1865 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1866 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1867 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1868 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1869} 1870 1871let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1872 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1873 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1874 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1875 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1876 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1877 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1878 1879 let isAsmParserOnly = 1 in { 1880 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1881 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1882 } 1883} 1884 1885//===----------------------------------------------------------------------===// 1886// Message-security assist 1887//===----------------------------------------------------------------------===// 1888 1889let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1890 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1891 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1892 1893 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1894 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1895 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1896 1897 let Predicates = [FeatureMessageSecurityAssist4] in { 1898 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1899 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1900 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1901 GR128, GR128, GR128>; 1902 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1903 } 1904 1905 let Predicates = [FeatureMessageSecurityAssist5] in 1906 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1907 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1908 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1909 1910 let Predicates = [FeatureMessageSecurityAssist8] in 1911 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1912 GR128, GR128, GR128>; 1913 1914 let Predicates = [FeatureMessageSecurityAssist9] in 1915 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1916} 1917 1918//===----------------------------------------------------------------------===// 1919// Guarded storage 1920//===----------------------------------------------------------------------===// 1921 1922// These instructions use and/or modify the guarded storage control 1923// registers, which we do not otherwise model, so they should have 1924// hasSideEffects. 1925let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1926 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1927 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1928 1929 let mayLoad = 1 in 1930 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1931 let mayStore = 1 in 1932 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1933} 1934 1935//===----------------------------------------------------------------------===// 1936// Decimal arithmetic 1937//===----------------------------------------------------------------------===// 1938 1939defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1940def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1941 1942defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1943def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1944 1945let mayLoad = 1, mayStore = 1 in { 1946 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1947 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1948 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1949 1950 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1951 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1952 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1953 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1954 let Defs = [CC] in { 1955 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1956 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1957 } 1958} 1959 1960let mayLoad = 1, mayStore = 1 in { 1961 let Defs = [CC] in { 1962 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1963 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1964 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1965 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1966 } 1967 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1968 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1969 let Defs = [CC] in { 1970 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1971 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1972 } 1973} 1974 1975let Defs = [CC] in { 1976 def CP : CompareSSb<"cp", 0xF9>; 1977 def TP : TestRSL<"tp", 0xEBC0>; 1978} 1979 1980//===----------------------------------------------------------------------===// 1981// Access registers 1982//===----------------------------------------------------------------------===// 1983 1984// Read a 32-bit access register into a GR32. As with all GR32 operations, 1985// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1986// when a 64-bit address is stored in a pair of access registers. 1987def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1988 1989// Set access register. 1990def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1991 1992// Copy access register. 1993def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1994 1995// Load address extended. 1996defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1997 1998// Load access multiple. 1999defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2000 2001// Store access multiple. 2002defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2003 2004//===----------------------------------------------------------------------===// 2005// Program mask and addressing mode 2006//===----------------------------------------------------------------------===// 2007 2008// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2009let Uses = [CC] in 2010 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2011 2012// Set CC and program mask from a register. 2013let hasSideEffects = 1, Defs = [CC] in 2014 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2015 2016// Branch and link - like BAS, but also extracts CC and program mask. 2017let isCall = 1, Uses = [CC], Defs = [CC] in { 2018 def BAL : CallRX<"bal", 0x45>; 2019 def BALR : CallRR<"balr", 0x05>; 2020} 2021 2022// Test addressing mode. 2023let Defs = [CC] in 2024 def TAM : SideEffectInherentE<"tam", 0x010B>; 2025 2026// Set addressing mode. 2027let hasSideEffects = 1 in { 2028 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2029 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2030 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2031} 2032 2033// Branch and set mode. Not really a call, but also sets an output register. 2034let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2035 def BSM : CallRR<"bsm", 0x0B>; 2036 2037// Branch and save and set mode. 2038let isCall = 1, Defs = [CC] in 2039 def BASSM : CallRR<"bassm", 0x0C>; 2040 2041//===----------------------------------------------------------------------===// 2042// Transactional execution 2043//===----------------------------------------------------------------------===// 2044 2045let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2046 // Transaction Begin 2047 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2048 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2049 let hasNoSchedulingInfo = 1 in 2050 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2051 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2052 int_s390_tbeginc, imm32zx16>; 2053 } 2054 2055 // Transaction End 2056 let Defs = [CC] in 2057 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2058 2059 // Transaction Abort 2060 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2061 hasSideEffects = 1 in 2062 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2063 2064 // Nontransactional Store 2065 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2066 2067 // Extract Transaction Nesting Depth 2068 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2069} 2070 2071//===----------------------------------------------------------------------===// 2072// Processor assist 2073//===----------------------------------------------------------------------===// 2074 2075let Predicates = [FeatureProcessorAssist] in { 2076 let hasSideEffects = 1 in 2077 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2078 def : Pat<(int_s390_ppa_txassist GR32:$src), 2079 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2080 zero_reg, 1)>; 2081} 2082 2083//===----------------------------------------------------------------------===// 2084// Miscellaneous Instructions. 2085//===----------------------------------------------------------------------===// 2086 2087// Find leftmost one, AKA count leading zeros. The instruction actually 2088// returns a pair of GR64s, the first giving the number of leading zeros 2089// and the second giving a copy of the source with the leftmost one bit 2090// cleared. We only use the first result here. 2091let Defs = [CC] in 2092 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2093def : Pat<(i64 (ctlz GR64:$src)), 2094 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2095 2096// Population count. Counts bits set per byte or doubleword. 2097let Predicates = [FeatureMiscellaneousExtensions3] in { 2098 let Defs = [CC] in 2099 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2100 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2101} 2102let Predicates = [FeaturePopulationCount], Defs = [CC] in 2103 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2104 2105// Search a block of memory for a character. 2106let mayLoad = 1, Defs = [CC] in 2107 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2108let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2109 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2110 2111// Compare until substring equal. 2112let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2113 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2114 2115// Compare and form codeword. 2116let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2117 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2118 2119// Update tree. 2120let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2121 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2122 def UPT : SideEffectInherentE<"upt", 0x0102>; 2123 2124// Checksum. 2125let mayLoad = 1, Defs = [CC] in 2126 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2127 2128// Compression call. 2129let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2130 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2131 2132// Sort lists. 2133let Predicates = [FeatureEnhancedSort], 2134 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2135 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2136 2137// Deflate conversion call. 2138let Predicates = [FeatureDeflateConversion], 2139 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2140 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2141 GR128, GR128, GR64>; 2142 2143// Execute. 2144let hasSideEffects = 1 in { 2145 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2146 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2147} 2148 2149//===----------------------------------------------------------------------===// 2150// .insn directive instructions 2151//===----------------------------------------------------------------------===// 2152 2153let isCodeGenOnly = 1, hasSideEffects = 1 in { 2154 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2155 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2156 imm32sx16:$I2), 2157 ".insn ri,$enc,$R1,$I2", []>; 2158 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2159 AnyReg:$R3, brtarget16:$I2), 2160 ".insn rie,$enc,$R1,$R3,$I2", []>; 2161 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2162 brtarget32:$I2), 2163 ".insn ril,$enc,$R1,$I2", []>; 2164 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2165 uimm32:$I2), 2166 ".insn rilu,$enc,$R1,$I2", []>; 2167 def InsnRIS : DirectiveInsnRIS<(outs), 2168 (ins imm64zx48:$enc, AnyReg:$R1, 2169 imm32sx8:$I2, imm32zx4:$M3, 2170 bdaddr12only:$BD4), 2171 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2172 def InsnRR : DirectiveInsnRR<(outs), 2173 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2174 ".insn rr,$enc,$R1,$R2", []>; 2175 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2176 AnyReg:$R1, AnyReg:$R2), 2177 ".insn rre,$enc,$R1,$R2", []>; 2178 def InsnRRF : DirectiveInsnRRF<(outs), 2179 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2180 AnyReg:$R3, imm32zx4:$M4), 2181 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2182 def InsnRRS : DirectiveInsnRRS<(outs), 2183 (ins imm64zx48:$enc, AnyReg:$R1, 2184 AnyReg:$R2, imm32zx4:$M3, 2185 bdaddr12only:$BD4), 2186 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2187 def InsnRS : DirectiveInsnRS<(outs), 2188 (ins imm64zx32:$enc, AnyReg:$R1, 2189 AnyReg:$R3, bdaddr12only:$BD2), 2190 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2191 def InsnRSE : DirectiveInsnRSE<(outs), 2192 (ins imm64zx48:$enc, AnyReg:$R1, 2193 AnyReg:$R3, bdaddr12only:$BD2), 2194 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2195 def InsnRSI : DirectiveInsnRSI<(outs), 2196 (ins imm64zx48:$enc, AnyReg:$R1, 2197 AnyReg:$R3, brtarget16:$RI2), 2198 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2199 def InsnRSY : DirectiveInsnRSY<(outs), 2200 (ins imm64zx48:$enc, AnyReg:$R1, 2201 AnyReg:$R3, bdaddr20only:$BD2), 2202 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2203 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2204 bdxaddr12only:$XBD2), 2205 ".insn rx,$enc,$R1,$XBD2", []>; 2206 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2207 bdxaddr12only:$XBD2), 2208 ".insn rxe,$enc,$R1,$XBD2", []>; 2209 def InsnRXF : DirectiveInsnRXF<(outs), 2210 (ins imm64zx48:$enc, AnyReg:$R1, 2211 AnyReg:$R3, bdxaddr12only:$XBD2), 2212 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2213 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2214 bdxaddr20only:$XBD2), 2215 ".insn rxy,$enc,$R1,$XBD2", []>; 2216 def InsnS : DirectiveInsnS<(outs), 2217 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2218 ".insn s,$enc,$BD2", []>; 2219 def InsnSI : DirectiveInsnSI<(outs), 2220 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2221 imm32sx8:$I2), 2222 ".insn si,$enc,$BD1,$I2", []>; 2223 def InsnSIY : DirectiveInsnSIY<(outs), 2224 (ins imm64zx48:$enc, 2225 bdaddr20only:$BD1, imm32zx8:$I2), 2226 ".insn siy,$enc,$BD1,$I2", []>; 2227 def InsnSIL : DirectiveInsnSIL<(outs), 2228 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2229 imm32zx16:$I2), 2230 ".insn sil,$enc,$BD1,$I2", []>; 2231 def InsnSS : DirectiveInsnSS<(outs), 2232 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2233 bdaddr12only:$BD2, AnyReg:$R3), 2234 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2235 def InsnSSE : DirectiveInsnSSE<(outs), 2236 (ins imm64zx48:$enc, 2237 bdaddr12only:$BD1,bdaddr12only:$BD2), 2238 ".insn sse,$enc,$BD1,$BD2", []>; 2239 def InsnSSF : DirectiveInsnSSF<(outs), 2240 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2241 bdaddr12only:$BD2, AnyReg:$R3), 2242 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2243 def InsnVRI : DirectiveInsnVRI<(outs), 2244 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2245 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2246 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2247 def InsnVRR : DirectiveInsnVRR<(outs), 2248 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2249 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2250 imm32zx4:$M6), 2251 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2252 def InsnVRS : DirectiveInsnVRS<(outs), 2253 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2254 bdaddr12only:$BD2, imm32zx4:$M4), 2255 ".insn vrs,$enc,$BD2,$M4", []>; 2256 def InsnVRV : DirectiveInsnVRV<(outs), 2257 (ins imm64zx48:$enc, VR128:$V1, 2258 bdvaddr12only:$VBD2, imm32zx4:$M3), 2259 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2260 def InsnVRX : DirectiveInsnVRX<(outs), 2261 (ins imm64zx48:$enc, VR128:$V1, 2262 bdxaddr12only:$XBD2, imm32zx4:$M3), 2263 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2264 def InsnVSI : DirectiveInsnVSI<(outs), 2265 (ins imm64zx48:$enc, VR128:$V1, 2266 bdaddr12only:$BD2, imm32zx8:$I3), 2267 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2268} 2269 2270//===----------------------------------------------------------------------===// 2271// Peepholes. 2272//===----------------------------------------------------------------------===// 2273 2274// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2275// equivalent to (and (xor x, -1), y) 2276def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2277 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2278 2279// Shift/rotate instructions only use the last 6 bits of the second operand 2280// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2281// last 16 bits. 2282// Complexity is added so that we match this before we match NILF on the AND 2283// operation alone. 2284let AddedComplexity = 4 in { 2285 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2286 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2287 2288 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2289 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2290 2291 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2292 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2293 2294 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2295 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2296 2297 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2298 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2299 2300 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2301 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2302 2303 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2304 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2305 2306 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2307 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2308} 2309 2310// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2311// use the last 6 bits of the second operand register (making it modulo 64). 2312let AddedComplexity = 4 in { 2313 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2314 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2315 2316 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2317 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2318 2319 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2320 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2321 2322 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2323 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2324} 2325 2326// Peepholes for turning scalar operations into block operations. 2327defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2328 XCSequence, 1>; 2329defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2330 XCSequence, 2>; 2331defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2332 XCSequence, 4>; 2333defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2334 OCSequence, XCSequence, 1>; 2335defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2336 XCSequence, 2>; 2337defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2338 XCSequence, 4>; 2339defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2340 XCSequence, 8>; 2341