1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Stack allocation 12//===----------------------------------------------------------------------===// 13 14let hasNoSchedulingInfo = 1 in { 15 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt), 16 [(callseq_start timm:$amt)]>; 17 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 18 [(callseq_end timm:$amt1, timm:$amt2)]>; 19} 20 21let hasSideEffects = 0 in { 22 // Takes as input the value of the stack pointer after a dynamic allocation 23 // has been made. Sets the output to the address of the dynamically- 24 // allocated area itself, skipping the outgoing arguments. 25 // 26 // This expands to an LA or LAY instruction. We restrict the offset 27 // to the range of LA and keep the LAY range in reserve for when 28 // the size of the outgoing arguments is added. 29 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31} 32 33//===----------------------------------------------------------------------===// 34// Branch instructions 35//===----------------------------------------------------------------------===// 36 37// Conditional branches. 38let isBranch = 1, isTerminator = 1, Uses = [CC] in { 39 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 40 // with the condition-code mask being the first operand. It seems friendlier 41 // to use mnemonic forms like JE and JLH when writing out the assembly though. 42 let isCodeGenOnly = 1 in { 43 // An assembler extended mnemonic for BRC. 44 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 45 // An assembler extended mnemonic for BRCL. (The extension is "G" 46 // rather than "L" because "JL" is "Jump if Less".) 47 def BRCL : CondBranchRIL<"jg#", 0xC04>; 48 let isIndirectBranch = 1 in { 49 def BC : CondBranchRX<"b#", 0x47>; 50 def BCR : CondBranchRR<"b#r", 0x07>; 51 } 52 } 53 54 // Allow using the raw forms directly from the assembler (and occasional 55 // special code generation needs) as well. 56 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 57 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 58 let isIndirectBranch = 1 in { 59 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 60 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 61 } 62 63 // Define AsmParser extended mnemonics for each general condition-code mask 64 // (integer or floating-point) 65 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 66 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 67 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 68 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 69 let isIndirectBranch = 1 in { 70 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 71 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 72 } 73 } 74} 75 76// Unconditional branches. These are in fact simply variants of the 77// conditional branches with the condition mask set to "always". 78let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 79 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 80 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 81 let isIndirectBranch = 1 in { 82 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 83 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 84 } 85} 86 87// NOPs. These are again variants of the conditional branches, 88// with the condition mask set to "never". 89def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 90def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 91 92// Fused compare-and-branch instructions. 93// 94// These instructions do not use or clobber the condition codes. 95// We nevertheless pretend that the relative compare-and-branch 96// instructions clobber CC, so that we can lower them to separate 97// comparisons and BRCLs if the branch ends up being out of range. 98let isBranch = 1, isTerminator = 1 in { 99 // As for normal branches, we handle these instructions internally in 100 // their raw CRJ-like form, but use assembly macros like CRJE when writing 101 // them out. Using the *Pair multiclasses, we also create the raw forms. 102 let Defs = [CC] in { 103 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 104 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 105 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 106 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 107 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 108 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 109 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 110 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 111 } 112 let isIndirectBranch = 1 in { 113 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 114 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 115 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 116 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 117 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 118 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 119 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 120 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 121 } 122 123 // Define AsmParser mnemonics for each integer condition-code mask. 124 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 125 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 126 let Defs = [CC] in { 127 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 128 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 129 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 130 imm32sx8>; 131 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 132 imm64sx8>; 133 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 134 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 135 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 136 imm32zx8>; 137 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 138 imm64zx8>; 139 } 140 let isIndirectBranch = 1 in { 141 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 142 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 143 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 144 imm32sx8>; 145 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 146 imm64sx8>; 147 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 148 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 149 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 150 imm32zx8>; 151 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 152 imm64zx8>; 153 } 154 } 155} 156 157// Decrement a register and branch if it is nonzero. These don't clobber CC, 158// but we might need to split long relative branches into sequences that do. 159let isBranch = 1, isTerminator = 1 in { 160 let Defs = [CC] in { 161 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 162 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 163 } 164 // This doesn't need to clobber CC since we never need to split it. 165 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 166 Requires<[FeatureHighWord]>; 167 168 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 169 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 170 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 171 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 172} 173 174let isBranch = 1, isTerminator = 1 in { 175 let Defs = [CC] in { 176 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 177 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 178 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 179 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 180 } 181 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 182 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 183 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 184 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 185} 186 187//===----------------------------------------------------------------------===// 188// Trap instructions 189//===----------------------------------------------------------------------===// 190 191// Unconditional trap. 192// FIXME: This trap instruction should be marked as isTerminator, but there is 193// currently a general bug that allows non-terminators to be placed between 194// terminators. Temporarily leave this unmarked until the bug is fixed. 195let isBarrier = 1, hasCtrlDep = 1 in 196 def Trap : Alias<4, (outs), (ins), [(trap)]>; 197 198// Conditional trap. 199let isTerminator = 1, hasCtrlDep = 1, Uses = [CC] in 200 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 201 202// Fused compare-and-trap instructions. 203let isTerminator = 1, hasCtrlDep = 1 in { 204 // These patterns work the same way as for compare-and-branch. 205 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 206 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 207 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 208 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 209 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 210 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 211 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 212 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 213 let Predicates = [FeatureMiscellaneousExtensions] in { 214 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 215 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 216 } 217 218 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 219 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 220 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 221 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 222 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 223 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 224 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 225 imm32sx16>; 226 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 227 imm64sx16>; 228 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 229 imm32zx16>; 230 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 231 imm64zx16>; 232 let Predicates = [FeatureMiscellaneousExtensions] in { 233 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 234 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 235 } 236 } 237} 238 239//===----------------------------------------------------------------------===// 240// Call and return instructions 241//===----------------------------------------------------------------------===// 242 243// Define the general form of the call instructions for the asm parser. 244// These instructions don't hard-code %r14 as the return address register. 245let isCall = 1, Defs = [CC] in { 246 def BRAS : CallRI <"bras", 0xA75>; 247 def BRASL : CallRIL<"brasl", 0xC05>; 248 def BAS : CallRX <"bas", 0x4D>; 249 def BASR : CallRR <"basr", 0x0D>; 250} 251 252// Regular calls. 253let isCall = 1, Defs = [R14D, CC] in { 254 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 255 [(z_call pcrel32:$I2)]>; 256 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 257 [(z_call ADDR64:$R2)]>; 258} 259 260// TLS calls. These will be lowered into a call to __tls_get_offset, 261// with an extra relocation specifying the TLS symbol. 262let isCall = 1, Defs = [R14D, CC] in { 263 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 264 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 265 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 266 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 267} 268 269// Sibling calls. Indirect sibling calls must be via R1, since R2 upwards 270// are argument registers and since branching to R0 is a no-op. 271let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 272 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 273 [(z_sibcall pcrel32:$I2)]>; 274 let Uses = [R1D] in 275 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>; 276} 277 278// Conditional sibling calls. 279let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 280 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 281 pcrel32:$I2), []>; 282 let Uses = [R1D] in 283 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 284} 285 286// Fused compare and conditional sibling calls. 287let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in { 288 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 289 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 290 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 291 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 292 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 293 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 294 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 295 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 296} 297 298// A return instruction (br %r14). 299let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 300 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 301 302// A conditional return instruction (bcr <cond>, %r14). 303let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 304 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 305 306// Fused compare and conditional returns. 307let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 308 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 309 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 310 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 311 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 312 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 313 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 314 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 315 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 316} 317 318//===----------------------------------------------------------------------===// 319// Select instructions 320//===----------------------------------------------------------------------===// 321 322def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>; 323def Select32 : SelectWrapper<GR32>; 324def Select64 : SelectWrapper<GR64>; 325 326// We don't define 32-bit Mux stores if we don't have STOCFH, because the 327// low-only STOC should then always be used if possible. 328defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 329 nonvolatile_anyextloadi8, bdxaddr20only>, 330 Requires<[FeatureHighWord]>; 331defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 332 nonvolatile_anyextloadi16, bdxaddr20only>, 333 Requires<[FeatureHighWord]>; 334defm CondStore32Mux : CondStores<GRX32, nonvolatile_store, 335 nonvolatile_load, bdxaddr20only>, 336 Requires<[FeatureLoadStoreOnCond2]>; 337defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 338 nonvolatile_anyextloadi8, bdxaddr20only>; 339defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 340 nonvolatile_anyextloadi16, bdxaddr20only>; 341defm CondStore32 : CondStores<GR32, nonvolatile_store, 342 nonvolatile_load, bdxaddr20only>; 343 344defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 345 nonvolatile_anyextloadi8, bdxaddr20only>; 346defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 347 nonvolatile_anyextloadi16, bdxaddr20only>; 348defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 349 nonvolatile_anyextloadi32, bdxaddr20only>; 350defm CondStore64 : CondStores<GR64, nonvolatile_store, 351 nonvolatile_load, bdxaddr20only>; 352 353//===----------------------------------------------------------------------===// 354// Move instructions 355//===----------------------------------------------------------------------===// 356 357// Register moves. 358let hasSideEffects = 0 in { 359 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers. 360 def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>, 361 Requires<[FeatureHighWord]>; 362 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 363 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 364} 365let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 366 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 367 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 368} 369 370// Immediate moves. 371let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 372 isReMaterializable = 1 in { 373 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 374 // deopending on the choice of register. 375 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 376 Requires<[FeatureHighWord]>; 377 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 378 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 379 380 // Other 16-bit immediates. 381 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 382 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 383 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 384 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 385 386 // 32-bit immediates. 387 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 388 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 389 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 390} 391 392// Register loads. 393let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 394 // Expands to L, LY or LFH, depending on the choice of register. 395 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 396 Requires<[FeatureHighWord]>; 397 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 398 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 399 Requires<[FeatureHighWord]>; 400 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 401 402 // These instructions are split after register allocation, so we don't 403 // want a custom inserter. 404 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 405 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 406 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 407 } 408} 409let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 410 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 411 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 412} 413 414let canFoldAsLoad = 1 in { 415 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 416 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 417} 418 419// Load and zero rightmost byte. 420let Predicates = [FeatureLoadAndZeroRightmostByte] in { 421 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 422 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 423 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 424 (LZRF bdxaddr20only:$src)>; 425 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 426 (LZRG bdxaddr20only:$src)>; 427} 428 429// Load and trap. 430let Predicates = [FeatureLoadAndTrap] in { 431 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 432 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 433 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 434} 435 436// Register stores. 437let SimpleBDXStore = 1 in { 438 // Expands to ST, STY or STFH, depending on the choice of register. 439 def STMux : StoreRXYPseudo<store, GRX32, 4>, 440 Requires<[FeatureHighWord]>; 441 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 442 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 443 Requires<[FeatureHighWord]>; 444 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 445 446 // These instructions are split after register allocation, so we don't 447 // want a custom inserter. 448 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 449 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 450 [(store GR128:$src, bdxaddr20only128:$dst)]>; 451 } 452} 453def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 454def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 455 456// 8-bit immediate stores to 8-bit fields. 457defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 458 459// 16-bit immediate stores to 16-, 32- or 64-bit fields. 460def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 461def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 462def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 463 464// Memory-to-memory moves. 465let mayLoad = 1, mayStore = 1 in 466 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 467 468// String moves. 469let mayLoad = 1, mayStore = 1, Defs = [CC] in 470 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 471 472//===----------------------------------------------------------------------===// 473// Conditional move instructions 474//===----------------------------------------------------------------------===// 475 476let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 477 // Load immediate on condition. Matched via DAG pattern and created 478 // by the PeepholeOptimizer via FoldImmediate. 479 let hasSideEffects = 0 in { 480 // Expands to LOCHI or LOCHHI, depending on the choice of register. 481 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 482 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 483 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 484 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 485 } 486 487 // Move register on condition. Expanded from Select* pseudos and 488 // created by early if-conversion. 489 let hasSideEffects = 0, isCommutable = 1 in { 490 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 491 // depending on the choice of registers. 492 def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>; 493 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 494 } 495 496 // Load on condition. Matched via DAG pattern. 497 // Expands to LOC or LOCFH, depending on the choice of register. 498 def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>; 499 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>; 500 501 // Store on condition. Expanded from CondStore* pseudos. 502 // Expands to STOC or STOCFH, depending on the choice of register. 503 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 504 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 505 506 // Define AsmParser extended mnemonics for each general condition-code mask. 507 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 508 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 509 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 510 imm32sx16>; 511 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 512 imm64sx16>; 513 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 514 imm32sx16>; 515 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 516 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 517 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 518 } 519} 520 521let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 522 // Move register on condition. Expanded from Select* pseudos and 523 // created by early if-conversion. 524 let hasSideEffects = 0, isCommutable = 1 in { 525 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 526 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 527 } 528 529 // Load on condition. Matched via DAG pattern. 530 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; 531 defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; 532 533 // Store on condition. Expanded from CondStore* pseudos. 534 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 535 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 536 537 // Define AsmParser extended mnemonics for each general condition-code mask. 538 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 539 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 540 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 541 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 542 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 543 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 544 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 545 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 546 } 547} 548//===----------------------------------------------------------------------===// 549// Sign extensions 550//===----------------------------------------------------------------------===// 551// 552// Note that putting these before zero extensions mean that we will prefer 553// them for anyextload*. There's not really much to choose between the two 554// either way, but signed-extending loads have a short LH and a long LHY, 555// while zero-extending loads have only the long LLH. 556// 557//===----------------------------------------------------------------------===// 558 559// 32-bit extensions from registers. 560let hasSideEffects = 0 in { 561 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 562 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 563} 564 565// 64-bit extensions from registers. 566let hasSideEffects = 0 in { 567 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 568 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 569 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 570} 571let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 572 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 573 574// Match 32-to-64-bit sign extensions in which the source is already 575// in a 64-bit register. 576def : Pat<(sext_inreg GR64:$src, i32), 577 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 578 579// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 580// depending on the choice of register. 581def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 582 Requires<[FeatureHighWord]>; 583def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 584def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 585 Requires<[FeatureHighWord]>; 586 587// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 588// depending on the choice of register. 589def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 590 Requires<[FeatureHighWord]>; 591defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 592def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 593 Requires<[FeatureHighWord]>; 594def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 595 596// 64-bit extensions from memory. 597def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 598def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 599def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 600def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 601def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 602let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 603 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 604 605//===----------------------------------------------------------------------===// 606// Zero extensions 607//===----------------------------------------------------------------------===// 608 609// 32-bit extensions from registers. 610let hasSideEffects = 0 in { 611 // Expands to LLCR or RISB[LH]G, depending on the choice of registers. 612 def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 613 Requires<[FeatureHighWord]>; 614 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 615 // Expands to LLHR or RISB[LH]G, depending on the choice of registers. 616 def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 617 Requires<[FeatureHighWord]>; 618 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 619} 620 621// 64-bit extensions from registers. 622let hasSideEffects = 0 in { 623 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 624 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 625 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 626} 627 628// Match 32-to-64-bit zero extensions in which the source is already 629// in a 64-bit register. 630def : Pat<(and GR64:$src, 0xffffffff), 631 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 632 633// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 634// depending on the choice of register. 635def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 636 Requires<[FeatureHighWord]>; 637def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 638def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 639 Requires<[FeatureHighWord]>; 640 641// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 642// depending on the choice of register. 643def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 644 Requires<[FeatureHighWord]>; 645def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 646def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 647 Requires<[FeatureHighWord]>; 648def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 649 650// 64-bit extensions from memory. 651def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 652def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 653def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 654def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 655def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 656 657// 31-to-64-bit zero extensions. 658def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 659def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 660def : Pat<(and GR64:$src, 0x7fffffff), 661 (LLGTR GR64:$src)>; 662def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 663 (LLGT bdxaddr20only:$src)>; 664 665// Load and zero rightmost byte. 666let Predicates = [FeatureLoadAndZeroRightmostByte] in { 667 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 668 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 669 (LLZRGF bdxaddr20only:$src)>; 670} 671 672// Load and trap. 673let Predicates = [FeatureLoadAndTrap] in { 674 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 675 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 676} 677 678//===----------------------------------------------------------------------===// 679// Truncations 680//===----------------------------------------------------------------------===// 681 682// Truncations of 64-bit registers to 32-bit registers. 683def : Pat<(i32 (trunc GR64:$src)), 684 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 685 686// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 687// STC, STCY or STCH, depending on the choice of register. 688def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 689 Requires<[FeatureHighWord]>; 690defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 691def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 692 Requires<[FeatureHighWord]>; 693 694// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 695// STH, STHY or STHH, depending on the choice of register. 696def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 697 Requires<[FeatureHighWord]>; 698defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 699def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 700 Requires<[FeatureHighWord]>; 701def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 702 703// Truncations of 64-bit registers to memory. 704defm : StoreGR64Pair<STC, STCY, truncstorei8>; 705defm : StoreGR64Pair<STH, STHY, truncstorei16>; 706def : StoreGR64PC<STHRL, aligned_truncstorei16>; 707defm : StoreGR64Pair<ST, STY, truncstorei32>; 708def : StoreGR64PC<STRL, aligned_truncstorei32>; 709 710//===----------------------------------------------------------------------===// 711// Multi-register moves 712//===----------------------------------------------------------------------===// 713 714// Multi-register loads. 715defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 716def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 717def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 718 719// Multi-register stores. 720defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 721def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 722def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 723 724//===----------------------------------------------------------------------===// 725// Byte swaps 726//===----------------------------------------------------------------------===// 727 728// Byte-swapping register moves. 729let hasSideEffects = 0 in { 730 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 731 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 732} 733 734// Byte-swapping loads. Unlike normal loads, these instructions are 735// allowed to access storage more than once. 736def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>; 737def LRV : UnaryRXY<"lrv", 0xE31E, z_lrv, GR32, 4>; 738def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>; 739 740// Likewise byte-swapping stores. 741def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>; 742def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>; 743def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>; 744 745//===----------------------------------------------------------------------===// 746// Load address instructions 747//===----------------------------------------------------------------------===// 748 749// Load BDX-style addresses. 750let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1 in 751 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 752 753// Load a PC-relative address. There's no version of this instruction 754// with a 16-bit offset, so there's no relaxation. 755let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, 756 isReMaterializable = 1 in 757 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 758 759// Load the Global Offset Table address. This will be lowered into a 760// larl $R1, _GLOBAL_OFFSET_TABLE_ 761// instruction. 762def GOT : Alias<6, (outs GR64:$R1), (ins), 763 [(set GR64:$R1, (global_offset_table))]>; 764 765//===----------------------------------------------------------------------===// 766// Absolute and Negation 767//===----------------------------------------------------------------------===// 768 769let Defs = [CC] in { 770 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 771 def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>; 772 def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>; 773 } 774 let CCValues = 0xE, CompareZeroCCMask = 0xE in 775 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 776} 777def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>; 778def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>; 779defm : SXU<z_iabs, LPGFR>; 780defm : SXU<z_iabs64, LPGFR>; 781 782let Defs = [CC] in { 783 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 784 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 785 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 786 } 787 let CCValues = 0xE, CompareZeroCCMask = 0xE in 788 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 789} 790def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>; 791def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>; 792defm : SXU<z_inegabs, LNGFR>; 793defm : SXU<z_inegabs64, LNGFR>; 794 795let Defs = [CC] in { 796 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 797 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 798 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 799 } 800 let CCValues = 0xE, CompareZeroCCMask = 0xE in 801 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 802} 803defm : SXU<ineg, LCGFR>; 804 805//===----------------------------------------------------------------------===// 806// Insertion 807//===----------------------------------------------------------------------===// 808 809let isCodeGenOnly = 1 in 810 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 811defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 812 813defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 814defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 815 816defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 817defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 818 819let Defs = [CC] in { 820 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 821 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 822} 823 824// Insertions of a 16-bit immediate, leaving other bits unaffected. 825// We don't have or_as_insert equivalents of these operations because 826// OI is available instead. 827// 828// IIxMux expands to II[LH]x, depending on the choice of register. 829def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 830 Requires<[FeatureHighWord]>; 831def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 832 Requires<[FeatureHighWord]>; 833def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 834def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 835def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 836def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 837def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 838def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 839def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 840def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 841 842// ...likewise for 32-bit immediates. For GR32s this is a general 843// full-width move. (We use IILF rather than something like LLILF 844// for 32-bit moves because IILF leaves the upper 32 bits of the 845// GR64 unchanged.) 846let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 847 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 848 Requires<[FeatureHighWord]>; 849 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 850 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 851} 852def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 853def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 854 855// An alternative model of inserthf, with the first operand being 856// a zero-extended value. 857def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 858 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 859 imm64hf32:$imm)>; 860 861//===----------------------------------------------------------------------===// 862// Addition 863//===----------------------------------------------------------------------===// 864 865// Plain addition. 866let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 867 // Addition of a register. 868 let isCommutable = 1 in { 869 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, add, GR32, GR32>; 870 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, add, GR64, GR64>; 871 } 872 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 873 874 // Addition of signed 16-bit immediates. 875 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>; 876 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>; 877 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>; 878 879 // Addition of signed 32-bit immediates. 880 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>, 881 Requires<[FeatureHighWord]>; 882 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>; 883 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>, 884 Requires<[FeatureHighWord]>; 885 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>; 886 887 // Addition of memory. 888 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; 889 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; 890 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; 891 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; 892 893 // Addition to memory. 894 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 895 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 896} 897defm : SXB<add, GR64, AGFR>; 898 899// Addition producing a carry. 900let Defs = [CC] in { 901 // Addition of a register. 902 let isCommutable = 1 in { 903 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, addc, GR32, GR32>; 904 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, addc, GR64, GR64>; 905 } 906 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 907 908 // Addition of signed 16-bit immediates. 909 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>, 910 Requires<[FeatureDistinctOps]>; 911 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>, 912 Requires<[FeatureDistinctOps]>; 913 914 // Addition of unsigned 32-bit immediates. 915 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>; 916 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>; 917 918 // Addition of memory. 919 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>; 920 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>; 921 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>; 922} 923defm : ZXB<addc, GR64, ALGFR>; 924 925// Addition producing and using a carry. 926let Defs = [CC], Uses = [CC] in { 927 // Addition of a register. 928 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>; 929 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>; 930 931 // Addition of memory. 932 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>; 933 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>; 934} 935 936//===----------------------------------------------------------------------===// 937// Subtraction 938//===----------------------------------------------------------------------===// 939 940// Plain subtraction. Although immediate forms exist, we use the 941// add-immediate instruction instead. 942let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { 943 // Subtraction of a register. 944 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, sub, GR32, GR32>; 945 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 946 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, sub, GR64, GR64>; 947 948 // Subtraction of memory. 949 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; 950 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; 951 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; 952 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; 953} 954defm : SXB<sub, GR64, SGFR>; 955 956// Subtraction producing a carry. 957let Defs = [CC] in { 958 // Subtraction of a register. 959 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, subc, GR32, GR32>; 960 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 961 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, subc, GR64, GR64>; 962 963 // Subtraction of unsigned 32-bit immediates. These don't match 964 // subc because we prefer addc for constants. 965 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>; 966 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>; 967 968 // Subtraction of memory. 969 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>; 970 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>; 971 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>; 972} 973defm : ZXB<subc, GR64, SLGFR>; 974 975// Subtraction producing and using a carry. 976let Defs = [CC], Uses = [CC] in { 977 // Subtraction of a register. 978 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>; 979 def SLBGR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>; 980 981 // Subtraction of memory. 982 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>; 983 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>; 984} 985 986//===----------------------------------------------------------------------===// 987// AND 988//===----------------------------------------------------------------------===// 989 990let Defs = [CC] in { 991 // ANDs of a register. 992 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 993 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 994 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 995 } 996 997 let isConvertibleToThreeAddress = 1 in { 998 // ANDs of a 16-bit immediate, leaving other bits unaffected. 999 // The CC result only reflects the 16-bit field, not the full register. 1000 // 1001 // NIxMux expands to NI[LH]x, depending on the choice of register. 1002 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1003 Requires<[FeatureHighWord]>; 1004 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1005 Requires<[FeatureHighWord]>; 1006 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1007 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1008 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1009 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1010 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1011 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1012 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1013 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1014 1015 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1016 // The CC result only reflects the 32-bit field, which means we can 1017 // use it as a zero indicator for i32 operations but not otherwise. 1018 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1019 // Expands to NILF or NIHF, depending on the choice of register. 1020 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1021 Requires<[FeatureHighWord]>; 1022 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1023 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1024 } 1025 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1026 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1027 } 1028 1029 // ANDs of memory. 1030 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1031 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>; 1032 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>; 1033 } 1034 1035 // AND to memory 1036 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1037 1038 // Block AND. 1039 let mayLoad = 1, mayStore = 1 in 1040 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1041} 1042defm : RMWIByte<and, bdaddr12pair, NI>; 1043defm : RMWIByte<and, bdaddr20pair, NIY>; 1044 1045//===----------------------------------------------------------------------===// 1046// OR 1047//===----------------------------------------------------------------------===// 1048 1049let Defs = [CC] in { 1050 // ORs of a register. 1051 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1052 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1053 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1054 } 1055 1056 // ORs of a 16-bit immediate, leaving other bits unaffected. 1057 // The CC result only reflects the 16-bit field, not the full register. 1058 // 1059 // OIxMux expands to OI[LH]x, depending on the choice of register. 1060 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1061 Requires<[FeatureHighWord]>; 1062 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1063 Requires<[FeatureHighWord]>; 1064 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1065 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1066 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1067 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1068 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1069 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1070 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1071 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1072 1073 // ORs of a 32-bit immediate, leaving other bits unaffected. 1074 // The CC result only reflects the 32-bit field, which means we can 1075 // use it as a zero indicator for i32 operations but not otherwise. 1076 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1077 // Expands to OILF or OIHF, depending on the choice of register. 1078 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1079 Requires<[FeatureHighWord]>; 1080 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1081 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1082 } 1083 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1084 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1085 1086 // ORs of memory. 1087 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1088 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>; 1089 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>; 1090 } 1091 1092 // OR to memory 1093 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1094 1095 // Block OR. 1096 let mayLoad = 1, mayStore = 1 in 1097 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1098} 1099defm : RMWIByte<or, bdaddr12pair, OI>; 1100defm : RMWIByte<or, bdaddr20pair, OIY>; 1101 1102//===----------------------------------------------------------------------===// 1103// XOR 1104//===----------------------------------------------------------------------===// 1105 1106let Defs = [CC] in { 1107 // XORs of a register. 1108 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1109 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1110 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1111 } 1112 1113 // XORs of a 32-bit immediate, leaving other bits unaffected. 1114 // The CC result only reflects the 32-bit field, which means we can 1115 // use it as a zero indicator for i32 operations but not otherwise. 1116 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1117 // Expands to XILF or XIHF, depending on the choice of register. 1118 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1119 Requires<[FeatureHighWord]>; 1120 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1121 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1122 } 1123 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1124 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1125 1126 // XORs of memory. 1127 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1128 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>; 1129 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>; 1130 } 1131 1132 // XOR to memory 1133 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1134 1135 // Block XOR. 1136 let mayLoad = 1, mayStore = 1 in 1137 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1138} 1139defm : RMWIByte<xor, bdaddr12pair, XI>; 1140defm : RMWIByte<xor, bdaddr20pair, XIY>; 1141 1142//===----------------------------------------------------------------------===// 1143// Multiplication 1144//===----------------------------------------------------------------------===// 1145 1146// Multiplication of a register. 1147let isCommutable = 1 in { 1148 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1149 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1150} 1151def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1152defm : SXB<mul, GR64, MSGFR>; 1153 1154// Multiplication of a signed 16-bit immediate. 1155def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1156def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1157 1158// Multiplication of a signed 32-bit immediate. 1159def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1160def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1161 1162// Multiplication of memory. 1163defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1164defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1165def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1166def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1167 1168// Multiplication of a register, producing two results. 1169def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>; 1170 1171// Multiplication of memory, producing two results. 1172def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>; 1173 1174//===----------------------------------------------------------------------===// 1175// Division and remainder 1176//===----------------------------------------------------------------------===// 1177 1178let hasSideEffects = 1 in { // Do not speculatively execute. 1179 // Division and remainder, from registers. 1180 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, z_sdivrem32, GR128, GR32>; 1181 def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>; 1182 def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>; 1183 def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>; 1184 1185 // Division and remainder, from memory. 1186 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>; 1187 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>; 1188 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>; 1189 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>; 1190} 1191 1192//===----------------------------------------------------------------------===// 1193// Shifts 1194//===----------------------------------------------------------------------===// 1195 1196// Shift left. 1197let hasSideEffects = 0 in { 1198 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>; 1199 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1200 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>; 1201} 1202 1203// Logical shift right. 1204let hasSideEffects = 0 in { 1205 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>; 1206 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>; 1207} 1208 1209// Arithmetic shift right. 1210let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1211 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>; 1212 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>; 1213} 1214 1215// Rotate left. 1216let hasSideEffects = 0 in { 1217 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>; 1218 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>; 1219} 1220 1221// Rotate second operand left and inserted selected bits into first operand. 1222// These can act like 32-bit operands provided that the constant start and 1223// end bits (operands 2 and 3) are in the range [32, 64). 1224let Defs = [CC] in { 1225 let isCodeGenOnly = 1 in 1226 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1227 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1228 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1229} 1230 1231// On zEC12 we have a variant of RISBG that does not set CC. 1232let Predicates = [FeatureMiscellaneousExtensions] in 1233 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1234 1235// Forms of RISBG that only affect one word of the destination register. 1236// They do not set CC. 1237let Predicates = [FeatureHighWord] in { 1238 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1239 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1240 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1241 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1242 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1243 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1244 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1245} 1246 1247// Rotate second operand left and perform a logical operation with selected 1248// bits of the first operand. The CC result only describes the selected bits, 1249// so isn't useful for a full comparison against zero. 1250let Defs = [CC] in { 1251 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1252 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1253 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1254} 1255 1256//===----------------------------------------------------------------------===// 1257// Comparison 1258//===----------------------------------------------------------------------===// 1259 1260// Signed comparisons. We put these before the unsigned comparisons because 1261// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1262// of the unsigned forms do. 1263let Defs = [CC], CCValues = 0xE in { 1264 // Comparison with a register. 1265 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1266 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1267 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1268 1269 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1270 // depending on the choice of register. 1271 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1272 Requires<[FeatureHighWord]>; 1273 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1274 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1275 1276 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1277 // depending on the choice of register. 1278 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1279 Requires<[FeatureHighWord]>; 1280 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1281 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1282 Requires<[FeatureHighWord]>; 1283 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1284 1285 // Comparison with memory. 1286 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1287 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1288 Requires<[FeatureHighWord]>; 1289 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1290 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1291 Requires<[FeatureHighWord]>; 1292 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1293 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1294 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1295 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1296 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1297 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1298 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1299 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1300 1301 // Comparison between memory and a signed 16-bit immediate. 1302 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1303 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1304 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1305} 1306defm : SXB<z_scmp, GR64, CGFR>; 1307 1308// Unsigned comparisons. 1309let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1310 // Comparison with a register. 1311 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1312 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1313 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1314 1315 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1316 // or CLIH, depending on the choice of register. 1317 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1318 Requires<[FeatureHighWord]>; 1319 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1320 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1321 Requires<[FeatureHighWord]>; 1322 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1323 1324 // Comparison with memory. 1325 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1326 Requires<[FeatureHighWord]>; 1327 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1328 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1329 Requires<[FeatureHighWord]>; 1330 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1331 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1332 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1333 aligned_azextloadi16>; 1334 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1335 aligned_load>; 1336 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1337 aligned_azextloadi16>; 1338 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1339 aligned_azextloadi32>; 1340 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1341 aligned_load>; 1342 1343 // Comparison between memory and an unsigned 8-bit immediate. 1344 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1345 1346 // Comparison between memory and an unsigned 16-bit immediate. 1347 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1348 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1349 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1350} 1351defm : ZXB<z_ucmp, GR64, CLGFR>; 1352 1353// Memory-to-memory comparison. 1354let mayLoad = 1, Defs = [CC] in 1355 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1356 1357// String comparison. 1358let mayLoad = 1, Defs = [CC] in 1359 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1360 1361// Test under mask. 1362let Defs = [CC] in { 1363 // TMxMux expands to TM[LH]x, depending on the choice of register. 1364 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1365 Requires<[FeatureHighWord]>; 1366 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1367 Requires<[FeatureHighWord]>; 1368 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1369 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1370 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1371 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1372 1373 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1374 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1375 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1376 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1377 1378 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1379} 1380 1381def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1382def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1383 1384//===----------------------------------------------------------------------===// 1385// Prefetch and execution hint 1386//===----------------------------------------------------------------------===// 1387 1388def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1389def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1390 1391let Predicates = [FeatureExecutionHint] in { 1392 // Branch Prediction Preload 1393 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1394 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1395 1396 // Next Instruction Access Intent 1397 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1398} 1399 1400//===----------------------------------------------------------------------===// 1401// Atomic operations 1402//===----------------------------------------------------------------------===// 1403 1404// A serialization instruction that acts as a barrier for all memory 1405// accesses, which expands to "bcr 14, 0". 1406let hasSideEffects = 1 in 1407def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>; 1408 1409// A pseudo instruction that serves as a compiler barrier. 1410let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1411def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1412 1413let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1414 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1415 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1416 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1417 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1418 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1419 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1420 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1421 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1422 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1423 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1424} 1425 1426def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1427def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1428def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1429 1430def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1431def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1432let Predicates = [FeatureNoInterlockedAccess1] in { 1433 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1434 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1435 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1436 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1437 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1438 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1439} 1440 1441def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1442def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1443def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1444 1445def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1446def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1447let Predicates = [FeatureNoInterlockedAccess1] in { 1448 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1449 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1450 imm32ll16c>; 1451 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1452 imm32lh16c>; 1453 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1454 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1455 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1456 imm64ll16c>; 1457 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1458 imm64lh16c>; 1459 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1460 imm64hl16c>; 1461 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1462 imm64hh16c>; 1463 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1464 imm64lf32c>; 1465 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1466 imm64hf32c>; 1467} 1468 1469def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1470def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1471let Predicates = [FeatureNoInterlockedAccess1] in { 1472 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1473 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1474 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1475 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1476 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1477 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1478 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1479 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1480 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1481 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1482 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1483} 1484 1485def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1486def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1487let Predicates = [FeatureNoInterlockedAccess1] in { 1488 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1489 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1490 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1491 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1492 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1493} 1494 1495def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1496def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1497 imm32lh16c>; 1498def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1499def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1500 imm32ll16c>; 1501def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1502 imm32lh16c>; 1503def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1504def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1505def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1506 imm64ll16c>; 1507def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1508 imm64lh16c>; 1509def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1510 imm64hl16c>; 1511def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1512 imm64hh16c>; 1513def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1514 imm64lf32c>; 1515def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1516 imm64hf32c>; 1517 1518def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1519def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1520def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1521 1522def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1523def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1524def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1525 1526def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1527def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1528def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1529 1530def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1531def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1532def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1533 1534def ATOMIC_CMP_SWAPW 1535 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1536 ADDR32:$bitshift, ADDR32:$negbitshift, 1537 uimm32:$bitsize), 1538 [(set GR32:$dst, 1539 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1540 ADDR32:$bitshift, ADDR32:$negbitshift, 1541 uimm32:$bitsize))]> { 1542 let Defs = [CC]; 1543 let mayLoad = 1; 1544 let mayStore = 1; 1545 let usesCustomInserter = 1; 1546 let hasNoSchedulingInfo = 1; 1547} 1548 1549// Test and set. 1550let mayLoad = 1, Defs = [CC] in 1551 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1552 1553// Compare and swap. 1554let Defs = [CC] in { 1555 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>; 1556 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>; 1557} 1558 1559// Compare double and swap. 1560let Defs = [CC] in { 1561 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1562 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, null_frag, GR128>; 1563} 1564 1565// Compare and swap and store. 1566let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1567 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1568 1569// Perform locked operation. 1570let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1571 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1572 1573// Load/store pair from/to quadword. 1574def LPQ : UnaryRXY<"lpq", 0xE38F, null_frag, GR128, 16>; 1575def STPQ : StoreRXY<"stpq", 0xE38E, null_frag, GR128, 16>; 1576 1577// Load pair disjoint. 1578let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1579 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1580 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1581} 1582 1583//===----------------------------------------------------------------------===// 1584// Access registers 1585//===----------------------------------------------------------------------===// 1586 1587// Read a 32-bit access register into a GR32. As with all GR32 operations, 1588// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1589// when a 64-bit address is stored in a pair of access registers. 1590def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1591 1592// Set access register. 1593def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1594 1595// Copy access register. 1596def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1597 1598// Load address extended. 1599defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1600 1601// Load access multiple. 1602defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1603 1604// Load access multiple. 1605defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1606 1607//===----------------------------------------------------------------------===// 1608// Program mask and addressing mode 1609//===----------------------------------------------------------------------===// 1610 1611// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1612let Uses = [CC] in 1613 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 1614 1615// Set CC and program mask from a register. 1616let hasSideEffects = 1, Defs = [CC] in 1617 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 1618 1619// Branch and link - like BAS, but also extracts CC and program mask. 1620let isCall = 1, Uses = [CC], Defs = [CC] in { 1621 def BAL : CallRX<"bal", 0x45>; 1622 def BALR : CallRR<"balr", 0x05>; 1623} 1624 1625// Test addressing mode. 1626let Defs = [CC] in 1627 def TAM : SideEffectInherentE<"tam", 0x010B>; 1628 1629// Set addressing mode. 1630let hasSideEffects = 1 in { 1631 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 1632 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 1633 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 1634} 1635 1636// Branch and set mode. Not really a call, but also sets an output register. 1637let isBranch = 1, isTerminator = 1, isBarrier = 1 in 1638 def BSM : CallRR<"bsm", 0x0B>; 1639 1640// Branch and save and set mode. 1641let isCall = 1, Defs = [CC] in 1642 def BASSM : CallRR<"bassm", 0x0C>; 1643 1644//===----------------------------------------------------------------------===// 1645// Transactional execution 1646//===----------------------------------------------------------------------===// 1647 1648let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 1649 // Transaction Begin 1650 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 1651 def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 1652 def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 1653 1654 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 1655 int_s390_tbeginc, imm32zx16>; 1656 } 1657 1658 // Transaction End 1659 let Defs = [CC] in 1660 def TEND : SideEffectInherentS<"tend", 0xB2F8, z_tend>; 1661 1662 // Transaction Abort 1663 let isTerminator = 1, isBarrier = 1 in 1664 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 1665 1666 // Nontransactional Store 1667 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 1668 1669 // Extract Transaction Nesting Depth 1670 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 1671} 1672 1673//===----------------------------------------------------------------------===// 1674// Processor assist 1675//===----------------------------------------------------------------------===// 1676 1677let Predicates = [FeatureProcessorAssist] in { 1678 let hasSideEffects = 1 in 1679 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 1680 def : Pat<(int_s390_ppa_txassist GR32:$src), 1681 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1682 0, 1)>; 1683} 1684 1685//===----------------------------------------------------------------------===// 1686// Miscellaneous Instructions. 1687//===----------------------------------------------------------------------===// 1688 1689// Find leftmost one, AKA count leading zeros. The instruction actually 1690// returns a pair of GR64s, the first giving the number of leading zeros 1691// and the second giving a copy of the source with the leftmost one bit 1692// cleared. We only use the first result here. 1693let Defs = [CC] in 1694 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 1695def : Pat<(ctlz GR64:$src), 1696 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 1697 1698// Population count. Counts bits set per byte. 1699let Predicates = [FeaturePopulationCount], Defs = [CC] in 1700 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 1701 1702// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 1703def : Pat<(i64 (anyext GR32:$src)), 1704 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 1705 1706// Extend GR32s and GR64s to GR128s. 1707let usesCustomInserter = 1 in { 1708 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1709 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>; 1710 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 1711} 1712 1713// Search a block of memory for a character. 1714let mayLoad = 1, Defs = [CC] in 1715 defm SRST : StringRRE<"srst", 0xb25e, z_search_string>; 1716 1717// Supervisor call. 1718let hasSideEffects = 1, isCall = 1, Defs = [CC] in 1719 def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>; 1720 1721// Store clock. 1722let hasSideEffects = 1, Defs = [CC] in { 1723 def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>; 1724 def STCKF : StoreInherentS<"stckf", 0xB27C, null_frag, 8>; 1725 def STCKE : StoreInherentS<"stcke", 0xB278, null_frag, 16>; 1726} 1727 1728// Store facility list. 1729let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in 1730 def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>; 1731 1732// Extract CPU time. 1733let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in 1734 def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>; 1735 1736// Execute. 1737let hasSideEffects = 1 in { 1738 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 1739 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 1740} 1741 1742// Program return. 1743let hasSideEffects = 1, Defs = [CC] in 1744 def PR : SideEffectInherentE<"pr", 0x0101>; 1745 1746// Move with key. 1747let mayLoad = 1, mayStore = 1, Defs = [CC] in 1748 def MVCK : MemoryBinarySSd<"mvck", 0xD9, GR64>; 1749 1750// Store real address. 1751def STRAG : StoreSSE<"strag", 0xE502>; 1752 1753//===----------------------------------------------------------------------===// 1754// .insn directive instructions 1755//===----------------------------------------------------------------------===// 1756 1757let isCodeGenOnly = 1 in { 1758 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 1759 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 1760 imm32sx16:$I2), 1761 ".insn ri,$enc,$R1,$I2", []>; 1762 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1763 AnyReg:$R3, brtarget16:$I2), 1764 ".insn rie,$enc,$R1,$R3,$I2", []>; 1765 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1766 brtarget32:$I2), 1767 ".insn ril,$enc,$R1,$I2", []>; 1768 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1769 uimm32:$I2), 1770 ".insn rilu,$enc,$R1,$I2", []>; 1771 def InsnRIS : DirectiveInsnRIS<(outs), 1772 (ins imm64zx48:$enc, AnyReg:$R1, 1773 imm32sx8:$I2, imm32zx4:$M3, 1774 bdaddr12only:$BD4), 1775 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 1776 def InsnRR : DirectiveInsnRR<(outs), 1777 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 1778 ".insn rr,$enc,$R1,$R2", []>; 1779 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 1780 AnyReg:$R1, AnyReg:$R2), 1781 ".insn rre,$enc,$R1,$R2", []>; 1782 def InsnRRF : DirectiveInsnRRF<(outs), 1783 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 1784 AnyReg:$R3, imm32zx4:$M4), 1785 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 1786 def InsnRRS : DirectiveInsnRRS<(outs), 1787 (ins imm64zx48:$enc, AnyReg:$R1, 1788 AnyReg:$R2, imm32zx4:$M3, 1789 bdaddr12only:$BD4), 1790 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 1791 def InsnRS : DirectiveInsnRS<(outs), 1792 (ins imm64zx32:$enc, AnyReg:$R1, 1793 AnyReg:$R3, bdaddr12only:$BD2), 1794 ".insn rs,$enc,$R1,$R3,$BD2", []>; 1795 def InsnRSE : DirectiveInsnRSE<(outs), 1796 (ins imm64zx48:$enc, AnyReg:$R1, 1797 AnyReg:$R3, bdaddr12only:$BD2), 1798 ".insn rse,$enc,$R1,$R3,$BD2", []>; 1799 def InsnRSI : DirectiveInsnRSI<(outs), 1800 (ins imm64zx48:$enc, AnyReg:$R1, 1801 AnyReg:$R3, brtarget16:$RI2), 1802 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 1803 def InsnRSY : DirectiveInsnRSY<(outs), 1804 (ins imm64zx48:$enc, AnyReg:$R1, 1805 AnyReg:$R3, bdaddr20only:$BD2), 1806 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 1807 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 1808 bdxaddr12only:$XBD2), 1809 ".insn rx,$enc,$R1,$XBD2", []>; 1810 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1811 bdxaddr12only:$XBD2), 1812 ".insn rxe,$enc,$R1,$XBD2", []>; 1813 def InsnRXF : DirectiveInsnRXF<(outs), 1814 (ins imm64zx48:$enc, AnyReg:$R1, 1815 AnyReg:$R3, bdxaddr12only:$XBD2), 1816 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 1817 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 1818 bdxaddr20only:$XBD2), 1819 ".insn rxy,$enc,$R1,$XBD2", []>; 1820 def InsnS : DirectiveInsnS<(outs), 1821 (ins imm64zx32:$enc, bdaddr12only:$BD2), 1822 ".insn s,$enc,$BD2", []>; 1823 def InsnSI : DirectiveInsnSI<(outs), 1824 (ins imm64zx32:$enc, bdaddr12only:$BD1, 1825 imm32sx8:$I2), 1826 ".insn si,$enc,$BD1,$I2", []>; 1827 def InsnSIY : DirectiveInsnSIY<(outs), 1828 (ins imm64zx48:$enc, 1829 bdaddr20only:$BD1, imm32zx8:$I2), 1830 ".insn siy,$enc,$BD1,$I2", []>; 1831 def InsnSIL : DirectiveInsnSIL<(outs), 1832 (ins imm64zx48:$enc, bdaddr12only:$BD1, 1833 imm32zx16:$I2), 1834 ".insn sil,$enc,$BD1,$I2", []>; 1835 def InsnSS : DirectiveInsnSS<(outs), 1836 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 1837 bdaddr12only:$BD2, AnyReg:$R3), 1838 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 1839 def InsnSSE : DirectiveInsnSSE<(outs), 1840 (ins imm64zx48:$enc, 1841 bdaddr12only:$BD1,bdaddr12only:$BD2), 1842 ".insn sse,$enc,$BD1,$BD2", []>; 1843 def InsnSSF : DirectiveInsnSSF<(outs), 1844 (ins imm64zx48:$enc, bdaddr12only:$BD1, 1845 bdaddr12only:$BD2, AnyReg:$R3), 1846 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 1847} 1848 1849//===----------------------------------------------------------------------===// 1850// Peepholes. 1851//===----------------------------------------------------------------------===// 1852 1853// Use AL* for GR64 additions of unsigned 32-bit values. 1854defm : ZXB<add, GR64, ALGFR>; 1855def : Pat<(add GR64:$src1, imm64zx32:$src2), 1856 (ALGFI GR64:$src1, imm64zx32:$src2)>; 1857def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1858 (ALGF GR64:$src1, bdxaddr20only:$addr)>; 1859 1860// Use SL* for GR64 subtractions of unsigned 32-bit values. 1861defm : ZXB<sub, GR64, SLGFR>; 1862def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1863 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1864def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)), 1865 (SLGF GR64:$src1, bdxaddr20only:$addr)>; 1866 1867// Optimize sign-extended 1/0 selects to -1/0 selects. This is important 1868// for vector legalization. 1869def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)), 1870 (i32 31)), 1871 (i32 31)), 1872 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1873def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, 1874 imm32zx4:$cc)))), 1875 (i32 63)), 1876 (i32 63)), 1877 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>; 1878 1879// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 1880// equivalent to (and (xor x, -1), y) 1881def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 1882 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 1883 1884// Shift/rotate instructions only use the last 6 bits of the second operand 1885// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 1886// last 16 bits. 1887// Complexity is added so that we match this before we match NILF on the AND 1888// operation alone. 1889let AddedComplexity = 4 in { 1890 def : Pat<(shl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1891 (SLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1892 1893 def : Pat<(sra GR32:$val, (and GR32:$shift, uimm32:$imm)), 1894 (SRA GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1895 1896 def : Pat<(srl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1897 (SRL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1898 1899 def : Pat<(shl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1900 (SLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1901 1902 def : Pat<(sra GR64:$val, (and GR32:$shift, uimm32:$imm)), 1903 (SRAG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1904 1905 def : Pat<(srl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1906 (SRLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1907 1908 def : Pat<(rotl GR32:$val, (and GR32:$shift, uimm32:$imm)), 1909 (RLL GR32:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1910 1911 def : Pat<(rotl GR64:$val, (and GR32:$shift, uimm32:$imm)), 1912 (RLLG GR64:$val, (NILL GR32:$shift, uimm32:$imm), 0)>; 1913} 1914 1915// Peepholes for turning scalar operations into block operations. 1916defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 1917 XCSequence, 1>; 1918defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 1919 XCSequence, 2>; 1920defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 1921 XCSequence, 4>; 1922defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 1923 OCSequence, XCSequence, 1>; 1924defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 1925 XCSequence, 2>; 1926defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 1927 XCSequence, 4>; 1928defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 1929 XCSequence, 8>; 1930