1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the SystemZ implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 16 17 #include "SystemZ.h" 18 #include "SystemZRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "SystemZGenInstrInfo.inc" 23 24 namespace llvm { 25 26 class SystemZTargetMachine; 27 28 namespace SystemZII { 29 enum { 30 // See comments in SystemZInstrFormats.td. 31 SimpleBDXLoad = (1 << 0), 32 SimpleBDXStore = (1 << 1), 33 Has20BitOffset = (1 << 2), 34 HasIndex = (1 << 3), 35 Is128Bit = (1 << 4), 36 AccessSizeMask = (31 << 5), 37 AccessSizeShift = 5, 38 CCValuesMask = (15 << 10), 39 CCValuesShift = 10, 40 CompareZeroCCMaskMask = (15 << 14), 41 CompareZeroCCMaskShift = 14, 42 CCMaskFirst = (1 << 18), 43 CCMaskLast = (1 << 19), 44 IsLogical = (1 << 20) 45 }; 46 static inline unsigned getAccessSize(unsigned int Flags) { 47 return (Flags & AccessSizeMask) >> AccessSizeShift; 48 } 49 static inline unsigned getCCValues(unsigned int Flags) { 50 return (Flags & CCValuesMask) >> CCValuesShift; 51 } 52 static inline unsigned getCompareZeroCCMask(unsigned int Flags) { 53 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift; 54 } 55 56 // SystemZ MachineOperand target flags. 57 enum { 58 // Masks out the bits for the access model. 59 MO_SYMBOL_MODIFIER = (3 << 0), 60 61 // @GOT (aka @GOTENT) 62 MO_GOT = (1 << 0), 63 64 // @INDNTPOFF 65 MO_INDNTPOFF = (2 << 0) 66 }; 67 // Classifies a branch. 68 enum BranchType { 69 // An instruction that branches on the current value of CC. 70 BranchNormal, 71 72 // An instruction that peforms a 32-bit signed comparison and branches 73 // on the result. 74 BranchC, 75 76 // An instruction that peforms a 32-bit unsigned comparison and branches 77 // on the result. 78 BranchCL, 79 80 // An instruction that peforms a 64-bit signed comparison and branches 81 // on the result. 82 BranchCG, 83 84 // An instruction that peforms a 64-bit unsigned comparison and branches 85 // on the result. 86 BranchCLG, 87 88 // An instruction that decrements a 32-bit register and branches if 89 // the result is nonzero. 90 BranchCT, 91 92 // An instruction that decrements a 64-bit register and branches if 93 // the result is nonzero. 94 BranchCTG 95 }; 96 // Information about a branch instruction. 97 struct Branch { 98 // The type of the branch. 99 BranchType Type; 100 101 // CCMASK_<N> is set if CC might be equal to N. 102 unsigned CCValid; 103 104 // CCMASK_<N> is set if the branch should be taken when CC == N. 105 unsigned CCMask; 106 107 // The target of the branch. 108 const MachineOperand *Target; 109 110 Branch(BranchType type, unsigned ccValid, unsigned ccMask, 111 const MachineOperand *target) 112 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {} 113 }; 114 // Kinds of branch in compare-and-branch instructions. Together with type 115 // of the converted compare, this identifies the compare-and-branch 116 // instruction. 117 enum CompareAndBranchType { 118 // Relative branch - CRJ etc. 119 CompareAndBranch, 120 121 // Indirect branch, used for return - CRBReturn etc. 122 CompareAndReturn, 123 124 // Indirect branch, used for sibcall - CRBCall etc. 125 CompareAndSibcall 126 }; 127 } // end namespace SystemZII 128 129 class SystemZSubtarget; 130 class SystemZInstrInfo : public SystemZGenInstrInfo { 131 const SystemZRegisterInfo RI; 132 SystemZSubtarget &STI; 133 134 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const; 135 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const; 136 void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode, 137 unsigned HighOpcode, bool ConvertHigh) const; 138 void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode, 139 unsigned LowOpcodeK, unsigned HighOpcode) const; 140 void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode, 141 unsigned HighOpcode) const; 142 void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode, 143 unsigned Size) const; 144 void expandLoadStackGuard(MachineInstr *MI) const; 145 void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 146 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 147 unsigned LowLowOpcode, unsigned Size, bool KillSrc) const; 148 virtual void anchor(); 149 150 public: 151 explicit SystemZInstrInfo(SystemZSubtarget &STI); 152 153 // Override TargetInstrInfo. 154 unsigned isLoadFromStackSlot(const MachineInstr *MI, 155 int &FrameIndex) const override; 156 unsigned isStoreToStackSlot(const MachineInstr *MI, 157 int &FrameIndex) const override; 158 bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, 159 int &SrcFrameIndex) const override; 160 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 161 MachineBasicBlock *&FBB, 162 SmallVectorImpl<MachineOperand> &Cond, 163 bool AllowModify) const override; 164 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 165 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 166 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 167 DebugLoc DL) const override; 168 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 169 unsigned &SrcReg2, int &Mask, int &Value) const override; 170 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 171 unsigned SrcReg2, int Mask, int Value, 172 const MachineRegisterInfo *MRI) const override; 173 bool isPredicable(MachineInstr &MI) const override; 174 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 175 unsigned ExtraPredCycles, 176 BranchProbability Probability) const override; 177 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 178 unsigned NumCyclesT, unsigned ExtraPredCyclesT, 179 MachineBasicBlock &FMBB, 180 unsigned NumCyclesF, unsigned ExtraPredCyclesF, 181 BranchProbability Probability) const override; 182 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 183 BranchProbability Probability) const override; 184 bool PredicateInstruction(MachineInstr &MI, 185 ArrayRef<MachineOperand> Pred) const override; 186 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 187 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 188 bool KillSrc) const override; 189 void storeRegToStackSlot(MachineBasicBlock &MBB, 190 MachineBasicBlock::iterator MBBI, 191 unsigned SrcReg, bool isKill, int FrameIndex, 192 const TargetRegisterClass *RC, 193 const TargetRegisterInfo *TRI) const override; 194 void loadRegFromStackSlot(MachineBasicBlock &MBB, 195 MachineBasicBlock::iterator MBBI, 196 unsigned DestReg, int FrameIdx, 197 const TargetRegisterClass *RC, 198 const TargetRegisterInfo *TRI) const override; 199 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 200 MachineBasicBlock::iterator &MBBI, 201 LiveVariables *LV) const override; 202 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 203 ArrayRef<unsigned> Ops, 204 MachineBasicBlock::iterator InsertPt, 205 int FrameIndex) const override; 206 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 207 ArrayRef<unsigned> Ops, 208 MachineBasicBlock::iterator InsertPt, 209 MachineInstr *LoadMI) const override; 210 bool expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const override; 211 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 212 override; 213 214 // Return the SystemZRegisterInfo, which this class owns. 215 const SystemZRegisterInfo &getRegisterInfo() const { return RI; } 216 217 // Return the size in bytes of MI. 218 uint64_t getInstSizeInBytes(const MachineInstr *MI) const; 219 220 // Return true if MI is a conditional or unconditional branch. 221 // When returning true, set Cond to the mask of condition-code 222 // values on which the instruction will branch, and set Target 223 // to the operand that contains the branch target. This target 224 // can be a register or a basic block. 225 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const; 226 227 // Get the load and store opcodes for a given register class. 228 void getLoadStoreOpcodes(const TargetRegisterClass *RC, 229 unsigned &LoadOpcode, unsigned &StoreOpcode) const; 230 231 // Opcode is the opcode of an instruction that has an address operand, 232 // and the caller wants to perform that instruction's operation on an 233 // address that has displacement Offset. Return the opcode of a suitable 234 // instruction (which might be Opcode itself) or 0 if no such instruction 235 // exists. 236 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const; 237 238 // If Opcode is a load instruction that has a LOAD AND TEST form, 239 // return the opcode for the testing form, otherwise return 0. 240 unsigned getLoadAndTest(unsigned Opcode) const; 241 242 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits 243 // Mask of the R2 operand, given that only the low BitSize bits of Mask are 244 // significant. Set Start and End to the I3 and I4 operands if so. 245 bool isRxSBGMask(uint64_t Mask, unsigned BitSize, 246 unsigned &Start, unsigned &End) const; 247 248 // If Opcode is a COMPARE opcode for which an associated COMPARE AND 249 // BRANCH exists, return the opcode for the latter, otherwise return 0. 250 // MI, if nonnull, is the compare instruction. 251 unsigned getCompareAndBranch(unsigned Opcode, 252 SystemZII::CompareAndBranchType Type, 253 const MachineInstr *MI = nullptr) const; 254 255 // Emit code before MBBI in MI to move immediate value Value into 256 // physical register Reg. 257 void loadImmediate(MachineBasicBlock &MBB, 258 MachineBasicBlock::iterator MBBI, 259 unsigned Reg, uint64_t Value) const; 260 }; 261 } // end namespace llvm 262 263 #endif 264