1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the SystemZ implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SystemZ.h" 15 #include "SystemZInstrBuilder.h" 16 #include "SystemZInstrInfo.h" 17 #include "SystemZMachineFunctionInfo.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZGenInstrInfo.inc" 20 #include "llvm/Function.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/PseudoSourceValue.h" 25 #include "llvm/Support/ErrorHandling.h" 26 using namespace llvm; 27 28 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) 29 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)), 30 RI(tm, *this), TM(tm) { 31 // Fill the spill offsets map 32 static const unsigned SpillOffsTab[][2] = { 33 { SystemZ::R2D, 0x10 }, 34 { SystemZ::R3D, 0x18 }, 35 { SystemZ::R4D, 0x20 }, 36 { SystemZ::R5D, 0x28 }, 37 { SystemZ::R6D, 0x30 }, 38 { SystemZ::R7D, 0x38 }, 39 { SystemZ::R8D, 0x40 }, 40 { SystemZ::R9D, 0x48 }, 41 { SystemZ::R10D, 0x50 }, 42 { SystemZ::R11D, 0x58 }, 43 { SystemZ::R12D, 0x60 }, 44 { SystemZ::R13D, 0x68 }, 45 { SystemZ::R14D, 0x70 }, 46 { SystemZ::R15D, 0x78 } 47 }; 48 49 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS); 50 51 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i) 52 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1]; 53 } 54 55 /// isGVStub - Return true if the GV requires an extra load to get the 56 /// real address. 57 static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) { 58 return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false); 59 } 60 61 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MI, 63 unsigned SrcReg, bool isKill, int FrameIdx, 64 const TargetRegisterClass *RC, 65 const TargetRegisterInfo *TRI) const { 66 DebugLoc DL; 67 if (MI != MBB.end()) DL = MI->getDebugLoc(); 68 69 unsigned Opc = 0; 70 if (RC == &SystemZ::GR32RegClass || 71 RC == &SystemZ::ADDR32RegClass) 72 Opc = SystemZ::MOV32mr; 73 else if (RC == &SystemZ::GR64RegClass || 74 RC == &SystemZ::ADDR64RegClass) { 75 Opc = SystemZ::MOV64mr; 76 } else if (RC == &SystemZ::FP32RegClass) { 77 Opc = SystemZ::FMOV32mr; 78 } else if (RC == &SystemZ::FP64RegClass) { 79 Opc = SystemZ::FMOV64mr; 80 } else if (RC == &SystemZ::GR64PRegClass) { 81 Opc = SystemZ::MOV64Pmr; 82 } else if (RC == &SystemZ::GR128RegClass) { 83 Opc = SystemZ::MOV128mr; 84 } else 85 llvm_unreachable("Unsupported regclass to store"); 86 87 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 88 .addReg(SrcReg, getKillRegState(isKill)); 89 } 90 91 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 92 MachineBasicBlock::iterator MI, 93 unsigned DestReg, int FrameIdx, 94 const TargetRegisterClass *RC, 95 const TargetRegisterInfo *TRI) const{ 96 DebugLoc DL; 97 if (MI != MBB.end()) DL = MI->getDebugLoc(); 98 99 unsigned Opc = 0; 100 if (RC == &SystemZ::GR32RegClass || 101 RC == &SystemZ::ADDR32RegClass) 102 Opc = SystemZ::MOV32rm; 103 else if (RC == &SystemZ::GR64RegClass || 104 RC == &SystemZ::ADDR64RegClass) { 105 Opc = SystemZ::MOV64rm; 106 } else if (RC == &SystemZ::FP32RegClass) { 107 Opc = SystemZ::FMOV32rm; 108 } else if (RC == &SystemZ::FP64RegClass) { 109 Opc = SystemZ::FMOV64rm; 110 } else if (RC == &SystemZ::GR64PRegClass) { 111 Opc = SystemZ::MOV64Prm; 112 } else if (RC == &SystemZ::GR128RegClass) { 113 Opc = SystemZ::MOV128rm; 114 } else 115 llvm_unreachable("Unsupported regclass to load"); 116 117 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 118 } 119 120 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 121 MachineBasicBlock::iterator I, DebugLoc DL, 122 unsigned DestReg, unsigned SrcReg, 123 bool KillSrc) const { 124 unsigned Opc; 125 if (SystemZ::GR64RegClass.contains(DestReg, SrcReg)) 126 Opc = SystemZ::MOV64rr; 127 else if (SystemZ::GR32RegClass.contains(DestReg, SrcReg)) 128 Opc = SystemZ::MOV32rr; 129 else if (SystemZ::GR64PRegClass.contains(DestReg, SrcReg)) 130 Opc = SystemZ::MOV64rrP; 131 else if (SystemZ::GR128RegClass.contains(DestReg, SrcReg)) 132 Opc = SystemZ::MOV128rr; 133 else if (SystemZ::FP32RegClass.contains(DestReg, SrcReg)) 134 Opc = SystemZ::FMOV32rr; 135 else if (SystemZ::FP64RegClass.contains(DestReg, SrcReg)) 136 Opc = SystemZ::FMOV64rr; 137 else 138 llvm_unreachable("Impossible reg-to-reg copy"); 139 140 BuildMI(MBB, I, DL, get(Opc), DestReg) 141 .addReg(SrcReg, getKillRegState(KillSrc)); 142 } 143 144 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 145 int &FrameIndex) const { 146 switch (MI->getOpcode()) { 147 default: break; 148 case SystemZ::MOV32rm: 149 case SystemZ::MOV32rmy: 150 case SystemZ::MOV64rm: 151 case SystemZ::MOVSX32rm8: 152 case SystemZ::MOVSX32rm16y: 153 case SystemZ::MOVSX64rm8: 154 case SystemZ::MOVSX64rm16: 155 case SystemZ::MOVSX64rm32: 156 case SystemZ::MOVZX32rm8: 157 case SystemZ::MOVZX32rm16: 158 case SystemZ::MOVZX64rm8: 159 case SystemZ::MOVZX64rm16: 160 case SystemZ::MOVZX64rm32: 161 case SystemZ::FMOV32rm: 162 case SystemZ::FMOV32rmy: 163 case SystemZ::FMOV64rm: 164 case SystemZ::FMOV64rmy: 165 case SystemZ::MOV64Prm: 166 case SystemZ::MOV64Prmy: 167 case SystemZ::MOV128rm: 168 if (MI->getOperand(1).isFI() && 169 MI->getOperand(2).isImm() && MI->getOperand(3).isReg() && 170 MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) { 171 FrameIndex = MI->getOperand(1).getIndex(); 172 return MI->getOperand(0).getReg(); 173 } 174 break; 175 } 176 return 0; 177 } 178 179 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 180 int &FrameIndex) const { 181 switch (MI->getOpcode()) { 182 default: break; 183 case SystemZ::MOV32mr: 184 case SystemZ::MOV32mry: 185 case SystemZ::MOV64mr: 186 case SystemZ::MOV32m8r: 187 case SystemZ::MOV32m8ry: 188 case SystemZ::MOV32m16r: 189 case SystemZ::MOV32m16ry: 190 case SystemZ::MOV64m8r: 191 case SystemZ::MOV64m8ry: 192 case SystemZ::MOV64m16r: 193 case SystemZ::MOV64m16ry: 194 case SystemZ::MOV64m32r: 195 case SystemZ::MOV64m32ry: 196 case SystemZ::FMOV32mr: 197 case SystemZ::FMOV32mry: 198 case SystemZ::FMOV64mr: 199 case SystemZ::FMOV64mry: 200 case SystemZ::MOV64Pmr: 201 case SystemZ::MOV64Pmry: 202 case SystemZ::MOV128mr: 203 if (MI->getOperand(0).isFI() && 204 MI->getOperand(1).isImm() && MI->getOperand(2).isReg() && 205 MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) { 206 FrameIndex = MI->getOperand(0).getIndex(); 207 return MI->getOperand(3).getReg(); 208 } 209 break; 210 } 211 return 0; 212 } 213 214 bool 215 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 216 MachineBasicBlock::iterator MI, 217 const std::vector<CalleeSavedInfo> &CSI, 218 const TargetRegisterInfo *TRI) const { 219 if (CSI.empty()) 220 return false; 221 222 DebugLoc DL; 223 if (MI != MBB.end()) DL = MI->getDebugLoc(); 224 225 MachineFunction &MF = *MBB.getParent(); 226 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 227 unsigned CalleeFrameSize = 0; 228 229 // Scan the callee-saved and find the bounds of register spill area. 230 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0; 231 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 232 unsigned Reg = CSI[i].getReg(); 233 if (!SystemZ::FP64RegClass.contains(Reg)) { 234 unsigned Offset = RegSpillOffsets[Reg]; 235 CalleeFrameSize += 8; 236 if (StartOffset > Offset) { 237 LowReg = Reg; StartOffset = Offset; 238 } 239 if (EndOffset < Offset) { 240 HighReg = Reg; EndOffset = RegSpillOffsets[Reg]; 241 } 242 } 243 } 244 245 // Save information for epilogue inserter. 246 MFI->setCalleeSavedFrameSize(CalleeFrameSize); 247 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg); 248 249 // Save GPRs 250 if (StartOffset) { 251 // Build a store instruction. Use STORE MULTIPLE instruction if there are many 252 // registers to store, otherwise - just STORE. 253 MachineInstrBuilder MIB = 254 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 255 SystemZ::MOV64mr : SystemZ::MOV64mrm))); 256 257 // Add store operands. 258 MIB.addReg(SystemZ::R15D).addImm(StartOffset); 259 if (LowReg == HighReg) 260 MIB.addReg(0); 261 MIB.addReg(LowReg, RegState::Kill); 262 if (LowReg != HighReg) 263 MIB.addReg(HighReg, RegState::Kill); 264 265 // Do a second scan adding regs as being killed by instruction 266 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 267 unsigned Reg = CSI[i].getReg(); 268 // Add the callee-saved register as live-in. It's killed at the spill. 269 MBB.addLiveIn(Reg); 270 if (Reg != LowReg && Reg != HighReg) 271 MIB.addReg(Reg, RegState::ImplicitKill); 272 } 273 } 274 275 // Save FPRs 276 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 277 unsigned Reg = CSI[i].getReg(); 278 if (SystemZ::FP64RegClass.contains(Reg)) { 279 MBB.addLiveIn(Reg); 280 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), 281 &SystemZ::FP64RegClass, &RI); 282 } 283 } 284 285 return true; 286 } 287 288 bool 289 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 290 MachineBasicBlock::iterator MI, 291 const std::vector<CalleeSavedInfo> &CSI, 292 const TargetRegisterInfo *TRI) const { 293 if (CSI.empty()) 294 return false; 295 296 DebugLoc DL; 297 if (MI != MBB.end()) DL = MI->getDebugLoc(); 298 299 MachineFunction &MF = *MBB.getParent(); 300 const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo(); 301 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 302 303 // Restore FP registers 304 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 305 unsigned Reg = CSI[i].getReg(); 306 if (SystemZ::FP64RegClass.contains(Reg)) 307 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 308 &SystemZ::FP64RegClass, &RI); 309 } 310 311 // Restore GP registers 312 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg(); 313 unsigned StartOffset = RegSpillOffsets[LowReg]; 314 315 if (StartOffset) { 316 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many 317 // registers to load, otherwise - just LOAD. 318 MachineInstrBuilder MIB = 319 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 320 SystemZ::MOV64rm : SystemZ::MOV64rmm))); 321 // Add store operands. 322 MIB.addReg(LowReg, RegState::Define); 323 if (LowReg != HighReg) 324 MIB.addReg(HighReg, RegState::Define); 325 326 MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)); 327 MIB.addImm(StartOffset); 328 if (LowReg == HighReg) 329 MIB.addReg(0); 330 331 // Do a second scan adding regs as being defined by instruction 332 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 333 unsigned Reg = CSI[i].getReg(); 334 if (Reg != LowReg && Reg != HighReg) 335 MIB.addReg(Reg, RegState::ImplicitDefine); 336 } 337 } 338 339 return true; 340 } 341 342 bool SystemZInstrInfo:: 343 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 344 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 345 346 SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm()); 347 Cond[0].setImm(getOppositeCondition(CC)); 348 return false; 349 } 350 351 bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 352 const TargetInstrDesc &TID = MI->getDesc(); 353 if (!TID.isTerminator()) return false; 354 355 // Conditional branch is a special case. 356 if (TID.isBranch() && !TID.isBarrier()) 357 return true; 358 if (!TID.isPredicable()) 359 return true; 360 return !isPredicated(MI); 361 } 362 363 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 364 MachineBasicBlock *&TBB, 365 MachineBasicBlock *&FBB, 366 SmallVectorImpl<MachineOperand> &Cond, 367 bool AllowModify) const { 368 // Start from the bottom of the block and work up, examining the 369 // terminator instructions. 370 MachineBasicBlock::iterator I = MBB.end(); 371 while (I != MBB.begin()) { 372 --I; 373 if (I->isDebugValue()) 374 continue; 375 // Working from the bottom, when we see a non-terminator 376 // instruction, we're done. 377 if (!isUnpredicatedTerminator(I)) 378 break; 379 380 // A terminator that isn't a branch can't easily be handled 381 // by this analysis. 382 if (!I->getDesc().isBranch()) 383 return true; 384 385 // Handle unconditional branches. 386 if (I->getOpcode() == SystemZ::JMP) { 387 if (!AllowModify) { 388 TBB = I->getOperand(0).getMBB(); 389 continue; 390 } 391 392 // If the block has any instructions after a JMP, delete them. 393 while (llvm::next(I) != MBB.end()) 394 llvm::next(I)->eraseFromParent(); 395 Cond.clear(); 396 FBB = 0; 397 398 // Delete the JMP if it's equivalent to a fall-through. 399 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 400 TBB = 0; 401 I->eraseFromParent(); 402 I = MBB.end(); 403 continue; 404 } 405 406 // TBB is used to indicate the unconditinal destination. 407 TBB = I->getOperand(0).getMBB(); 408 continue; 409 } 410 411 // Handle conditional branches. 412 SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); 413 if (BranchCode == SystemZCC::INVALID) 414 return true; // Can't handle indirect branch. 415 416 // Working from the bottom, handle the first conditional branch. 417 if (Cond.empty()) { 418 FBB = TBB; 419 TBB = I->getOperand(0).getMBB(); 420 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 421 continue; 422 } 423 424 // Handle subsequent conditional branches. Only handle the case where all 425 // conditional branches branch to the same destination. 426 assert(Cond.size() == 1); 427 assert(TBB); 428 429 // Only handle the case where all conditional branches branch to 430 // the same destination. 431 if (TBB != I->getOperand(0).getMBB()) 432 return true; 433 434 SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm(); 435 // If the conditions are the same, we can leave them alone. 436 if (OldBranchCode == BranchCode) 437 continue; 438 439 return true; 440 } 441 442 return false; 443 } 444 445 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 446 MachineBasicBlock::iterator I = MBB.end(); 447 unsigned Count = 0; 448 449 while (I != MBB.begin()) { 450 --I; 451 if (I->isDebugValue()) 452 continue; 453 if (I->getOpcode() != SystemZ::JMP && 454 getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID) 455 break; 456 // Remove the branch. 457 I->eraseFromParent(); 458 I = MBB.end(); 459 ++Count; 460 } 461 462 return Count; 463 } 464 465 unsigned 466 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 467 MachineBasicBlock *FBB, 468 const SmallVectorImpl<MachineOperand> &Cond, 469 DebugLoc DL) const { 470 // Shouldn't be a fall through. 471 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 472 assert((Cond.size() == 1 || Cond.size() == 0) && 473 "SystemZ branch conditions have one component!"); 474 475 if (Cond.empty()) { 476 // Unconditional branch? 477 assert(!FBB && "Unconditional branch with multiple successors!"); 478 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB); 479 return 1; 480 } 481 482 // Conditional branch. 483 unsigned Count = 0; 484 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm(); 485 BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB); 486 ++Count; 487 488 if (FBB) { 489 // Two-way Conditional branch. Insert the second branch. 490 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB); 491 ++Count; 492 } 493 return Count; 494 } 495 496 const TargetInstrDesc& 497 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const { 498 switch (CC) { 499 default: 500 llvm_unreachable("Unknown condition code!"); 501 case SystemZCC::O: return get(SystemZ::JO); 502 case SystemZCC::H: return get(SystemZ::JH); 503 case SystemZCC::NLE: return get(SystemZ::JNLE); 504 case SystemZCC::L: return get(SystemZ::JL); 505 case SystemZCC::NHE: return get(SystemZ::JNHE); 506 case SystemZCC::LH: return get(SystemZ::JLH); 507 case SystemZCC::NE: return get(SystemZ::JNE); 508 case SystemZCC::E: return get(SystemZ::JE); 509 case SystemZCC::NLH: return get(SystemZ::JNLH); 510 case SystemZCC::HE: return get(SystemZ::JHE); 511 case SystemZCC::NL: return get(SystemZ::JNL); 512 case SystemZCC::LE: return get(SystemZ::JLE); 513 case SystemZCC::NH: return get(SystemZ::JNH); 514 case SystemZCC::NO: return get(SystemZ::JNO); 515 } 516 } 517 518 SystemZCC::CondCodes 519 SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const { 520 switch (Opc) { 521 default: return SystemZCC::INVALID; 522 case SystemZ::JO: return SystemZCC::O; 523 case SystemZ::JH: return SystemZCC::H; 524 case SystemZ::JNLE: return SystemZCC::NLE; 525 case SystemZ::JL: return SystemZCC::L; 526 case SystemZ::JNHE: return SystemZCC::NHE; 527 case SystemZ::JLH: return SystemZCC::LH; 528 case SystemZ::JNE: return SystemZCC::NE; 529 case SystemZ::JE: return SystemZCC::E; 530 case SystemZ::JNLH: return SystemZCC::NLH; 531 case SystemZ::JHE: return SystemZCC::HE; 532 case SystemZ::JNL: return SystemZCC::NL; 533 case SystemZ::JLE: return SystemZCC::LE; 534 case SystemZ::JNH: return SystemZCC::NH; 535 case SystemZ::JNO: return SystemZCC::NO; 536 } 537 } 538 539 SystemZCC::CondCodes 540 SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const { 541 switch (CC) { 542 default: 543 llvm_unreachable("Invalid condition!"); 544 case SystemZCC::O: return SystemZCC::NO; 545 case SystemZCC::H: return SystemZCC::NH; 546 case SystemZCC::NLE: return SystemZCC::LE; 547 case SystemZCC::L: return SystemZCC::NL; 548 case SystemZCC::NHE: return SystemZCC::HE; 549 case SystemZCC::LH: return SystemZCC::NLH; 550 case SystemZCC::NE: return SystemZCC::E; 551 case SystemZCC::E: return SystemZCC::NE; 552 case SystemZCC::NLH: return SystemZCC::LH; 553 case SystemZCC::HE: return SystemZCC::NHE; 554 case SystemZCC::NL: return SystemZCC::L; 555 case SystemZCC::LE: return SystemZCC::NLE; 556 case SystemZCC::NH: return SystemZCC::H; 557 case SystemZCC::NO: return SystemZCC::O; 558 } 559 } 560 561 const TargetInstrDesc& 562 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const { 563 switch (Opc) { 564 default: 565 llvm_unreachable("Don't have long disp version of this instruction"); 566 case SystemZ::MOV32mr: return get(SystemZ::MOV32mry); 567 case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy); 568 case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y); 569 case SystemZ::MOV32m8r: return get(SystemZ::MOV32m8ry); 570 case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry); 571 case SystemZ::MOV64m8r: return get(SystemZ::MOV64m8ry); 572 case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry); 573 case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry); 574 case SystemZ::MOV8mi: return get(SystemZ::MOV8miy); 575 case SystemZ::MUL32rm: return get(SystemZ::MUL32rmy); 576 case SystemZ::CMP32rm: return get(SystemZ::CMP32rmy); 577 case SystemZ::UCMP32rm: return get(SystemZ::UCMP32rmy); 578 case SystemZ::FMOV32mr: return get(SystemZ::FMOV32mry); 579 case SystemZ::FMOV64mr: return get(SystemZ::FMOV64mry); 580 case SystemZ::FMOV32rm: return get(SystemZ::FMOV32rmy); 581 case SystemZ::FMOV64rm: return get(SystemZ::FMOV64rmy); 582 case SystemZ::MOV64Pmr: return get(SystemZ::MOV64Pmry); 583 case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy); 584 } 585 } 586