1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZInstrInfo.h"
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 
21 using namespace llvm;
22 
23 #define GET_INSTRINFO_CTOR_DTOR
24 #define GET_INSTRMAP_INFO
25 #include "SystemZGenInstrInfo.inc"
26 
27 // Return a mask with Count low bits set.
28 static uint64_t allOnes(unsigned int Count) {
29   return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
30 }
31 
32 // Reg should be a 32-bit GPR.  Return true if it is a high register rather
33 // than a low register.
34 static bool isHighReg(unsigned int Reg) {
35   if (SystemZ::GRH32BitRegClass.contains(Reg))
36     return true;
37   assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
38   return false;
39 }
40 
41 // Pin the vtable to this file.
42 void SystemZInstrInfo::anchor() {}
43 
44 SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
45   : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
46     RI(), STI(sti) {
47 }
48 
49 // MI is a 128-bit load or store.  Split it into two 64-bit loads or stores,
50 // each having the opcode given by NewOpcode.
51 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
52                                  unsigned NewOpcode) const {
53   MachineBasicBlock *MBB = MI->getParent();
54   MachineFunction &MF = *MBB->getParent();
55 
56   // Get two load or store instructions.  Use the original instruction for one
57   // of them (arbitrarily the second here) and create a clone for the other.
58   MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
59   MBB->insert(MI, EarlierMI);
60 
61   // Set up the two 64-bit registers.
62   MachineOperand &HighRegOp = EarlierMI->getOperand(0);
63   MachineOperand &LowRegOp = MI->getOperand(0);
64   HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
65   LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
66 
67   // The address in the first (high) instruction is already correct.
68   // Adjust the offset in the second (low) instruction.
69   MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
70   MachineOperand &LowOffsetOp = MI->getOperand(2);
71   LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
72 
73   // Clear the kill flags for the base and index registers in the first
74   // instruction.
75   EarlierMI->getOperand(1).setIsKill(false);
76   EarlierMI->getOperand(3).setIsKill(false);
77 
78   // Set the opcodes.
79   unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
80   unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
81   assert(HighOpcode && LowOpcode && "Both offsets should be in range");
82 
83   EarlierMI->setDesc(get(HighOpcode));
84   MI->setDesc(get(LowOpcode));
85 }
86 
87 // Split ADJDYNALLOC instruction MI.
88 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
89   MachineBasicBlock *MBB = MI->getParent();
90   MachineFunction &MF = *MBB->getParent();
91   MachineFrameInfo *MFFrame = MF.getFrameInfo();
92   MachineOperand &OffsetMO = MI->getOperand(2);
93 
94   uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
95                      SystemZMC::CallFrameSize +
96                      OffsetMO.getImm());
97   unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
98   assert(NewOpcode && "No support for huge argument lists yet");
99   MI->setDesc(get(NewOpcode));
100   OffsetMO.setImm(Offset);
101 }
102 
103 // MI is an RI-style pseudo instruction.  Replace it with LowOpcode
104 // if the first operand is a low GR32 and HighOpcode if the first operand
105 // is a high GR32.  ConvertHigh is true if LowOpcode takes a signed operand
106 // and HighOpcode takes an unsigned 32-bit operand.  In those cases,
107 // MI has the same kind of operand as LowOpcode, so needs to be converted
108 // if HighOpcode is used.
109 void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
110                                       unsigned HighOpcode,
111                                       bool ConvertHigh) const {
112   unsigned Reg = MI->getOperand(0).getReg();
113   bool IsHigh = isHighReg(Reg);
114   MI->setDesc(get(IsHigh ? HighOpcode : LowOpcode));
115   if (IsHigh && ConvertHigh)
116     MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
117 }
118 
119 // MI is a three-operand RIE-style pseudo instruction.  Replace it with
120 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
121 // followed by HighOpcode or LowOpcode, depending on whether the target
122 // is a high or low GR32.
123 void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
124                                        unsigned LowOpcodeK,
125                                        unsigned HighOpcode) const {
126   unsigned DestReg = MI->getOperand(0).getReg();
127   unsigned SrcReg = MI->getOperand(1).getReg();
128   bool DestIsHigh = isHighReg(DestReg);
129   bool SrcIsHigh = isHighReg(SrcReg);
130   if (!DestIsHigh && !SrcIsHigh)
131     MI->setDesc(get(LowOpcodeK));
132   else {
133     emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
134                   DestReg, SrcReg, SystemZ::LR, 32,
135                   MI->getOperand(1).isKill());
136     MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
137     MI->getOperand(1).setReg(DestReg);
138     MI->tieOperands(0, 1);
139   }
140 }
141 
142 // MI is an RXY-style pseudo instruction.  Replace it with LowOpcode
143 // if the first operand is a low GR32 and HighOpcode if the first operand
144 // is a high GR32.
145 void SystemZInstrInfo::expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
146                                        unsigned HighOpcode) const {
147   unsigned Reg = MI->getOperand(0).getReg();
148   unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
149                                        MI->getOperand(2).getImm());
150   MI->setDesc(get(Opcode));
151 }
152 
153 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
154 // of one GRX32 into another.  Replace it with LowOpcode if both operands
155 // are low registers, otherwise use RISB[LH]G.
156 void SystemZInstrInfo::expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
157                                         unsigned Size) const {
158   emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
159                 MI->getOperand(0).getReg(), MI->getOperand(1).getReg(),
160                 LowOpcode, Size, MI->getOperand(1).isKill());
161   MI->eraseFromParent();
162 }
163 
164 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
165   MachineBasicBlock *MBB = MI->getParent();
166   MachineFunction &MF = *MBB->getParent();
167   const unsigned Reg = MI->getOperand(0).getReg();
168 
169   // Conveniently, all 4 instructions are cloned from LOAD_STACK_GUARD,
170   // so they already have operand 0 set to reg.
171 
172   // ear <reg>, %a0
173   MachineInstr *Ear1MI = MF.CloneMachineInstr(MI);
174   MBB->insert(MI, Ear1MI);
175   Ear1MI->setDesc(get(SystemZ::EAR));
176   MachineInstrBuilder(MF, Ear1MI).addImm(0);
177 
178   // sllg <reg>, <reg>, 32
179   MachineInstr *SllgMI = MF.CloneMachineInstr(MI);
180   MBB->insert(MI, SllgMI);
181   SllgMI->setDesc(get(SystemZ::SLLG));
182   MachineInstrBuilder(MF, SllgMI).addReg(Reg).addReg(0).addImm(32);
183 
184   // ear <reg>, %a1
185   MachineInstr *Ear2MI = MF.CloneMachineInstr(MI);
186   MBB->insert(MI, Ear2MI);
187   Ear2MI->setDesc(get(SystemZ::EAR));
188   MachineInstrBuilder(MF, Ear2MI).addImm(1);
189 
190   // lg <reg>, 40(<reg>)
191   MI->setDesc(get(SystemZ::LG));
192   MachineInstrBuilder(MF, MI).addReg(Reg).addImm(40).addReg(0);
193 }
194 
195 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
196 // DestReg before MBBI in MBB.  Use LowLowOpcode when both DestReg and SrcReg
197 // are low registers, otherwise use RISB[LH]G.  Size is the number of bits
198 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
199 // KillSrc is true if this move is the last use of SrcReg.
200 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
201                                      MachineBasicBlock::iterator MBBI,
202                                      DebugLoc DL, unsigned DestReg,
203                                      unsigned SrcReg, unsigned LowLowOpcode,
204                                      unsigned Size, bool KillSrc) const {
205   unsigned Opcode;
206   bool DestIsHigh = isHighReg(DestReg);
207   bool SrcIsHigh = isHighReg(SrcReg);
208   if (DestIsHigh && SrcIsHigh)
209     Opcode = SystemZ::RISBHH;
210   else if (DestIsHigh && !SrcIsHigh)
211     Opcode = SystemZ::RISBHL;
212   else if (!DestIsHigh && SrcIsHigh)
213     Opcode = SystemZ::RISBLH;
214   else {
215     BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
216       .addReg(SrcReg, getKillRegState(KillSrc));
217     return;
218   }
219   unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
220   BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
221     .addReg(DestReg, RegState::Undef)
222     .addReg(SrcReg, getKillRegState(KillSrc))
223     .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
224 }
225 
226 // If MI is a simple load or store for a frame object, return the register
227 // it loads or stores and set FrameIndex to the index of the frame object.
228 // Return 0 otherwise.
229 //
230 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
231 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
232                         unsigned Flag) {
233   const MCInstrDesc &MCID = MI->getDesc();
234   if ((MCID.TSFlags & Flag) &&
235       MI->getOperand(1).isFI() &&
236       MI->getOperand(2).getImm() == 0 &&
237       MI->getOperand(3).getReg() == 0) {
238     FrameIndex = MI->getOperand(1).getIndex();
239     return MI->getOperand(0).getReg();
240   }
241   return 0;
242 }
243 
244 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
245                                                int &FrameIndex) const {
246   return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
247 }
248 
249 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
250                                               int &FrameIndex) const {
251   return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
252 }
253 
254 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
255                                        int &DestFrameIndex,
256                                        int &SrcFrameIndex) const {
257   // Check for MVC 0(Length,FI1),0(FI2)
258   const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
259   if (MI->getOpcode() != SystemZ::MVC ||
260       !MI->getOperand(0).isFI() ||
261       MI->getOperand(1).getImm() != 0 ||
262       !MI->getOperand(3).isFI() ||
263       MI->getOperand(4).getImm() != 0)
264     return false;
265 
266   // Check that Length covers the full slots.
267   int64_t Length = MI->getOperand(2).getImm();
268   unsigned FI1 = MI->getOperand(0).getIndex();
269   unsigned FI2 = MI->getOperand(3).getIndex();
270   if (MFI->getObjectSize(FI1) != Length ||
271       MFI->getObjectSize(FI2) != Length)
272     return false;
273 
274   DestFrameIndex = FI1;
275   SrcFrameIndex = FI2;
276   return true;
277 }
278 
279 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
280                                      MachineBasicBlock *&TBB,
281                                      MachineBasicBlock *&FBB,
282                                      SmallVectorImpl<MachineOperand> &Cond,
283                                      bool AllowModify) const {
284   // Most of the code and comments here are boilerplate.
285 
286   // Start from the bottom of the block and work up, examining the
287   // terminator instructions.
288   MachineBasicBlock::iterator I = MBB.end();
289   while (I != MBB.begin()) {
290     --I;
291     if (I->isDebugValue())
292       continue;
293 
294     // Working from the bottom, when we see a non-terminator instruction, we're
295     // done.
296     if (!isUnpredicatedTerminator(*I))
297       break;
298 
299     // A terminator that isn't a branch can't easily be handled by this
300     // analysis.
301     if (!I->isBranch())
302       return true;
303 
304     // Can't handle indirect branches.
305     SystemZII::Branch Branch(getBranchInfo(I));
306     if (!Branch.Target->isMBB())
307       return true;
308 
309     // Punt on compound branches.
310     if (Branch.Type != SystemZII::BranchNormal)
311       return true;
312 
313     if (Branch.CCMask == SystemZ::CCMASK_ANY) {
314       // Handle unconditional branches.
315       if (!AllowModify) {
316         TBB = Branch.Target->getMBB();
317         continue;
318       }
319 
320       // If the block has any instructions after a JMP, delete them.
321       while (std::next(I) != MBB.end())
322         std::next(I)->eraseFromParent();
323 
324       Cond.clear();
325       FBB = nullptr;
326 
327       // Delete the JMP if it's equivalent to a fall-through.
328       if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
329         TBB = nullptr;
330         I->eraseFromParent();
331         I = MBB.end();
332         continue;
333       }
334 
335       // TBB is used to indicate the unconditinal destination.
336       TBB = Branch.Target->getMBB();
337       continue;
338     }
339 
340     // Working from the bottom, handle the first conditional branch.
341     if (Cond.empty()) {
342       // FIXME: add X86-style branch swap
343       FBB = TBB;
344       TBB = Branch.Target->getMBB();
345       Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
346       Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
347       continue;
348     }
349 
350     // Handle subsequent conditional branches.
351     assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
352 
353     // Only handle the case where all conditional branches branch to the same
354     // destination.
355     if (TBB != Branch.Target->getMBB())
356       return true;
357 
358     // If the conditions are the same, we can leave them alone.
359     unsigned OldCCValid = Cond[0].getImm();
360     unsigned OldCCMask = Cond[1].getImm();
361     if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
362       continue;
363 
364     // FIXME: Try combining conditions like X86 does.  Should be easy on Z!
365     return false;
366   }
367 
368   return false;
369 }
370 
371 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
372   // Most of the code and comments here are boilerplate.
373   MachineBasicBlock::iterator I = MBB.end();
374   unsigned Count = 0;
375 
376   while (I != MBB.begin()) {
377     --I;
378     if (I->isDebugValue())
379       continue;
380     if (!I->isBranch())
381       break;
382     if (!getBranchInfo(I).Target->isMBB())
383       break;
384     // Remove the branch.
385     I->eraseFromParent();
386     I = MBB.end();
387     ++Count;
388   }
389 
390   return Count;
391 }
392 
393 bool SystemZInstrInfo::
394 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
395   assert(Cond.size() == 2 && "Invalid condition");
396   Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
397   return false;
398 }
399 
400 unsigned
401 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
402                                MachineBasicBlock *FBB,
403                                ArrayRef<MachineOperand> Cond,
404                                DebugLoc DL) const {
405   // In this function we output 32-bit branches, which should always
406   // have enough range.  They can be shortened and relaxed by later code
407   // in the pipeline, if desired.
408 
409   // Shouldn't be a fall through.
410   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
411   assert((Cond.size() == 2 || Cond.size() == 0) &&
412          "SystemZ branch conditions have one component!");
413 
414   if (Cond.empty()) {
415     // Unconditional branch?
416     assert(!FBB && "Unconditional branch with multiple successors!");
417     BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
418     return 1;
419   }
420 
421   // Conditional branch.
422   unsigned Count = 0;
423   unsigned CCValid = Cond[0].getImm();
424   unsigned CCMask = Cond[1].getImm();
425   BuildMI(&MBB, DL, get(SystemZ::BRC))
426     .addImm(CCValid).addImm(CCMask).addMBB(TBB);
427   ++Count;
428 
429   if (FBB) {
430     // Two-way Conditional branch. Insert the second branch.
431     BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
432     ++Count;
433   }
434   return Count;
435 }
436 
437 bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
438                                       unsigned &SrcReg, unsigned &SrcReg2,
439                                       int &Mask, int &Value) const {
440   assert(MI->isCompare() && "Caller should have checked for a comparison");
441 
442   if (MI->getNumExplicitOperands() == 2 &&
443       MI->getOperand(0).isReg() &&
444       MI->getOperand(1).isImm()) {
445     SrcReg = MI->getOperand(0).getReg();
446     SrcReg2 = 0;
447     Value = MI->getOperand(1).getImm();
448     Mask = ~0;
449     return true;
450   }
451 
452   return false;
453 }
454 
455 // If Reg is a virtual register, return its definition, otherwise return null.
456 static MachineInstr *getDef(unsigned Reg,
457                             const MachineRegisterInfo *MRI) {
458   if (TargetRegisterInfo::isPhysicalRegister(Reg))
459     return nullptr;
460   return MRI->getUniqueVRegDef(Reg);
461 }
462 
463 // Return true if MI is a shift of type Opcode by Imm bits.
464 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
465   return (MI->getOpcode() == Opcode &&
466           !MI->getOperand(2).getReg() &&
467           MI->getOperand(3).getImm() == Imm);
468 }
469 
470 // If the destination of MI has no uses, delete it as dead.
471 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
472   if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
473     MI->eraseFromParent();
474 }
475 
476 // Compare compares SrcReg against zero.  Check whether SrcReg contains
477 // the result of an IPM sequence whose input CC survives until Compare,
478 // and whether Compare is therefore redundant.  Delete it and return
479 // true if so.
480 static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
481                                   const MachineRegisterInfo *MRI,
482                                   const TargetRegisterInfo *TRI) {
483   MachineInstr *LGFR = nullptr;
484   MachineInstr *RLL = getDef(SrcReg, MRI);
485   if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
486     LGFR = RLL;
487     RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
488   }
489   if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
490     return false;
491 
492   MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
493   if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
494     return false;
495 
496   MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
497   if (!IPM || IPM->getOpcode() != SystemZ::IPM)
498     return false;
499 
500   // Check that there are no assignments to CC between the IPM and Compare,
501   if (IPM->getParent() != Compare->getParent())
502     return false;
503   MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
504   for (++MBBI; MBBI != MBBE; ++MBBI) {
505     MachineInstr *MI = MBBI;
506     if (MI->modifiesRegister(SystemZ::CC, TRI))
507       return false;
508   }
509 
510   Compare->eraseFromParent();
511   if (LGFR)
512     eraseIfDead(LGFR, MRI);
513   eraseIfDead(RLL, MRI);
514   eraseIfDead(SRL, MRI);
515   eraseIfDead(IPM, MRI);
516 
517   return true;
518 }
519 
520 bool
521 SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
522                                        unsigned SrcReg, unsigned SrcReg2,
523                                        int Mask, int Value,
524                                        const MachineRegisterInfo *MRI) const {
525   assert(!SrcReg2 && "Only optimizing constant comparisons so far");
526   bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
527   return Value == 0 && !IsLogical &&
528          removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
529 }
530 
531 // If Opcode is a move that has a conditional variant, return that variant,
532 // otherwise return 0.
533 static unsigned getConditionalMove(unsigned Opcode) {
534   switch (Opcode) {
535   case SystemZ::LR:  return SystemZ::LOCR;
536   case SystemZ::LGR: return SystemZ::LOCGR;
537   default:           return 0;
538   }
539 }
540 
541 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
542   unsigned Opcode = MI.getOpcode();
543   if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
544     return true;
545   if (Opcode == SystemZ::Return ||
546       Opcode == SystemZ::CallJG ||
547       Opcode == SystemZ::CallBR)
548     return true;
549   return false;
550 }
551 
552 bool SystemZInstrInfo::
553 isProfitableToIfCvt(MachineBasicBlock &MBB,
554                     unsigned NumCycles, unsigned ExtraPredCycles,
555                     BranchProbability Probability) const {
556   // Avoid using conditional returns at the end of a loop (since then
557   // we'd need to emit an unconditional branch to the beginning anyway,
558   // making the loop body longer).  This doesn't apply for low-probability
559   // loops (eg. compare-and-swap retry), so just decide based on branch
560   // probability instead of looping structure.
561   if (MBB.succ_empty() && Probability < BranchProbability(1, 8))
562     return false;
563   // For now only convert single instructions.
564   return NumCycles == 1;
565 }
566 
567 bool SystemZInstrInfo::
568 isProfitableToIfCvt(MachineBasicBlock &TMBB,
569                     unsigned NumCyclesT, unsigned ExtraPredCyclesT,
570                     MachineBasicBlock &FMBB,
571                     unsigned NumCyclesF, unsigned ExtraPredCyclesF,
572                     BranchProbability Probability) const {
573   // For now avoid converting mutually-exclusive cases.
574   return false;
575 }
576 
577 bool SystemZInstrInfo::
578 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
579                           BranchProbability Probability) const {
580   // For now only duplicate single instructions.
581   return NumCycles == 1;
582 }
583 
584 bool SystemZInstrInfo::PredicateInstruction(
585     MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
586   assert(Pred.size() == 2 && "Invalid condition");
587   unsigned CCValid = Pred[0].getImm();
588   unsigned CCMask = Pred[1].getImm();
589   assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
590   unsigned Opcode = MI.getOpcode();
591   if (STI.hasLoadStoreOnCond()) {
592     if (unsigned CondOpcode = getConditionalMove(Opcode)) {
593       MI.setDesc(get(CondOpcode));
594       MachineInstrBuilder(*MI.getParent()->getParent(), MI)
595           .addImm(CCValid)
596           .addImm(CCMask)
597           .addReg(SystemZ::CC, RegState::Implicit);
598       return true;
599     }
600   }
601   if (Opcode == SystemZ::Return) {
602     MI.setDesc(get(SystemZ::CondReturn));
603     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
604       .addImm(CCValid).addImm(CCMask)
605       .addReg(SystemZ::CC, RegState::Implicit);
606     return true;
607   }
608   if (Opcode == SystemZ::CallJG) {
609     const GlobalValue *Global = MI.getOperand(0).getGlobal();
610     const uint32_t *RegMask = MI.getOperand(1).getRegMask();
611     MI.RemoveOperand(1);
612     MI.RemoveOperand(0);
613     MI.setDesc(get(SystemZ::CallBRCL));
614     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
615       .addImm(CCValid).addImm(CCMask)
616       .addGlobalAddress(Global)
617       .addRegMask(RegMask)
618       .addReg(SystemZ::CC, RegState::Implicit);
619     return true;
620   }
621   if (Opcode == SystemZ::CallBR) {
622     const uint32_t *RegMask = MI.getOperand(0).getRegMask();
623     MI.RemoveOperand(0);
624     MI.setDesc(get(SystemZ::CallBCR));
625     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
626       .addImm(CCValid).addImm(CCMask)
627       .addRegMask(RegMask)
628       .addReg(SystemZ::CC, RegState::Implicit);
629     return true;
630   }
631   return false;
632 }
633 
634 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
635                                    MachineBasicBlock::iterator MBBI,
636                                    DebugLoc DL, unsigned DestReg,
637                                    unsigned SrcReg, bool KillSrc) const {
638   // Split 128-bit GPR moves into two 64-bit moves.  This handles ADDR128 too.
639   if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
640     copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
641                 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
642     copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
643                 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
644     return;
645   }
646 
647   if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
648     emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
649     return;
650   }
651 
652   // Everything else needs only one instruction.
653   unsigned Opcode;
654   if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
655     Opcode = SystemZ::LGR;
656   else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
657     // For z13 we prefer LDR over LER to avoid partial register dependencies.
658     Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
659   else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
660     Opcode = SystemZ::LDR;
661   else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
662     Opcode = SystemZ::LXR;
663   else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
664     Opcode = SystemZ::VLR32;
665   else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
666     Opcode = SystemZ::VLR64;
667   else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
668     Opcode = SystemZ::VLR;
669   else
670     llvm_unreachable("Impossible reg-to-reg copy");
671 
672   BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
673     .addReg(SrcReg, getKillRegState(KillSrc));
674 }
675 
676 void SystemZInstrInfo::storeRegToStackSlot(
677     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
678     bool isKill, int FrameIdx, const TargetRegisterClass *RC,
679     const TargetRegisterInfo *TRI) const {
680   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
681 
682   // Callers may expect a single instruction, so keep 128-bit moves
683   // together for now and lower them after register allocation.
684   unsigned LoadOpcode, StoreOpcode;
685   getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
686   addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
687                         .addReg(SrcReg, getKillRegState(isKill)),
688                     FrameIdx);
689 }
690 
691 void SystemZInstrInfo::loadRegFromStackSlot(
692     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
693     int FrameIdx, const TargetRegisterClass *RC,
694     const TargetRegisterInfo *TRI) const {
695   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
696 
697   // Callers may expect a single instruction, so keep 128-bit moves
698   // together for now and lower them after register allocation.
699   unsigned LoadOpcode, StoreOpcode;
700   getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
701   addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
702                     FrameIdx);
703 }
704 
705 // Return true if MI is a simple load or store with a 12-bit displacement
706 // and no index.  Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
707 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
708   const MCInstrDesc &MCID = MI->getDesc();
709   return ((MCID.TSFlags & Flag) &&
710           isUInt<12>(MI->getOperand(2).getImm()) &&
711           MI->getOperand(3).getReg() == 0);
712 }
713 
714 namespace {
715 struct LogicOp {
716   LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
717   LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
718     : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
719 
720   explicit operator bool() const { return RegSize; }
721 
722   unsigned RegSize, ImmLSB, ImmSize;
723 };
724 } // end anonymous namespace
725 
726 static LogicOp interpretAndImmediate(unsigned Opcode) {
727   switch (Opcode) {
728   case SystemZ::NILMux: return LogicOp(32,  0, 16);
729   case SystemZ::NIHMux: return LogicOp(32, 16, 16);
730   case SystemZ::NILL64: return LogicOp(64,  0, 16);
731   case SystemZ::NILH64: return LogicOp(64, 16, 16);
732   case SystemZ::NIHL64: return LogicOp(64, 32, 16);
733   case SystemZ::NIHH64: return LogicOp(64, 48, 16);
734   case SystemZ::NIFMux: return LogicOp(32,  0, 32);
735   case SystemZ::NILF64: return LogicOp(64,  0, 32);
736   case SystemZ::NIHF64: return LogicOp(64, 32, 32);
737   default:              return LogicOp();
738   }
739 }
740 
741 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
742   if (OldMI->registerDefIsDead(SystemZ::CC)) {
743     MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
744     if (CCDef != nullptr)
745       CCDef->setIsDead(true);
746   }
747 }
748 
749 // Used to return from convertToThreeAddress after replacing two-address
750 // instruction OldMI with three-address instruction NewMI.
751 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
752                                                  MachineInstr *NewMI,
753                                                  LiveVariables *LV) {
754   if (LV) {
755     unsigned NumOps = OldMI->getNumOperands();
756     for (unsigned I = 1; I < NumOps; ++I) {
757       MachineOperand &Op = OldMI->getOperand(I);
758       if (Op.isReg() && Op.isKill())
759         LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
760     }
761   }
762   transferDeadCC(OldMI, NewMI);
763   return NewMI;
764 }
765 
766 MachineInstr *
767 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
768                                         MachineBasicBlock::iterator &MBBI,
769                                         LiveVariables *LV) const {
770   MachineInstr *MI = MBBI;
771   MachineBasicBlock *MBB = MI->getParent();
772   MachineFunction *MF = MBB->getParent();
773   MachineRegisterInfo &MRI = MF->getRegInfo();
774 
775   unsigned Opcode = MI->getOpcode();
776   unsigned NumOps = MI->getNumOperands();
777 
778   // Try to convert something like SLL into SLLK, if supported.
779   // We prefer to keep the two-operand form where possible both
780   // because it tends to be shorter and because some instructions
781   // have memory forms that can be used during spilling.
782   if (STI.hasDistinctOps()) {
783     MachineOperand &Dest = MI->getOperand(0);
784     MachineOperand &Src = MI->getOperand(1);
785     unsigned DestReg = Dest.getReg();
786     unsigned SrcReg = Src.getReg();
787     // AHIMux is only really a three-operand instruction when both operands
788     // are low registers.  Try to constrain both operands to be low if
789     // possible.
790     if (Opcode == SystemZ::AHIMux &&
791         TargetRegisterInfo::isVirtualRegister(DestReg) &&
792         TargetRegisterInfo::isVirtualRegister(SrcReg) &&
793         MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
794         MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
795       MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
796       MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
797     }
798     int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
799     if (ThreeOperandOpcode >= 0) {
800       // Create three address instruction without adding the implicit
801       // operands. Those will instead be copied over from the original
802       // instruction by the loop below.
803       MachineInstrBuilder MIB(*MF,
804                               MF->CreateMachineInstr(get(ThreeOperandOpcode),
805                                     MI->getDebugLoc(), /*NoImplicit=*/true));
806       MIB.addOperand(Dest);
807       // Keep the kill state, but drop the tied flag.
808       MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
809       // Keep the remaining operands as-is.
810       for (unsigned I = 2; I < NumOps; ++I)
811         MIB.addOperand(MI->getOperand(I));
812       MBB->insert(MI, MIB);
813       return finishConvertToThreeAddress(MI, MIB, LV);
814     }
815   }
816 
817   // Try to convert an AND into an RISBG-type instruction.
818   if (LogicOp And = interpretAndImmediate(Opcode)) {
819     uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
820     // AND IMMEDIATE leaves the other bits of the register unchanged.
821     Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
822     unsigned Start, End;
823     if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
824       unsigned NewOpcode;
825       if (And.RegSize == 64) {
826         NewOpcode = SystemZ::RISBG;
827         // Prefer RISBGN if available, since it does not clobber CC.
828         if (STI.hasMiscellaneousExtensions())
829           NewOpcode = SystemZ::RISBGN;
830       } else {
831         NewOpcode = SystemZ::RISBMux;
832         Start &= 31;
833         End &= 31;
834       }
835       MachineOperand &Dest = MI->getOperand(0);
836       MachineOperand &Src = MI->getOperand(1);
837       MachineInstrBuilder MIB =
838         BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
839         .addOperand(Dest).addReg(0)
840         .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
841         .addImm(Start).addImm(End + 128).addImm(0);
842       return finishConvertToThreeAddress(MI, MIB, LV);
843     }
844   }
845   return nullptr;
846 }
847 
848 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
849     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
850     MachineBasicBlock::iterator InsertPt, int FrameIndex,
851     LiveIntervals *LIS) const {
852   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
853   const MachineFrameInfo *MFI = MF.getFrameInfo();
854   unsigned Size = MFI->getObjectSize(FrameIndex);
855   unsigned Opcode = MI->getOpcode();
856 
857   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
858     if (LIS != nullptr &&
859         (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
860         isInt<8>(MI->getOperand(2).getImm()) &&
861         !MI->getOperand(3).getReg()) {
862 
863       // Check CC liveness, since new instruction introduces a dead
864       // def of CC.
865       MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
866       LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
867       ++CCUnit;
868       assert (!CCUnit.isValid() && "CC only has one reg unit.");
869       SlotIndex MISlot =
870         LIS->getSlotIndexes()->getInstructionIndex(*MI).getRegSlot();
871       if (!CCLiveRange.liveAt(MISlot)) {
872         // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
873         MachineInstr *BuiltMI =
874           BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
875                   get(SystemZ::AGSI))
876           .addFrameIndex(FrameIndex)
877           .addImm(0)
878           .addImm(MI->getOperand(2).getImm());
879         BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
880         CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
881         return BuiltMI;
882       }
883     }
884     return nullptr;
885   }
886 
887   // All other cases require a single operand.
888   if (Ops.size() != 1)
889     return nullptr;
890 
891   unsigned OpNum = Ops[0];
892   assert(Size == MF.getRegInfo()
893          .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
894          "Invalid size combination");
895 
896   if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
897       OpNum == 0 &&
898       isInt<8>(MI->getOperand(2).getImm())) {
899     // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
900     Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
901     MachineInstr *BuiltMI =
902       BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
903                    get(Opcode))
904         .addFrameIndex(FrameIndex)
905         .addImm(0)
906         .addImm(MI->getOperand(2).getImm());
907     transferDeadCC(MI, BuiltMI);
908     return BuiltMI;
909   }
910 
911   if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
912     bool Op0IsGPR = (Opcode == SystemZ::LGDR);
913     bool Op1IsGPR = (Opcode == SystemZ::LDGR);
914     // If we're spilling the destination of an LDGR or LGDR, store the
915     // source register instead.
916     if (OpNum == 0) {
917       unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
918       return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
919                      get(StoreOpcode))
920           .addOperand(MI->getOperand(1))
921           .addFrameIndex(FrameIndex)
922           .addImm(0)
923           .addReg(0);
924     }
925     // If we're spilling the source of an LDGR or LGDR, load the
926     // destination register instead.
927     if (OpNum == 1) {
928       unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
929       unsigned Dest = MI->getOperand(0).getReg();
930       return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
931                      get(LoadOpcode), Dest)
932           .addFrameIndex(FrameIndex)
933           .addImm(0)
934           .addReg(0);
935     }
936   }
937 
938   // Look for cases where the source of a simple store or the destination
939   // of a simple load is being spilled.  Try to use MVC instead.
940   //
941   // Although MVC is in practice a fast choice in these cases, it is still
942   // logically a bytewise copy.  This means that we cannot use it if the
943   // load or store is volatile.  We also wouldn't be able to use MVC if
944   // the two memories partially overlap, but that case cannot occur here,
945   // because we know that one of the memories is a full frame index.
946   //
947   // For performance reasons, we also want to avoid using MVC if the addresses
948   // might be equal.  We don't worry about that case here, because spill slot
949   // coloring happens later, and because we have special code to remove
950   // MVCs that turn out to be redundant.
951   if (OpNum == 0 && MI->hasOneMemOperand()) {
952     MachineMemOperand *MMO = *MI->memoperands_begin();
953     if (MMO->getSize() == Size && !MMO->isVolatile()) {
954       // Handle conversion of loads.
955       if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
956         return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
957                        get(SystemZ::MVC))
958             .addFrameIndex(FrameIndex)
959             .addImm(0)
960             .addImm(Size)
961             .addOperand(MI->getOperand(1))
962             .addImm(MI->getOperand(2).getImm())
963             .addMemOperand(MMO);
964       }
965       // Handle conversion of stores.
966       if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
967         return BuildMI(*InsertPt->getParent(), InsertPt, MI->getDebugLoc(),
968                        get(SystemZ::MVC))
969             .addOperand(MI->getOperand(1))
970             .addImm(MI->getOperand(2).getImm())
971             .addImm(Size)
972             .addFrameIndex(FrameIndex)
973             .addImm(0)
974             .addMemOperand(MMO);
975       }
976     }
977   }
978 
979   // If the spilled operand is the final one, try to change <INSN>R
980   // into <INSN>.
981   int MemOpcode = SystemZ::getMemOpcode(Opcode);
982   if (MemOpcode >= 0) {
983     unsigned NumOps = MI->getNumExplicitOperands();
984     if (OpNum == NumOps - 1) {
985       const MCInstrDesc &MemDesc = get(MemOpcode);
986       uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
987       assert(AccessBytes != 0 && "Size of access should be known");
988       assert(AccessBytes <= Size && "Access outside the frame index");
989       uint64_t Offset = Size - AccessBytes;
990       MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
991                                         MI->getDebugLoc(), get(MemOpcode));
992       for (unsigned I = 0; I < OpNum; ++I)
993         MIB.addOperand(MI->getOperand(I));
994       MIB.addFrameIndex(FrameIndex).addImm(Offset);
995       if (MemDesc.TSFlags & SystemZII::HasIndex)
996         MIB.addReg(0);
997       transferDeadCC(MI, MIB);
998       return MIB;
999     }
1000   }
1001 
1002   return nullptr;
1003 }
1004 
1005 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1006     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
1007     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI,
1008     LiveIntervals *LIS) const {
1009   return nullptr;
1010 }
1011 
1012 bool
1013 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1014   switch (MI->getOpcode()) {
1015   case SystemZ::L128:
1016     splitMove(MI, SystemZ::LG);
1017     return true;
1018 
1019   case SystemZ::ST128:
1020     splitMove(MI, SystemZ::STG);
1021     return true;
1022 
1023   case SystemZ::LX:
1024     splitMove(MI, SystemZ::LD);
1025     return true;
1026 
1027   case SystemZ::STX:
1028     splitMove(MI, SystemZ::STD);
1029     return true;
1030 
1031   case SystemZ::LBMux:
1032     expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1033     return true;
1034 
1035   case SystemZ::LHMux:
1036     expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1037     return true;
1038 
1039   case SystemZ::LLCRMux:
1040     expandZExtPseudo(MI, SystemZ::LLCR, 8);
1041     return true;
1042 
1043   case SystemZ::LLHRMux:
1044     expandZExtPseudo(MI, SystemZ::LLHR, 16);
1045     return true;
1046 
1047   case SystemZ::LLCMux:
1048     expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1049     return true;
1050 
1051   case SystemZ::LLHMux:
1052     expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1053     return true;
1054 
1055   case SystemZ::LMux:
1056     expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1057     return true;
1058 
1059   case SystemZ::STCMux:
1060     expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1061     return true;
1062 
1063   case SystemZ::STHMux:
1064     expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1065     return true;
1066 
1067   case SystemZ::STMux:
1068     expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1069     return true;
1070 
1071   case SystemZ::LHIMux:
1072     expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1073     return true;
1074 
1075   case SystemZ::IIFMux:
1076     expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1077     return true;
1078 
1079   case SystemZ::IILMux:
1080     expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1081     return true;
1082 
1083   case SystemZ::IIHMux:
1084     expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1085     return true;
1086 
1087   case SystemZ::NIFMux:
1088     expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1089     return true;
1090 
1091   case SystemZ::NILMux:
1092     expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1093     return true;
1094 
1095   case SystemZ::NIHMux:
1096     expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1097     return true;
1098 
1099   case SystemZ::OIFMux:
1100     expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1101     return true;
1102 
1103   case SystemZ::OILMux:
1104     expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1105     return true;
1106 
1107   case SystemZ::OIHMux:
1108     expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1109     return true;
1110 
1111   case SystemZ::XIFMux:
1112     expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1113     return true;
1114 
1115   case SystemZ::TMLMux:
1116     expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1117     return true;
1118 
1119   case SystemZ::TMHMux:
1120     expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1121     return true;
1122 
1123   case SystemZ::AHIMux:
1124     expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1125     return true;
1126 
1127   case SystemZ::AHIMuxK:
1128     expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1129     return true;
1130 
1131   case SystemZ::AFIMux:
1132     expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1133     return true;
1134 
1135   case SystemZ::CFIMux:
1136     expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1137     return true;
1138 
1139   case SystemZ::CLFIMux:
1140     expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1141     return true;
1142 
1143   case SystemZ::CMux:
1144     expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1145     return true;
1146 
1147   case SystemZ::CLMux:
1148     expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1149     return true;
1150 
1151   case SystemZ::RISBMux: {
1152     bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
1153     bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
1154     if (SrcIsHigh == DestIsHigh)
1155       MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1156     else {
1157       MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1158       MI->getOperand(5).setImm(MI->getOperand(5).getImm() ^ 32);
1159     }
1160     return true;
1161   }
1162 
1163   case SystemZ::ADJDYNALLOC:
1164     splitAdjDynAlloc(MI);
1165     return true;
1166 
1167   case TargetOpcode::LOAD_STACK_GUARD:
1168     expandLoadStackGuard(MI);
1169     return true;
1170 
1171   default:
1172     return false;
1173   }
1174 }
1175 
1176 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
1177   if (MI->getOpcode() == TargetOpcode::INLINEASM) {
1178     const MachineFunction *MF = MI->getParent()->getParent();
1179     const char *AsmStr = MI->getOperand(0).getSymbolName();
1180     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1181   }
1182   return MI->getDesc().getSize();
1183 }
1184 
1185 SystemZII::Branch
1186 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
1187   switch (MI->getOpcode()) {
1188   case SystemZ::BR:
1189   case SystemZ::J:
1190   case SystemZ::JG:
1191     return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1192                              SystemZ::CCMASK_ANY, &MI->getOperand(0));
1193 
1194   case SystemZ::BRC:
1195   case SystemZ::BRCL:
1196     return SystemZII::Branch(SystemZII::BranchNormal,
1197                              MI->getOperand(0).getImm(),
1198                              MI->getOperand(1).getImm(), &MI->getOperand(2));
1199 
1200   case SystemZ::BRCT:
1201     return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1202                              SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1203 
1204   case SystemZ::BRCTG:
1205     return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1206                              SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1207 
1208   case SystemZ::CIJ:
1209   case SystemZ::CRJ:
1210     return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1211                              MI->getOperand(2).getImm(), &MI->getOperand(3));
1212 
1213   case SystemZ::CLIJ:
1214   case SystemZ::CLRJ:
1215     return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1216                              MI->getOperand(2).getImm(), &MI->getOperand(3));
1217 
1218   case SystemZ::CGIJ:
1219   case SystemZ::CGRJ:
1220     return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1221                              MI->getOperand(2).getImm(), &MI->getOperand(3));
1222 
1223   case SystemZ::CLGIJ:
1224   case SystemZ::CLGRJ:
1225     return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1226                              MI->getOperand(2).getImm(), &MI->getOperand(3));
1227 
1228   default:
1229     llvm_unreachable("Unrecognized branch opcode");
1230   }
1231 }
1232 
1233 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1234                                            unsigned &LoadOpcode,
1235                                            unsigned &StoreOpcode) const {
1236   if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1237     LoadOpcode = SystemZ::L;
1238     StoreOpcode = SystemZ::ST;
1239   } else if (RC == &SystemZ::GRH32BitRegClass) {
1240     LoadOpcode = SystemZ::LFH;
1241     StoreOpcode = SystemZ::STFH;
1242   } else if (RC == &SystemZ::GRX32BitRegClass) {
1243     LoadOpcode = SystemZ::LMux;
1244     StoreOpcode = SystemZ::STMux;
1245   } else if (RC == &SystemZ::GR64BitRegClass ||
1246              RC == &SystemZ::ADDR64BitRegClass) {
1247     LoadOpcode = SystemZ::LG;
1248     StoreOpcode = SystemZ::STG;
1249   } else if (RC == &SystemZ::GR128BitRegClass ||
1250              RC == &SystemZ::ADDR128BitRegClass) {
1251     LoadOpcode = SystemZ::L128;
1252     StoreOpcode = SystemZ::ST128;
1253   } else if (RC == &SystemZ::FP32BitRegClass) {
1254     LoadOpcode = SystemZ::LE;
1255     StoreOpcode = SystemZ::STE;
1256   } else if (RC == &SystemZ::FP64BitRegClass) {
1257     LoadOpcode = SystemZ::LD;
1258     StoreOpcode = SystemZ::STD;
1259   } else if (RC == &SystemZ::FP128BitRegClass) {
1260     LoadOpcode = SystemZ::LX;
1261     StoreOpcode = SystemZ::STX;
1262   } else if (RC == &SystemZ::VR32BitRegClass) {
1263     LoadOpcode = SystemZ::VL32;
1264     StoreOpcode = SystemZ::VST32;
1265   } else if (RC == &SystemZ::VR64BitRegClass) {
1266     LoadOpcode = SystemZ::VL64;
1267     StoreOpcode = SystemZ::VST64;
1268   } else if (RC == &SystemZ::VF128BitRegClass ||
1269              RC == &SystemZ::VR128BitRegClass) {
1270     LoadOpcode = SystemZ::VL;
1271     StoreOpcode = SystemZ::VST;
1272   } else
1273     llvm_unreachable("Unsupported regclass to load or store");
1274 }
1275 
1276 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1277                                               int64_t Offset) const {
1278   const MCInstrDesc &MCID = get(Opcode);
1279   int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1280   if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1281     // Get the instruction to use for unsigned 12-bit displacements.
1282     int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1283     if (Disp12Opcode >= 0)
1284       return Disp12Opcode;
1285 
1286     // All address-related instructions can use unsigned 12-bit
1287     // displacements.
1288     return Opcode;
1289   }
1290   if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1291     // Get the instruction to use for signed 20-bit displacements.
1292     int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1293     if (Disp20Opcode >= 0)
1294       return Disp20Opcode;
1295 
1296     // Check whether Opcode allows signed 20-bit displacements.
1297     if (MCID.TSFlags & SystemZII::Has20BitOffset)
1298       return Opcode;
1299   }
1300   return 0;
1301 }
1302 
1303 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1304   switch (Opcode) {
1305   case SystemZ::L:      return SystemZ::LT;
1306   case SystemZ::LY:     return SystemZ::LT;
1307   case SystemZ::LG:     return SystemZ::LTG;
1308   case SystemZ::LGF:    return SystemZ::LTGF;
1309   case SystemZ::LR:     return SystemZ::LTR;
1310   case SystemZ::LGFR:   return SystemZ::LTGFR;
1311   case SystemZ::LGR:    return SystemZ::LTGR;
1312   case SystemZ::LER:    return SystemZ::LTEBR;
1313   case SystemZ::LDR:    return SystemZ::LTDBR;
1314   case SystemZ::LXR:    return SystemZ::LTXBR;
1315   case SystemZ::LCDFR:  return SystemZ::LCDBR;
1316   case SystemZ::LPDFR:  return SystemZ::LPDBR;
1317   case SystemZ::LNDFR:  return SystemZ::LNDBR;
1318   case SystemZ::LCDFR_32:  return SystemZ::LCEBR;
1319   case SystemZ::LPDFR_32:  return SystemZ::LPEBR;
1320   case SystemZ::LNDFR_32:  return SystemZ::LNEBR;
1321   // On zEC12 we prefer to use RISBGN.  But if there is a chance to
1322   // actually use the condition code, we may turn it back into RISGB.
1323   // Note that RISBG is not really a "load-and-test" instruction,
1324   // but sets the same condition code values, so is OK to use here.
1325   case SystemZ::RISBGN: return SystemZ::RISBG;
1326   default:              return 0;
1327   }
1328 }
1329 
1330 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1331 // have already been filtered out.  Store the first set bit in LSB and
1332 // the number of set bits in Length if so.
1333 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1334   unsigned First = findFirstSet(Mask);
1335   uint64_t Top = (Mask >> First) + 1;
1336   if ((Top & -Top) == Top) {
1337     LSB = First;
1338     Length = findFirstSet(Top);
1339     return true;
1340   }
1341   return false;
1342 }
1343 
1344 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1345                                    unsigned &Start, unsigned &End) const {
1346   // Reject trivial all-zero masks.
1347   Mask &= allOnes(BitSize);
1348   if (Mask == 0)
1349     return false;
1350 
1351   // Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
1352   // the msb and End specifies the index of the lsb.
1353   unsigned LSB, Length;
1354   if (isStringOfOnes(Mask, LSB, Length)) {
1355     Start = 63 - (LSB + Length - 1);
1356     End = 63 - LSB;
1357     return true;
1358   }
1359 
1360   // Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
1361   // of the low 1s and End specifies the lsb of the high 1s.
1362   if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1363     assert(LSB > 0 && "Bottom bit must be set");
1364     assert(LSB + Length < BitSize && "Top bit must be set");
1365     Start = 63 - (LSB - 1);
1366     End = 63 - (LSB + Length);
1367     return true;
1368   }
1369 
1370   return false;
1371 }
1372 
1373 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
1374                                                SystemZII::CompareAndBranchType Type,
1375                                                const MachineInstr *MI) const {
1376   switch (Opcode) {
1377   case SystemZ::CHI:
1378   case SystemZ::CGHI:
1379     if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1380       return 0;
1381     break;
1382   case SystemZ::CLFI:
1383   case SystemZ::CLGFI:
1384     if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1385       return 0;
1386   }
1387   switch (Type) {
1388   case SystemZII::CompareAndBranch:
1389     switch (Opcode) {
1390     case SystemZ::CR:
1391       return SystemZ::CRJ;
1392     case SystemZ::CGR:
1393       return SystemZ::CGRJ;
1394     case SystemZ::CHI:
1395       return SystemZ::CIJ;
1396     case SystemZ::CGHI:
1397       return SystemZ::CGIJ;
1398     case SystemZ::CLR:
1399       return SystemZ::CLRJ;
1400     case SystemZ::CLGR:
1401       return SystemZ::CLGRJ;
1402     case SystemZ::CLFI:
1403       return SystemZ::CLIJ;
1404     case SystemZ::CLGFI:
1405       return SystemZ::CLGIJ;
1406     default:
1407       return 0;
1408     }
1409   case SystemZII::CompareAndReturn:
1410     switch (Opcode) {
1411     case SystemZ::CR:
1412       return SystemZ::CRBReturn;
1413     case SystemZ::CGR:
1414       return SystemZ::CGRBReturn;
1415     case SystemZ::CHI:
1416       return SystemZ::CIBReturn;
1417     case SystemZ::CGHI:
1418       return SystemZ::CGIBReturn;
1419     case SystemZ::CLR:
1420       return SystemZ::CLRBReturn;
1421     case SystemZ::CLGR:
1422       return SystemZ::CLGRBReturn;
1423     case SystemZ::CLFI:
1424       return SystemZ::CLIBReturn;
1425     case SystemZ::CLGFI:
1426       return SystemZ::CLGIBReturn;
1427     default:
1428       return 0;
1429     }
1430   case SystemZII::CompareAndSibcall:
1431     switch (Opcode) {
1432     case SystemZ::CR:
1433       return SystemZ::CRBCall;
1434     case SystemZ::CGR:
1435       return SystemZ::CGRBCall;
1436     case SystemZ::CHI:
1437       return SystemZ::CIBCall;
1438     case SystemZ::CGHI:
1439       return SystemZ::CGIBCall;
1440     case SystemZ::CLR:
1441       return SystemZ::CLRBCall;
1442     case SystemZ::CLGR:
1443       return SystemZ::CLGRBCall;
1444     case SystemZ::CLFI:
1445       return SystemZ::CLIBCall;
1446     case SystemZ::CLGFI:
1447       return SystemZ::CLGIBCall;
1448     default:
1449       return 0;
1450     }
1451   }
1452   return 0;
1453 }
1454 
1455 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1456                                      MachineBasicBlock::iterator MBBI,
1457                                      unsigned Reg, uint64_t Value) const {
1458   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1459   unsigned Opcode;
1460   if (isInt<16>(Value))
1461     Opcode = SystemZ::LGHI;
1462   else if (SystemZ::isImmLL(Value))
1463     Opcode = SystemZ::LLILL;
1464   else if (SystemZ::isImmLH(Value)) {
1465     Opcode = SystemZ::LLILH;
1466     Value >>= 16;
1467   } else {
1468     assert(isInt<32>(Value) && "Huge values not handled yet");
1469     Opcode = SystemZ::LGFI;
1470   }
1471   BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1472 }
1473