1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the SystemZ implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SystemZ.h" 15 #include "SystemZInstrBuilder.h" 16 #include "SystemZInstrInfo.h" 17 #include "SystemZMachineFunctionInfo.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZGenInstrInfo.inc" 20 #include "llvm/Function.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/PseudoSourceValue.h" 25 #include "llvm/Support/ErrorHandling.h" 26 using namespace llvm; 27 28 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) 29 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)), 30 RI(tm, *this), TM(tm) { 31 // Fill the spill offsets map 32 static const unsigned SpillOffsTab[][2] = { 33 { SystemZ::R2D, 0x10 }, 34 { SystemZ::R3D, 0x18 }, 35 { SystemZ::R4D, 0x20 }, 36 { SystemZ::R5D, 0x28 }, 37 { SystemZ::R6D, 0x30 }, 38 { SystemZ::R7D, 0x38 }, 39 { SystemZ::R8D, 0x40 }, 40 { SystemZ::R9D, 0x48 }, 41 { SystemZ::R10D, 0x50 }, 42 { SystemZ::R11D, 0x58 }, 43 { SystemZ::R12D, 0x60 }, 44 { SystemZ::R13D, 0x68 }, 45 { SystemZ::R14D, 0x70 }, 46 { SystemZ::R15D, 0x78 } 47 }; 48 49 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS); 50 51 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i) 52 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1]; 53 } 54 55 /// isGVStub - Return true if the GV requires an extra load to get the 56 /// real address. 57 static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) { 58 return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false); 59 } 60 61 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MI, 63 unsigned SrcReg, bool isKill, int FrameIdx, 64 const TargetRegisterClass *RC, 65 const TargetRegisterInfo *TRI) const { 66 DebugLoc DL; 67 if (MI != MBB.end()) DL = MI->getDebugLoc(); 68 69 unsigned Opc = 0; 70 if (RC == &SystemZ::GR32RegClass || 71 RC == &SystemZ::ADDR32RegClass) 72 Opc = SystemZ::MOV32mr; 73 else if (RC == &SystemZ::GR64RegClass || 74 RC == &SystemZ::ADDR64RegClass) { 75 Opc = SystemZ::MOV64mr; 76 } else if (RC == &SystemZ::FP32RegClass) { 77 Opc = SystemZ::FMOV32mr; 78 } else if (RC == &SystemZ::FP64RegClass) { 79 Opc = SystemZ::FMOV64mr; 80 } else if (RC == &SystemZ::GR64PRegClass) { 81 Opc = SystemZ::MOV64Pmr; 82 } else if (RC == &SystemZ::GR128RegClass) { 83 Opc = SystemZ::MOV128mr; 84 } else 85 llvm_unreachable("Unsupported regclass to store"); 86 87 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 88 .addReg(SrcReg, getKillRegState(isKill)); 89 } 90 91 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 92 MachineBasicBlock::iterator MI, 93 unsigned DestReg, int FrameIdx, 94 const TargetRegisterClass *RC, 95 const TargetRegisterInfo *TRI) const{ 96 DebugLoc DL; 97 if (MI != MBB.end()) DL = MI->getDebugLoc(); 98 99 unsigned Opc = 0; 100 if (RC == &SystemZ::GR32RegClass || 101 RC == &SystemZ::ADDR32RegClass) 102 Opc = SystemZ::MOV32rm; 103 else if (RC == &SystemZ::GR64RegClass || 104 RC == &SystemZ::ADDR64RegClass) { 105 Opc = SystemZ::MOV64rm; 106 } else if (RC == &SystemZ::FP32RegClass) { 107 Opc = SystemZ::FMOV32rm; 108 } else if (RC == &SystemZ::FP64RegClass) { 109 Opc = SystemZ::FMOV64rm; 110 } else if (RC == &SystemZ::GR64PRegClass) { 111 Opc = SystemZ::MOV64Prm; 112 } else if (RC == &SystemZ::GR128RegClass) { 113 Opc = SystemZ::MOV128rm; 114 } else 115 llvm_unreachable("Unsupported regclass to load"); 116 117 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 118 } 119 120 bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 121 MachineBasicBlock::iterator I, 122 unsigned DestReg, unsigned SrcReg, 123 const TargetRegisterClass *DestRC, 124 const TargetRegisterClass *SrcRC, 125 DebugLoc DL) const { 126 127 // Determine if DstRC and SrcRC have a common superclass. 128 const TargetRegisterClass *CommonRC = DestRC; 129 if (DestRC == SrcRC) 130 /* Same regclass for source and dest */; 131 else if (CommonRC->hasSuperClass(SrcRC)) 132 CommonRC = SrcRC; 133 else if (!CommonRC->hasSubClass(SrcRC)) 134 CommonRC = 0; 135 136 if (CommonRC) { 137 if (CommonRC == &SystemZ::GR64RegClass || 138 CommonRC == &SystemZ::ADDR64RegClass) { 139 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg); 140 } else if (CommonRC == &SystemZ::GR32RegClass || 141 CommonRC == &SystemZ::ADDR32RegClass) { 142 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg); 143 } else if (CommonRC == &SystemZ::GR64PRegClass) { 144 BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg); 145 } else if (CommonRC == &SystemZ::GR128RegClass) { 146 BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg); 147 } else if (CommonRC == &SystemZ::FP32RegClass) { 148 BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg); 149 } else if (CommonRC == &SystemZ::FP64RegClass) { 150 BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg); 151 } else { 152 return false; 153 } 154 155 return true; 156 } 157 158 if ((SrcRC == &SystemZ::GR64RegClass && 159 DestRC == &SystemZ::ADDR64RegClass) || 160 (DestRC == &SystemZ::GR64RegClass && 161 SrcRC == &SystemZ::ADDR64RegClass)) { 162 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg); 163 return true; 164 } else if ((SrcRC == &SystemZ::GR32RegClass && 165 DestRC == &SystemZ::ADDR32RegClass) || 166 (DestRC == &SystemZ::GR32RegClass && 167 SrcRC == &SystemZ::ADDR32RegClass)) { 168 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg); 169 return true; 170 } 171 172 return false; 173 } 174 175 bool 176 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, 177 unsigned &SrcReg, unsigned &DstReg, 178 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 179 switch (MI.getOpcode()) { 180 default: 181 return false; 182 case SystemZ::MOV32rr: 183 case SystemZ::MOV64rr: 184 case SystemZ::MOV64rrP: 185 case SystemZ::MOV128rr: 186 case SystemZ::FMOV32rr: 187 case SystemZ::FMOV64rr: 188 assert(MI.getNumOperands() >= 2 && 189 MI.getOperand(0).isReg() && 190 MI.getOperand(1).isReg() && 191 "invalid register-register move instruction"); 192 SrcReg = MI.getOperand(1).getReg(); 193 DstReg = MI.getOperand(0).getReg(); 194 SrcSubIdx = MI.getOperand(1).getSubReg(); 195 DstSubIdx = MI.getOperand(0).getSubReg(); 196 return true; 197 } 198 } 199 200 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 201 int &FrameIndex) const { 202 switch (MI->getOpcode()) { 203 default: break; 204 case SystemZ::MOV32rm: 205 case SystemZ::MOV32rmy: 206 case SystemZ::MOV64rm: 207 case SystemZ::MOVSX32rm8: 208 case SystemZ::MOVSX32rm16y: 209 case SystemZ::MOVSX64rm8: 210 case SystemZ::MOVSX64rm16: 211 case SystemZ::MOVSX64rm32: 212 case SystemZ::MOVZX32rm8: 213 case SystemZ::MOVZX32rm16: 214 case SystemZ::MOVZX64rm8: 215 case SystemZ::MOVZX64rm16: 216 case SystemZ::MOVZX64rm32: 217 case SystemZ::FMOV32rm: 218 case SystemZ::FMOV32rmy: 219 case SystemZ::FMOV64rm: 220 case SystemZ::FMOV64rmy: 221 case SystemZ::MOV64Prm: 222 case SystemZ::MOV64Prmy: 223 case SystemZ::MOV128rm: 224 if (MI->getOperand(1).isFI() && 225 MI->getOperand(2).isImm() && MI->getOperand(3).isReg() && 226 MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) { 227 FrameIndex = MI->getOperand(1).getIndex(); 228 return MI->getOperand(0).getReg(); 229 } 230 break; 231 } 232 return 0; 233 } 234 235 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 236 int &FrameIndex) const { 237 switch (MI->getOpcode()) { 238 default: break; 239 case SystemZ::MOV32mr: 240 case SystemZ::MOV32mry: 241 case SystemZ::MOV64mr: 242 case SystemZ::MOV32m8r: 243 case SystemZ::MOV32m8ry: 244 case SystemZ::MOV32m16r: 245 case SystemZ::MOV32m16ry: 246 case SystemZ::MOV64m8r: 247 case SystemZ::MOV64m8ry: 248 case SystemZ::MOV64m16r: 249 case SystemZ::MOV64m16ry: 250 case SystemZ::MOV64m32r: 251 case SystemZ::MOV64m32ry: 252 case SystemZ::FMOV32mr: 253 case SystemZ::FMOV32mry: 254 case SystemZ::FMOV64mr: 255 case SystemZ::FMOV64mry: 256 case SystemZ::MOV64Pmr: 257 case SystemZ::MOV64Pmry: 258 case SystemZ::MOV128mr: 259 if (MI->getOperand(0).isFI() && 260 MI->getOperand(1).isImm() && MI->getOperand(2).isReg() && 261 MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) { 262 FrameIndex = MI->getOperand(0).getIndex(); 263 return MI->getOperand(3).getReg(); 264 } 265 break; 266 } 267 return 0; 268 } 269 270 bool 271 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 272 MachineBasicBlock::iterator MI, 273 const std::vector<CalleeSavedInfo> &CSI, 274 const TargetRegisterInfo *TRI) const { 275 if (CSI.empty()) 276 return false; 277 278 DebugLoc DL; 279 if (MI != MBB.end()) DL = MI->getDebugLoc(); 280 281 MachineFunction &MF = *MBB.getParent(); 282 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 283 unsigned CalleeFrameSize = 0; 284 285 // Scan the callee-saved and find the bounds of register spill area. 286 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0; 287 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 288 unsigned Reg = CSI[i].getReg(); 289 if (!SystemZ::FP64RegClass.contains(Reg)) { 290 unsigned Offset = RegSpillOffsets[Reg]; 291 CalleeFrameSize += 8; 292 if (StartOffset > Offset) { 293 LowReg = Reg; StartOffset = Offset; 294 } 295 if (EndOffset < Offset) { 296 HighReg = Reg; EndOffset = RegSpillOffsets[Reg]; 297 } 298 } 299 } 300 301 // Save information for epilogue inserter. 302 MFI->setCalleeSavedFrameSize(CalleeFrameSize); 303 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg); 304 305 // Save GPRs 306 if (StartOffset) { 307 // Build a store instruction. Use STORE MULTIPLE instruction if there are many 308 // registers to store, otherwise - just STORE. 309 MachineInstrBuilder MIB = 310 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 311 SystemZ::MOV64mr : SystemZ::MOV64mrm))); 312 313 // Add store operands. 314 MIB.addReg(SystemZ::R15D).addImm(StartOffset); 315 if (LowReg == HighReg) 316 MIB.addReg(0); 317 MIB.addReg(LowReg, RegState::Kill); 318 if (LowReg != HighReg) 319 MIB.addReg(HighReg, RegState::Kill); 320 321 // Do a second scan adding regs as being killed by instruction 322 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 323 unsigned Reg = CSI[i].getReg(); 324 // Add the callee-saved register as live-in. It's killed at the spill. 325 MBB.addLiveIn(Reg); 326 if (Reg != LowReg && Reg != HighReg) 327 MIB.addReg(Reg, RegState::ImplicitKill); 328 } 329 } 330 331 // Save FPRs 332 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 333 unsigned Reg = CSI[i].getReg(); 334 if (SystemZ::FP64RegClass.contains(Reg)) { 335 MBB.addLiveIn(Reg); 336 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), 337 &SystemZ::FP64RegClass, &RI); 338 } 339 } 340 341 return true; 342 } 343 344 bool 345 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 346 MachineBasicBlock::iterator MI, 347 const std::vector<CalleeSavedInfo> &CSI, 348 const TargetRegisterInfo *TRI) const { 349 if (CSI.empty()) 350 return false; 351 352 DebugLoc DL; 353 if (MI != MBB.end()) DL = MI->getDebugLoc(); 354 355 MachineFunction &MF = *MBB.getParent(); 356 const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo(); 357 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 358 359 // Restore FP registers 360 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 361 unsigned Reg = CSI[i].getReg(); 362 if (SystemZ::FP64RegClass.contains(Reg)) 363 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 364 &SystemZ::FP64RegClass, &RI); 365 } 366 367 // Restore GP registers 368 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg(); 369 unsigned StartOffset = RegSpillOffsets[LowReg]; 370 371 if (StartOffset) { 372 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many 373 // registers to load, otherwise - just LOAD. 374 MachineInstrBuilder MIB = 375 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 376 SystemZ::MOV64rm : SystemZ::MOV64rmm))); 377 // Add store operands. 378 MIB.addReg(LowReg, RegState::Define); 379 if (LowReg != HighReg) 380 MIB.addReg(HighReg, RegState::Define); 381 382 MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)); 383 MIB.addImm(StartOffset); 384 if (LowReg == HighReg) 385 MIB.addReg(0); 386 387 // Do a second scan adding regs as being defined by instruction 388 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 389 unsigned Reg = CSI[i].getReg(); 390 if (Reg != LowReg && Reg != HighReg) 391 MIB.addReg(Reg, RegState::ImplicitDefine); 392 } 393 } 394 395 return true; 396 } 397 398 bool SystemZInstrInfo:: 399 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 400 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 401 402 SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm()); 403 Cond[0].setImm(getOppositeCondition(CC)); 404 return false; 405 } 406 407 bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 408 const TargetInstrDesc &TID = MI->getDesc(); 409 if (!TID.isTerminator()) return false; 410 411 // Conditional branch is a special case. 412 if (TID.isBranch() && !TID.isBarrier()) 413 return true; 414 if (!TID.isPredicable()) 415 return true; 416 return !isPredicated(MI); 417 } 418 419 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 420 MachineBasicBlock *&TBB, 421 MachineBasicBlock *&FBB, 422 SmallVectorImpl<MachineOperand> &Cond, 423 bool AllowModify) const { 424 // Start from the bottom of the block and work up, examining the 425 // terminator instructions. 426 MachineBasicBlock::iterator I = MBB.end(); 427 while (I != MBB.begin()) { 428 --I; 429 if (I->isDebugValue()) 430 continue; 431 // Working from the bottom, when we see a non-terminator 432 // instruction, we're done. 433 if (!isUnpredicatedTerminator(I)) 434 break; 435 436 // A terminator that isn't a branch can't easily be handled 437 // by this analysis. 438 if (!I->getDesc().isBranch()) 439 return true; 440 441 // Handle unconditional branches. 442 if (I->getOpcode() == SystemZ::JMP) { 443 if (!AllowModify) { 444 TBB = I->getOperand(0).getMBB(); 445 continue; 446 } 447 448 // If the block has any instructions after a JMP, delete them. 449 while (llvm::next(I) != MBB.end()) 450 llvm::next(I)->eraseFromParent(); 451 Cond.clear(); 452 FBB = 0; 453 454 // Delete the JMP if it's equivalent to a fall-through. 455 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 456 TBB = 0; 457 I->eraseFromParent(); 458 I = MBB.end(); 459 continue; 460 } 461 462 // TBB is used to indicate the unconditinal destination. 463 TBB = I->getOperand(0).getMBB(); 464 continue; 465 } 466 467 // Handle conditional branches. 468 SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); 469 if (BranchCode == SystemZCC::INVALID) 470 return true; // Can't handle indirect branch. 471 472 // Working from the bottom, handle the first conditional branch. 473 if (Cond.empty()) { 474 FBB = TBB; 475 TBB = I->getOperand(0).getMBB(); 476 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 477 continue; 478 } 479 480 // Handle subsequent conditional branches. Only handle the case where all 481 // conditional branches branch to the same destination. 482 assert(Cond.size() == 1); 483 assert(TBB); 484 485 // Only handle the case where all conditional branches branch to 486 // the same destination. 487 if (TBB != I->getOperand(0).getMBB()) 488 return true; 489 490 SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm(); 491 // If the conditions are the same, we can leave them alone. 492 if (OldBranchCode == BranchCode) 493 continue; 494 495 return true; 496 } 497 498 return false; 499 } 500 501 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 502 MachineBasicBlock::iterator I = MBB.end(); 503 unsigned Count = 0; 504 505 while (I != MBB.begin()) { 506 --I; 507 if (I->isDebugValue()) 508 continue; 509 if (I->getOpcode() != SystemZ::JMP && 510 getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID) 511 break; 512 // Remove the branch. 513 I->eraseFromParent(); 514 I = MBB.end(); 515 ++Count; 516 } 517 518 return Count; 519 } 520 521 unsigned 522 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 523 MachineBasicBlock *FBB, 524 const SmallVectorImpl<MachineOperand> &Cond) const { 525 // FIXME: this should probably have a DebugLoc operand 526 DebugLoc DL; 527 // Shouldn't be a fall through. 528 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 529 assert((Cond.size() == 1 || Cond.size() == 0) && 530 "SystemZ branch conditions have one component!"); 531 532 if (Cond.empty()) { 533 // Unconditional branch? 534 assert(!FBB && "Unconditional branch with multiple successors!"); 535 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB); 536 return 1; 537 } 538 539 // Conditional branch. 540 unsigned Count = 0; 541 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm(); 542 BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB); 543 ++Count; 544 545 if (FBB) { 546 // Two-way Conditional branch. Insert the second branch. 547 BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB); 548 ++Count; 549 } 550 return Count; 551 } 552 553 const TargetInstrDesc& 554 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const { 555 switch (CC) { 556 default: 557 llvm_unreachable("Unknown condition code!"); 558 case SystemZCC::O: return get(SystemZ::JO); 559 case SystemZCC::H: return get(SystemZ::JH); 560 case SystemZCC::NLE: return get(SystemZ::JNLE); 561 case SystemZCC::L: return get(SystemZ::JL); 562 case SystemZCC::NHE: return get(SystemZ::JNHE); 563 case SystemZCC::LH: return get(SystemZ::JLH); 564 case SystemZCC::NE: return get(SystemZ::JNE); 565 case SystemZCC::E: return get(SystemZ::JE); 566 case SystemZCC::NLH: return get(SystemZ::JNLH); 567 case SystemZCC::HE: return get(SystemZ::JHE); 568 case SystemZCC::NL: return get(SystemZ::JNL); 569 case SystemZCC::LE: return get(SystemZ::JLE); 570 case SystemZCC::NH: return get(SystemZ::JNH); 571 case SystemZCC::NO: return get(SystemZ::JNO); 572 } 573 } 574 575 SystemZCC::CondCodes 576 SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const { 577 switch (Opc) { 578 default: return SystemZCC::INVALID; 579 case SystemZ::JO: return SystemZCC::O; 580 case SystemZ::JH: return SystemZCC::H; 581 case SystemZ::JNLE: return SystemZCC::NLE; 582 case SystemZ::JL: return SystemZCC::L; 583 case SystemZ::JNHE: return SystemZCC::NHE; 584 case SystemZ::JLH: return SystemZCC::LH; 585 case SystemZ::JNE: return SystemZCC::NE; 586 case SystemZ::JE: return SystemZCC::E; 587 case SystemZ::JNLH: return SystemZCC::NLH; 588 case SystemZ::JHE: return SystemZCC::HE; 589 case SystemZ::JNL: return SystemZCC::NL; 590 case SystemZ::JLE: return SystemZCC::LE; 591 case SystemZ::JNH: return SystemZCC::NH; 592 case SystemZ::JNO: return SystemZCC::NO; 593 } 594 } 595 596 SystemZCC::CondCodes 597 SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const { 598 switch (CC) { 599 default: 600 llvm_unreachable("Invalid condition!"); 601 case SystemZCC::O: return SystemZCC::NO; 602 case SystemZCC::H: return SystemZCC::NH; 603 case SystemZCC::NLE: return SystemZCC::LE; 604 case SystemZCC::L: return SystemZCC::NL; 605 case SystemZCC::NHE: return SystemZCC::HE; 606 case SystemZCC::LH: return SystemZCC::NLH; 607 case SystemZCC::NE: return SystemZCC::E; 608 case SystemZCC::E: return SystemZCC::NE; 609 case SystemZCC::NLH: return SystemZCC::LH; 610 case SystemZCC::HE: return SystemZCC::NHE; 611 case SystemZCC::NL: return SystemZCC::L; 612 case SystemZCC::LE: return SystemZCC::NLE; 613 case SystemZCC::NH: return SystemZCC::H; 614 case SystemZCC::NO: return SystemZCC::O; 615 } 616 } 617 618 const TargetInstrDesc& 619 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const { 620 switch (Opc) { 621 default: 622 llvm_unreachable("Don't have long disp version of this instruction"); 623 case SystemZ::MOV32mr: return get(SystemZ::MOV32mry); 624 case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy); 625 case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y); 626 case SystemZ::MOV32m8r: return get(SystemZ::MOV32m8ry); 627 case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry); 628 case SystemZ::MOV64m8r: return get(SystemZ::MOV64m8ry); 629 case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry); 630 case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry); 631 case SystemZ::MOV8mi: return get(SystemZ::MOV8miy); 632 case SystemZ::MUL32rm: return get(SystemZ::MUL32rmy); 633 case SystemZ::CMP32rm: return get(SystemZ::CMP32rmy); 634 case SystemZ::UCMP32rm: return get(SystemZ::UCMP32rmy); 635 case SystemZ::FMOV32mr: return get(SystemZ::FMOV32mry); 636 case SystemZ::FMOV64mr: return get(SystemZ::FMOV64mry); 637 case SystemZ::FMOV32rm: return get(SystemZ::FMOV32rmy); 638 case SystemZ::FMOV64rm: return get(SystemZ::FMOV64rmy); 639 case SystemZ::MOV64Pmr: return get(SystemZ::MOV64Pmry); 640 case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy); 641 } 642 } 643