1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZInstrInfo.h"
15 #include "MCTargetDesc/SystemZMCTargetDesc.h"
16 #include "SystemZ.h"
17 #include "SystemZInstrBuilder.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/CodeGen/LiveInterval.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineBasicBlock.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SlotIndexes.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCRegisterInfo.h"
32 #include "llvm/Support/BranchProbability.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
38 #include <cassert>
39 #include <cstdint>
40 #include <iterator>
41 
42 using namespace llvm;
43 
44 #define GET_INSTRINFO_CTOR_DTOR
45 #define GET_INSTRMAP_INFO
46 #include "SystemZGenInstrInfo.inc"
47 
48 // Return a mask with Count low bits set.
49 static uint64_t allOnes(unsigned int Count) {
50   return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
51 }
52 
53 // Reg should be a 32-bit GPR.  Return true if it is a high register rather
54 // than a low register.
55 static bool isHighReg(unsigned int Reg) {
56   if (SystemZ::GRH32BitRegClass.contains(Reg))
57     return true;
58   assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
59   return false;
60 }
61 
62 // Pin the vtable to this file.
63 void SystemZInstrInfo::anchor() {}
64 
65 SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
66   : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
67     RI(), STI(sti) {
68 }
69 
70 // MI is a 128-bit load or store.  Split it into two 64-bit loads or stores,
71 // each having the opcode given by NewOpcode.
72 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
73                                  unsigned NewOpcode) const {
74   MachineBasicBlock *MBB = MI->getParent();
75   MachineFunction &MF = *MBB->getParent();
76 
77   // Get two load or store instructions.  Use the original instruction for one
78   // of them (arbitrarily the second here) and create a clone for the other.
79   MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
80   MBB->insert(MI, EarlierMI);
81 
82   // Set up the two 64-bit registers and remember super reg and its flags.
83   MachineOperand &HighRegOp = EarlierMI->getOperand(0);
84   MachineOperand &LowRegOp = MI->getOperand(0);
85   unsigned Reg128 = LowRegOp.getReg();
86   unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
87   unsigned Reg128Undef  = getUndefRegState(LowRegOp.isUndef());
88   HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
89   LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
90 
91   if (MI->mayStore()) {
92     // Add implicit uses of the super register in case one of the subregs is
93     // undefined. We could track liveness and skip storing an undefined
94     // subreg, but this is hopefully rare (discovered with llvm-stress).
95     // If Reg128 was killed, set kill flag on MI.
96     unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
97     MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
98     MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
99   }
100 
101   // The address in the first (high) instruction is already correct.
102   // Adjust the offset in the second (low) instruction.
103   MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
104   MachineOperand &LowOffsetOp = MI->getOperand(2);
105   LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
106 
107   // Clear the kill flags on the registers in the first instruction.
108   if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
109     EarlierMI->getOperand(0).setIsKill(false);
110   EarlierMI->getOperand(1).setIsKill(false);
111   EarlierMI->getOperand(3).setIsKill(false);
112 
113   // Set the opcodes.
114   unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
115   unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
116   assert(HighOpcode && LowOpcode && "Both offsets should be in range");
117 
118   EarlierMI->setDesc(get(HighOpcode));
119   MI->setDesc(get(LowOpcode));
120 }
121 
122 // Split ADJDYNALLOC instruction MI.
123 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
124   MachineBasicBlock *MBB = MI->getParent();
125   MachineFunction &MF = *MBB->getParent();
126   MachineFrameInfo &MFFrame = MF.getFrameInfo();
127   MachineOperand &OffsetMO = MI->getOperand(2);
128 
129   uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
130                      SystemZMC::CallFrameSize +
131                      OffsetMO.getImm());
132   unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
133   assert(NewOpcode && "No support for huge argument lists yet");
134   MI->setDesc(get(NewOpcode));
135   OffsetMO.setImm(Offset);
136 }
137 
138 // MI is an RI-style pseudo instruction.  Replace it with LowOpcode
139 // if the first operand is a low GR32 and HighOpcode if the first operand
140 // is a high GR32.  ConvertHigh is true if LowOpcode takes a signed operand
141 // and HighOpcode takes an unsigned 32-bit operand.  In those cases,
142 // MI has the same kind of operand as LowOpcode, so needs to be converted
143 // if HighOpcode is used.
144 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
145                                       unsigned HighOpcode,
146                                       bool ConvertHigh) const {
147   unsigned Reg = MI.getOperand(0).getReg();
148   bool IsHigh = isHighReg(Reg);
149   MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
150   if (IsHigh && ConvertHigh)
151     MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
152 }
153 
154 // MI is a three-operand RIE-style pseudo instruction.  Replace it with
155 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
156 // followed by HighOpcode or LowOpcode, depending on whether the target
157 // is a high or low GR32.
158 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
159                                        unsigned LowOpcodeK,
160                                        unsigned HighOpcode) const {
161   unsigned DestReg = MI.getOperand(0).getReg();
162   unsigned SrcReg = MI.getOperand(1).getReg();
163   bool DestIsHigh = isHighReg(DestReg);
164   bool SrcIsHigh = isHighReg(SrcReg);
165   if (!DestIsHigh && !SrcIsHigh)
166     MI.setDesc(get(LowOpcodeK));
167   else {
168     emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
169                   SystemZ::LR, 32, MI.getOperand(1).isKill(),
170                   MI.getOperand(1).isUndef());
171     MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
172     MI.getOperand(1).setReg(DestReg);
173     MI.tieOperands(0, 1);
174   }
175 }
176 
177 // MI is an RXY-style pseudo instruction.  Replace it with LowOpcode
178 // if the first operand is a low GR32 and HighOpcode if the first operand
179 // is a high GR32.
180 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
181                                        unsigned HighOpcode) const {
182   unsigned Reg = MI.getOperand(0).getReg();
183   unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
184                                        MI.getOperand(2).getImm());
185   MI.setDesc(get(Opcode));
186 }
187 
188 // MI is a load-on-condition pseudo instruction with a single register
189 // (source or destination) operand.  Replace it with LowOpcode if the
190 // register is a low GR32 and HighOpcode if the register is a high GR32.
191 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
192                                        unsigned HighOpcode) const {
193   unsigned Reg = MI.getOperand(0).getReg();
194   unsigned Opcode = isHighReg(Reg) ? HighOpcode : LowOpcode;
195   MI.setDesc(get(Opcode));
196 }
197 
198 // MI is a load-register-on-condition pseudo instruction.  Replace it with
199 // LowOpcode if source and destination are both low GR32s and HighOpcode if
200 // source and destination are both high GR32s.
201 void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
202                                         unsigned HighOpcode) const {
203   unsigned DestReg = MI.getOperand(0).getReg();
204   unsigned SrcReg = MI.getOperand(2).getReg();
205   bool DestIsHigh = isHighReg(DestReg);
206   bool SrcIsHigh = isHighReg(SrcReg);
207 
208   if (!DestIsHigh && !SrcIsHigh)
209     MI.setDesc(get(LowOpcode));
210   else if (DestIsHigh && SrcIsHigh)
211     MI.setDesc(get(HighOpcode));
212 
213   // If we were unable to implement the pseudo with a single instruction, we
214   // need to convert it back into a branch sequence.  This cannot be done here
215   // since the caller of expandPostRAPseudo does not handle changes to the CFG
216   // correctly.  This change is defered to the SystemZExpandPseudo pass.
217 }
218 
219 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
220 // of one GRX32 into another.  Replace it with LowOpcode if both operands
221 // are low registers, otherwise use RISB[LH]G.
222 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
223                                         unsigned Size) const {
224   MachineInstrBuilder MIB =
225     emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
226                MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
227                Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
228 
229   // Keep the remaining operands as-is.
230   for (unsigned I = 2; I < MI.getNumOperands(); ++I)
231     MIB.add(MI.getOperand(I));
232 
233   MI.eraseFromParent();
234 }
235 
236 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
237   MachineBasicBlock *MBB = MI->getParent();
238   MachineFunction &MF = *MBB->getParent();
239   const unsigned Reg64 = MI->getOperand(0).getReg();
240   const unsigned Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
241 
242   // EAR can only load the low subregister so us a shift for %a0 to produce
243   // the GR containing %a0 and %a1.
244 
245   // ear <reg>, %a0
246   BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
247     .addReg(SystemZ::A0)
248     .addReg(Reg64, RegState::ImplicitDefine);
249 
250   // sllg <reg>, <reg>, 32
251   BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
252     .addReg(Reg64)
253     .addReg(0)
254     .addImm(32);
255 
256   // ear <reg>, %a1
257   BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
258     .addReg(SystemZ::A1);
259 
260   // lg <reg>, 40(<reg>)
261   MI->setDesc(get(SystemZ::LG));
262   MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
263 }
264 
265 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
266 // DestReg before MBBI in MBB.  Use LowLowOpcode when both DestReg and SrcReg
267 // are low registers, otherwise use RISB[LH]G.  Size is the number of bits
268 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
269 // KillSrc is true if this move is the last use of SrcReg.
270 MachineInstrBuilder
271 SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
272                                 MachineBasicBlock::iterator MBBI,
273                                 const DebugLoc &DL, unsigned DestReg,
274                                 unsigned SrcReg, unsigned LowLowOpcode,
275                                 unsigned Size, bool KillSrc,
276                                 bool UndefSrc) const {
277   unsigned Opcode;
278   bool DestIsHigh = isHighReg(DestReg);
279   bool SrcIsHigh = isHighReg(SrcReg);
280   if (DestIsHigh && SrcIsHigh)
281     Opcode = SystemZ::RISBHH;
282   else if (DestIsHigh && !SrcIsHigh)
283     Opcode = SystemZ::RISBHL;
284   else if (!DestIsHigh && SrcIsHigh)
285     Opcode = SystemZ::RISBLH;
286   else {
287     return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
288       .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
289   }
290   unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
291   return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
292     .addReg(DestReg, RegState::Undef)
293     .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
294     .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
295 }
296 
297 MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
298                                                        bool NewMI,
299                                                        unsigned OpIdx1,
300                                                        unsigned OpIdx2) const {
301   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
302     if (NewMI)
303       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
304     return MI;
305   };
306 
307   switch (MI.getOpcode()) {
308   case SystemZ::LOCRMux:
309   case SystemZ::LOCFHR:
310   case SystemZ::LOCR:
311   case SystemZ::LOCGR: {
312     auto &WorkingMI = cloneIfNew(MI);
313     // Invert condition.
314     unsigned CCValid = WorkingMI.getOperand(3).getImm();
315     unsigned CCMask = WorkingMI.getOperand(4).getImm();
316     WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
317     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
318                                                    OpIdx1, OpIdx2);
319   }
320   default:
321     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
322   }
323 }
324 
325 // If MI is a simple load or store for a frame object, return the register
326 // it loads or stores and set FrameIndex to the index of the frame object.
327 // Return 0 otherwise.
328 //
329 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
330 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
331                         unsigned Flag) {
332   const MCInstrDesc &MCID = MI.getDesc();
333   if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
334       MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
335     FrameIndex = MI.getOperand(1).getIndex();
336     return MI.getOperand(0).getReg();
337   }
338   return 0;
339 }
340 
341 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
342                                                int &FrameIndex) const {
343   return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
344 }
345 
346 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
347                                               int &FrameIndex) const {
348   return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
349 }
350 
351 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
352                                        int &DestFrameIndex,
353                                        int &SrcFrameIndex) const {
354   // Check for MVC 0(Length,FI1),0(FI2)
355   const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
356   if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
357       MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
358       MI.getOperand(4).getImm() != 0)
359     return false;
360 
361   // Check that Length covers the full slots.
362   int64_t Length = MI.getOperand(2).getImm();
363   unsigned FI1 = MI.getOperand(0).getIndex();
364   unsigned FI2 = MI.getOperand(3).getIndex();
365   if (MFI.getObjectSize(FI1) != Length ||
366       MFI.getObjectSize(FI2) != Length)
367     return false;
368 
369   DestFrameIndex = FI1;
370   SrcFrameIndex = FI2;
371   return true;
372 }
373 
374 bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
375                                      MachineBasicBlock *&TBB,
376                                      MachineBasicBlock *&FBB,
377                                      SmallVectorImpl<MachineOperand> &Cond,
378                                      bool AllowModify) const {
379   // Most of the code and comments here are boilerplate.
380 
381   // Start from the bottom of the block and work up, examining the
382   // terminator instructions.
383   MachineBasicBlock::iterator I = MBB.end();
384   while (I != MBB.begin()) {
385     --I;
386     if (I->isDebugValue())
387       continue;
388 
389     // Working from the bottom, when we see a non-terminator instruction, we're
390     // done.
391     if (!isUnpredicatedTerminator(*I))
392       break;
393 
394     // A terminator that isn't a branch can't easily be handled by this
395     // analysis.
396     if (!I->isBranch())
397       return true;
398 
399     // Can't handle indirect branches.
400     SystemZII::Branch Branch(getBranchInfo(*I));
401     if (!Branch.Target->isMBB())
402       return true;
403 
404     // Punt on compound branches.
405     if (Branch.Type != SystemZII::BranchNormal)
406       return true;
407 
408     if (Branch.CCMask == SystemZ::CCMASK_ANY) {
409       // Handle unconditional branches.
410       if (!AllowModify) {
411         TBB = Branch.Target->getMBB();
412         continue;
413       }
414 
415       // If the block has any instructions after a JMP, delete them.
416       while (std::next(I) != MBB.end())
417         std::next(I)->eraseFromParent();
418 
419       Cond.clear();
420       FBB = nullptr;
421 
422       // Delete the JMP if it's equivalent to a fall-through.
423       if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
424         TBB = nullptr;
425         I->eraseFromParent();
426         I = MBB.end();
427         continue;
428       }
429 
430       // TBB is used to indicate the unconditinal destination.
431       TBB = Branch.Target->getMBB();
432       continue;
433     }
434 
435     // Working from the bottom, handle the first conditional branch.
436     if (Cond.empty()) {
437       // FIXME: add X86-style branch swap
438       FBB = TBB;
439       TBB = Branch.Target->getMBB();
440       Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
441       Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
442       continue;
443     }
444 
445     // Handle subsequent conditional branches.
446     assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
447 
448     // Only handle the case where all conditional branches branch to the same
449     // destination.
450     if (TBB != Branch.Target->getMBB())
451       return true;
452 
453     // If the conditions are the same, we can leave them alone.
454     unsigned OldCCValid = Cond[0].getImm();
455     unsigned OldCCMask = Cond[1].getImm();
456     if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
457       continue;
458 
459     // FIXME: Try combining conditions like X86 does.  Should be easy on Z!
460     return false;
461   }
462 
463   return false;
464 }
465 
466 unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
467                                         int *BytesRemoved) const {
468   assert(!BytesRemoved && "code size not handled");
469 
470   // Most of the code and comments here are boilerplate.
471   MachineBasicBlock::iterator I = MBB.end();
472   unsigned Count = 0;
473 
474   while (I != MBB.begin()) {
475     --I;
476     if (I->isDebugValue())
477       continue;
478     if (!I->isBranch())
479       break;
480     if (!getBranchInfo(*I).Target->isMBB())
481       break;
482     // Remove the branch.
483     I->eraseFromParent();
484     I = MBB.end();
485     ++Count;
486   }
487 
488   return Count;
489 }
490 
491 bool SystemZInstrInfo::
492 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
493   assert(Cond.size() == 2 && "Invalid condition");
494   Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
495   return false;
496 }
497 
498 unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
499                                         MachineBasicBlock *TBB,
500                                         MachineBasicBlock *FBB,
501                                         ArrayRef<MachineOperand> Cond,
502                                         const DebugLoc &DL,
503                                         int *BytesAdded) const {
504   // In this function we output 32-bit branches, which should always
505   // have enough range.  They can be shortened and relaxed by later code
506   // in the pipeline, if desired.
507 
508   // Shouldn't be a fall through.
509   assert(TBB && "insertBranch must not be told to insert a fallthrough");
510   assert((Cond.size() == 2 || Cond.size() == 0) &&
511          "SystemZ branch conditions have one component!");
512   assert(!BytesAdded && "code size not handled");
513 
514   if (Cond.empty()) {
515     // Unconditional branch?
516     assert(!FBB && "Unconditional branch with multiple successors!");
517     BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
518     return 1;
519   }
520 
521   // Conditional branch.
522   unsigned Count = 0;
523   unsigned CCValid = Cond[0].getImm();
524   unsigned CCMask = Cond[1].getImm();
525   BuildMI(&MBB, DL, get(SystemZ::BRC))
526     .addImm(CCValid).addImm(CCMask).addMBB(TBB);
527   ++Count;
528 
529   if (FBB) {
530     // Two-way Conditional branch. Insert the second branch.
531     BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
532     ++Count;
533   }
534   return Count;
535 }
536 
537 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
538                                       unsigned &SrcReg2, int &Mask,
539                                       int &Value) const {
540   assert(MI.isCompare() && "Caller should have checked for a comparison");
541 
542   if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
543       MI.getOperand(1).isImm()) {
544     SrcReg = MI.getOperand(0).getReg();
545     SrcReg2 = 0;
546     Value = MI.getOperand(1).getImm();
547     Mask = ~0;
548     return true;
549   }
550 
551   return false;
552 }
553 
554 // If Reg is a virtual register, return its definition, otherwise return null.
555 static MachineInstr *getDef(unsigned Reg,
556                             const MachineRegisterInfo *MRI) {
557   if (TargetRegisterInfo::isPhysicalRegister(Reg))
558     return nullptr;
559   return MRI->getUniqueVRegDef(Reg);
560 }
561 
562 // Return true if MI is a shift of type Opcode by Imm bits.
563 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
564   return (MI->getOpcode() == Opcode &&
565           !MI->getOperand(2).getReg() &&
566           MI->getOperand(3).getImm() == Imm);
567 }
568 
569 // If the destination of MI has no uses, delete it as dead.
570 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
571   if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
572     MI->eraseFromParent();
573 }
574 
575 // Compare compares SrcReg against zero.  Check whether SrcReg contains
576 // the result of an IPM sequence whose input CC survives until Compare,
577 // and whether Compare is therefore redundant.  Delete it and return
578 // true if so.
579 static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg,
580                                   const MachineRegisterInfo *MRI,
581                                   const TargetRegisterInfo *TRI) {
582   MachineInstr *LGFR = nullptr;
583   MachineInstr *RLL = getDef(SrcReg, MRI);
584   if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
585     LGFR = RLL;
586     RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
587   }
588   if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
589     return false;
590 
591   MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
592   if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
593     return false;
594 
595   MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
596   if (!IPM || IPM->getOpcode() != SystemZ::IPM)
597     return false;
598 
599   // Check that there are no assignments to CC between the IPM and Compare,
600   if (IPM->getParent() != Compare.getParent())
601     return false;
602   MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare.getIterator();
603   for (++MBBI; MBBI != MBBE; ++MBBI) {
604     MachineInstr &MI = *MBBI;
605     if (MI.modifiesRegister(SystemZ::CC, TRI))
606       return false;
607   }
608 
609   Compare.eraseFromParent();
610   if (LGFR)
611     eraseIfDead(LGFR, MRI);
612   eraseIfDead(RLL, MRI);
613   eraseIfDead(SRL, MRI);
614   eraseIfDead(IPM, MRI);
615 
616   return true;
617 }
618 
619 bool SystemZInstrInfo::optimizeCompareInstr(
620     MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask,
621     int Value, const MachineRegisterInfo *MRI) const {
622   assert(!SrcReg2 && "Only optimizing constant comparisons so far");
623   bool IsLogical = (Compare.getDesc().TSFlags & SystemZII::IsLogical) != 0;
624   return Value == 0 && !IsLogical &&
625          removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
626 }
627 
628 bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
629                                        ArrayRef<MachineOperand> Pred,
630                                        unsigned TrueReg, unsigned FalseReg,
631                                        int &CondCycles, int &TrueCycles,
632                                        int &FalseCycles) const {
633   // Not all subtargets have LOCR instructions.
634   if (!STI.hasLoadStoreOnCond())
635     return false;
636   if (Pred.size() != 2)
637     return false;
638 
639   // Check register classes.
640   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
641   const TargetRegisterClass *RC =
642     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
643   if (!RC)
644     return false;
645 
646   // We have LOCR instructions for 32 and 64 bit general purpose registers.
647   if ((STI.hasLoadStoreOnCond2() &&
648        SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
649       SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
650       SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
651     CondCycles = 2;
652     TrueCycles = 2;
653     FalseCycles = 2;
654     return true;
655   }
656 
657   // Can't do anything else.
658   return false;
659 }
660 
661 void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
662                                     MachineBasicBlock::iterator I,
663                                     const DebugLoc &DL, unsigned DstReg,
664                                     ArrayRef<MachineOperand> Pred,
665                                     unsigned TrueReg,
666                                     unsigned FalseReg) const {
667   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
668   const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
669 
670   assert(Pred.size() == 2 && "Invalid condition");
671   unsigned CCValid = Pred[0].getImm();
672   unsigned CCMask = Pred[1].getImm();
673 
674   unsigned Opc;
675   if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
676     if (STI.hasLoadStoreOnCond2())
677       Opc = SystemZ::LOCRMux;
678     else {
679       Opc = SystemZ::LOCR;
680       MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
681       unsigned TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
682       unsigned FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
683       BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
684       BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
685       TrueReg = TReg;
686       FalseReg = FReg;
687     }
688   } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
689     Opc = SystemZ::LOCGR;
690   else
691     llvm_unreachable("Invalid register class");
692 
693   BuildMI(MBB, I, DL, get(Opc), DstReg)
694     .addReg(FalseReg).addReg(TrueReg)
695     .addImm(CCValid).addImm(CCMask);
696 }
697 
698 bool SystemZInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
699                                      unsigned Reg,
700                                      MachineRegisterInfo *MRI) const {
701   unsigned DefOpc = DefMI.getOpcode();
702   if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
703       DefOpc != SystemZ::LGHI)
704     return false;
705   if (DefMI.getOperand(0).getReg() != Reg)
706     return false;
707   int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
708 
709   unsigned UseOpc = UseMI.getOpcode();
710   unsigned NewUseOpc;
711   unsigned UseIdx;
712   int CommuteIdx = -1;
713   switch (UseOpc) {
714   case SystemZ::LOCRMux:
715     if (!STI.hasLoadStoreOnCond2())
716       return false;
717     NewUseOpc = SystemZ::LOCHIMux;
718     if (UseMI.getOperand(2).getReg() == Reg)
719       UseIdx = 2;
720     else if (UseMI.getOperand(1).getReg() == Reg)
721       UseIdx = 2, CommuteIdx = 1;
722     else
723       return false;
724     break;
725   case SystemZ::LOCGR:
726     if (!STI.hasLoadStoreOnCond2())
727       return false;
728     NewUseOpc = SystemZ::LOCGHI;
729     if (UseMI.getOperand(2).getReg() == Reg)
730       UseIdx = 2;
731     else if (UseMI.getOperand(1).getReg() == Reg)
732       UseIdx = 2, CommuteIdx = 1;
733     else
734       return false;
735     break;
736   default:
737     return false;
738   }
739 
740   if (CommuteIdx != -1)
741     if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
742       return false;
743 
744   bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
745   UseMI.setDesc(get(NewUseOpc));
746   UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
747   if (DeleteDef)
748     DefMI.eraseFromParent();
749 
750   return true;
751 }
752 
753 bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
754   unsigned Opcode = MI.getOpcode();
755   if (Opcode == SystemZ::Return ||
756       Opcode == SystemZ::Trap ||
757       Opcode == SystemZ::CallJG ||
758       Opcode == SystemZ::CallBR)
759     return true;
760   return false;
761 }
762 
763 bool SystemZInstrInfo::
764 isProfitableToIfCvt(MachineBasicBlock &MBB,
765                     unsigned NumCycles, unsigned ExtraPredCycles,
766                     BranchProbability Probability) const {
767   // Avoid using conditional returns at the end of a loop (since then
768   // we'd need to emit an unconditional branch to the beginning anyway,
769   // making the loop body longer).  This doesn't apply for low-probability
770   // loops (eg. compare-and-swap retry), so just decide based on branch
771   // probability instead of looping structure.
772   // However, since Compare and Trap instructions cost the same as a regular
773   // Compare instruction, we should allow the if conversion to convert this
774   // into a Conditional Compare regardless of the branch probability.
775   if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
776       MBB.succ_empty() && Probability < BranchProbability(1, 8))
777     return false;
778   // For now only convert single instructions.
779   return NumCycles == 1;
780 }
781 
782 bool SystemZInstrInfo::
783 isProfitableToIfCvt(MachineBasicBlock &TMBB,
784                     unsigned NumCyclesT, unsigned ExtraPredCyclesT,
785                     MachineBasicBlock &FMBB,
786                     unsigned NumCyclesF, unsigned ExtraPredCyclesF,
787                     BranchProbability Probability) const {
788   // For now avoid converting mutually-exclusive cases.
789   return false;
790 }
791 
792 bool SystemZInstrInfo::
793 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
794                           BranchProbability Probability) const {
795   // For now only duplicate single instructions.
796   return NumCycles == 1;
797 }
798 
799 bool SystemZInstrInfo::PredicateInstruction(
800     MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
801   assert(Pred.size() == 2 && "Invalid condition");
802   unsigned CCValid = Pred[0].getImm();
803   unsigned CCMask = Pred[1].getImm();
804   assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
805   unsigned Opcode = MI.getOpcode();
806   if (Opcode == SystemZ::Trap) {
807     MI.setDesc(get(SystemZ::CondTrap));
808     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
809       .addImm(CCValid).addImm(CCMask)
810       .addReg(SystemZ::CC, RegState::Implicit);
811     return true;
812   }
813   if (Opcode == SystemZ::Return) {
814     MI.setDesc(get(SystemZ::CondReturn));
815     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
816       .addImm(CCValid).addImm(CCMask)
817       .addReg(SystemZ::CC, RegState::Implicit);
818     return true;
819   }
820   if (Opcode == SystemZ::CallJG) {
821     MachineOperand FirstOp = MI.getOperand(0);
822     const uint32_t *RegMask = MI.getOperand(1).getRegMask();
823     MI.RemoveOperand(1);
824     MI.RemoveOperand(0);
825     MI.setDesc(get(SystemZ::CallBRCL));
826     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
827         .addImm(CCValid)
828         .addImm(CCMask)
829         .add(FirstOp)
830         .addRegMask(RegMask)
831         .addReg(SystemZ::CC, RegState::Implicit);
832     return true;
833   }
834   if (Opcode == SystemZ::CallBR) {
835     const uint32_t *RegMask = MI.getOperand(0).getRegMask();
836     MI.RemoveOperand(0);
837     MI.setDesc(get(SystemZ::CallBCR));
838     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
839       .addImm(CCValid).addImm(CCMask)
840       .addRegMask(RegMask)
841       .addReg(SystemZ::CC, RegState::Implicit);
842     return true;
843   }
844   return false;
845 }
846 
847 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
848                                    MachineBasicBlock::iterator MBBI,
849                                    const DebugLoc &DL, unsigned DestReg,
850                                    unsigned SrcReg, bool KillSrc) const {
851   // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
852   // super register in case one of the subregs is undefined.
853   // This handles ADDR128 too.
854   if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
855     copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
856                 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
857     MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
858       .addReg(SrcReg, RegState::Implicit);
859     copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
860                 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
861     MachineInstrBuilder(*MBB.getParent(), std::prev(MBBI))
862       .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
863     return;
864   }
865 
866   if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
867     emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc,
868                   false);
869     return;
870   }
871 
872   // Move 128-bit floating-point values between VR128 and FP128.
873   if (SystemZ::VR128BitRegClass.contains(DestReg) &&
874       SystemZ::FP128BitRegClass.contains(SrcReg)) {
875     unsigned SrcRegHi =
876       RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
877                              SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
878     unsigned SrcRegLo =
879       RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
880                              SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
881 
882     BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
883       .addReg(SrcRegHi, getKillRegState(KillSrc))
884       .addReg(SrcRegLo, getKillRegState(KillSrc));
885     return;
886   }
887   if (SystemZ::FP128BitRegClass.contains(DestReg) &&
888       SystemZ::VR128BitRegClass.contains(SrcReg)) {
889     unsigned DestRegHi =
890       RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
891                              SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
892     unsigned DestRegLo =
893       RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
894                              SystemZ::subreg_r64, &SystemZ::VR128BitRegClass);
895 
896     if (DestRegHi != SrcReg)
897       copyPhysReg(MBB, MBBI, DL, DestRegHi, SrcReg, false);
898     BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
899       .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
900     return;
901   }
902 
903   // Everything else needs only one instruction.
904   unsigned Opcode;
905   if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
906     Opcode = SystemZ::LGR;
907   else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
908     // For z13 we prefer LDR over LER to avoid partial register dependencies.
909     Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
910   else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
911     Opcode = SystemZ::LDR;
912   else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
913     Opcode = SystemZ::LXR;
914   else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
915     Opcode = SystemZ::VLR32;
916   else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
917     Opcode = SystemZ::VLR64;
918   else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
919     Opcode = SystemZ::VLR;
920   else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
921     Opcode = SystemZ::CPYA;
922   else if (SystemZ::AR32BitRegClass.contains(DestReg) &&
923            SystemZ::GR32BitRegClass.contains(SrcReg))
924     Opcode = SystemZ::SAR;
925   else if (SystemZ::GR32BitRegClass.contains(DestReg) &&
926            SystemZ::AR32BitRegClass.contains(SrcReg))
927     Opcode = SystemZ::EAR;
928   else
929     llvm_unreachable("Impossible reg-to-reg copy");
930 
931   BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
932     .addReg(SrcReg, getKillRegState(KillSrc));
933 }
934 
935 void SystemZInstrInfo::storeRegToStackSlot(
936     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
937     bool isKill, int FrameIdx, const TargetRegisterClass *RC,
938     const TargetRegisterInfo *TRI) const {
939   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
940 
941   // Callers may expect a single instruction, so keep 128-bit moves
942   // together for now and lower them after register allocation.
943   unsigned LoadOpcode, StoreOpcode;
944   getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
945   addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
946                         .addReg(SrcReg, getKillRegState(isKill)),
947                     FrameIdx);
948 }
949 
950 void SystemZInstrInfo::loadRegFromStackSlot(
951     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
952     int FrameIdx, const TargetRegisterClass *RC,
953     const TargetRegisterInfo *TRI) const {
954   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
955 
956   // Callers may expect a single instruction, so keep 128-bit moves
957   // together for now and lower them after register allocation.
958   unsigned LoadOpcode, StoreOpcode;
959   getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
960   addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
961                     FrameIdx);
962 }
963 
964 // Return true if MI is a simple load or store with a 12-bit displacement
965 // and no index.  Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
966 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
967   const MCInstrDesc &MCID = MI->getDesc();
968   return ((MCID.TSFlags & Flag) &&
969           isUInt<12>(MI->getOperand(2).getImm()) &&
970           MI->getOperand(3).getReg() == 0);
971 }
972 
973 namespace {
974 
975 struct LogicOp {
976   LogicOp() = default;
977   LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
978     : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
979 
980   explicit operator bool() const { return RegSize; }
981 
982   unsigned RegSize = 0;
983   unsigned ImmLSB = 0;
984   unsigned ImmSize = 0;
985 };
986 
987 } // end anonymous namespace
988 
989 static LogicOp interpretAndImmediate(unsigned Opcode) {
990   switch (Opcode) {
991   case SystemZ::NILMux: return LogicOp(32,  0, 16);
992   case SystemZ::NIHMux: return LogicOp(32, 16, 16);
993   case SystemZ::NILL64: return LogicOp(64,  0, 16);
994   case SystemZ::NILH64: return LogicOp(64, 16, 16);
995   case SystemZ::NIHL64: return LogicOp(64, 32, 16);
996   case SystemZ::NIHH64: return LogicOp(64, 48, 16);
997   case SystemZ::NIFMux: return LogicOp(32,  0, 32);
998   case SystemZ::NILF64: return LogicOp(64,  0, 32);
999   case SystemZ::NIHF64: return LogicOp(64, 32, 32);
1000   default:              return LogicOp();
1001   }
1002 }
1003 
1004 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
1005   if (OldMI->registerDefIsDead(SystemZ::CC)) {
1006     MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
1007     if (CCDef != nullptr)
1008       CCDef->setIsDead(true);
1009   }
1010 }
1011 
1012 // Used to return from convertToThreeAddress after replacing two-address
1013 // instruction OldMI with three-address instruction NewMI.
1014 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
1015                                                  MachineInstr *NewMI,
1016                                                  LiveVariables *LV) {
1017   if (LV) {
1018     unsigned NumOps = OldMI->getNumOperands();
1019     for (unsigned I = 1; I < NumOps; ++I) {
1020       MachineOperand &Op = OldMI->getOperand(I);
1021       if (Op.isReg() && Op.isKill())
1022         LV->replaceKillInstruction(Op.getReg(), *OldMI, *NewMI);
1023     }
1024   }
1025   transferDeadCC(OldMI, NewMI);
1026   return NewMI;
1027 }
1028 
1029 MachineInstr *SystemZInstrInfo::convertToThreeAddress(
1030     MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
1031   MachineBasicBlock *MBB = MI.getParent();
1032   MachineFunction *MF = MBB->getParent();
1033   MachineRegisterInfo &MRI = MF->getRegInfo();
1034 
1035   unsigned Opcode = MI.getOpcode();
1036   unsigned NumOps = MI.getNumOperands();
1037 
1038   // Try to convert something like SLL into SLLK, if supported.
1039   // We prefer to keep the two-operand form where possible both
1040   // because it tends to be shorter and because some instructions
1041   // have memory forms that can be used during spilling.
1042   if (STI.hasDistinctOps()) {
1043     MachineOperand &Dest = MI.getOperand(0);
1044     MachineOperand &Src = MI.getOperand(1);
1045     unsigned DestReg = Dest.getReg();
1046     unsigned SrcReg = Src.getReg();
1047     // AHIMux is only really a three-operand instruction when both operands
1048     // are low registers.  Try to constrain both operands to be low if
1049     // possible.
1050     if (Opcode == SystemZ::AHIMux &&
1051         TargetRegisterInfo::isVirtualRegister(DestReg) &&
1052         TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1053         MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
1054         MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
1055       MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
1056       MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
1057     }
1058     int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
1059     if (ThreeOperandOpcode >= 0) {
1060       // Create three address instruction without adding the implicit
1061       // operands. Those will instead be copied over from the original
1062       // instruction by the loop below.
1063       MachineInstrBuilder MIB(
1064           *MF, MF->CreateMachineInstr(get(ThreeOperandOpcode), MI.getDebugLoc(),
1065                                       /*NoImplicit=*/true));
1066       MIB.add(Dest);
1067       // Keep the kill state, but drop the tied flag.
1068       MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
1069       // Keep the remaining operands as-is.
1070       for (unsigned I = 2; I < NumOps; ++I)
1071         MIB.add(MI.getOperand(I));
1072       MBB->insert(MI, MIB);
1073       return finishConvertToThreeAddress(&MI, MIB, LV);
1074     }
1075   }
1076 
1077   // Try to convert an AND into an RISBG-type instruction.
1078   if (LogicOp And = interpretAndImmediate(Opcode)) {
1079     uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
1080     // AND IMMEDIATE leaves the other bits of the register unchanged.
1081     Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
1082     unsigned Start, End;
1083     if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
1084       unsigned NewOpcode;
1085       if (And.RegSize == 64) {
1086         NewOpcode = SystemZ::RISBG;
1087         // Prefer RISBGN if available, since it does not clobber CC.
1088         if (STI.hasMiscellaneousExtensions())
1089           NewOpcode = SystemZ::RISBGN;
1090       } else {
1091         NewOpcode = SystemZ::RISBMux;
1092         Start &= 31;
1093         End &= 31;
1094       }
1095       MachineOperand &Dest = MI.getOperand(0);
1096       MachineOperand &Src = MI.getOperand(1);
1097       MachineInstrBuilder MIB =
1098           BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
1099               .add(Dest)
1100               .addReg(0)
1101               .addReg(Src.getReg(), getKillRegState(Src.isKill()),
1102                       Src.getSubReg())
1103               .addImm(Start)
1104               .addImm(End + 128)
1105               .addImm(0);
1106       return finishConvertToThreeAddress(&MI, MIB, LV);
1107     }
1108   }
1109   return nullptr;
1110 }
1111 
1112 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1113     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1114     MachineBasicBlock::iterator InsertPt, int FrameIndex,
1115     LiveIntervals *LIS) const {
1116   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1117   const MachineFrameInfo &MFI = MF.getFrameInfo();
1118   unsigned Size = MFI.getObjectSize(FrameIndex);
1119   unsigned Opcode = MI.getOpcode();
1120 
1121   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1122     if (LIS != nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1123         isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1124 
1125       // Check CC liveness, since new instruction introduces a dead
1126       // def of CC.
1127       MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
1128       LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
1129       ++CCUnit;
1130       assert(!CCUnit.isValid() && "CC only has one reg unit.");
1131       SlotIndex MISlot =
1132           LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1133       if (!CCLiveRange.liveAt(MISlot)) {
1134         // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1135         MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1136                                         MI.getDebugLoc(), get(SystemZ::AGSI))
1137                                     .addFrameIndex(FrameIndex)
1138                                     .addImm(0)
1139                                     .addImm(MI.getOperand(2).getImm());
1140         BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1141         CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
1142         return BuiltMI;
1143       }
1144     }
1145     return nullptr;
1146   }
1147 
1148   // All other cases require a single operand.
1149   if (Ops.size() != 1)
1150     return nullptr;
1151 
1152   unsigned OpNum = Ops[0];
1153   assert(Size * 8 ==
1154            TRI->getRegSizeInBits(*MF.getRegInfo()
1155                                .getRegClass(MI.getOperand(OpNum).getReg())) &&
1156          "Invalid size combination");
1157 
1158   if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1159       isInt<8>(MI.getOperand(2).getImm())) {
1160     // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1161     Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1162     MachineInstr *BuiltMI =
1163         BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1164             .addFrameIndex(FrameIndex)
1165             .addImm(0)
1166             .addImm(MI.getOperand(2).getImm());
1167     transferDeadCC(&MI, BuiltMI);
1168     return BuiltMI;
1169   }
1170 
1171   if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1172     bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1173     bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1174     // If we're spilling the destination of an LDGR or LGDR, store the
1175     // source register instead.
1176     if (OpNum == 0) {
1177       unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1178       return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1179                      get(StoreOpcode))
1180           .add(MI.getOperand(1))
1181           .addFrameIndex(FrameIndex)
1182           .addImm(0)
1183           .addReg(0);
1184     }
1185     // If we're spilling the source of an LDGR or LGDR, load the
1186     // destination register instead.
1187     if (OpNum == 1) {
1188       unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1189       return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1190                      get(LoadOpcode))
1191         .add(MI.getOperand(0))
1192         .addFrameIndex(FrameIndex)
1193         .addImm(0)
1194         .addReg(0);
1195     }
1196   }
1197 
1198   // Look for cases where the source of a simple store or the destination
1199   // of a simple load is being spilled.  Try to use MVC instead.
1200   //
1201   // Although MVC is in practice a fast choice in these cases, it is still
1202   // logically a bytewise copy.  This means that we cannot use it if the
1203   // load or store is volatile.  We also wouldn't be able to use MVC if
1204   // the two memories partially overlap, but that case cannot occur here,
1205   // because we know that one of the memories is a full frame index.
1206   //
1207   // For performance reasons, we also want to avoid using MVC if the addresses
1208   // might be equal.  We don't worry about that case here, because spill slot
1209   // coloring happens later, and because we have special code to remove
1210   // MVCs that turn out to be redundant.
1211   if (OpNum == 0 && MI.hasOneMemOperand()) {
1212     MachineMemOperand *MMO = *MI.memoperands_begin();
1213     if (MMO->getSize() == Size && !MMO->isVolatile()) {
1214       // Handle conversion of loads.
1215       if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
1216         return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1217                        get(SystemZ::MVC))
1218             .addFrameIndex(FrameIndex)
1219             .addImm(0)
1220             .addImm(Size)
1221             .add(MI.getOperand(1))
1222             .addImm(MI.getOperand(2).getImm())
1223             .addMemOperand(MMO);
1224       }
1225       // Handle conversion of stores.
1226       if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
1227         return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1228                        get(SystemZ::MVC))
1229             .add(MI.getOperand(1))
1230             .addImm(MI.getOperand(2).getImm())
1231             .addImm(Size)
1232             .addFrameIndex(FrameIndex)
1233             .addImm(0)
1234             .addMemOperand(MMO);
1235       }
1236     }
1237   }
1238 
1239   // If the spilled operand is the final one, try to change <INSN>R
1240   // into <INSN>.
1241   int MemOpcode = SystemZ::getMemOpcode(Opcode);
1242   if (MemOpcode >= 0) {
1243     unsigned NumOps = MI.getNumExplicitOperands();
1244     if (OpNum == NumOps - 1) {
1245       const MCInstrDesc &MemDesc = get(MemOpcode);
1246       uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1247       assert(AccessBytes != 0 && "Size of access should be known");
1248       assert(AccessBytes <= Size && "Access outside the frame index");
1249       uint64_t Offset = Size - AccessBytes;
1250       MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1251                                         MI.getDebugLoc(), get(MemOpcode));
1252       for (unsigned I = 0; I < OpNum; ++I)
1253         MIB.add(MI.getOperand(I));
1254       MIB.addFrameIndex(FrameIndex).addImm(Offset);
1255       if (MemDesc.TSFlags & SystemZII::HasIndex)
1256         MIB.addReg(0);
1257       transferDeadCC(&MI, MIB);
1258       return MIB;
1259     }
1260   }
1261 
1262   return nullptr;
1263 }
1264 
1265 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1266     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1267     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1268     LiveIntervals *LIS) const {
1269   return nullptr;
1270 }
1271 
1272 bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1273   switch (MI.getOpcode()) {
1274   case SystemZ::L128:
1275     splitMove(MI, SystemZ::LG);
1276     return true;
1277 
1278   case SystemZ::ST128:
1279     splitMove(MI, SystemZ::STG);
1280     return true;
1281 
1282   case SystemZ::LX:
1283     splitMove(MI, SystemZ::LD);
1284     return true;
1285 
1286   case SystemZ::STX:
1287     splitMove(MI, SystemZ::STD);
1288     return true;
1289 
1290   case SystemZ::LBMux:
1291     expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1292     return true;
1293 
1294   case SystemZ::LHMux:
1295     expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1296     return true;
1297 
1298   case SystemZ::LLCRMux:
1299     expandZExtPseudo(MI, SystemZ::LLCR, 8);
1300     return true;
1301 
1302   case SystemZ::LLHRMux:
1303     expandZExtPseudo(MI, SystemZ::LLHR, 16);
1304     return true;
1305 
1306   case SystemZ::LLCMux:
1307     expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1308     return true;
1309 
1310   case SystemZ::LLHMux:
1311     expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1312     return true;
1313 
1314   case SystemZ::LMux:
1315     expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1316     return true;
1317 
1318   case SystemZ::LOCMux:
1319     expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1320     return true;
1321 
1322   case SystemZ::LOCHIMux:
1323     expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1324     return true;
1325 
1326   case SystemZ::LOCRMux:
1327     expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1328     return true;
1329 
1330   case SystemZ::STCMux:
1331     expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1332     return true;
1333 
1334   case SystemZ::STHMux:
1335     expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1336     return true;
1337 
1338   case SystemZ::STMux:
1339     expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1340     return true;
1341 
1342   case SystemZ::STOCMux:
1343     expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1344     return true;
1345 
1346   case SystemZ::LHIMux:
1347     expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1348     return true;
1349 
1350   case SystemZ::IIFMux:
1351     expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1352     return true;
1353 
1354   case SystemZ::IILMux:
1355     expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1356     return true;
1357 
1358   case SystemZ::IIHMux:
1359     expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1360     return true;
1361 
1362   case SystemZ::NIFMux:
1363     expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1364     return true;
1365 
1366   case SystemZ::NILMux:
1367     expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1368     return true;
1369 
1370   case SystemZ::NIHMux:
1371     expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1372     return true;
1373 
1374   case SystemZ::OIFMux:
1375     expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1376     return true;
1377 
1378   case SystemZ::OILMux:
1379     expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1380     return true;
1381 
1382   case SystemZ::OIHMux:
1383     expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1384     return true;
1385 
1386   case SystemZ::XIFMux:
1387     expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1388     return true;
1389 
1390   case SystemZ::TMLMux:
1391     expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1392     return true;
1393 
1394   case SystemZ::TMHMux:
1395     expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1396     return true;
1397 
1398   case SystemZ::AHIMux:
1399     expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1400     return true;
1401 
1402   case SystemZ::AHIMuxK:
1403     expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1404     return true;
1405 
1406   case SystemZ::AFIMux:
1407     expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1408     return true;
1409 
1410   case SystemZ::CHIMux:
1411     expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1412     return true;
1413 
1414   case SystemZ::CFIMux:
1415     expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1416     return true;
1417 
1418   case SystemZ::CLFIMux:
1419     expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1420     return true;
1421 
1422   case SystemZ::CMux:
1423     expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1424     return true;
1425 
1426   case SystemZ::CLMux:
1427     expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1428     return true;
1429 
1430   case SystemZ::RISBMux: {
1431     bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
1432     bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
1433     if (SrcIsHigh == DestIsHigh)
1434       MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1435     else {
1436       MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1437       MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1438     }
1439     return true;
1440   }
1441 
1442   case SystemZ::ADJDYNALLOC:
1443     splitAdjDynAlloc(MI);
1444     return true;
1445 
1446   case TargetOpcode::LOAD_STACK_GUARD:
1447     expandLoadStackGuard(&MI);
1448     return true;
1449 
1450   default:
1451     return false;
1452   }
1453 }
1454 
1455 unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1456   if (MI.getOpcode() == TargetOpcode::INLINEASM) {
1457     const MachineFunction *MF = MI.getParent()->getParent();
1458     const char *AsmStr = MI.getOperand(0).getSymbolName();
1459     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1460   }
1461   return MI.getDesc().getSize();
1462 }
1463 
1464 SystemZII::Branch
1465 SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1466   switch (MI.getOpcode()) {
1467   case SystemZ::BR:
1468   case SystemZ::BI:
1469   case SystemZ::J:
1470   case SystemZ::JG:
1471     return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1472                              SystemZ::CCMASK_ANY, &MI.getOperand(0));
1473 
1474   case SystemZ::BRC:
1475   case SystemZ::BRCL:
1476     return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1477                              MI.getOperand(1).getImm(), &MI.getOperand(2));
1478 
1479   case SystemZ::BRCT:
1480   case SystemZ::BRCTH:
1481     return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1482                              SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1483 
1484   case SystemZ::BRCTG:
1485     return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1486                              SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1487 
1488   case SystemZ::CIJ:
1489   case SystemZ::CRJ:
1490     return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1491                              MI.getOperand(2).getImm(), &MI.getOperand(3));
1492 
1493   case SystemZ::CLIJ:
1494   case SystemZ::CLRJ:
1495     return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1496                              MI.getOperand(2).getImm(), &MI.getOperand(3));
1497 
1498   case SystemZ::CGIJ:
1499   case SystemZ::CGRJ:
1500     return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1501                              MI.getOperand(2).getImm(), &MI.getOperand(3));
1502 
1503   case SystemZ::CLGIJ:
1504   case SystemZ::CLGRJ:
1505     return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1506                              MI.getOperand(2).getImm(), &MI.getOperand(3));
1507 
1508   default:
1509     llvm_unreachable("Unrecognized branch opcode");
1510   }
1511 }
1512 
1513 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1514                                            unsigned &LoadOpcode,
1515                                            unsigned &StoreOpcode) const {
1516   if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1517     LoadOpcode = SystemZ::L;
1518     StoreOpcode = SystemZ::ST;
1519   } else if (RC == &SystemZ::GRH32BitRegClass) {
1520     LoadOpcode = SystemZ::LFH;
1521     StoreOpcode = SystemZ::STFH;
1522   } else if (RC == &SystemZ::GRX32BitRegClass) {
1523     LoadOpcode = SystemZ::LMux;
1524     StoreOpcode = SystemZ::STMux;
1525   } else if (RC == &SystemZ::GR64BitRegClass ||
1526              RC == &SystemZ::ADDR64BitRegClass) {
1527     LoadOpcode = SystemZ::LG;
1528     StoreOpcode = SystemZ::STG;
1529   } else if (RC == &SystemZ::GR128BitRegClass ||
1530              RC == &SystemZ::ADDR128BitRegClass) {
1531     LoadOpcode = SystemZ::L128;
1532     StoreOpcode = SystemZ::ST128;
1533   } else if (RC == &SystemZ::FP32BitRegClass) {
1534     LoadOpcode = SystemZ::LE;
1535     StoreOpcode = SystemZ::STE;
1536   } else if (RC == &SystemZ::FP64BitRegClass) {
1537     LoadOpcode = SystemZ::LD;
1538     StoreOpcode = SystemZ::STD;
1539   } else if (RC == &SystemZ::FP128BitRegClass) {
1540     LoadOpcode = SystemZ::LX;
1541     StoreOpcode = SystemZ::STX;
1542   } else if (RC == &SystemZ::VR32BitRegClass) {
1543     LoadOpcode = SystemZ::VL32;
1544     StoreOpcode = SystemZ::VST32;
1545   } else if (RC == &SystemZ::VR64BitRegClass) {
1546     LoadOpcode = SystemZ::VL64;
1547     StoreOpcode = SystemZ::VST64;
1548   } else if (RC == &SystemZ::VF128BitRegClass ||
1549              RC == &SystemZ::VR128BitRegClass) {
1550     LoadOpcode = SystemZ::VL;
1551     StoreOpcode = SystemZ::VST;
1552   } else
1553     llvm_unreachable("Unsupported regclass to load or store");
1554 }
1555 
1556 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1557                                               int64_t Offset) const {
1558   const MCInstrDesc &MCID = get(Opcode);
1559   int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1560   if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1561     // Get the instruction to use for unsigned 12-bit displacements.
1562     int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1563     if (Disp12Opcode >= 0)
1564       return Disp12Opcode;
1565 
1566     // All address-related instructions can use unsigned 12-bit
1567     // displacements.
1568     return Opcode;
1569   }
1570   if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1571     // Get the instruction to use for signed 20-bit displacements.
1572     int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1573     if (Disp20Opcode >= 0)
1574       return Disp20Opcode;
1575 
1576     // Check whether Opcode allows signed 20-bit displacements.
1577     if (MCID.TSFlags & SystemZII::Has20BitOffset)
1578       return Opcode;
1579   }
1580   return 0;
1581 }
1582 
1583 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1584   switch (Opcode) {
1585   case SystemZ::L:      return SystemZ::LT;
1586   case SystemZ::LY:     return SystemZ::LT;
1587   case SystemZ::LG:     return SystemZ::LTG;
1588   case SystemZ::LGF:    return SystemZ::LTGF;
1589   case SystemZ::LR:     return SystemZ::LTR;
1590   case SystemZ::LGFR:   return SystemZ::LTGFR;
1591   case SystemZ::LGR:    return SystemZ::LTGR;
1592   case SystemZ::LER:    return SystemZ::LTEBR;
1593   case SystemZ::LDR:    return SystemZ::LTDBR;
1594   case SystemZ::LXR:    return SystemZ::LTXBR;
1595   case SystemZ::LCDFR:  return SystemZ::LCDBR;
1596   case SystemZ::LPDFR:  return SystemZ::LPDBR;
1597   case SystemZ::LNDFR:  return SystemZ::LNDBR;
1598   case SystemZ::LCDFR_32:  return SystemZ::LCEBR;
1599   case SystemZ::LPDFR_32:  return SystemZ::LPEBR;
1600   case SystemZ::LNDFR_32:  return SystemZ::LNEBR;
1601   // On zEC12 we prefer to use RISBGN.  But if there is a chance to
1602   // actually use the condition code, we may turn it back into RISGB.
1603   // Note that RISBG is not really a "load-and-test" instruction,
1604   // but sets the same condition code values, so is OK to use here.
1605   case SystemZ::RISBGN: return SystemZ::RISBG;
1606   default:              return 0;
1607   }
1608 }
1609 
1610 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1611 // have already been filtered out.  Store the first set bit in LSB and
1612 // the number of set bits in Length if so.
1613 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1614   unsigned First = findFirstSet(Mask);
1615   uint64_t Top = (Mask >> First) + 1;
1616   if ((Top & -Top) == Top) {
1617     LSB = First;
1618     Length = findFirstSet(Top);
1619     return true;
1620   }
1621   return false;
1622 }
1623 
1624 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1625                                    unsigned &Start, unsigned &End) const {
1626   // Reject trivial all-zero masks.
1627   Mask &= allOnes(BitSize);
1628   if (Mask == 0)
1629     return false;
1630 
1631   // Handle the 1+0+ or 0+1+0* cases.  Start then specifies the index of
1632   // the msb and End specifies the index of the lsb.
1633   unsigned LSB, Length;
1634   if (isStringOfOnes(Mask, LSB, Length)) {
1635     Start = 63 - (LSB + Length - 1);
1636     End = 63 - LSB;
1637     return true;
1638   }
1639 
1640   // Handle the wrap-around 1+0+1+ cases.  Start then specifies the msb
1641   // of the low 1s and End specifies the lsb of the high 1s.
1642   if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1643     assert(LSB > 0 && "Bottom bit must be set");
1644     assert(LSB + Length < BitSize && "Top bit must be set");
1645     Start = 63 - (LSB - 1);
1646     End = 63 - (LSB + Length);
1647     return true;
1648   }
1649 
1650   return false;
1651 }
1652 
1653 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1654                                            SystemZII::FusedCompareType Type,
1655                                            const MachineInstr *MI) const {
1656   switch (Opcode) {
1657   case SystemZ::CHI:
1658   case SystemZ::CGHI:
1659     if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1660       return 0;
1661     break;
1662   case SystemZ::CLFI:
1663   case SystemZ::CLGFI:
1664     if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1665       return 0;
1666     break;
1667   case SystemZ::CL:
1668   case SystemZ::CLG:
1669     if (!STI.hasMiscellaneousExtensions())
1670       return 0;
1671     if (!(MI && MI->getOperand(3).getReg() == 0))
1672       return 0;
1673     break;
1674   }
1675   switch (Type) {
1676   case SystemZII::CompareAndBranch:
1677     switch (Opcode) {
1678     case SystemZ::CR:
1679       return SystemZ::CRJ;
1680     case SystemZ::CGR:
1681       return SystemZ::CGRJ;
1682     case SystemZ::CHI:
1683       return SystemZ::CIJ;
1684     case SystemZ::CGHI:
1685       return SystemZ::CGIJ;
1686     case SystemZ::CLR:
1687       return SystemZ::CLRJ;
1688     case SystemZ::CLGR:
1689       return SystemZ::CLGRJ;
1690     case SystemZ::CLFI:
1691       return SystemZ::CLIJ;
1692     case SystemZ::CLGFI:
1693       return SystemZ::CLGIJ;
1694     default:
1695       return 0;
1696     }
1697   case SystemZII::CompareAndReturn:
1698     switch (Opcode) {
1699     case SystemZ::CR:
1700       return SystemZ::CRBReturn;
1701     case SystemZ::CGR:
1702       return SystemZ::CGRBReturn;
1703     case SystemZ::CHI:
1704       return SystemZ::CIBReturn;
1705     case SystemZ::CGHI:
1706       return SystemZ::CGIBReturn;
1707     case SystemZ::CLR:
1708       return SystemZ::CLRBReturn;
1709     case SystemZ::CLGR:
1710       return SystemZ::CLGRBReturn;
1711     case SystemZ::CLFI:
1712       return SystemZ::CLIBReturn;
1713     case SystemZ::CLGFI:
1714       return SystemZ::CLGIBReturn;
1715     default:
1716       return 0;
1717     }
1718   case SystemZII::CompareAndSibcall:
1719     switch (Opcode) {
1720     case SystemZ::CR:
1721       return SystemZ::CRBCall;
1722     case SystemZ::CGR:
1723       return SystemZ::CGRBCall;
1724     case SystemZ::CHI:
1725       return SystemZ::CIBCall;
1726     case SystemZ::CGHI:
1727       return SystemZ::CGIBCall;
1728     case SystemZ::CLR:
1729       return SystemZ::CLRBCall;
1730     case SystemZ::CLGR:
1731       return SystemZ::CLGRBCall;
1732     case SystemZ::CLFI:
1733       return SystemZ::CLIBCall;
1734     case SystemZ::CLGFI:
1735       return SystemZ::CLGIBCall;
1736     default:
1737       return 0;
1738     }
1739   case SystemZII::CompareAndTrap:
1740     switch (Opcode) {
1741     case SystemZ::CR:
1742       return SystemZ::CRT;
1743     case SystemZ::CGR:
1744       return SystemZ::CGRT;
1745     case SystemZ::CHI:
1746       return SystemZ::CIT;
1747     case SystemZ::CGHI:
1748       return SystemZ::CGIT;
1749     case SystemZ::CLR:
1750       return SystemZ::CLRT;
1751     case SystemZ::CLGR:
1752       return SystemZ::CLGRT;
1753     case SystemZ::CLFI:
1754       return SystemZ::CLFIT;
1755     case SystemZ::CLGFI:
1756       return SystemZ::CLGIT;
1757     case SystemZ::CL:
1758       return SystemZ::CLT;
1759     case SystemZ::CLG:
1760       return SystemZ::CLGT;
1761     default:
1762       return 0;
1763     }
1764   }
1765   return 0;
1766 }
1767 
1768 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1769   if (!STI.hasLoadAndTrap())
1770     return 0;
1771   switch (Opcode) {
1772   case SystemZ::L:
1773   case SystemZ::LY:
1774     return SystemZ::LAT;
1775   case SystemZ::LG:
1776     return SystemZ::LGAT;
1777   case SystemZ::LFH:
1778     return SystemZ::LFHAT;
1779   case SystemZ::LLGF:
1780     return SystemZ::LLGFAT;
1781   case SystemZ::LLGT:
1782     return SystemZ::LLGTAT;
1783   }
1784   return 0;
1785 }
1786 
1787 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1788                                      MachineBasicBlock::iterator MBBI,
1789                                      unsigned Reg, uint64_t Value) const {
1790   DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1791   unsigned Opcode;
1792   if (isInt<16>(Value))
1793     Opcode = SystemZ::LGHI;
1794   else if (SystemZ::isImmLL(Value))
1795     Opcode = SystemZ::LLILL;
1796   else if (SystemZ::isImmLH(Value)) {
1797     Opcode = SystemZ::LLILH;
1798     Value >>= 16;
1799   } else {
1800     assert(isInt<32>(Value) && "Huge values not handled yet");
1801     Opcode = SystemZ::LGFI;
1802   }
1803   BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1804 }
1805 
1806 bool SystemZInstrInfo::
1807 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1808                                 AliasAnalysis *AA) const {
1809 
1810   if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
1811     return false;
1812 
1813   // If mem-operands show that the same address Value is used by both
1814   // instructions, check for non-overlapping offsets and widths. Not
1815   // sure if a register based analysis would be an improvement...
1816 
1817   MachineMemOperand *MMOa = *MIa.memoperands_begin();
1818   MachineMemOperand *MMOb = *MIb.memoperands_begin();
1819   const Value *VALa = MMOa->getValue();
1820   const Value *VALb = MMOb->getValue();
1821   bool SameVal = (VALa && VALb && (VALa == VALb));
1822   if (!SameVal) {
1823     const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1824     const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1825     if (PSVa && PSVb && (PSVa == PSVb))
1826       SameVal = true;
1827   }
1828   if (SameVal) {
1829     int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
1830     int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
1831     int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1832     int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1833     int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1834     if (LowOffset + LowWidth <= HighOffset)
1835       return true;
1836   }
1837 
1838   return false;
1839 }
1840