1 //===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the SystemZ implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SystemZ.h" 15 #include "SystemZInstrBuilder.h" 16 #include "SystemZInstrInfo.h" 17 #include "SystemZMachineFunctionInfo.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZGenInstrInfo.inc" 20 #include "llvm/Function.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/CodeGen/PseudoSourceValue.h" 25 26 using namespace llvm; 27 28 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) 29 : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)), 30 RI(tm, *this), TM(tm) { 31 // Fill the spill offsets map 32 static const unsigned SpillOffsTab[][2] = { 33 { SystemZ::R2D, 0x10 }, 34 { SystemZ::R3D, 0x18 }, 35 { SystemZ::R4D, 0x20 }, 36 { SystemZ::R5D, 0x28 }, 37 { SystemZ::R6D, 0x30 }, 38 { SystemZ::R7D, 0x38 }, 39 { SystemZ::R8D, 0x40 }, 40 { SystemZ::R9D, 0x48 }, 41 { SystemZ::R10D, 0x50 }, 42 { SystemZ::R11D, 0x58 }, 43 { SystemZ::R12D, 0x60 }, 44 { SystemZ::R13D, 0x68 }, 45 { SystemZ::R14D, 0x70 }, 46 { SystemZ::R15D, 0x78 } 47 }; 48 49 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS); 50 51 for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i) 52 RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1]; 53 } 54 55 /// isGVStub - Return true if the GV requires an extra load to get the 56 /// real address. 57 static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) { 58 return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false); 59 } 60 61 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MI, 63 unsigned SrcReg, bool isKill, int FrameIdx, 64 const TargetRegisterClass *RC) const { 65 DebugLoc DL = DebugLoc::getUnknownLoc(); 66 if (MI != MBB.end()) DL = MI->getDebugLoc(); 67 68 unsigned Opc = 0; 69 if (RC == &SystemZ::GR32RegClass || 70 RC == &SystemZ::ADDR32RegClass) 71 Opc = SystemZ::MOV32mr; 72 else if (RC == &SystemZ::GR64RegClass || 73 RC == &SystemZ::ADDR64RegClass) { 74 Opc = SystemZ::MOV64mr; 75 } else if (RC == &SystemZ::FP32RegClass) { 76 Opc = SystemZ::FMOV32mr; 77 } else if (RC == &SystemZ::FP64RegClass) { 78 Opc = SystemZ::FMOV64mr; 79 } else if (RC == &SystemZ::GR64PRegClass) { 80 Opc = SystemZ::MOV64Pmr; 81 } else if (RC == &SystemZ::GR128RegClass) { 82 Opc = SystemZ::MOV128mr; 83 } else 84 llvm_unreachable("Unsupported regclass to store"); 85 86 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 87 .addReg(SrcReg, getKillRegState(isKill)); 88 } 89 90 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 91 MachineBasicBlock::iterator MI, 92 unsigned DestReg, int FrameIdx, 93 const TargetRegisterClass *RC) const{ 94 DebugLoc DL = DebugLoc::getUnknownLoc(); 95 if (MI != MBB.end()) DL = MI->getDebugLoc(); 96 97 unsigned Opc = 0; 98 if (RC == &SystemZ::GR32RegClass || 99 RC == &SystemZ::ADDR32RegClass) 100 Opc = SystemZ::MOV32rm; 101 else if (RC == &SystemZ::GR64RegClass || 102 RC == &SystemZ::ADDR64RegClass) { 103 Opc = SystemZ::MOV64rm; 104 } else if (RC == &SystemZ::FP32RegClass) { 105 Opc = SystemZ::FMOV32rm; 106 } else if (RC == &SystemZ::FP64RegClass) { 107 Opc = SystemZ::FMOV64rm; 108 } else if (RC == &SystemZ::GR64PRegClass) { 109 Opc = SystemZ::MOV64Prm; 110 } else if (RC == &SystemZ::GR128RegClass) { 111 Opc = SystemZ::MOV128rm; 112 } else 113 llvm_unreachable("Unsupported regclass to load"); 114 115 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 116 } 117 118 bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 119 MachineBasicBlock::iterator I, 120 unsigned DestReg, unsigned SrcReg, 121 const TargetRegisterClass *DestRC, 122 const TargetRegisterClass *SrcRC) const { 123 DebugLoc DL = DebugLoc::getUnknownLoc(); 124 if (I != MBB.end()) DL = I->getDebugLoc(); 125 126 // Determine if DstRC and SrcRC have a common superclass. 127 const TargetRegisterClass *CommonRC = DestRC; 128 if (DestRC == SrcRC) 129 /* Same regclass for source and dest */; 130 else if (CommonRC->hasSuperClass(SrcRC)) 131 CommonRC = SrcRC; 132 else if (!CommonRC->hasSubClass(SrcRC)) 133 CommonRC = 0; 134 135 if (CommonRC) { 136 if (CommonRC == &SystemZ::GR64RegClass || 137 CommonRC == &SystemZ::ADDR64RegClass) { 138 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg); 139 } else if (CommonRC == &SystemZ::GR32RegClass || 140 CommonRC == &SystemZ::ADDR32RegClass) { 141 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg); 142 } else if (CommonRC == &SystemZ::GR64PRegClass) { 143 BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg); 144 } else if (CommonRC == &SystemZ::GR128RegClass) { 145 BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg); 146 } else if (CommonRC == &SystemZ::FP32RegClass) { 147 BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg); 148 } else if (CommonRC == &SystemZ::FP64RegClass) { 149 BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg); 150 } else { 151 return false; 152 } 153 154 return true; 155 } 156 157 if ((SrcRC == &SystemZ::GR64RegClass && 158 DestRC == &SystemZ::ADDR64RegClass) || 159 (DestRC == &SystemZ::GR64RegClass && 160 SrcRC == &SystemZ::ADDR64RegClass)) { 161 BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg); 162 return true; 163 } else if ((SrcRC == &SystemZ::GR32RegClass && 164 DestRC == &SystemZ::ADDR32RegClass) || 165 (DestRC == &SystemZ::GR32RegClass && 166 SrcRC == &SystemZ::ADDR32RegClass)) { 167 BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg); 168 return true; 169 } 170 171 return false; 172 } 173 174 bool 175 SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, 176 unsigned &SrcReg, unsigned &DstReg, 177 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 178 switch (MI.getOpcode()) { 179 default: 180 return false; 181 case SystemZ::MOV32rr: 182 case SystemZ::MOV64rr: 183 case SystemZ::MOV64rrP: 184 case SystemZ::MOV128rr: 185 case SystemZ::FMOV32rr: 186 case SystemZ::FMOV64rr: 187 assert(MI.getNumOperands() >= 2 && 188 MI.getOperand(0).isReg() && 189 MI.getOperand(1).isReg() && 190 "invalid register-register move instruction"); 191 SrcReg = MI.getOperand(1).getReg(); 192 DstReg = MI.getOperand(0).getReg(); 193 SrcSubIdx = MI.getOperand(1).getSubReg(); 194 DstSubIdx = MI.getOperand(0).getSubReg(); 195 return true; 196 } 197 } 198 199 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 200 int &FrameIndex) const { 201 switch (MI->getOpcode()) { 202 default: break; 203 case SystemZ::MOV32rm: 204 case SystemZ::MOV32rmy: 205 case SystemZ::MOV64rm: 206 case SystemZ::MOVSX32rm8: 207 case SystemZ::MOVSX32rm16y: 208 case SystemZ::MOVSX64rm8: 209 case SystemZ::MOVSX64rm16: 210 case SystemZ::MOVSX64rm32: 211 case SystemZ::MOVZX32rm8: 212 case SystemZ::MOVZX32rm16: 213 case SystemZ::MOVZX64rm8: 214 case SystemZ::MOVZX64rm16: 215 case SystemZ::MOVZX64rm32: 216 case SystemZ::FMOV32rm: 217 case SystemZ::FMOV32rmy: 218 case SystemZ::FMOV64rm: 219 case SystemZ::FMOV64rmy: 220 case SystemZ::MOV64Prm: 221 case SystemZ::MOV64Prmy: 222 case SystemZ::MOV128rm: 223 if (MI->getOperand(1).isFI() && 224 MI->getOperand(2).isImm() && MI->getOperand(3).isReg() && 225 MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) { 226 FrameIndex = MI->getOperand(1).getIndex(); 227 return MI->getOperand(0).getReg(); 228 } 229 break; 230 } 231 return 0; 232 } 233 234 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 235 int &FrameIndex) const { 236 switch (MI->getOpcode()) { 237 default: break; 238 case SystemZ::MOV32mr: 239 case SystemZ::MOV32mry: 240 case SystemZ::MOV64mr: 241 case SystemZ::MOV32m8r: 242 case SystemZ::MOV32m8ry: 243 case SystemZ::MOV32m16r: 244 case SystemZ::MOV32m16ry: 245 case SystemZ::MOV64m8r: 246 case SystemZ::MOV64m8ry: 247 case SystemZ::MOV64m16r: 248 case SystemZ::MOV64m16ry: 249 case SystemZ::MOV64m32r: 250 case SystemZ::MOV64m32ry: 251 case SystemZ::FMOV32mr: 252 case SystemZ::FMOV32mry: 253 case SystemZ::FMOV64mr: 254 case SystemZ::FMOV64mry: 255 case SystemZ::MOV64Pmr: 256 case SystemZ::MOV64Pmry: 257 case SystemZ::MOV128mr: 258 if (MI->getOperand(0).isFI() && 259 MI->getOperand(1).isImm() && MI->getOperand(2).isReg() && 260 MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) { 261 FrameIndex = MI->getOperand(0).getIndex(); 262 return MI->getOperand(3).getReg(); 263 } 264 break; 265 } 266 return 0; 267 } 268 269 bool SystemZInstrInfo::isInvariantLoad(const MachineInstr *MI) const { 270 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 271 const MachineOperand &MO = MI->getOperand(i); 272 // Loads from constant pools are trivially invariant. 273 if (MO.isCPI()) 274 return true; 275 276 if (MO.isGlobal()) 277 return isGVStub(MO.getGlobal(), TM); 278 279 // If this is a load from an invariant stack slot, the load is a constant. 280 if (MO.isFI()) { 281 const MachineFrameInfo &MFI = 282 *MI->getParent()->getParent()->getFrameInfo(); 283 int Idx = MO.getIndex(); 284 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx); 285 } 286 } 287 288 // All other instances of these instructions are presumed to have other 289 // issues. 290 return false; 291 } 292 293 bool 294 SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 295 MachineBasicBlock::iterator MI, 296 const std::vector<CalleeSavedInfo> &CSI) const { 297 if (CSI.empty()) 298 return false; 299 300 DebugLoc DL = DebugLoc::getUnknownLoc(); 301 if (MI != MBB.end()) DL = MI->getDebugLoc(); 302 303 MachineFunction &MF = *MBB.getParent(); 304 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 305 unsigned CalleeFrameSize = 0; 306 307 // Scan the callee-saved and find the bounds of register spill area. 308 unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0; 309 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 310 unsigned Reg = CSI[i].getReg(); 311 const TargetRegisterClass *RegClass = CSI[i].getRegClass(); 312 if (RegClass != &SystemZ::FP64RegClass) { 313 unsigned Offset = RegSpillOffsets[Reg]; 314 CalleeFrameSize += 8; 315 if (StartOffset > Offset) { 316 LowReg = Reg; StartOffset = Offset; 317 } 318 if (EndOffset < Offset) { 319 HighReg = Reg; EndOffset = RegSpillOffsets[Reg]; 320 } 321 } 322 } 323 324 // Save information for epilogue inserter. 325 MFI->setCalleeSavedFrameSize(CalleeFrameSize); 326 MFI->setLowReg(LowReg); MFI->setHighReg(HighReg); 327 328 // Save GPRs 329 if (StartOffset) { 330 // Build a store instruction. Use STORE MULTIPLE instruction if there are many 331 // registers to store, otherwise - just STORE. 332 MachineInstrBuilder MIB = 333 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 334 SystemZ::MOV64mr : SystemZ::MOV64mrm))); 335 336 // Add store operands. 337 MIB.addReg(SystemZ::R15D).addImm(StartOffset); 338 if (LowReg == HighReg) 339 MIB.addReg(0); 340 MIB.addReg(LowReg, RegState::Kill); 341 if (LowReg != HighReg) 342 MIB.addReg(HighReg, RegState::Kill); 343 344 // Do a second scan adding regs as being killed by instruction 345 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 346 unsigned Reg = CSI[i].getReg(); 347 // Add the callee-saved register as live-in. It's killed at the spill. 348 MBB.addLiveIn(Reg); 349 if (Reg != LowReg && Reg != HighReg) 350 MIB.addReg(Reg, RegState::ImplicitKill); 351 } 352 } 353 354 // Save FPRs 355 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 356 unsigned Reg = CSI[i].getReg(); 357 const TargetRegisterClass *RegClass = CSI[i].getRegClass(); 358 if (RegClass == &SystemZ::FP64RegClass) { 359 MBB.addLiveIn(Reg); 360 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass); 361 } 362 } 363 364 return true; 365 } 366 367 bool 368 SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 369 MachineBasicBlock::iterator MI, 370 const std::vector<CalleeSavedInfo> &CSI) const { 371 if (CSI.empty()) 372 return false; 373 374 DebugLoc DL = DebugLoc::getUnknownLoc(); 375 if (MI != MBB.end()) DL = MI->getDebugLoc(); 376 377 MachineFunction &MF = *MBB.getParent(); 378 const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo(); 379 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>(); 380 381 // Restore FP registers 382 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 383 unsigned Reg = CSI[i].getReg(); 384 const TargetRegisterClass *RegClass = CSI[i].getRegClass(); 385 if (RegClass == &SystemZ::FP64RegClass) 386 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass); 387 } 388 389 // Restore GP registers 390 unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg(); 391 unsigned StartOffset = RegSpillOffsets[LowReg]; 392 393 if (StartOffset) { 394 // Build a load instruction. Use LOAD MULTIPLE instruction if there are many 395 // registers to load, otherwise - just LOAD. 396 MachineInstrBuilder MIB = 397 BuildMI(MBB, MI, DL, get((LowReg == HighReg ? 398 SystemZ::MOV64rm : SystemZ::MOV64rmm))); 399 // Add store operands. 400 MIB.addReg(LowReg, RegState::Define); 401 if (LowReg != HighReg) 402 MIB.addReg(HighReg, RegState::Define); 403 404 MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)); 405 MIB.addImm(StartOffset); 406 if (LowReg == HighReg) 407 MIB.addReg(0); 408 409 // Do a second scan adding regs as being defined by instruction 410 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 411 unsigned Reg = CSI[i].getReg(); 412 if (Reg != LowReg && Reg != HighReg) 413 MIB.addReg(Reg, RegState::ImplicitDefine); 414 } 415 } 416 417 return true; 418 } 419 420 bool SystemZInstrInfo:: 421 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 422 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 423 424 SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm()); 425 Cond[0].setImm(getOppositeCondition(CC)); 426 return false; 427 } 428 429 bool SystemZInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB)const{ 430 if (MBB.empty()) return false; 431 432 switch (MBB.back().getOpcode()) { 433 case SystemZ::RET: // Return. 434 case SystemZ::JMP: // Uncond branch. 435 case SystemZ::JMPr: // Indirect branch. 436 return true; 437 default: return false; 438 } 439 } 440 441 bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 442 const TargetInstrDesc &TID = MI->getDesc(); 443 if (!TID.isTerminator()) return false; 444 445 // Conditional branch is a special case. 446 if (TID.isBranch() && !TID.isBarrier()) 447 return true; 448 if (!TID.isPredicable()) 449 return true; 450 return !isPredicated(MI); 451 } 452 453 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 454 MachineBasicBlock *&TBB, 455 MachineBasicBlock *&FBB, 456 SmallVectorImpl<MachineOperand> &Cond, 457 bool AllowModify) const { 458 // Start from the bottom of the block and work up, examining the 459 // terminator instructions. 460 MachineBasicBlock::iterator I = MBB.end(); 461 while (I != MBB.begin()) { 462 --I; 463 // Working from the bottom, when we see a non-terminator 464 // instruction, we're done. 465 if (!isUnpredicatedTerminator(I)) 466 break; 467 468 // A terminator that isn't a branch can't easily be handled 469 // by this analysis. 470 if (!I->getDesc().isBranch()) 471 return true; 472 473 // Handle unconditional branches. 474 if (I->getOpcode() == SystemZ::JMP) { 475 if (!AllowModify) { 476 TBB = I->getOperand(0).getMBB(); 477 continue; 478 } 479 480 // If the block has any instructions after a JMP, delete them. 481 while (next(I) != MBB.end()) 482 next(I)->eraseFromParent(); 483 Cond.clear(); 484 FBB = 0; 485 486 // Delete the JMP if it's equivalent to a fall-through. 487 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 488 TBB = 0; 489 I->eraseFromParent(); 490 I = MBB.end(); 491 continue; 492 } 493 494 // TBB is used to indicate the unconditinal destination. 495 TBB = I->getOperand(0).getMBB(); 496 continue; 497 } 498 499 // Handle conditional branches. 500 SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode()); 501 if (BranchCode == SystemZCC::INVALID) 502 return true; // Can't handle indirect branch. 503 504 // Working from the bottom, handle the first conditional branch. 505 if (Cond.empty()) { 506 FBB = TBB; 507 TBB = I->getOperand(0).getMBB(); 508 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 509 continue; 510 } 511 512 // Handle subsequent conditional branches. Only handle the case where all 513 // conditional branches branch to the same destination. 514 assert(Cond.size() == 1); 515 assert(TBB); 516 517 // Only handle the case where all conditional branches branch to 518 // the same destination. 519 if (TBB != I->getOperand(0).getMBB()) 520 return true; 521 522 SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm(); 523 // If the conditions are the same, we can leave them alone. 524 if (OldBranchCode == BranchCode) 525 continue; 526 527 return true; 528 } 529 530 return false; 531 } 532 533 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 534 MachineBasicBlock::iterator I = MBB.end(); 535 unsigned Count = 0; 536 537 while (I != MBB.begin()) { 538 --I; 539 if (I->getOpcode() != SystemZ::JMP && 540 getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID) 541 break; 542 // Remove the branch. 543 I->eraseFromParent(); 544 I = MBB.end(); 545 ++Count; 546 } 547 548 return Count; 549 } 550 551 unsigned 552 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 553 MachineBasicBlock *FBB, 554 const SmallVectorImpl<MachineOperand> &Cond) const { 555 // FIXME: this should probably have a DebugLoc operand 556 DebugLoc dl = DebugLoc::getUnknownLoc(); 557 // Shouldn't be a fall through. 558 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 559 assert((Cond.size() == 1 || Cond.size() == 0) && 560 "SystemZ branch conditions have one component!"); 561 562 if (Cond.empty()) { 563 // Unconditional branch? 564 assert(!FBB && "Unconditional branch with multiple successors!"); 565 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(TBB); 566 return 1; 567 } 568 569 // Conditional branch. 570 unsigned Count = 0; 571 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm(); 572 BuildMI(&MBB, dl, getBrCond(CC)).addMBB(TBB); 573 ++Count; 574 575 if (FBB) { 576 // Two-way Conditional branch. Insert the second branch. 577 BuildMI(&MBB, dl, get(SystemZ::JMP)).addMBB(FBB); 578 ++Count; 579 } 580 return Count; 581 } 582 583 const TargetInstrDesc& 584 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const { 585 switch (CC) { 586 default: 587 llvm_unreachable("Unknown condition code!"); 588 case SystemZCC::O: return get(SystemZ::JO); 589 case SystemZCC::H: return get(SystemZ::JH); 590 case SystemZCC::NLE: return get(SystemZ::JNLE); 591 case SystemZCC::L: return get(SystemZ::JL); 592 case SystemZCC::NHE: return get(SystemZ::JNHE); 593 case SystemZCC::LH: return get(SystemZ::JLH); 594 case SystemZCC::NE: return get(SystemZ::JNE); 595 case SystemZCC::E: return get(SystemZ::JE); 596 case SystemZCC::NLH: return get(SystemZ::JNLH); 597 case SystemZCC::HE: return get(SystemZ::JHE); 598 case SystemZCC::NL: return get(SystemZ::JNL); 599 case SystemZCC::LE: return get(SystemZ::JLE); 600 case SystemZCC::NH: return get(SystemZ::JNH); 601 case SystemZCC::NO: return get(SystemZ::JNO); 602 } 603 } 604 605 SystemZCC::CondCodes 606 SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const { 607 switch (Opc) { 608 default: return SystemZCC::INVALID; 609 case SystemZ::JO: return SystemZCC::O; 610 case SystemZ::JH: return SystemZCC::H; 611 case SystemZ::JNLE: return SystemZCC::NLE; 612 case SystemZ::JL: return SystemZCC::L; 613 case SystemZ::JNHE: return SystemZCC::NHE; 614 case SystemZ::JLH: return SystemZCC::LH; 615 case SystemZ::JNE: return SystemZCC::NE; 616 case SystemZ::JE: return SystemZCC::E; 617 case SystemZ::JNLH: return SystemZCC::NLH; 618 case SystemZ::JHE: return SystemZCC::HE; 619 case SystemZ::JNL: return SystemZCC::NL; 620 case SystemZ::JLE: return SystemZCC::LE; 621 case SystemZ::JNH: return SystemZCC::NH; 622 case SystemZ::JNO: return SystemZCC::NO; 623 } 624 } 625 626 SystemZCC::CondCodes 627 SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const { 628 switch (CC) { 629 default: 630 llvm_unreachable("Invalid condition!"); 631 case SystemZCC::O: return SystemZCC::NO; 632 case SystemZCC::H: return SystemZCC::NH; 633 case SystemZCC::NLE: return SystemZCC::LE; 634 case SystemZCC::L: return SystemZCC::NL; 635 case SystemZCC::NHE: return SystemZCC::HE; 636 case SystemZCC::LH: return SystemZCC::NLH; 637 case SystemZCC::NE: return SystemZCC::E; 638 case SystemZCC::E: return SystemZCC::NE; 639 case SystemZCC::NLH: return SystemZCC::LH; 640 case SystemZCC::HE: return SystemZCC::NHE; 641 case SystemZCC::NL: return SystemZCC::L; 642 case SystemZCC::LE: return SystemZCC::NLE; 643 case SystemZCC::NH: return SystemZCC::H; 644 case SystemZCC::NO: return SystemZCC::O; 645 } 646 } 647 648 const TargetInstrDesc& 649 SystemZInstrInfo::getLongDispOpc(unsigned Opc) const { 650 switch (Opc) { 651 default: 652 llvm_unreachable("Don't have long disp version of this instruction"); 653 case SystemZ::MOV32mr: return get(SystemZ::MOV32mry); 654 case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy); 655 case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y); 656 case SystemZ::MOV32m8r: return get(SystemZ::MOV32m8ry); 657 case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry); 658 case SystemZ::MOV64m8r: return get(SystemZ::MOV64m8ry); 659 case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry); 660 case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry); 661 case SystemZ::MOV8mi: return get(SystemZ::MOV8miy); 662 case SystemZ::MUL32rm: return get(SystemZ::MUL32rmy); 663 case SystemZ::CMP32rm: return get(SystemZ::CMP32rmy); 664 case SystemZ::UCMP32rm: return get(SystemZ::UCMP32rmy); 665 case SystemZ::FMOV32mr: return get(SystemZ::FMOV32mry); 666 case SystemZ::FMOV64mr: return get(SystemZ::FMOV64mry); 667 case SystemZ::FMOV32rm: return get(SystemZ::FMOV32rmy); 668 case SystemZ::FMOV64rm: return get(SystemZ::FMOV64rmy); 669 case SystemZ::MOV64Pmr: return get(SystemZ::MOV64Pmry); 670 case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy); 671 } 672 } 673