1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Basic SystemZ instruction definition
12//===----------------------------------------------------------------------===//
13
14class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15                  list<dag> pattern> : Instruction {
16  let Namespace = "SystemZ";
17
18  dag OutOperandList = outs;
19  dag InOperandList = ins;
20  let Size = size;
21  let Pattern = pattern;
22  let AsmString = asmstr;
23
24  // Some instructions come in pairs, one having a 12-bit displacement
25  // and the other having a 20-bit displacement.  Both instructions in
26  // the pair have the same DispKey and their DispSizes are "12" and "20"
27  // respectively.
28  string DispKey = "";
29  string DispSize = "none";
30
31  // Many register-based <INSN>R instructions have a memory-based <INSN>
32  // counterpart.  OpKey uniquely identifies <INSN>, while OpType is
33  // "reg" for <INSN>R and "mem" for <INSN>.
34  string OpKey = "";
35  string OpType = "none";
36
37  // Many distinct-operands instructions have older 2-operand equivalents.
38  // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39  // with NumOpsValue being "2" or "3" as appropriate.
40  string NumOpsKey = "";
41  string NumOpsValue = "none";
42
43  // True if this instruction is a simple D(X,B) load of a register
44  // (with no sign or zero extension).
45  bit SimpleBDXLoad = 0;
46
47  // True if this instruction is a simple D(X,B) store of a register
48  // (with no truncation).
49  bit SimpleBDXStore = 0;
50
51  // True if this instruction has a 20-bit displacement field.
52  bit Has20BitOffset = 0;
53
54  // True if addresses in this instruction have an index register.
55  bit HasIndex = 0;
56
57  // True if this is a 128-bit pseudo instruction that combines two 64-bit
58  // operations.
59  bit Is128Bit = 0;
60
61  // The access size of all memory operands in bytes, or 0 if not known.
62  bits<5> AccessBytes = 0;
63
64  // If the instruction sets CC to a useful value, this gives the mask
65  // of all possible CC results.  The mask has the same form as
66  // SystemZ::CCMASK_*.
67  bits<4> CCValues = 0;
68
69  // The subset of CCValues that have the same meaning as they would after
70  // a comparison of the first operand against zero.
71  bits<4> CompareZeroCCMask = 0;
72
73  // True if the instruction is conditional and if the CC mask operand
74  // comes first (as for BRC, etc.).
75  bit CCMaskFirst = 0;
76
77  // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
78  bit CCMaskLast = 0;
79
80  // True if the instruction is the "logical" rather than "arithmetic" form,
81  // in cases where a distinction exists.
82  bit IsLogical = 0;
83
84  let TSFlags{0}     = SimpleBDXLoad;
85  let TSFlags{1}     = SimpleBDXStore;
86  let TSFlags{2}     = Has20BitOffset;
87  let TSFlags{3}     = HasIndex;
88  let TSFlags{4}     = Is128Bit;
89  let TSFlags{9-5}   = AccessBytes;
90  let TSFlags{13-10} = CCValues;
91  let TSFlags{17-14} = CompareZeroCCMask;
92  let TSFlags{18}    = CCMaskFirst;
93  let TSFlags{19}    = CCMaskLast;
94  let TSFlags{20}    = IsLogical;
95}
96
97//===----------------------------------------------------------------------===//
98// Mappings between instructions
99//===----------------------------------------------------------------------===//
100
101// Return the version of an instruction that has an unsigned 12-bit
102// displacement.
103def getDisp12Opcode : InstrMapping {
104  let FilterClass = "InstSystemZ";
105  let RowFields = ["DispKey"];
106  let ColFields = ["DispSize"];
107  let KeyCol = ["20"];
108  let ValueCols = [["12"]];
109}
110
111// Return the version of an instruction that has a signed 20-bit displacement.
112def getDisp20Opcode : InstrMapping {
113  let FilterClass = "InstSystemZ";
114  let RowFields = ["DispKey"];
115  let ColFields = ["DispSize"];
116  let KeyCol = ["12"];
117  let ValueCols = [["20"]];
118}
119
120// Return the memory form of a register instruction.
121def getMemOpcode : InstrMapping {
122  let FilterClass = "InstSystemZ";
123  let RowFields = ["OpKey"];
124  let ColFields = ["OpType"];
125  let KeyCol = ["reg"];
126  let ValueCols = [["mem"]];
127}
128
129// Return the 3-operand form of a 2-operand instruction.
130def getThreeOperandOpcode : InstrMapping {
131  let FilterClass = "InstSystemZ";
132  let RowFields = ["NumOpsKey"];
133  let ColFields = ["NumOpsValue"];
134  let KeyCol = ["2"];
135  let ValueCols = [["3"]];
136}
137
138//===----------------------------------------------------------------------===//
139// Instruction formats
140//===----------------------------------------------------------------------===//
141//
142// Formats are specified using operand field declarations of the form:
143//
144//   bits<4> Rn   : register input or output for operand n
145//   bits<5> Vn   : vector register input or output for operand n
146//   bits<m> In   : immediate value of width m for operand n
147//   bits<4> BDn  : address operand n, which has a base and a displacement
148//   bits<m> XBDn : address operand n, which has an index, a base and a
149//                  displacement
150//   bits<m> VBDn : address operand n, which has a vector index, a base and a
151//                  displacement
152//   bits<4> Xn   : index register for address operand n
153//   bits<4> Mn   : mode value for operand n
154//
155// The operand numbers ("n" in the list above) follow the architecture manual.
156// Assembly operands sometimes have a different order; in particular, R3 often
157// is often written between operands 1 and 2.
158//
159//===----------------------------------------------------------------------===//
160
161class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162  : InstSystemZ<2, outs, ins, asmstr, pattern> {
163  field bits<16> Inst;
164  field bits<16> SoftFail = 0;
165
166  let Inst = op;
167}
168
169class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
170  : InstSystemZ<2, outs, ins, asmstr, pattern> {
171  field bits<16> Inst;
172  field bits<16> SoftFail = 0;
173
174  bits<8> I1;
175
176  let Inst{15-8} = op;
177  let Inst{7-0}  = I1;
178}
179
180class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
181  : InstSystemZ<4, outs, ins, asmstr, pattern> {
182  field bits<32> Inst;
183  field bits<32> SoftFail = 0;
184
185  bits<4> R1;
186  bits<16> I2;
187
188  let Inst{31-24} = op{11-4};
189  let Inst{23-20} = R1;
190  let Inst{19-16} = op{3-0};
191  let Inst{15-0}  = I2;
192}
193
194class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195  : InstSystemZ<6, outs, ins, asmstr, pattern> {
196  field bits<48> Inst;
197  field bits<48> SoftFail = 0;
198
199  bits<4> R1;
200  bits<16> I2;
201  bits<4> M3;
202
203  let Inst{47-40} = op{15-8};
204  let Inst{39-36} = R1;
205  let Inst{35-32} = 0;
206  let Inst{31-16} = I2;
207  let Inst{15-12} = M3;
208  let Inst{11-8}  = 0;
209  let Inst{7-0}   = op{7-0};
210}
211
212class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
213  : InstSystemZ<6, outs, ins, asmstr, pattern> {
214  field bits<48> Inst;
215  field bits<48> SoftFail = 0;
216
217  bits<4> R1;
218  bits<4> R2;
219  bits<4> M3;
220  bits<16> RI4;
221
222  let Inst{47-40} = op{15-8};
223  let Inst{39-36} = R1;
224  let Inst{35-32} = R2;
225  let Inst{31-16} = RI4;
226  let Inst{15-12} = M3;
227  let Inst{11-8}  = 0;
228  let Inst{7-0}   = op{7-0};
229}
230
231class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
232  : InstSystemZ<6, outs, ins, asmstr, pattern> {
233  field bits<48> Inst;
234  field bits<48> SoftFail = 0;
235
236  bits<4> R1;
237  bits<8> I2;
238  bits<4> M3;
239  bits<16> RI4;
240
241  let Inst{47-40} = op{15-8};
242  let Inst{39-36} = R1;
243  let Inst{35-32} = M3;
244  let Inst{31-16} = RI4;
245  let Inst{15-8}  = I2;
246  let Inst{7-0}   = op{7-0};
247}
248
249class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
250  : InstSystemZ<6, outs, ins, asmstr, pattern> {
251  field bits<48> Inst;
252  field bits<48> SoftFail = 0;
253
254  bits<4> R1;
255  bits<4> R3;
256  bits<16> I2;
257
258  let Inst{47-40} = op{15-8};
259  let Inst{39-36} = R1;
260  let Inst{35-32} = R3;
261  let Inst{31-16} = I2;
262  let Inst{15-8}  = 0;
263  let Inst{7-0}   = op{7-0};
264}
265
266class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
267  : InstSystemZ<6, outs, ins, asmstr, pattern> {
268  field bits<48> Inst;
269  field bits<48> SoftFail = 0;
270
271  bits<4> R1;
272  bits<4> R2;
273  bits<8> I3;
274  bits<8> I4;
275  bits<8> I5;
276
277  let Inst{47-40} = op{15-8};
278  let Inst{39-36} = R1;
279  let Inst{35-32} = R2;
280  let Inst{31-24} = I3;
281  let Inst{23-16} = I4;
282  let Inst{15-8}  = I5;
283  let Inst{7-0}   = op{7-0};
284}
285
286class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
287  : InstSystemZ<6, outs, ins, asmstr, pattern> {
288  field bits<48> Inst;
289  field bits<48> SoftFail = 0;
290
291  bits<4> R1;
292  bits<32> I2;
293
294  let Inst{47-40} = op{11-4};
295  let Inst{39-36} = R1;
296  let Inst{35-32} = op{3-0};
297  let Inst{31-0}  = I2;
298}
299
300class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
301  : InstSystemZ<6, outs, ins, asmstr, pattern> {
302  field bits<48> Inst;
303  field bits<48> SoftFail = 0;
304
305  bits<4> R1;
306  bits<8> I2;
307  bits<4> M3;
308  bits<16> BD4;
309
310  let Inst{47-40} = op{15-8};
311  let Inst{39-36} = R1;
312  let Inst{35-32} = M3;
313  let Inst{31-16} = BD4;
314  let Inst{15-8}  = I2;
315  let Inst{7-0}   = op{7-0};
316}
317
318class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
319  : InstSystemZ<2, outs, ins, asmstr, pattern> {
320  field bits<16> Inst;
321  field bits<16> SoftFail = 0;
322
323  bits<4> R1;
324  bits<4> R2;
325
326  let Inst{15-8} = op;
327  let Inst{7-4}  = R1;
328  let Inst{3-0}  = R2;
329}
330
331class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
332  : InstSystemZ<4, outs, ins, asmstr, pattern> {
333  field bits<32> Inst;
334  field bits<32> SoftFail = 0;
335
336  bits<4> R1;
337  bits<4> R3;
338  bits<4> R2;
339
340  let Inst{31-16} = op;
341  let Inst{15-12} = R1;
342  let Inst{11-8}  = 0;
343  let Inst{7-4}   = R3;
344  let Inst{3-0}   = R2;
345}
346
347class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
348  : InstSystemZ<4, outs, ins, asmstr, pattern> {
349  field bits<32> Inst;
350  field bits<32> SoftFail = 0;
351
352  bits<4> R1;
353  bits<4> R2;
354
355  let Inst{31-16} = op;
356  let Inst{15-8}  = 0;
357  let Inst{7-4}   = R1;
358  let Inst{3-0}   = R2;
359}
360
361class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
362  : InstSystemZ<4, outs, ins, asmstr, pattern> {
363  field bits<32> Inst;
364  field bits<32> SoftFail = 0;
365
366  bits<4> R1;
367  bits<4> R2;
368  bits<4> R3;
369  bits<4> R4;
370
371  let Inst{31-16} = op;
372  let Inst{15-12} = R3;
373  let Inst{11-8}  = R4;
374  let Inst{7-4}   = R1;
375  let Inst{3-0}   = R2;
376}
377
378class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
379  : InstSystemZ<4, outs, ins, asmstr, pattern> {
380  field bits<32> Inst;
381  field bits<32> SoftFail = 0;
382
383  bits<4> R1;
384  bits<4> R2;
385  bits<4> M3;
386
387  let Inst{31-16} = op;
388  let Inst{15-12} = M3;
389  let Inst{11-8}  = 0;
390  let Inst{7-4}   = R1;
391  let Inst{3-0}   = R2;
392}
393
394class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
395  : InstSystemZ<6, outs, ins, asmstr, pattern> {
396  field bits<48> Inst;
397  field bits<48> SoftFail = 0;
398
399  bits<4> R1;
400  bits<4> R2;
401  bits<4> M3;
402  bits<16> BD4;
403
404  let Inst{47-40} = op{15-8};
405  let Inst{39-36} = R1;
406  let Inst{35-32} = R2;
407  let Inst{31-16} = BD4;
408  let Inst{15-12} = M3;
409  let Inst{11-8}  = 0;
410  let Inst{7-0}   = op{7-0};
411}
412
413class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
414  : InstSystemZ<4, outs, ins, asmstr, pattern> {
415  field bits<32> Inst;
416  field bits<32> SoftFail = 0;
417
418  bits<4> R1;
419  bits<20> XBD2;
420
421  let Inst{31-24} = op;
422  let Inst{23-20} = R1;
423  let Inst{19-0}  = XBD2;
424
425  let HasIndex = 1;
426}
427
428class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
429  : InstSystemZ<6, outs, ins, asmstr, pattern> {
430  field bits<48> Inst;
431  field bits<48> SoftFail = 0;
432
433  bits<4> R1;
434  bits<20> XBD2;
435  bits<4> M3;
436
437  let Inst{47-40} = op{15-8};
438  let Inst{39-36} = R1;
439  let Inst{35-16} = XBD2;
440  let Inst{15-12} = M3;
441  let Inst{11-8}  = 0;
442  let Inst{7-0}   = op{7-0};
443
444  let HasIndex = 1;
445}
446
447class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
448  : InstSystemZ<6, outs, ins, asmstr, pattern> {
449  field bits<48> Inst;
450  field bits<48> SoftFail = 0;
451
452  bits<4> R1;
453  bits<4> R3;
454  bits<20> XBD2;
455
456  let Inst{47-40} = op{15-8};
457  let Inst{39-36} = R3;
458  let Inst{35-16} = XBD2;
459  let Inst{15-12} = R1;
460  let Inst{11-8}  = 0;
461  let Inst{7-0}   = op{7-0};
462
463  let HasIndex = 1;
464}
465
466class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
467  : InstSystemZ<6, outs, ins, asmstr, pattern> {
468  field bits<48> Inst;
469  field bits<48> SoftFail = 0;
470
471  bits<4> R1;
472  bits<28> XBD2;
473
474  let Inst{47-40} = op{15-8};
475  let Inst{39-36} = R1;
476  let Inst{35-8}  = XBD2;
477  let Inst{7-0}   = op{7-0};
478
479  let Has20BitOffset = 1;
480  let HasIndex = 1;
481}
482
483class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
484  : InstSystemZ<4, outs, ins, asmstr, pattern> {
485  field bits<32> Inst;
486  field bits<32> SoftFail = 0;
487
488  bits<4> R1;
489  bits<4> R3;
490  bits<16> BD2;
491
492  let Inst{31-24} = op;
493  let Inst{23-20} = R1;
494  let Inst{19-16} = R3;
495  let Inst{15-0}  = BD2;
496}
497
498class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
499  : InstSystemZ<4, outs, ins, asmstr, pattern> {
500  field bits<32> Inst;
501  field bits<32> SoftFail = 0;
502
503  bits<4> R1;
504  bits<4> R3;
505  bits<16> RI2;
506
507  let Inst{31-24} = op;
508  let Inst{23-20} = R1;
509  let Inst{19-16} = R3;
510  let Inst{15-0}  = RI2;
511}
512
513class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
514  : InstSystemZ<6, outs, ins, asmstr, pattern> {
515  field bits<48> Inst;
516  field bits<48> SoftFail = 0;
517
518  bits<4> R1;
519  bits<4> R3;
520  bits<24> BD2;
521
522  let Inst{47-40} = op{15-8};
523  let Inst{39-36} = R1;
524  let Inst{35-32} = R3;
525  let Inst{31-8}  = BD2;
526  let Inst{7-0}   = op{7-0};
527
528  let Has20BitOffset = 1;
529}
530
531class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
532  : InstSystemZ<4, outs, ins, asmstr, pattern> {
533  field bits<32> Inst;
534  field bits<32> SoftFail = 0;
535
536  bits<16> BD1;
537  bits<8> I2;
538
539  let Inst{31-24} = op;
540  let Inst{23-16} = I2;
541  let Inst{15-0}  = BD1;
542}
543
544class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
545  : InstSystemZ<6, outs, ins, asmstr, pattern> {
546  field bits<48> Inst;
547  field bits<48> SoftFail = 0;
548
549  bits<16> BD1;
550  bits<16> I2;
551
552  let Inst{47-32} = op;
553  let Inst{31-16} = BD1;
554  let Inst{15-0}  = I2;
555}
556
557class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
558  : InstSystemZ<6, outs, ins, asmstr, pattern> {
559  field bits<48> Inst;
560  field bits<48> SoftFail = 0;
561
562  bits<24> BD1;
563  bits<8> I2;
564
565  let Inst{47-40} = op{15-8};
566  let Inst{39-32} = I2;
567  let Inst{31-8}  = BD1;
568  let Inst{7-0}   = op{7-0};
569
570  let Has20BitOffset = 1;
571}
572
573class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
574  : InstSystemZ<6, outs, ins, asmstr, pattern> {
575  field bits<48> Inst;
576  field bits<48> SoftFail = 0;
577
578  bits<24> BDL1;
579  bits<16> BD2;
580
581  let Inst{47-40} = op;
582  let Inst{39-16} = BDL1;
583  let Inst{15-0}  = BD2;
584}
585
586class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
587  : InstSystemZ<6, outs, ins, asmstr, pattern> {
588  field bits<48> Inst;
589  field bits<48> SoftFail = 0;
590
591  bits<20> XBD1;
592  bits<16> BD2;
593  bits<4> R3;
594
595  let Inst{47-40} = op;
596  let Inst{39-36} = XBD1{19-16};
597  let Inst{35-32} = R3;
598  let Inst{31-16} = XBD1{15-0};
599  let Inst{15-0}  = BD2;
600}
601
602class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
603  : InstSystemZ<6, outs, ins, asmstr, pattern> {
604  field bits<48> Inst;
605  field bits<48> SoftFail = 0;
606
607  bits<16> BD1;
608  bits<16> BD2;
609
610  let Inst{47-32} = op;
611  let Inst{31-16} = BD1;
612  let Inst{15-0}  = BD2;
613}
614
615class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
616  : InstSystemZ<6, outs, ins, asmstr, pattern> {
617  field bits<48> Inst;
618  field bits<48> SoftFail = 0;
619
620  bits<16> BD1;
621  bits<16> BD2;
622  bits<4>  R3;
623
624  let Inst{47-40} = op{11-4};
625  let Inst{39-36} = R3;
626  let Inst{35-32} = op{3-0};
627  let Inst{31-16} = BD1;
628  let Inst{15-0}  = BD2;
629}
630
631class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
632  : InstSystemZ<4, outs, ins, asmstr, pattern> {
633  field bits<32> Inst;
634  field bits<32> SoftFail = 0;
635
636  bits<16> BD2;
637
638  let Inst{31-16} = op;
639  let Inst{15-0}  = BD2;
640}
641
642class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
643  : InstSystemZ<6, outs, ins, asmstr, pattern> {
644  field bits<48> Inst;
645  field bits<48> SoftFail = 0;
646
647  bits<5> V1;
648  bits<16> I2;
649  bits<4> M3;
650
651  let Inst{47-40} = op{15-8};
652  let Inst{39-36} = V1{3-0};
653  let Inst{35-32} = 0;
654  let Inst{31-16} = I2;
655  let Inst{15-12} = M3;
656  let Inst{11}    = V1{4};
657  let Inst{10-8}  = 0;
658  let Inst{7-0}   = op{7-0};
659}
660
661class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
662  : InstSystemZ<6, outs, ins, asmstr, pattern> {
663  field bits<48> Inst;
664  field bits<48> SoftFail = 0;
665
666  bits<5> V1;
667  bits<8> I2;
668  bits<8> I3;
669  bits<4> M4;
670
671  let Inst{47-40} = op{15-8};
672  let Inst{39-36} = V1{3-0};
673  let Inst{35-32} = 0;
674  let Inst{31-24} = I2;
675  let Inst{23-16} = I3;
676  let Inst{15-12} = M4;
677  let Inst{11}    = V1{4};
678  let Inst{10-8}  = 0;
679  let Inst{7-0}   = op{7-0};
680}
681
682class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
683  : InstSystemZ<6, outs, ins, asmstr, pattern> {
684  field bits<48> Inst;
685  field bits<48> SoftFail = 0;
686
687  bits<5> V1;
688  bits<5> V3;
689  bits<16> I2;
690  bits<4> M4;
691
692  let Inst{47-40} = op{15-8};
693  let Inst{39-36} = V1{3-0};
694  let Inst{35-32} = V3{3-0};
695  let Inst{31-16} = I2;
696  let Inst{15-12} = M4;
697  let Inst{11}    = V1{4};
698  let Inst{10}    = V3{4};
699  let Inst{9-8}   = 0;
700  let Inst{7-0}   = op{7-0};
701}
702
703class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
704  : InstSystemZ<6, outs, ins, asmstr, pattern> {
705  field bits<48> Inst;
706  field bits<48> SoftFail = 0;
707
708  bits<5> V1;
709  bits<5> V2;
710  bits<5> V3;
711  bits<8> I4;
712  bits<4> M5;
713
714  let Inst{47-40} = op{15-8};
715  let Inst{39-36} = V1{3-0};
716  let Inst{35-32} = V2{3-0};
717  let Inst{31-28} = V3{3-0};
718  let Inst{27-24} = 0;
719  let Inst{23-16} = I4;
720  let Inst{15-12} = M5;
721  let Inst{11}    = V1{4};
722  let Inst{10}    = V2{4};
723  let Inst{9}     = V3{4};
724  let Inst{8}     = 0;
725  let Inst{7-0}   = op{7-0};
726}
727
728class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
729  : InstSystemZ<6, outs, ins, asmstr, pattern> {
730  field bits<48> Inst;
731  field bits<48> SoftFail = 0;
732
733  bits<5> V1;
734  bits<5> V2;
735  bits<12> I3;
736  bits<4> M4;
737  bits<4> M5;
738
739  let Inst{47-40} = op{15-8};
740  let Inst{39-36} = V1{3-0};
741  let Inst{35-32} = V2{3-0};
742  let Inst{31-20} = I3;
743  let Inst{19-16} = M5;
744  let Inst{15-12} = M4;
745  let Inst{11}    = V1{4};
746  let Inst{10}    = V2{4};
747  let Inst{9-8}   = 0;
748  let Inst{7-0}   = op{7-0};
749}
750
751// Depending on the instruction mnemonic, certain bits may be or-ed into
752// the M4 value provided as explicit operand.  These are passed as m4or.
753class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
754               bits<4> m4or = 0>
755  : InstSystemZ<6, outs, ins, asmstr, pattern> {
756  field bits<48> Inst;
757  field bits<48> SoftFail = 0;
758
759  bits<5> V1;
760  bits<5> V2;
761  bits<4> M3;
762  bits<4> M4;
763  bits<4> M5;
764
765  let Inst{47-40} = op{15-8};
766  let Inst{39-36} = V1{3-0};
767  let Inst{35-32} = V2{3-0};
768  let Inst{31-24} = 0;
769  let Inst{23-20} = M5;
770  let Inst{19}    = !if (!eq (m4or{3}, 1), 1, M4{3});
771  let Inst{18}    = !if (!eq (m4or{2}, 1), 1, M4{2});
772  let Inst{17}    = !if (!eq (m4or{1}, 1), 1, M4{1});
773  let Inst{16}    = !if (!eq (m4or{0}, 1), 1, M4{0});
774  let Inst{15-12} = M3;
775  let Inst{11}    = V1{4};
776  let Inst{10}    = V2{4};
777  let Inst{9-8}   = 0;
778  let Inst{7-0}   = op{7-0};
779}
780
781// Depending on the instruction mnemonic, certain bits may be or-ed into
782// the M5 value provided as explicit operand.  These are passed as m5or.
783class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
784               bits<4> m5or = 0>
785  : InstSystemZ<6, outs, ins, asmstr, pattern> {
786  field bits<48> Inst;
787  field bits<48> SoftFail = 0;
788
789  bits<5> V1;
790  bits<5> V2;
791  bits<5> V3;
792  bits<4> M4;
793  bits<4> M5;
794
795  let Inst{47-40} = op{15-8};
796  let Inst{39-36} = V1{3-0};
797  let Inst{35-32} = V2{3-0};
798  let Inst{31-28} = V3{3-0};
799  let Inst{27-24} = 0;
800  let Inst{23}    = !if (!eq (m5or{3}, 1), 1, M5{3});
801  let Inst{22}    = !if (!eq (m5or{2}, 1), 1, M5{2});
802  let Inst{21}    = !if (!eq (m5or{1}, 1), 1, M5{1});
803  let Inst{20}    = !if (!eq (m5or{0}, 1), 1, M5{0});
804  let Inst{19-16} = 0;
805  let Inst{15-12} = M4;
806  let Inst{11}    = V1{4};
807  let Inst{10}    = V2{4};
808  let Inst{9}     = V3{4};
809  let Inst{8}     = 0;
810  let Inst{7-0}   = op{7-0};
811}
812
813class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
814  : InstSystemZ<6, outs, ins, asmstr, pattern> {
815  field bits<48> Inst;
816  field bits<48> SoftFail = 0;
817
818  bits<5> V1;
819  bits<5> V2;
820  bits<5> V3;
821  bits<4> M4;
822  bits<4> M5;
823  bits<4> M6;
824
825  let Inst{47-40} = op{15-8};
826  let Inst{39-36} = V1{3-0};
827  let Inst{35-32} = V2{3-0};
828  let Inst{31-28} = V3{3-0};
829  let Inst{27-24} = 0;
830  let Inst{23-20} = M6;
831  let Inst{19-16} = M5;
832  let Inst{15-12} = M4;
833  let Inst{11}    = V1{4};
834  let Inst{10}    = V2{4};
835  let Inst{9}     = V3{4};
836  let Inst{8}     = 0;
837  let Inst{7-0}   = op{7-0};
838}
839
840// Depending on the instruction mnemonic, certain bits may be or-ed into
841// the M6 value provided as explicit operand.  These are passed as m6or.
842class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
843               bits<4> m6or = 0>
844  : InstSystemZ<6, outs, ins, asmstr, pattern> {
845  field bits<48> Inst;
846  field bits<48> SoftFail = 0;
847
848  bits<5> V1;
849  bits<5> V2;
850  bits<5> V3;
851  bits<5> V4;
852  bits<4> M5;
853  bits<4> M6;
854
855  let Inst{47-40} = op{15-8};
856  let Inst{39-36} = V1{3-0};
857  let Inst{35-32} = V2{3-0};
858  let Inst{31-28} = V3{3-0};
859  let Inst{27-24} = M5;
860  let Inst{23}    = !if (!eq (m6or{3}, 1), 1, M6{3});
861  let Inst{22}    = !if (!eq (m6or{2}, 1), 1, M6{2});
862  let Inst{21}    = !if (!eq (m6or{1}, 1), 1, M6{1});
863  let Inst{20}    = !if (!eq (m6or{0}, 1), 1, M6{0});
864  let Inst{19-16} = 0;
865  let Inst{15-12} = V4{3-0};
866  let Inst{11}    = V1{4};
867  let Inst{10}    = V2{4};
868  let Inst{9}     = V3{4};
869  let Inst{8}     = V4{4};
870  let Inst{7-0}   = op{7-0};
871}
872
873class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
874  : InstSystemZ<6, outs, ins, asmstr, pattern> {
875  field bits<48> Inst;
876  field bits<48> SoftFail = 0;
877
878  bits<5> V1;
879  bits<5> V2;
880  bits<5> V3;
881  bits<5> V4;
882  bits<4> M5;
883  bits<4> M6;
884
885  let Inst{47-40} = op{15-8};
886  let Inst{39-36} = V1{3-0};
887  let Inst{35-32} = V2{3-0};
888  let Inst{31-28} = V3{3-0};
889  let Inst{27-24} = M6;
890  let Inst{23-20} = 0;
891  let Inst{19-16} = M5;
892  let Inst{15-12} = V4{3-0};
893  let Inst{11}    = V1{4};
894  let Inst{10}    = V2{4};
895  let Inst{9}     = V3{4};
896  let Inst{8}     = V4{4};
897  let Inst{7-0}   = op{7-0};
898}
899
900class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
901  : InstSystemZ<6, outs, ins, asmstr, pattern> {
902  field bits<48> Inst;
903  field bits<48> SoftFail = 0;
904
905  bits<5> V1;
906  bits<4> R2;
907  bits<4> R3;
908
909  let Inst{47-40} = op{15-8};
910  let Inst{39-36} = V1{3-0};
911  let Inst{35-32} = R2;
912  let Inst{31-28} = R3;
913  let Inst{27-12} = 0;
914  let Inst{11}    = V1{4};
915  let Inst{10-8}  = 0;
916  let Inst{7-0}   = op{7-0};
917}
918
919class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
920  : InstSystemZ<6, outs, ins, asmstr, pattern> {
921  field bits<48> Inst;
922  field bits<48> SoftFail = 0;
923
924  bits<5> V1;
925  bits<16> BD2;
926  bits<5> V3;
927  bits<4> M4;
928
929  let Inst{47-40} = op{15-8};
930  let Inst{39-36} = V1{3-0};
931  let Inst{35-32} = V3{3-0};
932  let Inst{31-16} = BD2;
933  let Inst{15-12} = M4;
934  let Inst{11}    = V1{4};
935  let Inst{10}    = V3{4};
936  let Inst{9-8}   = 0;
937  let Inst{7-0}   = op{7-0};
938}
939
940class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
941  : InstSystemZ<6, outs, ins, asmstr, pattern> {
942  field bits<48> Inst;
943  field bits<48> SoftFail = 0;
944
945  bits<5> V1;
946  bits<16> BD2;
947  bits<4> R3;
948  bits<4> M4;
949
950  let Inst{47-40} = op{15-8};
951  let Inst{39-36} = V1{3-0};
952  let Inst{35-32} = R3;
953  let Inst{31-16} = BD2;
954  let Inst{15-12} = M4;
955  let Inst{11}    = V1{4};
956  let Inst{10-8}  = 0;
957  let Inst{7-0}   = op{7-0};
958}
959
960class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
961  : InstSystemZ<6, outs, ins, asmstr, pattern> {
962  field bits<48> Inst;
963  field bits<48> SoftFail = 0;
964
965  bits<4> R1;
966  bits<16> BD2;
967  bits<5> V3;
968  bits<4> M4;
969
970  let Inst{47-40} = op{15-8};
971  let Inst{39-36} = R1;
972  let Inst{35-32} = V3{3-0};
973  let Inst{31-16} = BD2;
974  let Inst{15-12} = M4;
975  let Inst{11}    = 0;
976  let Inst{10}    = V3{4};
977  let Inst{9-8}   = 0;
978  let Inst{7-0}   = op{7-0};
979}
980
981class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
982  : InstSystemZ<6, outs, ins, asmstr, pattern> {
983  field bits<48> Inst;
984  field bits<48> SoftFail = 0;
985
986  bits<5> V1;
987  bits<21> VBD2;
988  bits<4> M3;
989
990  let Inst{47-40} = op{15-8};
991  let Inst{39-36} = V1{3-0};
992  let Inst{35-16} = VBD2{19-0};
993  let Inst{15-12} = M3;
994  let Inst{11}    = V1{4};
995  let Inst{10}    = VBD2{20};
996  let Inst{9-8}   = 0;
997  let Inst{7-0}   = op{7-0};
998}
999
1000class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1001  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1002  field bits<48> Inst;
1003  field bits<48> SoftFail = 0;
1004
1005  bits<5> V1;
1006  bits<20> XBD2;
1007  bits<4> M3;
1008
1009  let Inst{47-40} = op{15-8};
1010  let Inst{39-36} = V1{3-0};
1011  let Inst{35-16} = XBD2;
1012  let Inst{15-12} = M3;
1013  let Inst{11}    = V1{4};
1014  let Inst{10-8}  = 0;
1015  let Inst{7-0}   = op{7-0};
1016}
1017
1018//===----------------------------------------------------------------------===//
1019// Instruction classes for .insn directives
1020//===----------------------------------------------------------------------===//
1021
1022class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
1023  : InstE<0, outs, ins, asmstr, pattern> {
1024  bits<16> enc;
1025
1026  let Inst = enc;
1027}
1028
1029class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1030  : InstRI<0, outs, ins, asmstr, pattern> {
1031  bits<32> enc;
1032
1033  let Inst{31-24} = enc{31-24};
1034  let Inst{19-16} = enc{19-16};
1035}
1036
1037class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
1038  : InstRIEd<0, outs, ins, asmstr, pattern> {
1039  bits<48> enc;
1040
1041  let Inst{47-40} = enc{47-40};
1042  let Inst{7-0}   = enc{7-0};
1043}
1044
1045class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1046  : InstRIL<0, outs, ins, asmstr, pattern> {
1047  bits<48> enc;
1048  string type;
1049
1050  let Inst{47-40} = enc{47-40};
1051  let Inst{35-32} = enc{35-32};
1052}
1053
1054class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
1055  : InstRIS<0, outs, ins, asmstr, pattern> {
1056  bits<48> enc;
1057
1058  let Inst{47-40} = enc{47-40};
1059  let Inst{7-0}   = enc{7-0};
1060}
1061
1062class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1063  : InstRR<0, outs, ins, asmstr, pattern> {
1064  bits<16> enc;
1065
1066  let Inst{15-8} = enc{15-8};
1067}
1068
1069class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
1070  : InstRRE<0, outs, ins, asmstr, pattern> {
1071  bits<32> enc;
1072
1073  let Inst{31-16} = enc{31-16};
1074}
1075
1076class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
1077  : InstRRF<0, outs, ins, asmstr, pattern> {
1078  bits<32> enc;
1079
1080  let Inst{31-16} = enc{31-16};
1081}
1082
1083class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1084  : InstRRS<0, outs, ins, asmstr, pattern> {
1085  bits<48> enc;
1086
1087  let Inst{47-40} = enc{47-40};
1088  let Inst{7-0}   = enc{7-0};
1089}
1090
1091class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1092  : InstRS<0, outs, ins, asmstr, pattern> {
1093  bits<32> enc;
1094
1095  let Inst{31-24} = enc{31-24};
1096}
1097
1098// RSE is like RSY except with a 12 bit displacement (instead of 20).
1099class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1100  : InstRSY<6, outs, ins, asmstr, pattern> {
1101  bits <48> enc;
1102
1103  let Inst{47-40} = enc{47-40};
1104  let Inst{31-16} = BD2{15-0};
1105  let Inst{15-8}  = 0;
1106  let Inst{7-0}   = enc{7-0};
1107}
1108
1109class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1110  : InstRSI<0, outs, ins, asmstr, pattern> {
1111  bits<32> enc;
1112
1113  let Inst{31-24} = enc{31-24};
1114}
1115
1116class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
1117  : InstRSY<0, outs, ins, asmstr, pattern> {
1118  bits<48> enc;
1119
1120  let Inst{47-40} = enc{47-40};
1121  let Inst{7-0}   = enc{7-0};
1122}
1123
1124class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1125  : InstRX<0, outs, ins, asmstr, pattern> {
1126  bits<32> enc;
1127
1128  let Inst{31-24} = enc{31-24};
1129}
1130
1131class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
1132  : InstRXE<0, outs, ins, asmstr, pattern> {
1133  bits<48> enc;
1134
1135  let M3 = 0;
1136
1137  let Inst{47-40} = enc{47-40};
1138  let Inst{7-0}   = enc{7-0};
1139}
1140
1141class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
1142  : InstRXF<0, outs, ins, asmstr, pattern> {
1143  bits<48> enc;
1144
1145  let Inst{47-40} = enc{47-40};
1146  let Inst{7-0}   = enc{7-0};
1147}
1148
1149class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
1150  : InstRXY<0, outs, ins, asmstr, pattern> {
1151  bits<48> enc;
1152
1153  let Inst{47-40} = enc{47-40};
1154  let Inst{7-0}   = enc{7-0};
1155}
1156
1157class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
1158  : InstS<0, outs, ins, asmstr, pattern> {
1159  bits<32> enc;
1160
1161  let Inst{31-16} = enc{31-16};
1162}
1163
1164class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1165  : InstSI<0, outs, ins, asmstr, pattern> {
1166  bits<32> enc;
1167
1168  let Inst{31-24} = enc{31-24};
1169}
1170
1171class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
1172  : InstSIY<0, outs, ins, asmstr, pattern> {
1173  bits<48> enc;
1174
1175  let Inst{47-40} = enc{47-40};
1176  let Inst{7-0}   = enc{7-0};
1177}
1178
1179class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1180  : InstSIL<0, outs, ins, asmstr, pattern> {
1181  bits<48> enc;
1182
1183  let Inst{47-32} = enc{47-32};
1184}
1185
1186class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
1187  : InstSSd<0, outs, ins, asmstr, pattern> {
1188  bits<48> enc;
1189
1190  let Inst{47-40} = enc{47-40};
1191}
1192
1193class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1194  : InstSSE<0, outs, ins, asmstr, pattern> {
1195  bits<48> enc;
1196
1197  let Inst{47-32} = enc{47-32};
1198}
1199
1200class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
1201  : InstSSF<0, outs, ins, asmstr, pattern> {
1202  bits<48> enc;
1203
1204  let Inst{47-40} = enc{47-40};
1205  let Inst{35-32} = enc{35-32};
1206}
1207
1208//===----------------------------------------------------------------------===//
1209// Instruction definitions with semantics
1210//===----------------------------------------------------------------------===//
1211//
1212// These classes have the form [Cond]<Category><Format>, where <Format> is one
1213// of the formats defined above and where <Category> describes the inputs
1214// and outputs.  "Cond" is used if the instruction is conditional,
1215// in which case the 4-bit condition-code mask is added as a final operand.
1216// <Category> can be one of:
1217//
1218//   Inherent:
1219//     One register output operand and no input operands.
1220//
1221//   BranchUnary:
1222//     One register output operand, one register input operand and
1223//     one branch displacement.  The instructions stores a modified
1224//     form of the source register in the destination register and
1225//     branches on the result.
1226//
1227//   BranchBinary:
1228//     One register output operand, two register input operands and one branch
1229//     displacement. The instructions stores a modified form of one of the
1230//     source registers in the destination register and branches on the result.
1231//
1232//   LoadMultiple:
1233//     One address input operand and two explicit output operands.
1234//     The instruction loads a range of registers from the address,
1235//     with the explicit operands giving the first and last register
1236//     to load.  Other loaded registers are added as implicit definitions.
1237//
1238//   StoreMultiple:
1239//     Two explicit input register operands and an address operand.
1240//     The instruction stores a range of registers to the address,
1241//     with the explicit operands giving the first and last register
1242//     to store.  Other stored registers are added as implicit uses.
1243//
1244//   StoreLength:
1245//     One value operand, one length operand and one address operand.
1246//     The instruction stores the value operand to the address but
1247//     doesn't write more than the number of bytes specified by the
1248//     length operand.
1249//
1250//   Unary:
1251//     One register output operand and one input operand.
1252//
1253//   Store:
1254//     One address operand and one other input operand.  The instruction
1255//     stores to the address.
1256//
1257//   Binary:
1258//     One register output operand and two input operands.
1259//
1260//   StoreBinary:
1261//     One address operand and two other input operands.  The instruction
1262//     stores to the address.
1263//
1264//   Compare:
1265//     Two input operands and an implicit CC output operand.
1266//
1267//   Test:
1268//     Two input operands and an implicit CC output operand.  The second
1269//     input operand is an "address" operand used as a test class mask.
1270//
1271//   Ternary:
1272//     One register output operand and three input operands.
1273//
1274//   Quaternary:
1275//     One register output operand and four input operands.
1276//
1277//   LoadAndOp:
1278//     One output operand and two input operands, one of which is an address.
1279//     The instruction both reads from and writes to the address.
1280//
1281//   CmpSwap:
1282//     One output operand and three input operands, one of which is an address.
1283//     The instruction both reads from and writes to the address.
1284//
1285//   RotateSelect:
1286//     One output operand and five input operands.  The first two operands
1287//     are registers and the other three are immediates.
1288//
1289//   Prefetch:
1290//     One 4-bit immediate operand and one address operand.  The immediate
1291//     operand is 1 for a load prefetch and 2 for a store prefetch.
1292//
1293// The format determines which input operands are tied to output operands,
1294// and also determines the shape of any address operand.
1295//
1296// Multiclasses of the form <Category><Format>Pair define two instructions,
1297// one with <Category><Format> and one with <Category><Format>Y.  The name
1298// of the first instruction has no suffix, the name of the second has
1299// an extra "y".
1300//
1301//===----------------------------------------------------------------------===//
1302
1303class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1304                  dag src>
1305  : InstRRE<opcode, (outs cls:$R1), (ins),
1306            mnemonic#"\t$R1",
1307            [(set cls:$R1, src)]> {
1308  let R2 = 0;
1309}
1310
1311class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1312  : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1313  let I2 = value;
1314  let M3 = 0;
1315}
1316
1317class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
1318  : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
1319           mnemonic##"\t$R1, $I2", []> {
1320  let isBranch = 1;
1321  let isTerminator = 1;
1322  let Constraints = "$R1 = $R1src";
1323  let DisableEncoding = "$R1src";
1324}
1325
1326class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
1327  : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
1328            mnemonic##"\t$R1, $R3, $RI2", []> {
1329  let isBranch = 1;
1330  let isTerminator = 1;
1331  let Constraints = "$R1 = $R1src";
1332  let DisableEncoding = "$R1src";
1333}
1334
1335class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1336                     AddressingMode mode = bdaddr12only>
1337  : InstRS<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1338           mnemonic#"\t$R1, $R3, $BD2", []> {
1339  let mayLoad = 1;
1340}
1341
1342class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1343                      AddressingMode mode = bdaddr20only>
1344  : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1345            mnemonic#"\t$R1, $R3, $BD2", []> {
1346  let mayLoad = 1;
1347}
1348
1349multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1350                              bits<16> rsyOpcode, RegisterOperand cls> {
1351  let DispKey = mnemonic ## #cls in {
1352    let DispSize = "12" in
1353      def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1354    let DispSize = "20" in
1355      def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1356  }
1357}
1358
1359class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
1360  : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
1361             mnemonic#"\t$V1, $V3, $BD2", []> {
1362  let M4 = 0;
1363  let mayLoad = 1;
1364}
1365
1366class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1367                 RegisterOperand cls>
1368  : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1369            mnemonic#"\t$R1, $I2",
1370            [(operator cls:$R1, pcrel32:$I2)]> {
1371  let mayStore = 1;
1372  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1373  // However, BDXs have two extra operands and are therefore 6 units more
1374  // complex.
1375  let AddedComplexity = 7;
1376}
1377
1378class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1379              RegisterOperand cls, bits<5> bytes,
1380              AddressingMode mode = bdxaddr12only>
1381  : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1382           mnemonic#"\t$R1, $XBD2",
1383           [(operator cls:$R1, mode:$XBD2)]> {
1384  let OpKey = mnemonic ## cls;
1385  let OpType = "mem";
1386  let mayStore = 1;
1387  let AccessBytes = bytes;
1388}
1389
1390class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1391               RegisterOperand cls, bits<5> bytes,
1392               AddressingMode mode = bdxaddr20only>
1393  : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1394            mnemonic#"\t$R1, $XBD2",
1395            [(operator cls:$R1, mode:$XBD2)]> {
1396  let OpKey = mnemonic ## cls;
1397  let OpType = "mem";
1398  let mayStore = 1;
1399  let AccessBytes = bytes;
1400}
1401
1402multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1403                       SDPatternOperator operator, RegisterOperand cls,
1404                       bits<5> bytes> {
1405  let DispKey = mnemonic ## #cls in {
1406    let DispSize = "12" in
1407      def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1408    let DispSize = "20" in
1409      def Y  : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1410                        bdxaddr20pair>;
1411  }
1412}
1413
1414class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1415               TypedReg tr, bits<5> bytes, bits<4> type = 0>
1416  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
1417            mnemonic#"\t$V1, $XBD2",
1418            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1419  let M3 = type;
1420  let mayStore = 1;
1421  let AccessBytes = bytes;
1422}
1423
1424class StoreLengthVRSb<string mnemonic, bits<16> opcode,
1425                      SDPatternOperator operator, bits<5> bytes>
1426  : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1427             mnemonic#"\t$V1, $R3, $BD2",
1428             [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
1429  let M4 = 0;
1430  let mayStore = 1;
1431  let AccessBytes = bytes;
1432}
1433
1434class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1435                      AddressingMode mode = bdaddr12only>
1436  : InstRS<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1437           mnemonic#"\t$R1, $R3, $BD2", []> {
1438  let mayStore = 1;
1439}
1440
1441class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1442                       AddressingMode mode = bdaddr20only>
1443  : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1444            mnemonic#"\t$R1, $R3, $BD2", []> {
1445  let mayStore = 1;
1446}
1447
1448multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1449                               bits<16> rsyOpcode, RegisterOperand cls> {
1450  let DispKey = mnemonic ## #cls in {
1451    let DispSize = "12" in
1452      def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1453    let DispSize = "20" in
1454      def Y  : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1455  }
1456}
1457
1458class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
1459  : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
1460             mnemonic#"\t$V1, $V3, $BD2", []> {
1461  let M4 = 0;
1462  let mayStore = 1;
1463}
1464
1465// StoreSI* instructions are used to store an integer to memory, but the
1466// addresses are more restricted than for normal stores.  If we are in the
1467// situation of having to force either the address into a register or the
1468// constant into a register, it's usually better to do the latter.
1469// We therefore match the address in the same way as a normal store and
1470// only use the StoreSI* instruction if the matched address is suitable.
1471class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1472              Immediate imm>
1473  : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1474           mnemonic#"\t$BD1, $I2",
1475           [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1476  let mayStore = 1;
1477}
1478
1479class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1480               Immediate imm>
1481  : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
1482            mnemonic#"\t$BD1, $I2",
1483            [(operator imm:$I2, mviaddr20pair:$BD1)]> {
1484  let mayStore = 1;
1485}
1486
1487class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1488               Immediate imm>
1489  : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1490            mnemonic#"\t$BD1, $I2",
1491            [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1492  let mayStore = 1;
1493}
1494
1495multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1496                       SDPatternOperator operator, Immediate imm> {
1497  let DispKey = mnemonic in {
1498    let DispSize = "12" in
1499      def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
1500    let DispSize = "20" in
1501      def Y  : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
1502  }
1503}
1504
1505class CondStoreRSY<string mnemonic, bits<16> opcode,
1506                   RegisterOperand cls, bits<5> bytes,
1507                   AddressingMode mode = bdaddr20only>
1508  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3),
1509            mnemonic#"$R3\t$R1, $BD2", []>,
1510    Requires<[FeatureLoadStoreOnCond]> {
1511  let mayStore = 1;
1512  let AccessBytes = bytes;
1513  let CCMaskLast = 1;
1514}
1515
1516// Like CondStoreRSY, but used for the raw assembly form.  The condition-code
1517// mask is the third operand rather than being part of the mnemonic.
1518class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
1519                      RegisterOperand cls, bits<5> bytes,
1520                      AddressingMode mode = bdaddr20only>
1521  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3),
1522            mnemonic#"\t$R1, $BD2, $R3", []>,
1523    Requires<[FeatureLoadStoreOnCond]> {
1524  let mayStore = 1;
1525  let AccessBytes = bytes;
1526}
1527
1528// Like CondStoreRSY, but with a fixed CC mask.
1529class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
1530                        RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1531                        AddressingMode mode = bdaddr20only>
1532  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
1533            mnemonic#"\t$R1, $BD2", []>,
1534    Requires<[FeatureLoadStoreOnCond]> {
1535  let mayStore = 1;
1536  let AccessBytes = bytes;
1537  let R3 = ccmask;
1538}
1539
1540class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1541              RegisterOperand cls1, RegisterOperand cls2>
1542  : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
1543           mnemonic#"r\t$R1, $R2",
1544           [(set cls1:$R1, (operator cls2:$R2))]> {
1545  let OpKey = mnemonic ## cls1;
1546  let OpType = "reg";
1547}
1548
1549class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1550               RegisterOperand cls1, RegisterOperand cls2>
1551  : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
1552            mnemonic#"r\t$R1, $R2",
1553            [(set cls1:$R1, (operator cls2:$R2))]> {
1554  let OpKey = mnemonic ## cls1;
1555  let OpType = "reg";
1556}
1557
1558class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1559               RegisterOperand cls2>
1560  : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
1561            mnemonic#"r\t$R1, $R3, $R2", []> {
1562  let OpKey = mnemonic ## cls1;
1563  let OpType = "reg";
1564  let R4 = 0;
1565}
1566
1567class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1568                RegisterOperand cls2>
1569  : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
1570            mnemonic#"\t$R1, $R3, $R2, $R4", []>;
1571
1572// These instructions are generated by if conversion.  The old value of R1
1573// is added as an implicit use.
1574class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1575                   RegisterOperand cls2>
1576  : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
1577            mnemonic#"r$R3\t$R1, $R2", []>,
1578    Requires<[FeatureLoadStoreOnCond]> {
1579  let CCMaskLast = 1;
1580  let R4 = 0;
1581}
1582
1583class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1584                   Immediate imm>
1585  : InstRIEd<opcode, (outs cls:$R1),
1586                     (ins imm:$I2, cond4:$valid, cond4:$R3),
1587             mnemonic#"$R3\t$R1, $I2", []>,
1588    Requires<[FeatureLoadStoreOnCond2]> {
1589  let CCMaskLast = 1;
1590}
1591
1592// Like CondUnaryRRF, but used for the raw assembly form.  The condition-code
1593// mask is the third operand rather than being part of the mnemonic.
1594class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1595                      RegisterOperand cls2>
1596  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
1597            mnemonic#"r\t$R1, $R2, $R3", []>,
1598    Requires<[FeatureLoadStoreOnCond]> {
1599  let Constraints = "$R1 = $R1src";
1600  let DisableEncoding = "$R1src";
1601  let R4 = 0;
1602}
1603
1604class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1605                   Immediate imm>
1606  : InstRIEd<opcode, (outs cls:$R1),
1607                     (ins cls:$R1src, imm:$I2, imm32zx4:$R3),
1608             mnemonic#"\t$R1, $I2, $R3", []>,
1609    Requires<[FeatureLoadStoreOnCond2]> {
1610  let Constraints = "$R1 = $R1src";
1611  let DisableEncoding = "$R1src";
1612}
1613
1614// Like CondUnaryRRF, but with a fixed CC mask.
1615class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1616                        RegisterOperand cls2, bits<4> ccmask>
1617  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1618            mnemonic#"\t$R1, $R2", []>,
1619    Requires<[FeatureLoadStoreOnCond]> {
1620  let Constraints = "$R1 = $R1src";
1621  let DisableEncoding = "$R1src";
1622  let R3 = ccmask;
1623  let R4 = 0;
1624}
1625
1626class FixedCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1627                   Immediate imm, bits<4> ccmask>
1628  : InstRIEd<opcode, (outs cls:$R1),
1629                     (ins cls:$R1src, imm:$I2),
1630             mnemonic#"\t$R1, $I2", []>,
1631    Requires<[FeatureLoadStoreOnCond2]> {
1632  let Constraints = "$R1 = $R1src";
1633  let DisableEncoding = "$R1src";
1634  let R3 = ccmask;
1635}
1636
1637class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1638              RegisterOperand cls, Immediate imm>
1639  : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
1640           mnemonic#"\t$R1, $I2",
1641           [(set cls:$R1, (operator imm:$I2))]>;
1642
1643class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1644               RegisterOperand cls, Immediate imm>
1645  : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
1646            mnemonic#"\t$R1, $I2",
1647            [(set cls:$R1, (operator imm:$I2))]>;
1648
1649class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1650                 RegisterOperand cls>
1651  : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
1652            mnemonic#"\t$R1, $I2",
1653            [(set cls:$R1, (operator pcrel32:$I2))]> {
1654  let mayLoad = 1;
1655  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1656  // However, BDXs have two extra operands and are therefore 6 units more
1657  // complex.
1658  let AddedComplexity = 7;
1659}
1660
1661class CondUnaryRSY<string mnemonic, bits<16> opcode,
1662                   SDPatternOperator operator, RegisterOperand cls,
1663                   bits<5> bytes, AddressingMode mode = bdaddr20only>
1664  : InstRSY<opcode, (outs cls:$R1),
1665            (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
1666            mnemonic#"$R3\t$R1, $BD2",
1667            [(set cls:$R1,
1668                  (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src,
1669                                   cond4:$valid, cond4:$R3))]>,
1670    Requires<[FeatureLoadStoreOnCond]> {
1671  let Constraints = "$R1 = $R1src";
1672  let DisableEncoding = "$R1src";
1673  let mayLoad = 1;
1674  let AccessBytes = bytes;
1675  let CCMaskLast = 1;
1676}
1677
1678// Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
1679// mask is the third operand rather than being part of the mnemonic.
1680class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
1681                      RegisterOperand cls, bits<5> bytes,
1682                      AddressingMode mode = bdaddr20only>
1683  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3),
1684            mnemonic#"\t$R1, $BD2, $R3", []>,
1685    Requires<[FeatureLoadStoreOnCond]> {
1686  let mayLoad = 1;
1687  let AccessBytes = bytes;
1688  let Constraints = "$R1 = $R1src";
1689  let DisableEncoding = "$R1src";
1690}
1691
1692// Like CondUnaryRSY, but with a fixed CC mask.
1693class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
1694                        RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1695                        AddressingMode mode = bdaddr20only>
1696  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
1697            mnemonic#"\t$R1, $BD2", []>,
1698    Requires<[FeatureLoadStoreOnCond]> {
1699  let Constraints = "$R1 = $R1src";
1700  let DisableEncoding = "$R1src";
1701  let R3 = ccmask;
1702  let mayLoad = 1;
1703  let AccessBytes = bytes;
1704}
1705
1706class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1707              RegisterOperand cls, bits<5> bytes,
1708              AddressingMode mode = bdxaddr12only>
1709  : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
1710           mnemonic#"\t$R1, $XBD2",
1711           [(set cls:$R1, (operator mode:$XBD2))]> {
1712  let OpKey = mnemonic ## cls;
1713  let OpType = "mem";
1714  let mayLoad = 1;
1715  let AccessBytes = bytes;
1716}
1717
1718class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1719               RegisterOperand cls, bits<5> bytes>
1720  : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
1721            mnemonic#"\t$R1, $XBD2",
1722            [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
1723  let OpKey = mnemonic ## cls;
1724  let OpType = "mem";
1725  let mayLoad = 1;
1726  let AccessBytes = bytes;
1727  let M3 = 0;
1728}
1729
1730class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1731               RegisterOperand cls, bits<5> bytes,
1732               AddressingMode mode = bdxaddr20only>
1733  : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
1734            mnemonic#"\t$R1, $XBD2",
1735            [(set cls:$R1, (operator mode:$XBD2))]> {
1736  let OpKey = mnemonic ## cls;
1737  let OpType = "mem";
1738  let mayLoad = 1;
1739  let AccessBytes = bytes;
1740}
1741
1742multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1743                       SDPatternOperator operator, RegisterOperand cls,
1744                       bits<5> bytes> {
1745  let DispKey = mnemonic ## #cls in {
1746    let DispSize = "12" in
1747      def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1748    let DispSize = "20" in
1749      def Y  : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1750                        bdxaddr20pair>;
1751  }
1752}
1753
1754class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1755                TypedReg tr, Immediate imm, bits<4> type = 0>
1756  : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1757             mnemonic#"\t$V1, $I2",
1758             [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1759  let M3 = type;
1760}
1761
1762class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, Immediate imm>
1763  : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
1764             mnemonic#"\t$V1, $I2, $M3", []>;
1765
1766class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1767                TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
1768                bits<4> m5 = 0>
1769  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1770             mnemonic#"\t$V1, $V2",
1771             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1772  let M3 = type;
1773  let M4 = m4;
1774  let M5 = m5;
1775}
1776
1777class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
1778                       bits<4> m5 = 0>
1779  : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
1780             mnemonic#"\t$V1, $V2, $M3", []> {
1781  let M4 = m4;
1782  let M5 = m5;
1783}
1784
1785class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
1786  : InstVRRa<opcode, (outs VR128:$V1),
1787             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
1788             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
1789  let M5 = m5;
1790}
1791
1792// Declare a pair of instructions, one which sets CC and one which doesn't.
1793// The CC-setting form ends with "S" and sets the low bit of M5.
1794// The form that does not set CC has an extra operand to optionally allow
1795// specifying arbitrary M5 values in assembler.
1796multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
1797                               SDPatternOperator operator,
1798                               SDPatternOperator operator_cc,
1799                               TypedReg tr1, TypedReg tr2, bits<4> type> {
1800  let M3 = type, M4 = 0 in
1801    def "" : InstVRRa<opcode, (outs tr1.op:$V1),
1802                      (ins tr2.op:$V2, imm32zx4:$M5),
1803                      mnemonic#"\t$V1, $V2, $M5", []>;
1804  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
1805            (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
1806  def : InstAlias<mnemonic#"\t$V1, $V2",
1807                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
1808  let Defs = [CC] in
1809    def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
1810                      type, 0, 1>;
1811}
1812
1813multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
1814  let M4 = 0 in
1815    def "" : InstVRRa<opcode, (outs VR128:$V1),
1816                     (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
1817                     mnemonic#"\t$V1, $V2, $M3, $M5", []>;
1818  def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
1819                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
1820                                            imm32zx4:$M3, 0)>;
1821}
1822
1823class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1824               TypedReg tr, bits<5> bytes, bits<4> type = 0>
1825  : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
1826            mnemonic#"\t$V1, $XBD2",
1827            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1828  let M3 = type;
1829  let mayLoad = 1;
1830  let AccessBytes = bytes;
1831}
1832
1833class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
1834  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
1835            mnemonic#"\t$V1, $XBD2, $M3", []> {
1836  let mayLoad = 1;
1837}
1838
1839class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1840               RegisterOperand cls1, RegisterOperand cls2>
1841  : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1842           mnemonic#"r\t$R1, $R2",
1843           [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1844  let OpKey = mnemonic ## cls1;
1845  let OpType = "reg";
1846  let Constraints = "$R1 = $R1src";
1847  let DisableEncoding = "$R1src";
1848}
1849
1850class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1851                RegisterOperand cls1, RegisterOperand cls2>
1852  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1853            mnemonic#"r\t$R1, $R2",
1854            [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1855  let OpKey = mnemonic ## cls1;
1856  let OpType = "reg";
1857  let Constraints = "$R1 = $R1src";
1858  let DisableEncoding = "$R1src";
1859}
1860
1861class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1862                RegisterOperand cls1, RegisterOperand cls2>
1863  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1864            mnemonic#"r\t$R1, $R3, $R2",
1865            [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1866  let OpKey = mnemonic ## cls1;
1867  let OpType = "reg";
1868  let R4 = 0;
1869}
1870
1871class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1872                 RegisterOperand cls1, RegisterOperand cls2>
1873  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1874            mnemonic#"rk\t$R1, $R2, $R3",
1875            [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1876  let R4 = 0;
1877}
1878
1879multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1880                        SDPatternOperator operator, RegisterOperand cls1,
1881                        RegisterOperand cls2> {
1882  let NumOpsKey = mnemonic in {
1883    let NumOpsValue = "3" in
1884      def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1885              Requires<[FeatureDistinctOps]>;
1886    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1887      def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
1888  }
1889}
1890
1891multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
1892                         SDPatternOperator operator, RegisterOperand cls1,
1893                         RegisterOperand cls2> {
1894  let NumOpsKey = mnemonic in {
1895    let NumOpsValue = "3" in
1896      def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1897              Requires<[FeatureDistinctOps]>;
1898    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1899      def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
1900  }
1901}
1902
1903class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1904               RegisterOperand cls, Immediate imm>
1905  : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1906           mnemonic#"\t$R1, $I2",
1907           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1908  let Constraints = "$R1 = $R1src";
1909  let DisableEncoding = "$R1src";
1910}
1911
1912class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1913                RegisterOperand cls, Immediate imm>
1914  : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
1915             mnemonic#"\t$R1, $R3, $I2",
1916             [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
1917
1918multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
1919                        SDPatternOperator operator, RegisterOperand cls,
1920                        Immediate imm> {
1921  let NumOpsKey = mnemonic in {
1922    let NumOpsValue = "3" in
1923      def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
1924              Requires<[FeatureDistinctOps]>;
1925    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1926      def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
1927  }
1928}
1929
1930class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1931                RegisterOperand cls, Immediate imm>
1932  : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1933            mnemonic#"\t$R1, $I2",
1934            [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1935  let Constraints = "$R1 = $R1src";
1936  let DisableEncoding = "$R1src";
1937}
1938
1939class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1940               RegisterOperand cls>
1941  : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
1942           mnemonic#"\t$R1, $BD2",
1943           [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
1944  let R3 = 0;
1945  let Constraints = "$R1 = $R1src";
1946  let DisableEncoding = "$R1src";
1947}
1948
1949class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1950                RegisterOperand cls>
1951  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
1952            mnemonic#"\t$R1, $R3, $BD2",
1953            [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
1954
1955multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1956                        SDPatternOperator operator, RegisterOperand cls> {
1957  let NumOpsKey = mnemonic in {
1958    let NumOpsValue = "3" in
1959      def K  : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
1960               Requires<[FeatureDistinctOps]>;
1961    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1962      def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
1963  }
1964}
1965
1966class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1967               RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1968               AddressingMode mode = bdxaddr12only>
1969  : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1970           mnemonic#"\t$R1, $XBD2",
1971           [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1972  let OpKey = mnemonic ## cls;
1973  let OpType = "mem";
1974  let Constraints = "$R1 = $R1src";
1975  let DisableEncoding = "$R1src";
1976  let mayLoad = 1;
1977  let AccessBytes = bytes;
1978}
1979
1980class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1981                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1982  : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
1983            mnemonic#"\t$R1, $XBD2",
1984            [(set cls:$R1, (operator cls:$R1src,
1985                                     (load bdxaddr12only:$XBD2)))]> {
1986  let OpKey = mnemonic ## cls;
1987  let OpType = "mem";
1988  let Constraints = "$R1 = $R1src";
1989  let DisableEncoding = "$R1src";
1990  let mayLoad = 1;
1991  let AccessBytes = bytes;
1992  let M3 = 0;
1993}
1994
1995class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1996                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1997                AddressingMode mode = bdxaddr20only>
1998  : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1999            mnemonic#"\t$R1, $XBD2",
2000            [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
2001  let OpKey = mnemonic ## cls;
2002  let OpType = "mem";
2003  let Constraints = "$R1 = $R1src";
2004  let DisableEncoding = "$R1src";
2005  let mayLoad = 1;
2006  let AccessBytes = bytes;
2007}
2008
2009multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2010                        SDPatternOperator operator, RegisterOperand cls,
2011                        SDPatternOperator load, bits<5> bytes> {
2012  let DispKey = mnemonic ## #cls in {
2013    let DispSize = "12" in
2014      def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
2015                        bdxaddr12pair>;
2016    let DispSize = "20" in
2017      def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
2018                         bdxaddr20pair>;
2019  }
2020}
2021
2022class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2023               Operand imm, AddressingMode mode = bdaddr12only>
2024  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
2025           mnemonic#"\t$BD1, $I2",
2026           [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
2027  let mayLoad = 1;
2028  let mayStore = 1;
2029}
2030
2031class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2032                Operand imm, AddressingMode mode = bdaddr20only>
2033  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
2034            mnemonic#"\t$BD1, $I2",
2035            [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
2036  let mayLoad = 1;
2037  let mayStore = 1;
2038}
2039
2040multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
2041                        bits<16> siyOpcode, SDPatternOperator operator,
2042                        Operand imm> {
2043  let DispKey = mnemonic ## #cls in {
2044    let DispSize = "12" in
2045      def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
2046    let DispSize = "20" in
2047      def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
2048  }
2049}
2050
2051class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2052                 TypedReg tr, bits<4> type>
2053  : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
2054             mnemonic#"\t$V1, $I2, $I3",
2055             [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
2056  let M4 = type;
2057}
2058
2059class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
2060  : InstVRIb<opcode, (outs VR128:$V1),
2061             (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
2062             mnemonic#"\t$V1, $I2, $I3, $M4", []>;
2063
2064class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2065                 TypedReg tr1, TypedReg tr2, bits<4> type>
2066  : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
2067             mnemonic#"\t$V1, $V3, $I2",
2068             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2069                                                 imm32zx16:$I2)))]> {
2070  let M4 = type;
2071}
2072
2073class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
2074  : InstVRIc<opcode, (outs VR128:$V1),
2075             (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
2076             mnemonic#"\t$V1, $V3, $I2, $M4", []>;
2077
2078class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2079                 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
2080  : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
2081             mnemonic#"\t$V1, $V2, $I3",
2082             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2083                                                 imm32zx12:$I3)))]> {
2084  let M4 = type;
2085  let M5 = m5;
2086}
2087
2088class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
2089  : InstVRIe<opcode, (outs VR128:$V1),
2090             (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
2091             mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
2092
2093class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2094                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
2095  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
2096             mnemonic#"\t$V1, $V2, $M5",
2097             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2098                                                 imm32zx12:$M5)))]> {
2099  let M3 = type;
2100  let M4 = m4;
2101}
2102
2103class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
2104  : InstVRRa<opcode, (outs VR128:$V1),
2105             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
2106             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
2107
2108class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2109                 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
2110                 bits<4> modifier = 0>
2111  : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
2112             mnemonic#"\t$V1, $V2, $V3",
2113             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2114                                                 (tr2.vt tr2.op:$V3))))]> {
2115  let M4 = type;
2116  let M5 = modifier;
2117}
2118
2119// Declare a pair of instructions, one which sets CC and one which doesn't.
2120// The CC-setting form ends with "S" and sets the low bit of M5.
2121multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
2122                           SDPatternOperator operator,
2123                           SDPatternOperator operator_cc, TypedReg tr1,
2124                           TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
2125  def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2126                      !and (modifier, 14)>;
2127  let Defs = [CC] in
2128    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2129                       !add (!and (modifier, 14), 1)>;
2130}
2131
2132class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
2133  : InstVRRb<opcode, (outs VR128:$V1),
2134             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2135             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
2136
2137// Declare a pair of instructions, one which sets CC and one which doesn't.
2138// The CC-setting form ends with "S" and sets the low bit of M5.
2139// The form that does not set CC has an extra operand to optionally allow
2140// specifying arbitrary M5 values in assembler.
2141multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
2142                                SDPatternOperator operator,
2143                                SDPatternOperator operator_cc,
2144                                TypedReg tr1, TypedReg tr2, bits<4> type> {
2145  let M4 = type in
2146    def "" : InstVRRb<opcode, (outs tr1.op:$V1),
2147                      (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
2148                      mnemonic#"\t$V1, $V2, $V3, $M5", []>;
2149  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
2150            (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
2151  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2152                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2153                                            tr2.op:$V3, 0)>;
2154  let Defs = [CC] in
2155    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
2156}
2157
2158multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
2159  def "" : InstVRRb<opcode, (outs VR128:$V1),
2160                   (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2161                   mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
2162  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
2163                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
2164                                            imm32zx4:$M4, 0)>;
2165}
2166
2167class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2168                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
2169                 bits<4> m6 = 0>
2170  : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
2171             mnemonic#"\t$V1, $V2, $V3",
2172             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2173                                                 (tr2.vt tr2.op:$V3))))]> {
2174  let M4 = type;
2175  let M5 = m5;
2176  let M6 = m6;
2177}
2178
2179class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
2180                        bits<4> m6 = 0>
2181  : InstVRRc<opcode, (outs VR128:$V1),
2182             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
2183             mnemonic#"\t$V1, $V2, $V3, $M4", []> {
2184  let M5 = m5;
2185  let M6 = m6;
2186}
2187
2188class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
2189  : InstVRRc<opcode, (outs VR128:$V1),
2190             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2191             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
2192  let M6 = m6;
2193}
2194
2195// Declare a pair of instructions, one which sets CC and one which doesn't.
2196// The CC-setting form ends with "S" and sets the low bit of M5.
2197multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
2198                           SDPatternOperator operator,
2199                           SDPatternOperator operator_cc, TypedReg tr1,
2200                           TypedReg tr2, bits<4> type, bits<4> m5,
2201                           bits<4> modifier = 0> {
2202  def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
2203                      m5, !and (modifier, 14)>;
2204  let Defs = [CC] in
2205    def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2206                       m5, !add (!and (modifier, 14), 1)>;
2207}
2208
2209class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
2210  : InstVRRc<opcode, (outs VR128:$V1),
2211             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
2212                  imm32zx4:$M6),
2213             mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
2214
2215class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2216                 TypedReg tr>
2217  : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
2218             mnemonic#"\t$V1, $R2, $R3",
2219             [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
2220
2221class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2222                 TypedReg tr1, TypedReg tr2, bits<4> type>
2223  : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
2224             mnemonic#"\t$V1, $V3, $BD2",
2225             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2226                                                 shift12only:$BD2)))]> {
2227  let M4 = type;
2228}
2229
2230class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
2231  : InstVRSa<opcode, (outs VR128:$V1),
2232             (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
2233             mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2234
2235class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2236                 bits<5> bytes>
2237  : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
2238             mnemonic#"\t$V1, $R3, $BD2",
2239             [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
2240  let M4 = 0;
2241  let mayLoad = 1;
2242  let AccessBytes = bytes;
2243}
2244
2245class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2246                 TypedReg tr, bits<4> type>
2247  : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
2248           mnemonic#"\t$R1, $V3, $BD2",
2249           [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
2250  let M4 = type;
2251}
2252
2253class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
2254  : InstVRSc<opcode, (outs GR64:$R1),
2255             (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
2256             mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
2257
2258class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2259                TypedReg tr, bits<5> bytes>
2260  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
2261            mnemonic#"\t$V1, $XBD2, $M3",
2262            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
2263                                              imm32zx4:$M3)))]> {
2264  let mayLoad = 1;
2265  let AccessBytes = bytes;
2266}
2267
2268class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2269                     Immediate index>
2270  : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
2271            mnemonic#"\t$V1, $VBD2, $M3", []> {
2272  let mayStore = 1;
2273  let AccessBytes = bytes;
2274}
2275
2276class StoreBinaryVRX<string mnemonic, bits<16> opcode,
2277                     SDPatternOperator operator, TypedReg tr, bits<5> bytes,
2278                     Immediate index>
2279  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
2280            mnemonic#"\t$V1, $XBD2, $M3",
2281            [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
2282  let mayStore = 1;
2283  let AccessBytes = bytes;
2284}
2285
2286class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2287                RegisterOperand cls1, RegisterOperand cls2>
2288  : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2289           mnemonic#"r\t$R1, $R2",
2290           [(operator cls1:$R1, cls2:$R2)]> {
2291  let OpKey = mnemonic ## cls1;
2292  let OpType = "reg";
2293  let isCompare = 1;
2294}
2295
2296class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2297                 RegisterOperand cls1, RegisterOperand cls2>
2298  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2299            mnemonic#"r\t$R1, $R2",
2300            [(operator cls1:$R1, cls2:$R2)]> {
2301  let OpKey = mnemonic ## cls1;
2302  let OpType = "reg";
2303  let isCompare = 1;
2304}
2305
2306class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2307                RegisterOperand cls, Immediate imm>
2308  : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
2309           mnemonic#"\t$R1, $I2",
2310           [(operator cls:$R1, imm:$I2)]> {
2311  let isCompare = 1;
2312}
2313
2314class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2315                 RegisterOperand cls, Immediate imm>
2316  : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
2317            mnemonic#"\t$R1, $I2",
2318            [(operator cls:$R1, imm:$I2)]> {
2319  let isCompare = 1;
2320}
2321
2322class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2323                   RegisterOperand cls, SDPatternOperator load>
2324  : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
2325            mnemonic#"\t$R1, $I2",
2326            [(operator cls:$R1, (load pcrel32:$I2))]> {
2327  let isCompare = 1;
2328  let mayLoad = 1;
2329  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2330  // However, BDXs have two extra operands and are therefore 6 units more
2331  // complex.
2332  let AddedComplexity = 7;
2333}
2334
2335class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2336                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2337                AddressingMode mode = bdxaddr12only>
2338  : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2339           mnemonic#"\t$R1, $XBD2",
2340           [(operator cls:$R1, (load mode:$XBD2))]> {
2341  let OpKey = mnemonic ## cls;
2342  let OpType = "mem";
2343  let isCompare = 1;
2344  let mayLoad = 1;
2345  let AccessBytes = bytes;
2346}
2347
2348class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2349                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2350  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2351            mnemonic#"\t$R1, $XBD2",
2352            [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
2353  let OpKey = mnemonic ## cls;
2354  let OpType = "mem";
2355  let isCompare = 1;
2356  let mayLoad = 1;
2357  let AccessBytes = bytes;
2358  let M3 = 0;
2359}
2360
2361class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2362                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2363                 AddressingMode mode = bdxaddr20only>
2364  : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2365            mnemonic#"\t$R1, $XBD2",
2366            [(operator cls:$R1, (load mode:$XBD2))]> {
2367  let OpKey = mnemonic ## cls;
2368  let OpType = "mem";
2369  let isCompare = 1;
2370  let mayLoad = 1;
2371  let AccessBytes = bytes;
2372}
2373
2374multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2375                         SDPatternOperator operator, RegisterOperand cls,
2376                         SDPatternOperator load, bits<5> bytes> {
2377  let DispKey = mnemonic ## #cls in {
2378    let DispSize = "12" in
2379      def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
2380                         load, bytes, bdxaddr12pair>;
2381    let DispSize = "20" in
2382      def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
2383                          load, bytes, bdxaddr20pair>;
2384  }
2385}
2386
2387class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2388                SDPatternOperator load, Immediate imm,
2389                AddressingMode mode = bdaddr12only>
2390  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
2391           mnemonic#"\t$BD1, $I2",
2392           [(operator (load mode:$BD1), imm:$I2)]> {
2393  let isCompare = 1;
2394  let mayLoad = 1;
2395}
2396
2397class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2398                 SDPatternOperator load, Immediate imm>
2399  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2400            mnemonic#"\t$BD1, $I2",
2401            [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
2402  let isCompare = 1;
2403  let mayLoad = 1;
2404}
2405
2406class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2407                 SDPatternOperator load, Immediate imm,
2408                 AddressingMode mode = bdaddr20only>
2409  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
2410            mnemonic#"\t$BD1, $I2",
2411            [(operator (load mode:$BD1), imm:$I2)]> {
2412  let isCompare = 1;
2413  let mayLoad = 1;
2414}
2415
2416multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2417                         SDPatternOperator operator, SDPatternOperator load,
2418                         Immediate imm> {
2419  let DispKey = mnemonic in {
2420    let DispSize = "12" in
2421      def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
2422    let DispSize = "20" in
2423      def Y  : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
2424                          bdaddr20pair>;
2425  }
2426}
2427
2428class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2429                  TypedReg tr, bits<4> type>
2430  : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
2431             mnemonic#"\t$V1, $V2",
2432             [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
2433  let isCompare = 1;
2434  let M3 = type;
2435  let M4 = 0;
2436  let M5 = 0;
2437}
2438
2439class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
2440  : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
2441             mnemonic#"\t$V1, $V2, $M3", []> {
2442  let isCompare = 1;
2443  let M4 = 0;
2444  let M5 = 0;
2445}
2446
2447class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
2448  : InstVRRa<opcode, (outs),
2449             (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
2450             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
2451  let isCompare = 1;
2452  let M5 = 0;
2453}
2454
2455class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2456              RegisterOperand cls>
2457  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2458            mnemonic#"\t$R1, $XBD2",
2459            [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
2460  let M3 = 0;
2461}
2462
2463class TernaryRRD<string mnemonic, bits<16> opcode,
2464                 SDPatternOperator operator, RegisterOperand cls>
2465  : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
2466            mnemonic#"r\t$R1, $R3, $R2",
2467            [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
2468  let OpKey = mnemonic ## cls;
2469  let OpType = "reg";
2470  let Constraints = "$R1 = $R1src";
2471  let DisableEncoding = "$R1src";
2472}
2473
2474class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2475                bits<5> bytes, AddressingMode mode = bdaddr12only>
2476  : InstRS<opcode, (outs cls:$R1),
2477          (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2478           mnemonic#"\t$R1, $R3, $BD2", []> {
2479
2480  let Constraints = "$R1 = $R1src";
2481  let DisableEncoding = "$R1src";
2482  let mayLoad = 1;
2483  let AccessBytes = bytes;
2484}
2485
2486class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2487                bits<5> bytes, AddressingMode mode = bdaddr20only>
2488  : InstRSY<opcode, (outs cls:$R1),
2489           (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2490            mnemonic#"\t$R1, $R3, $BD2", []> {
2491
2492  let Constraints = "$R1 = $R1src";
2493  let DisableEncoding = "$R1src";
2494  let mayLoad = 1;
2495  let AccessBytes = bytes;
2496}
2497
2498multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2499                         RegisterOperand cls, bits<5> bytes> {
2500  let DispKey = mnemonic ## #cls in {
2501    let DispSize = "12" in
2502      def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
2503    let DispSize = "20" in
2504      def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
2505  }
2506}
2507
2508class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2509                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2510  : InstRXF<opcode, (outs cls:$R1),
2511            (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
2512            mnemonic#"\t$R1, $R3, $XBD2",
2513            [(set cls:$R1, (operator cls:$R1src, cls:$R3,
2514                                     (load bdxaddr12only:$XBD2)))]> {
2515  let OpKey = mnemonic ## cls;
2516  let OpType = "mem";
2517  let Constraints = "$R1 = $R1src";
2518  let DisableEncoding = "$R1src";
2519  let mayLoad = 1;
2520  let AccessBytes = bytes;
2521}
2522
2523class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2524                  TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
2525  : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
2526             mnemonic#"\t$V1, $I2, $M3",
2527             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2528                                                 imm:$I2, index:$M3)))]> {
2529  let Constraints = "$V1 = $V1src";
2530  let DisableEncoding = "$V1src";
2531}
2532
2533class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2534                  TypedReg tr1, TypedReg tr2, bits<4> type>
2535  : InstVRId<opcode, (outs tr1.op:$V1),
2536             (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2537             mnemonic#"\t$V1, $V2, $V3, $I4",
2538             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2539                                                 (tr2.vt tr2.op:$V3),
2540                                                 imm32zx8:$I4)))]> {
2541  let M5 = type;
2542}
2543
2544class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2545                  TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
2546  : InstVRRa<opcode, (outs tr1.op:$V1),
2547             (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
2548             mnemonic#"\t$V1, $V2, $M4, $M5",
2549             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2550                                                 imm32zx4:$M4,
2551                                                 imm32zx4:$M5)))],
2552             m4or> {
2553  let M3 = type;
2554}
2555
2556class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
2557  : InstVRRa<opcode, (outs VR128:$V1),
2558             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
2559             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
2560
2561class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2562                  TypedReg tr1, TypedReg tr2, bits<4> type,
2563                  SDPatternOperator m5mask, bits<4> m5or>
2564  : InstVRRb<opcode, (outs tr1.op:$V1),
2565             (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
2566             mnemonic#"\t$V1, $V2, $V3, $M5",
2567             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2568                                                 (tr2.vt tr2.op:$V3),
2569                                                 m5mask:$M5)))],
2570             m5or> {
2571  let M4 = type;
2572}
2573
2574// Declare a pair of instructions, one which sets CC and one which doesn't.
2575// The CC-setting form ends with "S" and sets the low bit of M5.
2576// Also create aliases to make use of M5 operand optional in assembler.
2577multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
2578                               SDPatternOperator operator,
2579                               SDPatternOperator operator_cc,
2580                               TypedReg tr1, TypedReg tr2, bits<4> type,
2581                               bits<4> modifier = 0> {
2582  def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2583                       imm32zx4even, !and (modifier, 14)>;
2584  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2585                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2586                                            tr2.op:$V3, 0)>;
2587  let Defs = [CC] in
2588    def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2589                        imm32zx4even, !add(!and (modifier, 14), 1)>;
2590  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
2591                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2592                                                tr2.op:$V3, 0)>;
2593}
2594
2595multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
2596  def "" : InstVRRb<opcode, (outs VR128:$V1),
2597                   (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2598                   mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
2599  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
2600                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
2601                                            imm32zx4:$M4, 0)>;
2602}
2603
2604class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2605                  TypedReg tr1, TypedReg tr2>
2606  : InstVRRc<opcode, (outs tr1.op:$V1),
2607             (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
2608             mnemonic#"\t$V1, $V2, $V3, $M4",
2609             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2610                                                 (tr2.vt tr2.op:$V3),
2611                                                 imm32zx4:$M4)))]> {
2612  let M5 = 0;
2613  let M6 = 0;
2614}
2615
2616class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2617                  TypedReg tr1, TypedReg tr2, bits<4> type = 0>
2618  : InstVRRd<opcode, (outs tr1.op:$V1),
2619             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2620             mnemonic#"\t$V1, $V2, $V3, $V4",
2621             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2622                                                 (tr2.vt tr2.op:$V3),
2623                                                 (tr1.vt tr1.op:$V4))))]> {
2624  let M5 = type;
2625  let M6 = 0;
2626}
2627
2628class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
2629  : InstVRRd<opcode, (outs VR128:$V1),
2630             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
2631             mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
2632  let M6 = 0;
2633}
2634
2635class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2636                  TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
2637  : InstVRRe<opcode, (outs tr1.op:$V1),
2638             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2639             mnemonic#"\t$V1, $V2, $V3, $V4",
2640             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2641                                                 (tr2.vt tr2.op:$V3),
2642                                                 (tr1.vt tr1.op:$V4))))]> {
2643  let M5 = m5;
2644  let M6 = type;
2645}
2646
2647class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
2648  : InstVRRe<opcode, (outs VR128:$V1),
2649             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
2650             mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
2651
2652class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2653                  TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
2654  : InstVRSb<opcode, (outs tr1.op:$V1),
2655             (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
2656             mnemonic#"\t$V1, $R3, $BD2",
2657             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2658                                                 cls:$R3,
2659                                                 shift12only:$BD2)))]> {
2660  let Constraints = "$V1 = $V1src";
2661  let DisableEncoding = "$V1src";
2662  let M4 = type;
2663}
2664
2665class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
2666  : InstVRSb<opcode, (outs VR128:$V1),
2667             (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
2668             mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
2669  let Constraints = "$V1 = $V1src";
2670  let DisableEncoding = "$V1src";
2671}
2672
2673class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2674                 Immediate index>
2675  : InstVRV<opcode, (outs VR128:$V1),
2676           (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
2677           mnemonic#"\t$V1, $VBD2, $M3", []> {
2678  let Constraints = "$V1 = $V1src";
2679  let DisableEncoding = "$V1src";
2680  let mayLoad = 1;
2681  let AccessBytes = bytes;
2682}
2683
2684class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2685                 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
2686  : InstVRX<opcode, (outs tr1.op:$V1),
2687           (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
2688           mnemonic#"\t$V1, $XBD2, $M3",
2689           [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2690                                               bdxaddr12only:$XBD2,
2691                                               index:$M3)))]> {
2692  let Constraints = "$V1 = $V1src";
2693  let DisableEncoding = "$V1src";
2694  let mayLoad = 1;
2695  let AccessBytes = bytes;
2696}
2697
2698class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2699                     TypedReg tr1, TypedReg tr2, bits<4> type>
2700  : InstVRId<opcode, (outs tr1.op:$V1),
2701             (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2702             mnemonic#"\t$V1, $V2, $V3, $I4",
2703             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2704                                                 (tr2.vt tr2.op:$V2),
2705                                                 (tr2.vt tr2.op:$V3),
2706                                                 imm32zx8:$I4)))]> {
2707  let Constraints = "$V1 = $V1src";
2708  let DisableEncoding = "$V1src";
2709  let M5 = type;
2710}
2711
2712class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
2713  : InstVRId<opcode, (outs VR128:$V1),
2714             (ins VR128:$V1src, VR128:$V2, VR128:$V3,
2715                  imm32zx8:$I4, imm32zx4:$M5),
2716             mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
2717  let Constraints = "$V1 = $V1src";
2718  let DisableEncoding = "$V1src";
2719}
2720
2721class QuaternaryVRRd<string mnemonic, bits<16> opcode,
2722                     SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
2723                     bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
2724  : InstVRRd<opcode, (outs tr1.op:$V1),
2725             (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
2726             mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
2727             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2728                                                 (tr2.vt tr2.op:$V3),
2729                                                 (tr2.vt tr2.op:$V4),
2730                                                 m6mask:$M6)))],
2731             m6or> {
2732  let M5 = type;
2733}
2734
2735// Declare a pair of instructions, one which sets CC and one which doesn't.
2736// The CC-setting form ends with "S" and sets the low bit of M6.
2737// Also create aliases to make use of M6 operand optional in assembler.
2738multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
2739                                  SDPatternOperator operator,
2740                                SDPatternOperator operator_cc,
2741                                TypedReg tr1, TypedReg tr2, bits<4> type,
2742                                bits<4> modifier = 0> {
2743  def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
2744                          imm32zx4even, !and (modifier, 14)>;
2745  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
2746                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2747                                            tr2.op:$V3, tr2.op:$V4, 0)>;
2748  let Defs = [CC] in
2749    def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2750                           imm32zx4even, !add (!and (modifier, 14), 1)>;
2751  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
2752                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2753                                                tr2.op:$V3, tr2.op:$V4, 0)>;
2754}
2755
2756multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
2757  def "" : InstVRRd<opcode, (outs VR128:$V1),
2758                   (ins VR128:$V2, VR128:$V3, VR128:$V4,
2759                        imm32zx4:$M5, imm32zx4:$M6),
2760                   mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
2761  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
2762                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
2763                                            VR128:$V4, imm32zx4:$M5, 0)>;
2764}
2765
2766class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2767                  RegisterOperand cls, AddressingMode mode = bdaddr20only>
2768  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
2769            mnemonic#"\t$R1, $R3, $BD2",
2770            [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
2771  let mayLoad = 1;
2772  let mayStore = 1;
2773}
2774
2775class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2776                RegisterOperand cls, AddressingMode mode = bdaddr12only>
2777  : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2778           mnemonic#"\t$R1, $R3, $BD2",
2779           [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2780  let Constraints = "$R1 = $R1src";
2781  let DisableEncoding = "$R1src";
2782  let mayLoad = 1;
2783  let mayStore = 1;
2784}
2785
2786class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2787                 RegisterOperand cls, AddressingMode mode = bdaddr20only>
2788  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2789            mnemonic#"\t$R1, $R3, $BD2",
2790            [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2791  let Constraints = "$R1 = $R1src";
2792  let DisableEncoding = "$R1src";
2793  let mayLoad = 1;
2794  let mayStore = 1;
2795}
2796
2797multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2798                         SDPatternOperator operator, RegisterOperand cls> {
2799  let DispKey = mnemonic ## #cls in {
2800    let DispSize = "12" in
2801      def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
2802    let DispSize = "20" in
2803      def Y  : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
2804  }
2805}
2806
2807class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2808                       RegisterOperand cls2>
2809  : InstRIEf<opcode, (outs cls1:$R1),
2810             (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2811                  imm32zx6:$I5),
2812             mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
2813  let Constraints = "$R1 = $R1src";
2814  let DisableEncoding = "$R1src";
2815}
2816
2817class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
2818  : InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2),
2819            mnemonic##"\t$R1, $XBD2",
2820            [(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>;
2821
2822class PrefetchRILPC<string mnemonic, bits<12> opcode,
2823                    SDPatternOperator operator>
2824  : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2),
2825            mnemonic##"\t$R1, $I2",
2826            [(operator imm32zx4:$R1, pcrel32:$I2)]> {
2827  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2828  // However, BDXs have two extra operands and are therefore 6 units more
2829  // complex.
2830  let AddedComplexity = 7;
2831}
2832
2833// A floating-point load-and test operation.  Create both a normal unary
2834// operation and one that acts as a comparison against zero.
2835// Note that the comparison against zero operation is not available if we
2836// have vector support, since load-and-test instructions will partially
2837// clobber the target (vector) register.
2838multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
2839                          RegisterOperand cls> {
2840  def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
2841  let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
2842    def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
2843}
2844
2845//===----------------------------------------------------------------------===//
2846// Pseudo instructions
2847//===----------------------------------------------------------------------===//
2848//
2849// Convenience instructions that get lowered to real instructions
2850// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
2851// or SystemZInstrInfo::expandPostRAPseudo().
2852//
2853//===----------------------------------------------------------------------===//
2854
2855class Pseudo<dag outs, dag ins, list<dag> pattern>
2856  : InstSystemZ<0, outs, ins, "", pattern> {
2857  let isPseudo = 1;
2858  let isCodeGenOnly = 1;
2859}
2860
2861// Like UnaryRI, but expanded after RA depending on the choice of register.
2862class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2863                    Immediate imm>
2864  : Pseudo<(outs cls:$R1), (ins imm:$I2),
2865           [(set cls:$R1, (operator imm:$I2))]>;
2866
2867// Like UnaryRXY, but expanded after RA depending on the choice of register.
2868class UnaryRXYPseudo<string key, SDPatternOperator operator,
2869                     RegisterOperand cls, bits<5> bytes,
2870                     AddressingMode mode = bdxaddr20only>
2871  : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
2872           [(set cls:$R1, (operator mode:$XBD2))]> {
2873  let OpKey = key ## cls;
2874  let OpType = "mem";
2875  let mayLoad = 1;
2876  let Has20BitOffset = 1;
2877  let HasIndex = 1;
2878  let AccessBytes = bytes;
2879}
2880
2881// Like UnaryRR, but expanded after RA depending on the choice of registers.
2882class UnaryRRPseudo<string key, SDPatternOperator operator,
2883                    RegisterOperand cls1, RegisterOperand cls2>
2884  : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
2885           [(set cls1:$R1, (operator cls2:$R2))]> {
2886  let OpKey = key ## cls1;
2887  let OpType = "reg";
2888}
2889
2890// Like BinaryRI, but expanded after RA depending on the choice of register.
2891class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2892                     Immediate imm>
2893  : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
2894           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2895  let Constraints = "$R1 = $R1src";
2896}
2897
2898// Like BinaryRIE, but expanded after RA depending on the choice of register.
2899class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
2900                      Immediate imm>
2901  : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
2902           [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2903
2904// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
2905multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
2906                              RegisterOperand cls, Immediate imm> {
2907  let NumOpsKey = key in {
2908    let NumOpsValue = "3" in
2909      def K : BinaryRIEPseudo<null_frag, cls, imm>,
2910              Requires<[FeatureHighWord, FeatureDistinctOps]>;
2911    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2912      def "" : BinaryRIPseudo<operator, cls, imm>,
2913               Requires<[FeatureHighWord]>;
2914  }
2915}
2916
2917// Like CompareRI, but expanded after RA depending on the choice of register.
2918class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2919                      Immediate imm>
2920  : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
2921
2922// Like CompareRXY, but expanded after RA depending on the choice of register.
2923class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2924                       SDPatternOperator load, bits<5> bytes,
2925                       AddressingMode mode = bdxaddr20only>
2926  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2927           [(operator cls:$R1, (load mode:$XBD2))]> {
2928  let mayLoad = 1;
2929  let Has20BitOffset = 1;
2930  let HasIndex = 1;
2931  let AccessBytes = bytes;
2932}
2933
2934// Like StoreRXY, but expanded after RA depending on the choice of register.
2935class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2936                     bits<5> bytes, AddressingMode mode = bdxaddr20only>
2937  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2938           [(operator cls:$R1, mode:$XBD2)]> {
2939  let mayStore = 1;
2940  let Has20BitOffset = 1;
2941  let HasIndex = 1;
2942  let AccessBytes = bytes;
2943}
2944
2945// Like RotateSelectRIEf, but expanded after RA depending on the choice
2946// of registers.
2947class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
2948  : Pseudo<(outs cls1:$R1),
2949           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2950                imm32zx6:$I5),
2951           []> {
2952  let Constraints = "$R1 = $R1src";
2953  let DisableEncoding = "$R1src";
2954}
2955
2956// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
2957// the value of the PSW's 2-bit condition code field.
2958class SelectWrapper<RegisterOperand cls>
2959  : Pseudo<(outs cls:$dst),
2960           (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
2961           [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
2962                                            imm32zx4:$valid, imm32zx4:$cc))]> {
2963  let usesCustomInserter = 1;
2964  // Although the instructions used by these nodes do not in themselves
2965  // change CC, the insertion requires new blocks, and CC cannot be live
2966  // across them.
2967  let Defs = [CC];
2968  let Uses = [CC];
2969}
2970
2971// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
2972multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
2973                      SDPatternOperator load, AddressingMode mode> {
2974  let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
2975    def "" : Pseudo<(outs),
2976                    (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2977                    [(store (z_select_ccmask cls:$new, (load mode:$addr),
2978                                             imm32zx4:$valid, imm32zx4:$cc),
2979                            mode:$addr)]>;
2980    def Inv : Pseudo<(outs),
2981                     (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2982                     [(store (z_select_ccmask (load mode:$addr), cls:$new,
2983                                              imm32zx4:$valid, imm32zx4:$cc),
2984                              mode:$addr)]>;
2985  }
2986}
2987
2988// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation.  PAT and OPERAND
2989// describe the second (non-memory) operand.
2990class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
2991                       dag pat, DAGOperand operand>
2992  : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
2993           [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
2994  let Defs = [CC];
2995  let Has20BitOffset = 1;
2996  let mayLoad = 1;
2997  let mayStore = 1;
2998  let usesCustomInserter = 1;
2999  let hasNoSchedulingInfo = 1;
3000}
3001
3002// Specializations of AtomicLoadWBinary.
3003class AtomicLoadBinaryReg32<SDPatternOperator operator>
3004  : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
3005class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
3006  : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
3007class AtomicLoadBinaryReg64<SDPatternOperator operator>
3008  : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
3009class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
3010  : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
3011
3012// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation.  PAT and OPERAND
3013// describe the second (non-memory) operand.
3014class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
3015                        DAGOperand operand>
3016  : Pseudo<(outs GR32:$dst),
3017           (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
3018                ADDR32:$negbitshift, uimm32:$bitsize),
3019           [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
3020                                      ADDR32:$negbitshift, uimm32:$bitsize))]> {
3021  let Defs = [CC];
3022  let Has20BitOffset = 1;
3023  let mayLoad = 1;
3024  let mayStore = 1;
3025  let usesCustomInserter = 1;
3026  let hasNoSchedulingInfo = 1;
3027}
3028
3029// Specializations of AtomicLoadWBinary.
3030class AtomicLoadWBinaryReg<SDPatternOperator operator>
3031  : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
3032class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
3033  : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
3034
3035// Define an instruction that operates on two fixed-length blocks of memory,
3036// and associated pseudo instructions for operating on blocks of any size.
3037// The Sequence form uses a straight-line sequence of instructions and
3038// the Loop form uses a loop of length-256 instructions followed by
3039// another instruction to handle the excess.
3040multiclass MemorySS<string mnemonic, bits<8> opcode,
3041                    SDPatternOperator sequence, SDPatternOperator loop> {
3042  def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
3043                                       bdaddr12only:$BD2),
3044                  mnemonic##"\t$BDL1, $BD2", []>;
3045  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
3046    def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
3047                                       imm64:$length),
3048                           [(sequence bdaddr12only:$dest, bdaddr12only:$src,
3049                                      imm64:$length)]>;
3050    def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
3051                                   imm64:$length, GR64:$count256),
3052                      [(loop bdaddr12only:$dest, bdaddr12only:$src,
3053                             imm64:$length, GR64:$count256)]>;
3054  }
3055}
3056
3057// Define an instruction that operates on two strings, both terminated
3058// by the character in R0.  The instruction processes a CPU-determinated
3059// number of bytes at a time and sets CC to 3 if the instruction needs
3060// to be repeated.  Also define a pseudo instruction that represents
3061// the full loop (the main instruction plus the branch on CC==3).
3062multiclass StringRRE<string mnemonic, bits<16> opcode,
3063                     SDPatternOperator operator> {
3064  def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
3065                   (ins GR64:$R1src, GR64:$R2src),
3066                   mnemonic#"\t$R1, $R2", []> {
3067    let Uses = [R0L];
3068    let Constraints = "$R1 = $R1src, $R2 = $R2src";
3069    let DisableEncoding = "$R1src, $R2src";
3070  }
3071  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
3072    def Loop : Pseudo<(outs GR64:$end),
3073                      (ins GR64:$start1, GR64:$start2, GR32:$char),
3074                      [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
3075                                                 GR32:$char))]>;
3076}
3077
3078// A pseudo instruction that is a direct alias of a real instruction.
3079// These aliases are used in cases where a particular register operand is
3080// fixed or where the same instruction is used with different register sizes.
3081// The size parameter is the size in bytes of the associated real instruction.
3082class Alias<int size, dag outs, dag ins, list<dag> pattern>
3083  : InstSystemZ<size, outs, ins, "", pattern> {
3084  let isPseudo = 1;
3085  let isCodeGenOnly = 1;
3086}
3087
3088class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
3089 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
3090
3091// An alias of a UnaryVRR*, but with different register sizes.
3092class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
3093  : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
3094          [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
3095
3096// An alias of a UnaryVRX, but with different register sizes.
3097class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
3098                    AddressingMode mode = bdxaddr12only>
3099  : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
3100          [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
3101
3102// An alias of a StoreVRX, but with different register sizes.
3103class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
3104                    AddressingMode mode = bdxaddr12only>
3105  : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
3106          [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
3107
3108// An alias of a BinaryRI, but with different register sizes.
3109class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
3110                    Immediate imm>
3111  : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3112          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3113  let Constraints = "$R1 = $R1src";
3114}
3115
3116// An alias of a BinaryRIL, but with different register sizes.
3117class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
3118                     Immediate imm>
3119  : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3120          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3121  let Constraints = "$R1 = $R1src";
3122}
3123
3124// An alias of a BinaryVRRf, but with different register sizes.
3125class BinaryAliasVRRf<RegisterOperand cls>
3126  : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
3127
3128// An alias of a CompareRI, but with different register sizes.
3129class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
3130                     Immediate imm>
3131  : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
3132  let isCompare = 1;
3133}
3134
3135// An alias of a RotateSelectRIEf, but with different register sizes.
3136class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
3137  : Alias<6, (outs cls1:$R1),
3138          (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
3139               imm32zx6:$I5), []> {
3140  let Constraints = "$R1 = $R1src";
3141}
3142