1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Basic SystemZ instruction definition
12//===----------------------------------------------------------------------===//
13
14class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15                  list<dag> pattern> : Instruction {
16  let Namespace = "SystemZ";
17
18  dag OutOperandList = outs;
19  dag InOperandList = ins;
20  let Size = size;
21  let Pattern = pattern;
22  let AsmString = asmstr;
23
24  // Some instructions come in pairs, one having a 12-bit displacement
25  // and the other having a 20-bit displacement.  Both instructions in
26  // the pair have the same DispKey and their DispSizes are "12" and "20"
27  // respectively.
28  string DispKey = "";
29  string DispSize = "none";
30
31  // Many register-based <INSN>R instructions have a memory-based <INSN>
32  // counterpart.  OpKey uniquely identifies <INSN>R, while OpType is
33  // "reg" for <INSN>R and "mem" for <INSN>.
34  string OpKey = "";
35  string OpType = "none";
36
37  // Many distinct-operands instructions have older 2-operand equivalents.
38  // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39  // with NumOpsValue being "2" or "3" as appropriate.
40  string NumOpsKey = "";
41  string NumOpsValue = "none";
42
43  // True if this instruction is a simple D(X,B) load of a register
44  // (with no sign or zero extension).
45  bit SimpleBDXLoad = 0;
46
47  // True if this instruction is a simple D(X,B) store of a register
48  // (with no truncation).
49  bit SimpleBDXStore = 0;
50
51  // True if this instruction has a 20-bit displacement field.
52  bit Has20BitOffset = 0;
53
54  // True if addresses in this instruction have an index register.
55  bit HasIndex = 0;
56
57  // True if this is a 128-bit pseudo instruction that combines two 64-bit
58  // operations.
59  bit Is128Bit = 0;
60
61  // The access size of all memory operands in bytes, or 0 if not known.
62  bits<5> AccessBytes = 0;
63
64  // If the instruction sets CC to a useful value, this gives the mask
65  // of all possible CC results.  The mask has the same form as
66  // SystemZ::CCMASK_*.
67  bits<4> CCValues = 0;
68
69  // The subset of CCValues that have the same meaning as they would after
70  // a comparison of the first operand against zero.
71  bits<4> CompareZeroCCMask = 0;
72
73  // True if the instruction is conditional and if the CC mask operand
74  // comes first (as for BRC, etc.).
75  bit CCMaskFirst = 0;
76
77  // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
78  bit CCMaskLast = 0;
79
80  // True if the instruction is the "logical" rather than "arithmetic" form,
81  // in cases where a distinction exists.
82  bit IsLogical = 0;
83
84  let TSFlags{0}     = SimpleBDXLoad;
85  let TSFlags{1}     = SimpleBDXStore;
86  let TSFlags{2}     = Has20BitOffset;
87  let TSFlags{3}     = HasIndex;
88  let TSFlags{4}     = Is128Bit;
89  let TSFlags{9-5}   = AccessBytes;
90  let TSFlags{13-10} = CCValues;
91  let TSFlags{17-14} = CompareZeroCCMask;
92  let TSFlags{18}    = CCMaskFirst;
93  let TSFlags{19}    = CCMaskLast;
94  let TSFlags{20}    = IsLogical;
95}
96
97//===----------------------------------------------------------------------===//
98// Mappings between instructions
99//===----------------------------------------------------------------------===//
100
101// Return the version of an instruction that has an unsigned 12-bit
102// displacement.
103def getDisp12Opcode : InstrMapping {
104  let FilterClass = "InstSystemZ";
105  let RowFields = ["DispKey"];
106  let ColFields = ["DispSize"];
107  let KeyCol = ["20"];
108  let ValueCols = [["12"]];
109}
110
111// Return the version of an instruction that has a signed 20-bit displacement.
112def getDisp20Opcode : InstrMapping {
113  let FilterClass = "InstSystemZ";
114  let RowFields = ["DispKey"];
115  let ColFields = ["DispSize"];
116  let KeyCol = ["12"];
117  let ValueCols = [["20"]];
118}
119
120// Return the memory form of a register instruction.
121def getMemOpcode : InstrMapping {
122  let FilterClass = "InstSystemZ";
123  let RowFields = ["OpKey"];
124  let ColFields = ["OpType"];
125  let KeyCol = ["reg"];
126  let ValueCols = [["mem"]];
127}
128
129// Return the 3-operand form of a 2-operand instruction.
130def getThreeOperandOpcode : InstrMapping {
131  let FilterClass = "InstSystemZ";
132  let RowFields = ["NumOpsKey"];
133  let ColFields = ["NumOpsValue"];
134  let KeyCol = ["2"];
135  let ValueCols = [["3"]];
136}
137
138//===----------------------------------------------------------------------===//
139// Instruction formats
140//===----------------------------------------------------------------------===//
141//
142// Formats are specified using operand field declarations of the form:
143//
144//   bits<4> Rn   : register input or output for operand n
145//   bits<5> Vn   : vector register input or output for operand n
146//   bits<m> In   : immediate value of width m for operand n
147//   bits<4> BDn  : address operand n, which has a base and a displacement
148//   bits<m> XBDn : address operand n, which has an index, a base and a
149//                  displacement
150//   bits<m> VBDn : address operand n, which has a vector index, a base and a
151//                  displacement
152//   bits<4> Xn   : index register for address operand n
153//   bits<4> Mn   : mode value for operand n
154//
155// The operand numbers ("n" in the list above) follow the architecture manual.
156// Assembly operands sometimes have a different order; in particular, R3 often
157// is often written between operands 1 and 2.
158//
159//===----------------------------------------------------------------------===//
160
161class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162  : InstSystemZ<2, outs, ins, asmstr, pattern> {
163  field bits<16> Inst;
164  field bits<16> SoftFail = 0;
165
166  let Inst = op;
167}
168
169class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
170  : InstSystemZ<2, outs, ins, asmstr, pattern> {
171  field bits<16> Inst;
172  field bits<16> SoftFail = 0;
173
174  bits<8> I1;
175
176  let Inst{15-8} = op;
177  let Inst{7-0}  = I1;
178}
179
180class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
181  : InstSystemZ<4, outs, ins, asmstr, pattern> {
182  field bits<32> Inst;
183  field bits<32> SoftFail = 0;
184
185  bits<4> I1;
186  bits<4> I2;
187
188  let Inst{31-16} = op;
189  let Inst{15-8}  = 0;
190  let Inst{7-4}   = I1;
191  let Inst{3-0}   = I2;
192}
193
194class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195  : InstSystemZ<6, outs, ins, asmstr, pattern> {
196  field bits<48> Inst;
197  field bits<48> SoftFail = 0;
198
199  bits<4> M1;
200  bits<12> RI2;
201  bits<24> RI3;
202
203  let Inst{47-40} = op;
204  let Inst{39-36} = M1;
205  let Inst{35-24} = RI2;
206  let Inst{23-0}  = RI3;
207}
208
209class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
210  : InstSystemZ<4, outs, ins, asmstr, pattern> {
211  field bits<32> Inst;
212  field bits<32> SoftFail = 0;
213
214  bits<4> R1;
215  bits<16> I2;
216
217  let Inst{31-24} = op{11-4};
218  let Inst{23-20} = R1;
219  let Inst{19-16} = op{3-0};
220  let Inst{15-0}  = I2;
221}
222
223class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
224  : InstSystemZ<4, outs, ins, asmstr, pattern> {
225  field bits<32> Inst;
226  field bits<32> SoftFail = 0;
227
228  bits<4> R1;
229  bits<16> RI2;
230
231  let Inst{31-24} = op{11-4};
232  let Inst{23-20} = R1;
233  let Inst{19-16} = op{3-0};
234  let Inst{15-0}  = RI2;
235}
236
237class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
238  : InstSystemZ<4, outs, ins, asmstr, pattern> {
239  field bits<32> Inst;
240  field bits<32> SoftFail = 0;
241
242  bits<4> M1;
243  bits<16> RI2;
244
245  let Inst{31-24} = op{11-4};
246  let Inst{23-20} = M1;
247  let Inst{19-16} = op{3-0};
248  let Inst{15-0}  = RI2;
249}
250
251class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
252  : InstSystemZ<6, outs, ins, asmstr, pattern> {
253  field bits<48> Inst;
254  field bits<48> SoftFail = 0;
255
256  bits<4> R1;
257  bits<16> I2;
258  bits<4> M3;
259
260  let Inst{47-40} = op{15-8};
261  let Inst{39-36} = R1;
262  let Inst{35-32} = 0;
263  let Inst{31-16} = I2;
264  let Inst{15-12} = M3;
265  let Inst{11-8}  = 0;
266  let Inst{7-0}   = op{7-0};
267}
268
269class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
270  : InstSystemZ<6, outs, ins, asmstr, pattern> {
271  field bits<48> Inst;
272  field bits<48> SoftFail = 0;
273
274  bits<4> R1;
275  bits<4> R2;
276  bits<4> M3;
277  bits<16> RI4;
278
279  let Inst{47-40} = op{15-8};
280  let Inst{39-36} = R1;
281  let Inst{35-32} = R2;
282  let Inst{31-16} = RI4;
283  let Inst{15-12} = M3;
284  let Inst{11-8}  = 0;
285  let Inst{7-0}   = op{7-0};
286}
287
288class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
289  : InstSystemZ<6, outs, ins, asmstr, pattern> {
290  field bits<48> Inst;
291  field bits<48> SoftFail = 0;
292
293  bits<4> R1;
294  bits<8> I2;
295  bits<4> M3;
296  bits<16> RI4;
297
298  let Inst{47-40} = op{15-8};
299  let Inst{39-36} = R1;
300  let Inst{35-32} = M3;
301  let Inst{31-16} = RI4;
302  let Inst{15-8}  = I2;
303  let Inst{7-0}   = op{7-0};
304}
305
306class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
307  : InstSystemZ<6, outs, ins, asmstr, pattern> {
308  field bits<48> Inst;
309  field bits<48> SoftFail = 0;
310
311  bits<4> R1;
312  bits<4> R3;
313  bits<16> I2;
314
315  let Inst{47-40} = op{15-8};
316  let Inst{39-36} = R1;
317  let Inst{35-32} = R3;
318  let Inst{31-16} = I2;
319  let Inst{15-8}  = 0;
320  let Inst{7-0}   = op{7-0};
321}
322
323class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
324  : InstSystemZ<6, outs, ins, asmstr, pattern> {
325  field bits<48> Inst;
326  field bits<48> SoftFail = 0;
327
328  bits<4> R1;
329  bits<4> R3;
330  bits<16> RI2;
331
332  let Inst{47-40} = op{15-8};
333  let Inst{39-36} = R1;
334  let Inst{35-32} = R3;
335  let Inst{31-16} = RI2;
336  let Inst{15-8}  = 0;
337  let Inst{7-0}   = op{7-0};
338}
339
340class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
341  : InstSystemZ<6, outs, ins, asmstr, pattern> {
342  field bits<48> Inst;
343  field bits<48> SoftFail = 0;
344
345  bits<4> R1;
346  bits<4> R2;
347  bits<8> I3;
348  bits<8> I4;
349  bits<8> I5;
350
351  let Inst{47-40} = op{15-8};
352  let Inst{39-36} = R1;
353  let Inst{35-32} = R2;
354  let Inst{31-24} = I3;
355  let Inst{23-16} = I4;
356  let Inst{15-8}  = I5;
357  let Inst{7-0}   = op{7-0};
358}
359
360class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
361  : InstSystemZ<6, outs, ins, asmstr, pattern> {
362  field bits<48> Inst;
363  field bits<48> SoftFail = 0;
364
365  bits<4> R1;
366  bits<4> M3;
367  bits<16> I2;
368
369  let Inst{47-40} = op{15-8};
370  let Inst{39-36} = R1;
371  let Inst{35-32} = M3;
372  let Inst{31-16} = I2;
373  let Inst{15-8}  = 0;
374  let Inst{7-0}   = op{7-0};
375}
376
377class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
378  : InstSystemZ<6, outs, ins, asmstr, pattern> {
379  field bits<48> Inst;
380  field bits<48> SoftFail = 0;
381
382  bits<4> R1;
383  bits<32> I2;
384
385  let Inst{47-40} = op{11-4};
386  let Inst{39-36} = R1;
387  let Inst{35-32} = op{3-0};
388  let Inst{31-0}  = I2;
389}
390
391class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
392  : InstSystemZ<6, outs, ins, asmstr, pattern> {
393  field bits<48> Inst;
394  field bits<48> SoftFail = 0;
395
396  bits<4> R1;
397  bits<32> RI2;
398
399  let Inst{47-40} = op{11-4};
400  let Inst{39-36} = R1;
401  let Inst{35-32} = op{3-0};
402  let Inst{31-0}  = RI2;
403}
404
405class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
406  : InstSystemZ<6, outs, ins, asmstr, pattern> {
407  field bits<48> Inst;
408  field bits<48> SoftFail = 0;
409
410  bits<4> M1;
411  bits<32> RI2;
412
413  let Inst{47-40} = op{11-4};
414  let Inst{39-36} = M1;
415  let Inst{35-32} = op{3-0};
416  let Inst{31-0}  = RI2;
417}
418
419class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
420  : InstSystemZ<6, outs, ins, asmstr, pattern> {
421  field bits<48> Inst;
422  field bits<48> SoftFail = 0;
423
424  bits<4> R1;
425  bits<8> I2;
426  bits<4> M3;
427  bits<16> BD4;
428
429  let Inst{47-40} = op{15-8};
430  let Inst{39-36} = R1;
431  let Inst{35-32} = M3;
432  let Inst{31-16} = BD4;
433  let Inst{15-8}  = I2;
434  let Inst{7-0}   = op{7-0};
435}
436
437class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
438  : InstSystemZ<2, outs, ins, asmstr, pattern> {
439  field bits<16> Inst;
440  field bits<16> SoftFail = 0;
441
442  bits<4> R1;
443  bits<4> R2;
444
445  let Inst{15-8} = op;
446  let Inst{7-4}  = R1;
447  let Inst{3-0}  = R2;
448}
449
450class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
451  : InstSystemZ<4, outs, ins, asmstr, pattern> {
452  field bits<32> Inst;
453  field bits<32> SoftFail = 0;
454
455  bits<4> R1;
456  bits<4> R3;
457  bits<4> R2;
458
459  let Inst{31-16} = op;
460  let Inst{15-12} = R1;
461  let Inst{11-8}  = 0;
462  let Inst{7-4}   = R3;
463  let Inst{3-0}   = R2;
464}
465
466class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
467  : InstSystemZ<4, outs, ins, asmstr, pattern> {
468  field bits<32> Inst;
469  field bits<32> SoftFail = 0;
470
471  bits<4> R1;
472  bits<4> R2;
473
474  let Inst{31-16} = op;
475  let Inst{15-8}  = 0;
476  let Inst{7-4}   = R1;
477  let Inst{3-0}   = R2;
478}
479
480class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
481  : InstSystemZ<4, outs, ins, asmstr, pattern> {
482  field bits<32> Inst;
483  field bits<32> SoftFail = 0;
484
485  bits<4> R1;
486  bits<4> R2;
487  bits<4> R3;
488  bits<4> M4;
489
490  let Inst{31-16} = op;
491  let Inst{15-12} = R3;
492  let Inst{11-8}  = M4;
493  let Inst{7-4}   = R1;
494  let Inst{3-0}   = R2;
495}
496
497class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
498  : InstSystemZ<4, outs, ins, asmstr, pattern> {
499  field bits<32> Inst;
500  field bits<32> SoftFail = 0;
501
502  bits<4> R1;
503  bits<4> R2;
504  bits<4> R3;
505  bits<4> M4;
506
507  let Inst{31-16} = op;
508  let Inst{15-12} = R3;
509  let Inst{11-8}  = M4;
510  let Inst{7-4}   = R1;
511  let Inst{3-0}   = R2;
512}
513
514class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
515  : InstSystemZ<4, outs, ins, asmstr, pattern> {
516  field bits<32> Inst;
517  field bits<32> SoftFail = 0;
518
519  bits<4> R1;
520  bits<4> R2;
521  bits<4> M3;
522
523  let Inst{31-16} = op;
524  let Inst{15-12} = M3;
525  let Inst{11-8}  = 0;
526  let Inst{7-4}   = R1;
527  let Inst{3-0}   = R2;
528}
529
530class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
531  : InstSystemZ<4, outs, ins, asmstr, pattern> {
532  field bits<32> Inst;
533  field bits<32> SoftFail = 0;
534
535  bits<4> R1;
536  bits<4> R2;
537  bits<4> M4;
538
539  let Inst{31-16} = op;
540  let Inst{15-12} = 0;
541  let Inst{11-8}  = M4;
542  let Inst{7-4}   = R1;
543  let Inst{3-0}   = R2;
544}
545
546class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
547  : InstSystemZ<4, outs, ins, asmstr, pattern> {
548  field bits<32> Inst;
549  field bits<32> SoftFail = 0;
550
551  bits<4> R1;
552  bits<4> R2;
553  bits<4> M3;
554  bits<4> M4;
555
556  let Inst{31-16} = op;
557  let Inst{15-12} = M3;
558  let Inst{11-8}  = M4;
559  let Inst{7-4}   = R1;
560  let Inst{3-0}   = R2;
561}
562
563class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
564  : InstSystemZ<6, outs, ins, asmstr, pattern> {
565  field bits<48> Inst;
566  field bits<48> SoftFail = 0;
567
568  bits<4> R1;
569  bits<4> R2;
570  bits<4> M3;
571  bits<16> BD4;
572
573  let Inst{47-40} = op{15-8};
574  let Inst{39-36} = R1;
575  let Inst{35-32} = R2;
576  let Inst{31-16} = BD4;
577  let Inst{15-12} = M3;
578  let Inst{11-8}  = 0;
579  let Inst{7-0}   = op{7-0};
580}
581
582class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
583  : InstSystemZ<4, outs, ins, asmstr, pattern> {
584  field bits<32> Inst;
585  field bits<32> SoftFail = 0;
586
587  bits<4> R1;
588  bits<20> XBD2;
589
590  let Inst{31-24} = op;
591  let Inst{23-20} = R1;
592  let Inst{19-0}  = XBD2;
593
594  let HasIndex = 1;
595}
596
597class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
598  : InstSystemZ<4, outs, ins, asmstr, pattern> {
599  field bits<32> Inst;
600  field bits<32> SoftFail = 0;
601
602  bits<4> M1;
603  bits<20> XBD2;
604
605  let Inst{31-24} = op;
606  let Inst{23-20} = M1;
607  let Inst{19-0}  = XBD2;
608
609  let HasIndex = 1;
610}
611
612class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
613  : InstSystemZ<6, outs, ins, asmstr, pattern> {
614  field bits<48> Inst;
615  field bits<48> SoftFail = 0;
616
617  bits<4> R1;
618  bits<20> XBD2;
619  bits<4> M3;
620
621  let Inst{47-40} = op{15-8};
622  let Inst{39-36} = R1;
623  let Inst{35-16} = XBD2;
624  let Inst{15-12} = M3;
625  let Inst{11-8}  = 0;
626  let Inst{7-0}   = op{7-0};
627
628  let HasIndex = 1;
629}
630
631class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
632  : InstSystemZ<6, outs, ins, asmstr, pattern> {
633  field bits<48> Inst;
634  field bits<48> SoftFail = 0;
635
636  bits<4> R1;
637  bits<4> R3;
638  bits<20> XBD2;
639
640  let Inst{47-40} = op{15-8};
641  let Inst{39-36} = R3;
642  let Inst{35-16} = XBD2;
643  let Inst{15-12} = R1;
644  let Inst{11-8}  = 0;
645  let Inst{7-0}   = op{7-0};
646
647  let HasIndex = 1;
648}
649
650class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
651  : InstSystemZ<6, outs, ins, asmstr, pattern> {
652  field bits<48> Inst;
653  field bits<48> SoftFail = 0;
654
655  bits<4> R1;
656  bits<28> XBD2;
657
658  let Inst{47-40} = op{15-8};
659  let Inst{39-36} = R1;
660  let Inst{35-8}  = XBD2;
661  let Inst{7-0}   = op{7-0};
662
663  let Has20BitOffset = 1;
664  let HasIndex = 1;
665}
666
667class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
668  : InstSystemZ<6, outs, ins, asmstr, pattern> {
669  field bits<48> Inst;
670  field bits<48> SoftFail = 0;
671
672  bits<4> M1;
673  bits<28> XBD2;
674
675  let Inst{47-40} = op{15-8};
676  let Inst{39-36} = M1;
677  let Inst{35-8}  = XBD2;
678  let Inst{7-0}   = op{7-0};
679
680  let Has20BitOffset = 1;
681  let HasIndex = 1;
682}
683
684class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
685  : InstSystemZ<4, outs, ins, asmstr, pattern> {
686  field bits<32> Inst;
687  field bits<32> SoftFail = 0;
688
689  bits<4> R1;
690  bits<4> R3;
691  bits<16> BD2;
692
693  let Inst{31-24} = op;
694  let Inst{23-20} = R1;
695  let Inst{19-16} = R3;
696  let Inst{15-0}  = BD2;
697}
698
699class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
700  : InstSystemZ<4, outs, ins, asmstr, pattern> {
701  field bits<32> Inst;
702  field bits<32> SoftFail = 0;
703
704  bits<4> R1;
705  bits<4> M3;
706  bits<16> BD2;
707
708  let Inst{31-24} = op;
709  let Inst{23-20} = R1;
710  let Inst{19-16} = M3;
711  let Inst{15-0}  = BD2;
712}
713
714class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
715  : InstSystemZ<4, outs, ins, asmstr, pattern> {
716  field bits<32> Inst;
717  field bits<32> SoftFail = 0;
718
719  bits<4> R1;
720  bits<4> R3;
721  bits<16> RI2;
722
723  let Inst{31-24} = op;
724  let Inst{23-20} = R1;
725  let Inst{19-16} = R3;
726  let Inst{15-0}  = RI2;
727}
728
729class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
730  : InstSystemZ<6, outs, ins, asmstr, pattern> {
731  field bits<48> Inst;
732  field bits<48> SoftFail = 0;
733
734  bits<20> BDL1;
735
736  let Inst{47-40} = op{15-8};
737  let Inst{39-36} = BDL1{19-16};
738  let Inst{35-32} = 0;
739  let Inst{31-16} = BDL1{15-0};
740  let Inst{15-8}  = 0;
741  let Inst{7-0}   = op{7-0};
742}
743
744class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
745  : InstSystemZ<6, outs, ins, asmstr, pattern> {
746  field bits<48> Inst;
747  field bits<48> SoftFail = 0;
748
749  bits<4> R1;
750  bits<24> BDL2;
751  bits<4> M3;
752
753  let Inst{47-40} = op{15-8};
754  let Inst{39-16} = BDL2;
755  let Inst{15-12} = R1;
756  let Inst{11-8}  = M3;
757  let Inst{7-0}   = op{7-0};
758}
759
760class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
761  : InstSystemZ<6, outs, ins, asmstr, pattern> {
762  field bits<48> Inst;
763  field bits<48> SoftFail = 0;
764
765  bits<4> R1;
766  bits<4> R3;
767  bits<24> BD2;
768
769  let Inst{47-40} = op{15-8};
770  let Inst{39-36} = R1;
771  let Inst{35-32} = R3;
772  let Inst{31-8}  = BD2;
773  let Inst{7-0}   = op{7-0};
774
775  let Has20BitOffset = 1;
776}
777
778class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
779  : InstSystemZ<6, outs, ins, asmstr, pattern> {
780  field bits<48> Inst;
781  field bits<48> SoftFail = 0;
782
783  bits<4> R1;
784  bits<4> M3;
785  bits<24> BD2;
786
787  let Inst{47-40} = op{15-8};
788  let Inst{39-36} = R1;
789  let Inst{35-32} = M3;
790  let Inst{31-8}  = BD2;
791  let Inst{7-0}   = op{7-0};
792
793  let Has20BitOffset = 1;
794}
795
796class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
797  : InstSystemZ<4, outs, ins, asmstr, pattern> {
798  field bits<32> Inst;
799  field bits<32> SoftFail = 0;
800
801  bits<16> BD1;
802  bits<8> I2;
803
804  let Inst{31-24} = op;
805  let Inst{23-16} = I2;
806  let Inst{15-0}  = BD1;
807}
808
809class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
810  : InstSystemZ<6, outs, ins, asmstr, pattern> {
811  field bits<48> Inst;
812  field bits<48> SoftFail = 0;
813
814  bits<16> BD1;
815  bits<16> I2;
816
817  let Inst{47-32} = op;
818  let Inst{31-16} = BD1;
819  let Inst{15-0}  = I2;
820}
821
822class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
823  : InstSystemZ<6, outs, ins, asmstr, pattern> {
824  field bits<48> Inst;
825  field bits<48> SoftFail = 0;
826
827  bits<24> BD1;
828  bits<8> I2;
829
830  let Inst{47-40} = op{15-8};
831  let Inst{39-32} = I2;
832  let Inst{31-8}  = BD1;
833  let Inst{7-0}   = op{7-0};
834
835  let Has20BitOffset = 1;
836}
837
838class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
839  : InstSystemZ<6, outs, ins, asmstr, pattern> {
840  field bits<48> Inst;
841  field bits<48> SoftFail = 0;
842
843  bits<4> M1;
844  bits<16> RI2;
845  bits<16> BD3;
846
847  let Inst{47-40} = op;
848  let Inst{39-36} = M1;
849  let Inst{35-32} = 0;
850  let Inst{31-16} = BD3;
851  let Inst{15-0}  = RI2;
852}
853
854class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
855  : InstSystemZ<6, outs, ins, asmstr, pattern> {
856  field bits<48> Inst;
857  field bits<48> SoftFail = 0;
858
859  bits<24> BDL1;
860  bits<16> BD2;
861
862  let Inst{47-40} = op;
863  let Inst{39-16} = BDL1;
864  let Inst{15-0}  = BD2;
865}
866
867class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
868  : InstSystemZ<6, outs, ins, asmstr, pattern> {
869  field bits<48> Inst;
870  field bits<48> SoftFail = 0;
871
872  bits<20> BDL1;
873  bits<20> BDL2;
874
875  let Inst{47-40} = op;
876  let Inst{39-36} = BDL1{19-16};
877  let Inst{35-32} = BDL2{19-16};
878  let Inst{31-16} = BDL1{15-0};
879  let Inst{15-0}  = BDL2{15-0};
880}
881
882class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
883  : InstSystemZ<6, outs, ins, asmstr, pattern> {
884  field bits<48> Inst;
885  field bits<48> SoftFail = 0;
886
887  bits<20> BDL1;
888  bits<16> BD2;
889  bits<4> I3;
890
891  let Inst{47-40} = op;
892  let Inst{39-36} = BDL1{19-16};
893  let Inst{35-32} = I3;
894  let Inst{31-16} = BDL1{15-0};
895  let Inst{15-0}  = BD2;
896}
897
898class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
899  : InstSystemZ<6, outs, ins, asmstr, pattern> {
900  field bits<48> Inst;
901  field bits<48> SoftFail = 0;
902
903  bits<20> RBD1;
904  bits<16> BD2;
905  bits<4> R3;
906
907  let Inst{47-40} = op;
908  let Inst{39-36} = RBD1{19-16};
909  let Inst{35-32} = R3;
910  let Inst{31-16} = RBD1{15-0};
911  let Inst{15-0}  = BD2;
912}
913
914class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
915  : InstSystemZ<6, outs, ins, asmstr, pattern> {
916  field bits<48> Inst;
917  field bits<48> SoftFail = 0;
918
919  bits<4> R1;
920  bits<16> BD2;
921  bits<4> R3;
922  bits<16> BD4;
923
924  let Inst{47-40} = op;
925  let Inst{39-36} = R1;
926  let Inst{35-32} = R3;
927  let Inst{31-16} = BD2;
928  let Inst{15-0}  = BD4;
929}
930
931class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
932  : InstSystemZ<6, outs, ins, asmstr, pattern> {
933  field bits<48> Inst;
934  field bits<48> SoftFail = 0;
935
936  bits<16> BD1;
937  bits<24> BDL2;
938
939  let Inst{47-40} = op;
940  let Inst{39-32} = BDL2{23-16};
941  let Inst{31-16} = BD1;
942  let Inst{15-0}  = BDL2{15-0};
943}
944
945class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
946  : InstSystemZ<6, outs, ins, asmstr, pattern> {
947  field bits<48> Inst;
948  field bits<48> SoftFail = 0;
949
950  bits<16> BD1;
951  bits<16> BD2;
952
953  let Inst{47-32} = op;
954  let Inst{31-16} = BD1;
955  let Inst{15-0}  = BD2;
956}
957
958class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
959  : InstSystemZ<6, outs, ins, asmstr, pattern> {
960  field bits<48> Inst;
961  field bits<48> SoftFail = 0;
962
963  bits<16> BD1;
964  bits<16> BD2;
965  bits<4>  R3;
966
967  let Inst{47-40} = op{11-4};
968  let Inst{39-36} = R3;
969  let Inst{35-32} = op{3-0};
970  let Inst{31-16} = BD1;
971  let Inst{15-0}  = BD2;
972}
973
974class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
975  : InstSystemZ<4, outs, ins, asmstr, pattern> {
976  field bits<32> Inst;
977  field bits<32> SoftFail = 0;
978
979  bits<16> BD2;
980
981  let Inst{31-16} = op;
982  let Inst{15-0}  = BD2;
983}
984
985class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
986  : InstSystemZ<6, outs, ins, asmstr, pattern> {
987  field bits<48> Inst;
988  field bits<48> SoftFail = 0;
989
990  bits<5> V1;
991  bits<16> I2;
992  bits<4> M3;
993
994  let Inst{47-40} = op{15-8};
995  let Inst{39-36} = V1{3-0};
996  let Inst{35-32} = 0;
997  let Inst{31-16} = I2;
998  let Inst{15-12} = M3;
999  let Inst{11}    = V1{4};
1000  let Inst{10-8}  = 0;
1001  let Inst{7-0}   = op{7-0};
1002}
1003
1004class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1005  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1006  field bits<48> Inst;
1007  field bits<48> SoftFail = 0;
1008
1009  bits<5> V1;
1010  bits<8> I2;
1011  bits<8> I3;
1012  bits<4> M4;
1013
1014  let Inst{47-40} = op{15-8};
1015  let Inst{39-36} = V1{3-0};
1016  let Inst{35-32} = 0;
1017  let Inst{31-24} = I2;
1018  let Inst{23-16} = I3;
1019  let Inst{15-12} = M4;
1020  let Inst{11}    = V1{4};
1021  let Inst{10-8}  = 0;
1022  let Inst{7-0}   = op{7-0};
1023}
1024
1025class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1026  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1027  field bits<48> Inst;
1028  field bits<48> SoftFail = 0;
1029
1030  bits<5> V1;
1031  bits<5> V3;
1032  bits<16> I2;
1033  bits<4> M4;
1034
1035  let Inst{47-40} = op{15-8};
1036  let Inst{39-36} = V1{3-0};
1037  let Inst{35-32} = V3{3-0};
1038  let Inst{31-16} = I2;
1039  let Inst{15-12} = M4;
1040  let Inst{11}    = V1{4};
1041  let Inst{10}    = V3{4};
1042  let Inst{9-8}   = 0;
1043  let Inst{7-0}   = op{7-0};
1044}
1045
1046class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1047  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1048  field bits<48> Inst;
1049  field bits<48> SoftFail = 0;
1050
1051  bits<5> V1;
1052  bits<5> V2;
1053  bits<5> V3;
1054  bits<8> I4;
1055  bits<4> M5;
1056
1057  let Inst{47-40} = op{15-8};
1058  let Inst{39-36} = V1{3-0};
1059  let Inst{35-32} = V2{3-0};
1060  let Inst{31-28} = V3{3-0};
1061  let Inst{27-24} = 0;
1062  let Inst{23-16} = I4;
1063  let Inst{15-12} = M5;
1064  let Inst{11}    = V1{4};
1065  let Inst{10}    = V2{4};
1066  let Inst{9}     = V3{4};
1067  let Inst{8}     = 0;
1068  let Inst{7-0}   = op{7-0};
1069}
1070
1071class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1072  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1073  field bits<48> Inst;
1074  field bits<48> SoftFail = 0;
1075
1076  bits<5> V1;
1077  bits<5> V2;
1078  bits<12> I3;
1079  bits<4> M4;
1080  bits<4> M5;
1081
1082  let Inst{47-40} = op{15-8};
1083  let Inst{39-36} = V1{3-0};
1084  let Inst{35-32} = V2{3-0};
1085  let Inst{31-20} = I3;
1086  let Inst{19-16} = M5;
1087  let Inst{15-12} = M4;
1088  let Inst{11}    = V1{4};
1089  let Inst{10}    = V2{4};
1090  let Inst{9-8}   = 0;
1091  let Inst{7-0}   = op{7-0};
1092}
1093
1094// Depending on the instruction mnemonic, certain bits may be or-ed into
1095// the M4 value provided as explicit operand.  These are passed as m4or.
1096class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1097               bits<4> m4or = 0>
1098  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1099  field bits<48> Inst;
1100  field bits<48> SoftFail = 0;
1101
1102  bits<5> V1;
1103  bits<5> V2;
1104  bits<4> M3;
1105  bits<4> M4;
1106  bits<4> M5;
1107
1108  let Inst{47-40} = op{15-8};
1109  let Inst{39-36} = V1{3-0};
1110  let Inst{35-32} = V2{3-0};
1111  let Inst{31-24} = 0;
1112  let Inst{23-20} = M5;
1113  let Inst{19}    = !if (!eq (m4or{3}, 1), 1, M4{3});
1114  let Inst{18}    = !if (!eq (m4or{2}, 1), 1, M4{2});
1115  let Inst{17}    = !if (!eq (m4or{1}, 1), 1, M4{1});
1116  let Inst{16}    = !if (!eq (m4or{0}, 1), 1, M4{0});
1117  let Inst{15-12} = M3;
1118  let Inst{11}    = V1{4};
1119  let Inst{10}    = V2{4};
1120  let Inst{9-8}   = 0;
1121  let Inst{7-0}   = op{7-0};
1122}
1123
1124// Depending on the instruction mnemonic, certain bits may be or-ed into
1125// the M5 value provided as explicit operand.  These are passed as m5or.
1126class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1127               bits<4> m5or = 0>
1128  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1129  field bits<48> Inst;
1130  field bits<48> SoftFail = 0;
1131
1132  bits<5> V1;
1133  bits<5> V2;
1134  bits<5> V3;
1135  bits<4> M4;
1136  bits<4> M5;
1137
1138  let Inst{47-40} = op{15-8};
1139  let Inst{39-36} = V1{3-0};
1140  let Inst{35-32} = V2{3-0};
1141  let Inst{31-28} = V3{3-0};
1142  let Inst{27-24} = 0;
1143  let Inst{23}    = !if (!eq (m5or{3}, 1), 1, M5{3});
1144  let Inst{22}    = !if (!eq (m5or{2}, 1), 1, M5{2});
1145  let Inst{21}    = !if (!eq (m5or{1}, 1), 1, M5{1});
1146  let Inst{20}    = !if (!eq (m5or{0}, 1), 1, M5{0});
1147  let Inst{19-16} = 0;
1148  let Inst{15-12} = M4;
1149  let Inst{11}    = V1{4};
1150  let Inst{10}    = V2{4};
1151  let Inst{9}     = V3{4};
1152  let Inst{8}     = 0;
1153  let Inst{7-0}   = op{7-0};
1154}
1155
1156class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1157  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1158  field bits<48> Inst;
1159  field bits<48> SoftFail = 0;
1160
1161  bits<5> V1;
1162  bits<5> V2;
1163  bits<5> V3;
1164  bits<4> M4;
1165  bits<4> M5;
1166  bits<4> M6;
1167
1168  let Inst{47-40} = op{15-8};
1169  let Inst{39-36} = V1{3-0};
1170  let Inst{35-32} = V2{3-0};
1171  let Inst{31-28} = V3{3-0};
1172  let Inst{27-24} = 0;
1173  let Inst{23-20} = M6;
1174  let Inst{19-16} = M5;
1175  let Inst{15-12} = M4;
1176  let Inst{11}    = V1{4};
1177  let Inst{10}    = V2{4};
1178  let Inst{9}     = V3{4};
1179  let Inst{8}     = 0;
1180  let Inst{7-0}   = op{7-0};
1181}
1182
1183// Depending on the instruction mnemonic, certain bits may be or-ed into
1184// the M6 value provided as explicit operand.  These are passed as m6or.
1185class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1186               bits<4> m6or = 0>
1187  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1188  field bits<48> Inst;
1189  field bits<48> SoftFail = 0;
1190
1191  bits<5> V1;
1192  bits<5> V2;
1193  bits<5> V3;
1194  bits<5> V4;
1195  bits<4> M5;
1196  bits<4> M6;
1197
1198  let Inst{47-40} = op{15-8};
1199  let Inst{39-36} = V1{3-0};
1200  let Inst{35-32} = V2{3-0};
1201  let Inst{31-28} = V3{3-0};
1202  let Inst{27-24} = M5;
1203  let Inst{23}    = !if (!eq (m6or{3}, 1), 1, M6{3});
1204  let Inst{22}    = !if (!eq (m6or{2}, 1), 1, M6{2});
1205  let Inst{21}    = !if (!eq (m6or{1}, 1), 1, M6{1});
1206  let Inst{20}    = !if (!eq (m6or{0}, 1), 1, M6{0});
1207  let Inst{19-16} = 0;
1208  let Inst{15-12} = V4{3-0};
1209  let Inst{11}    = V1{4};
1210  let Inst{10}    = V2{4};
1211  let Inst{9}     = V3{4};
1212  let Inst{8}     = V4{4};
1213  let Inst{7-0}   = op{7-0};
1214}
1215
1216class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1217  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1218  field bits<48> Inst;
1219  field bits<48> SoftFail = 0;
1220
1221  bits<5> V1;
1222  bits<5> V2;
1223  bits<5> V3;
1224  bits<5> V4;
1225  bits<4> M5;
1226  bits<4> M6;
1227
1228  let Inst{47-40} = op{15-8};
1229  let Inst{39-36} = V1{3-0};
1230  let Inst{35-32} = V2{3-0};
1231  let Inst{31-28} = V3{3-0};
1232  let Inst{27-24} = M6;
1233  let Inst{23-20} = 0;
1234  let Inst{19-16} = M5;
1235  let Inst{15-12} = V4{3-0};
1236  let Inst{11}    = V1{4};
1237  let Inst{10}    = V2{4};
1238  let Inst{9}     = V3{4};
1239  let Inst{8}     = V4{4};
1240  let Inst{7-0}   = op{7-0};
1241}
1242
1243class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1244  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1245  field bits<48> Inst;
1246  field bits<48> SoftFail = 0;
1247
1248  bits<5> V1;
1249  bits<4> R2;
1250  bits<4> R3;
1251
1252  let Inst{47-40} = op{15-8};
1253  let Inst{39-36} = V1{3-0};
1254  let Inst{35-32} = R2;
1255  let Inst{31-28} = R3;
1256  let Inst{27-12} = 0;
1257  let Inst{11}    = V1{4};
1258  let Inst{10-8}  = 0;
1259  let Inst{7-0}   = op{7-0};
1260}
1261
1262class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1263  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1264  field bits<48> Inst;
1265  field bits<48> SoftFail = 0;
1266
1267  bits<5> V1;
1268  bits<16> BD2;
1269  bits<5> V3;
1270  bits<4> M4;
1271
1272  let Inst{47-40} = op{15-8};
1273  let Inst{39-36} = V1{3-0};
1274  let Inst{35-32} = V3{3-0};
1275  let Inst{31-16} = BD2;
1276  let Inst{15-12} = M4;
1277  let Inst{11}    = V1{4};
1278  let Inst{10}    = V3{4};
1279  let Inst{9-8}   = 0;
1280  let Inst{7-0}   = op{7-0};
1281}
1282
1283class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1284  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1285  field bits<48> Inst;
1286  field bits<48> SoftFail = 0;
1287
1288  bits<5> V1;
1289  bits<16> BD2;
1290  bits<4> R3;
1291  bits<4> M4;
1292
1293  let Inst{47-40} = op{15-8};
1294  let Inst{39-36} = V1{3-0};
1295  let Inst{35-32} = R3;
1296  let Inst{31-16} = BD2;
1297  let Inst{15-12} = M4;
1298  let Inst{11}    = V1{4};
1299  let Inst{10-8}  = 0;
1300  let Inst{7-0}   = op{7-0};
1301}
1302
1303class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1304  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1305  field bits<48> Inst;
1306  field bits<48> SoftFail = 0;
1307
1308  bits<4> R1;
1309  bits<16> BD2;
1310  bits<5> V3;
1311  bits<4> M4;
1312
1313  let Inst{47-40} = op{15-8};
1314  let Inst{39-36} = R1;
1315  let Inst{35-32} = V3{3-0};
1316  let Inst{31-16} = BD2;
1317  let Inst{15-12} = M4;
1318  let Inst{11}    = 0;
1319  let Inst{10}    = V3{4};
1320  let Inst{9-8}   = 0;
1321  let Inst{7-0}   = op{7-0};
1322}
1323
1324class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1325  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1326  field bits<48> Inst;
1327  field bits<48> SoftFail = 0;
1328
1329  bits<5> V1;
1330  bits<21> VBD2;
1331  bits<4> M3;
1332
1333  let Inst{47-40} = op{15-8};
1334  let Inst{39-36} = V1{3-0};
1335  let Inst{35-16} = VBD2{19-0};
1336  let Inst{15-12} = M3;
1337  let Inst{11}    = V1{4};
1338  let Inst{10}    = VBD2{20};
1339  let Inst{9-8}   = 0;
1340  let Inst{7-0}   = op{7-0};
1341}
1342
1343class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1344  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1345  field bits<48> Inst;
1346  field bits<48> SoftFail = 0;
1347
1348  bits<5> V1;
1349  bits<20> XBD2;
1350  bits<4> M3;
1351
1352  let Inst{47-40} = op{15-8};
1353  let Inst{39-36} = V1{3-0};
1354  let Inst{35-16} = XBD2;
1355  let Inst{15-12} = M3;
1356  let Inst{11}    = V1{4};
1357  let Inst{10-8}  = 0;
1358  let Inst{7-0}   = op{7-0};
1359}
1360
1361//===----------------------------------------------------------------------===//
1362// Instruction classes for .insn directives
1363//===----------------------------------------------------------------------===//
1364
1365class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
1366  : InstE<0, outs, ins, asmstr, pattern> {
1367  bits<16> enc;
1368
1369  let Inst = enc;
1370}
1371
1372class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1373  : InstRIa<0, outs, ins, asmstr, pattern> {
1374  bits<32> enc;
1375
1376  let Inst{31-24} = enc{31-24};
1377  let Inst{19-16} = enc{19-16};
1378}
1379
1380class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
1381  : InstRIEd<0, outs, ins, asmstr, pattern> {
1382  bits<48> enc;
1383
1384  let Inst{47-40} = enc{47-40};
1385  let Inst{7-0}   = enc{7-0};
1386}
1387
1388class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1389  : InstRILa<0, outs, ins, asmstr, pattern> {
1390  bits<48> enc;
1391  string type;
1392
1393  let Inst{47-40} = enc{47-40};
1394  let Inst{35-32} = enc{35-32};
1395}
1396
1397class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
1398  : InstRIS<0, outs, ins, asmstr, pattern> {
1399  bits<48> enc;
1400
1401  let Inst{47-40} = enc{47-40};
1402  let Inst{7-0}   = enc{7-0};
1403}
1404
1405class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1406  : InstRR<0, outs, ins, asmstr, pattern> {
1407  bits<16> enc;
1408
1409  let Inst{15-8} = enc{15-8};
1410}
1411
1412class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
1413  : InstRRE<0, outs, ins, asmstr, pattern> {
1414  bits<32> enc;
1415
1416  let Inst{31-16} = enc{31-16};
1417}
1418
1419class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
1420  : InstRRFa<0, outs, ins, asmstr, pattern> {
1421  bits<32> enc;
1422
1423  let Inst{31-16} = enc{31-16};
1424}
1425
1426class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1427  : InstRRS<0, outs, ins, asmstr, pattern> {
1428  bits<48> enc;
1429
1430  let Inst{47-40} = enc{47-40};
1431  let Inst{7-0}   = enc{7-0};
1432}
1433
1434class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1435  : InstRSa<0, outs, ins, asmstr, pattern> {
1436  bits<32> enc;
1437
1438  let Inst{31-24} = enc{31-24};
1439}
1440
1441// RSE is like RSY except with a 12 bit displacement (instead of 20).
1442class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1443  : InstRSYa<6, outs, ins, asmstr, pattern> {
1444  bits <48> enc;
1445
1446  let Inst{47-40} = enc{47-40};
1447  let Inst{31-16} = BD2{15-0};
1448  let Inst{15-8}  = 0;
1449  let Inst{7-0}   = enc{7-0};
1450}
1451
1452class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1453  : InstRSI<0, outs, ins, asmstr, pattern> {
1454  bits<32> enc;
1455
1456  let Inst{31-24} = enc{31-24};
1457}
1458
1459class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
1460  : InstRSYa<0, outs, ins, asmstr, pattern> {
1461  bits<48> enc;
1462
1463  let Inst{47-40} = enc{47-40};
1464  let Inst{7-0}   = enc{7-0};
1465}
1466
1467class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1468  : InstRXa<0, outs, ins, asmstr, pattern> {
1469  bits<32> enc;
1470
1471  let Inst{31-24} = enc{31-24};
1472}
1473
1474class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
1475  : InstRXE<0, outs, ins, asmstr, pattern> {
1476  bits<48> enc;
1477
1478  let M3 = 0;
1479
1480  let Inst{47-40} = enc{47-40};
1481  let Inst{7-0}   = enc{7-0};
1482}
1483
1484class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
1485  : InstRXF<0, outs, ins, asmstr, pattern> {
1486  bits<48> enc;
1487
1488  let Inst{47-40} = enc{47-40};
1489  let Inst{7-0}   = enc{7-0};
1490}
1491
1492class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
1493  : InstRXYa<0, outs, ins, asmstr, pattern> {
1494  bits<48> enc;
1495
1496  let Inst{47-40} = enc{47-40};
1497  let Inst{7-0}   = enc{7-0};
1498}
1499
1500class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
1501  : InstS<0, outs, ins, asmstr, pattern> {
1502  bits<32> enc;
1503
1504  let Inst{31-16} = enc{31-16};
1505}
1506
1507class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1508  : InstSI<0, outs, ins, asmstr, pattern> {
1509  bits<32> enc;
1510
1511  let Inst{31-24} = enc{31-24};
1512}
1513
1514class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
1515  : InstSIY<0, outs, ins, asmstr, pattern> {
1516  bits<48> enc;
1517
1518  let Inst{47-40} = enc{47-40};
1519  let Inst{7-0}   = enc{7-0};
1520}
1521
1522class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1523  : InstSIL<0, outs, ins, asmstr, pattern> {
1524  bits<48> enc;
1525
1526  let Inst{47-32} = enc{47-32};
1527}
1528
1529class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
1530  : InstSSd<0, outs, ins, asmstr, pattern> {
1531  bits<48> enc;
1532
1533  let Inst{47-40} = enc{47-40};
1534}
1535
1536class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1537  : InstSSE<0, outs, ins, asmstr, pattern> {
1538  bits<48> enc;
1539
1540  let Inst{47-32} = enc{47-32};
1541}
1542
1543class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
1544  : InstSSF<0, outs, ins, asmstr, pattern> {
1545  bits<48> enc;
1546
1547  let Inst{47-40} = enc{47-40};
1548  let Inst{35-32} = enc{35-32};
1549}
1550
1551//===----------------------------------------------------------------------===//
1552// Variants of instructions with condition mask
1553//===----------------------------------------------------------------------===//
1554//
1555// For instructions using a condition mask (e.g. conditional branches,
1556// compare-and-branch instructions, or conditional move instructions),
1557// we generally need to create multiple instruction patterns:
1558//
1559// - One used for code generation, which encodes the condition mask as an
1560//   MI operand, but writes out an extended mnemonic for better readability.
1561// - One pattern for the base form of the instruction with an explicit
1562//   condition mask (encoded as a plain integer MI operand).
1563// - Specific patterns for each extended mnemonic, where the condition mask
1564//   is implied by the pattern name and not otherwise encoded at all.
1565//
1566// We need the latter primarily for the assembler and disassembler, since the
1567// assembler parser is not able to decode part of an instruction mnemonic
1568// into an operand.  Thus we provide separate patterns for each mnemonic.
1569//
1570// Note that in some cases there are two different mnemonics for the same
1571// condition mask.  In this case we cannot have both instructions available
1572// to the disassembler at the same time since the encodings are not distinct.
1573// Therefore the alternate forms are marked isAsmParserOnly.
1574//
1575// We don't make one of the two names an alias of the other because
1576// we need the custom parsing routines to select the correct register class.
1577//
1578// This section provides helpers for generating the specific forms.
1579//
1580//===----------------------------------------------------------------------===//
1581
1582// A class to describe a variant of an instruction with condition mask.
1583class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
1584  // The fixed condition mask to use.
1585  bits<4> ccmask = ccmaskin;
1586
1587  // The suffix to use for the extended assembler mnemonic.
1588  string suffix = suffixin;
1589
1590  // Whether this is an alternate that needs to be marked isAsmParserOnly.
1591  bit alternate = alternatein;
1592}
1593
1594// Condition mask 15 means "always true", which is used to define
1595// unconditional branches as a variant of conditional branches.
1596def CondAlways : CondVariant<15, "", 0>;
1597
1598// Condition masks for general instructions that can set all 4 bits.
1599def CondVariantO   : CondVariant<1,  "o",   0>;
1600def CondVariantH   : CondVariant<2,  "h",   0>;
1601def CondVariantP   : CondVariant<2,  "p",   1>;
1602def CondVariantNLE : CondVariant<3,  "nle", 0>;
1603def CondVariantL   : CondVariant<4,  "l",   0>;
1604def CondVariantM   : CondVariant<4,  "m",   1>;
1605def CondVariantNHE : CondVariant<5,  "nhe", 0>;
1606def CondVariantLH  : CondVariant<6,  "lh",  0>;
1607def CondVariantNE  : CondVariant<7,  "ne",  0>;
1608def CondVariantNZ  : CondVariant<7,  "nz",  1>;
1609def CondVariantE   : CondVariant<8,  "e",   0>;
1610def CondVariantZ   : CondVariant<8,  "z",   1>;
1611def CondVariantNLH : CondVariant<9,  "nlh", 0>;
1612def CondVariantHE  : CondVariant<10, "he",  0>;
1613def CondVariantNL  : CondVariant<11, "nl",  0>;
1614def CondVariantNM  : CondVariant<11, "nm",  1>;
1615def CondVariantLE  : CondVariant<12, "le",  0>;
1616def CondVariantNH  : CondVariant<13, "nh",  0>;
1617def CondVariantNP  : CondVariant<13, "np",  1>;
1618def CondVariantNO  : CondVariant<14, "no",  0>;
1619
1620// A helper class to look up one of the above by name.
1621class CV<string name>
1622  : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
1623                !cast<CondVariant>("CondVariant"#name).suffix,
1624                !cast<CondVariant>("CondVariant"#name).alternate>;
1625
1626// Condition masks for integer instructions (e.g. compare-and-branch).
1627// This is like the list above, except that condition 3 is not possible
1628// and that the low bit of the mask is therefore always 0.  This means
1629// that each condition has two names.  Conditions "o" and "no" are not used.
1630def IntCondVariantH   : CondVariant<2,  "h",   0>;
1631def IntCondVariantNLE : CondVariant<2,  "nle", 1>;
1632def IntCondVariantL   : CondVariant<4,  "l",   0>;
1633def IntCondVariantNHE : CondVariant<4,  "nhe", 1>;
1634def IntCondVariantLH  : CondVariant<6,  "lh",  0>;
1635def IntCondVariantNE  : CondVariant<6,  "ne",  1>;
1636def IntCondVariantE   : CondVariant<8,  "e",   0>;
1637def IntCondVariantNLH : CondVariant<8,  "nlh", 1>;
1638def IntCondVariantHE  : CondVariant<10, "he",  0>;
1639def IntCondVariantNL  : CondVariant<10, "nl",  1>;
1640def IntCondVariantLE  : CondVariant<12, "le",  0>;
1641def IntCondVariantNH  : CondVariant<12, "nh",  1>;
1642
1643// A helper class to look up one of the above by name.
1644class ICV<string name>
1645  : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
1646                !cast<CondVariant>("IntCondVariant"#name).suffix,
1647                !cast<CondVariant>("IntCondVariant"#name).alternate>;
1648
1649//===----------------------------------------------------------------------===//
1650// Instruction definitions with semantics
1651//===----------------------------------------------------------------------===//
1652//
1653// These classes have the form [Cond]<Category><Format>, where <Format> is one
1654// of the formats defined above and where <Category> describes the inputs
1655// and outputs.  "Cond" is used if the instruction is conditional,
1656// in which case the 4-bit condition-code mask is added as a final operand.
1657// <Category> can be one of:
1658//
1659//   Inherent:
1660//     One register output operand and no input operands.
1661//
1662//   InherentDual:
1663//     Two register output operands and no input operands.
1664//
1665//   StoreInherent:
1666//     One address operand.  The instruction stores to the address.
1667//
1668//   SideEffectInherent:
1669//     No input or output operands, but causes some side effect.
1670//
1671//   Branch:
1672//     One branch target.  The instruction branches to the target.
1673//
1674//   Call:
1675//     One output operand and one branch target.  The instruction stores
1676//     the return address to the output operand and branches to the target.
1677//
1678//   CmpBranch:
1679//     Two input operands and one optional branch target.  The instruction
1680//     compares the two input operands and branches or traps on the result.
1681//
1682//   BranchUnary:
1683//     One register output operand, one register input operand and one branch
1684//     target.  The instructions stores a modified form of the source register
1685//     in the destination register and branches on the result.
1686//
1687//   BranchBinary:
1688//     One register output operand, two register input operands and one branch
1689//     target. The instructions stores a modified form of one of the source
1690//     registers in the destination register and branches on the result.
1691//
1692//   LoadMultiple:
1693//     One address input operand and two explicit output operands.
1694//     The instruction loads a range of registers from the address,
1695//     with the explicit operands giving the first and last register
1696//     to load.  Other loaded registers are added as implicit definitions.
1697//
1698//   StoreMultiple:
1699//     Two explicit input register operands and an address operand.
1700//     The instruction stores a range of registers to the address,
1701//     with the explicit operands giving the first and last register
1702//     to store.  Other stored registers are added as implicit uses.
1703//
1704//   StoreLength:
1705//     One value operand, one length operand and one address operand.
1706//     The instruction stores the value operand to the address but
1707//     doesn't write more than the number of bytes specified by the
1708//     length operand.
1709//
1710//   LoadAddress:
1711//     One register output operand and one address operand.
1712//
1713//   SideEffectAddress:
1714//     One address operand.  No output operands, but causes some side effect.
1715//
1716//   Unary:
1717//     One register output operand and one input operand.
1718//
1719//   Store:
1720//     One address operand and one other input operand.  The instruction
1721//     stores to the address.
1722//
1723//   SideEffectUnary:
1724//     One input operand.  No output operands, but causes some side effect.
1725//
1726//   Binary:
1727//     One register output operand and two input operands.
1728//
1729//   StoreBinary:
1730//     One address operand and two other input operands.  The instruction
1731//     stores to the address.
1732//
1733//   SideEffectBinary:
1734//     Two input operands.  No output operands, but causes some side effect.
1735//
1736//   Compare:
1737//     Two input operands and an implicit CC output operand.
1738//
1739//   Test:
1740//     One or two input operands and an implicit CC output operand.  If
1741//     present, the second input operand is an "address" operand used as
1742//     a test class mask.
1743//
1744//   Ternary:
1745//     One register output operand and three input operands.
1746//
1747//   SideEffectTernary:
1748//     Three input operands.  No output operands, but causes some side effect.
1749//
1750//   Quaternary:
1751//     One register output operand and four input operands.
1752//
1753//   LoadAndOp:
1754//     One output operand and two input operands, one of which is an address.
1755//     The instruction both reads from and writes to the address.
1756//
1757//   CmpSwap:
1758//     One output operand and three input operands, one of which is an address.
1759//     The instruction both reads from and writes to the address.
1760//
1761//   RotateSelect:
1762//     One output operand and five input operands.  The first two operands
1763//     are registers and the other three are immediates.
1764//
1765//   Prefetch:
1766//     One 4-bit immediate operand and one address operand.  The immediate
1767//     operand is 1 for a load prefetch and 2 for a store prefetch.
1768//
1769//   BranchPreload:
1770//     One 4-bit immediate operand and two address operands.
1771//
1772// The format determines which input operands are tied to output operands,
1773// and also determines the shape of any address operand.
1774//
1775// Multiclasses of the form <Category><Format>Pair define two instructions,
1776// one with <Category><Format> and one with <Category><Format>Y.  The name
1777// of the first instruction has no suffix, the name of the second has
1778// an extra "y".
1779//
1780//===----------------------------------------------------------------------===//
1781
1782class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1783                  SDPatternOperator operator>
1784  : InstRRE<opcode, (outs cls:$R1), (ins),
1785            mnemonic#"\t$R1",
1786            [(set cls:$R1, (operator))]> {
1787  let R2 = 0;
1788}
1789
1790class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
1791  : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
1792            mnemonic#"\t$R1, $R2", []>;
1793
1794class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1795  : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1796  let I2 = value;
1797  let M3 = 0;
1798}
1799
1800class StoreInherentS<string mnemonic, bits<16> opcode,
1801                     SDPatternOperator operator, bits<5> bytes>
1802  : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
1803          mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
1804  let mayStore = 1;
1805  let AccessBytes = bytes;
1806}
1807
1808class SideEffectInherentE<string mnemonic, bits<16>opcode>
1809  : InstE<opcode, (outs), (ins), mnemonic, []>;
1810
1811class SideEffectInherentS<string mnemonic, bits<16> opcode,
1812                          SDPatternOperator operator>
1813  : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
1814  let BD2 = 0;
1815}
1816
1817class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
1818  : InstRRE<opcode, (outs), (ins), mnemonic, []> {
1819  let R1 = 0;
1820  let R2 = 0;
1821}
1822
1823// Allow an optional TLS marker symbol to generate TLS call relocations.
1824class CallRI<string mnemonic, bits<12> opcode>
1825  : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
1826            mnemonic#"\t$R1, $RI2", []>;
1827
1828// Allow an optional TLS marker symbol to generate TLS call relocations.
1829class CallRIL<string mnemonic, bits<12> opcode>
1830  : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
1831             mnemonic#"\t$R1, $RI2", []>;
1832
1833class CallRR<string mnemonic, bits<8> opcode>
1834  : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
1835           mnemonic#"\t$R1, $R2", []>;
1836
1837class CallRX<string mnemonic, bits<8> opcode>
1838  : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
1839            mnemonic#"\t$R1, $XBD2", []>;
1840
1841class CondBranchRI<string mnemonic, bits<12> opcode,
1842                   SDPatternOperator operator = null_frag>
1843  : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
1844            !subst("#", "${M1}", mnemonic)#"\t$RI2",
1845            [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
1846  let CCMaskFirst = 1;
1847}
1848
1849class AsmCondBranchRI<string mnemonic, bits<12> opcode>
1850  : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
1851            mnemonic#"\t$M1, $RI2", []>;
1852
1853class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
1854                        SDPatternOperator operator = null_frag>
1855  : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
1856            !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
1857  let isAsmParserOnly = V.alternate;
1858  let M1 = V.ccmask;
1859}
1860
1861class CondBranchRIL<string mnemonic, bits<12> opcode>
1862  : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
1863             !subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
1864  let CCMaskFirst = 1;
1865}
1866
1867class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
1868  : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
1869             mnemonic#"\t$M1, $RI2", []>;
1870
1871class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
1872  : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
1873             !subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
1874  let isAsmParserOnly = V.alternate;
1875  let M1 = V.ccmask;
1876}
1877
1878class CondBranchRR<string mnemonic, bits<8> opcode>
1879  : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
1880           !subst("#", "${R1}", mnemonic)#"\t$R2", []> {
1881  let CCMaskFirst = 1;
1882}
1883
1884class AsmCondBranchRR<string mnemonic, bits<8> opcode>
1885  : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
1886           mnemonic#"\t$R1, $R2", []>;
1887
1888class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
1889                      SDPatternOperator operator = null_frag>
1890  : InstRR<opcode, (outs), (ins ADDR64:$R2),
1891           !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
1892  let isAsmParserOnly = V.alternate;
1893  let R1 = V.ccmask;
1894}
1895
1896class CondBranchRX<string mnemonic, bits<8> opcode>
1897  : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
1898            !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
1899  let CCMaskFirst = 1;
1900}
1901
1902class AsmCondBranchRX<string mnemonic, bits<8> opcode>
1903  : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
1904            mnemonic#"\t$M1, $XBD2", []>;
1905
1906class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
1907  : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
1908            !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
1909  let isAsmParserOnly = V.alternate;
1910  let M1 = V.ccmask;
1911}
1912
1913class CmpBranchRIEa<string mnemonic, bits<16> opcode,
1914                    RegisterOperand cls, Immediate imm>
1915  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
1916             mnemonic#"$M3\t$R1, $I2", []>;
1917
1918class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
1919                       RegisterOperand cls, Immediate imm>
1920  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
1921             mnemonic#"\t$R1, $I2, $M3", []>;
1922
1923class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
1924                          RegisterOperand cls, Immediate imm>
1925  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
1926             mnemonic#V.suffix#"\t$R1, $I2", []> {
1927  let isAsmParserOnly = V.alternate;
1928  let M3 = V.ccmask;
1929}
1930
1931multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
1932                             RegisterOperand cls, Immediate imm> {
1933  let isCodeGenOnly = 1 in
1934    def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
1935  def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
1936}
1937
1938class CmpBranchRIEb<string mnemonic, bits<16> opcode,
1939                    RegisterOperand cls>
1940  : InstRIEb<opcode, (outs),
1941             (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
1942             mnemonic#"$M3\t$R1, $R2, $RI4", []>;
1943
1944class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
1945                       RegisterOperand cls>
1946  : InstRIEb<opcode, (outs),
1947             (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
1948             mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
1949
1950class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
1951                         RegisterOperand cls>
1952  : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
1953             mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
1954  let isAsmParserOnly = V.alternate;
1955  let M3 = V.ccmask;
1956}
1957
1958multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
1959                             RegisterOperand cls> {
1960  let isCodeGenOnly = 1 in
1961    def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
1962  def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
1963}
1964
1965class CmpBranchRIEc<string mnemonic, bits<16> opcode,
1966                    RegisterOperand cls, Immediate imm>
1967  : InstRIEc<opcode, (outs),
1968             (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
1969             mnemonic#"$M3\t$R1, $I2, $RI4", []>;
1970
1971class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
1972                       RegisterOperand cls, Immediate imm>
1973  : InstRIEc<opcode, (outs),
1974             (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
1975             mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
1976
1977class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
1978                         RegisterOperand cls, Immediate imm>
1979  : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
1980             mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
1981  let isAsmParserOnly = V.alternate;
1982  let M3 = V.ccmask;
1983}
1984
1985multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
1986                            RegisterOperand cls, Immediate imm> {
1987  let isCodeGenOnly = 1 in
1988    def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
1989  def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
1990}
1991
1992class CmpBranchRRFc<string mnemonic, bits<16> opcode,
1993                    RegisterOperand cls>
1994  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
1995             mnemonic#"$M3\t$R1, $R2", []>;
1996
1997class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
1998                       RegisterOperand cls>
1999  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2000             mnemonic#"\t$R1, $R2, $M3", []>;
2001
2002multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
2003                             RegisterOperand cls> {
2004  let isCodeGenOnly = 1 in
2005    def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2006  def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2007}
2008
2009class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
2010                          RegisterOperand cls>
2011  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2012             mnemonic#V.suffix#"\t$R1, $R2", []> {
2013  let isAsmParserOnly = V.alternate;
2014  let M3 = V.ccmask;
2015}
2016
2017class CmpBranchRRS<string mnemonic, bits<16> opcode,
2018                   RegisterOperand cls>
2019  : InstRRS<opcode, (outs),
2020            (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
2021            mnemonic#"$M3\t$R1, $R2, $BD4", []>;
2022
2023class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
2024                      RegisterOperand cls>
2025  : InstRRS<opcode, (outs),
2026            (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
2027            mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
2028
2029class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
2030                        RegisterOperand cls>
2031  : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
2032            mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
2033  let isAsmParserOnly = V.alternate;
2034  let M3 = V.ccmask;
2035}
2036
2037multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
2038                            RegisterOperand cls> {
2039  let isCodeGenOnly = 1 in
2040    def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2041  def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2042}
2043
2044class CmpBranchRIS<string mnemonic, bits<16> opcode,
2045                   RegisterOperand cls, Immediate imm>
2046  : InstRIS<opcode, (outs),
2047            (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
2048            mnemonic#"$M3\t$R1, $I2, $BD4", []>;
2049
2050class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
2051                      RegisterOperand cls, Immediate imm>
2052  : InstRIS<opcode, (outs),
2053            (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
2054            mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
2055
2056class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
2057                        RegisterOperand cls, Immediate imm>
2058  : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
2059            mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
2060  let isAsmParserOnly = V.alternate;
2061  let M3 = V.ccmask;
2062}
2063
2064multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
2065                            RegisterOperand cls, Immediate imm> {
2066  let isCodeGenOnly = 1 in
2067    def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2068  def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2069}
2070
2071class CmpBranchRSYb<string mnemonic, bits<16> opcode,
2072                    RegisterOperand cls>
2073  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
2074             mnemonic#"$M3\t$R1, $BD2", []>;
2075
2076class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
2077                       RegisterOperand cls>
2078  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
2079             mnemonic#"\t$R1, $M3, $BD2", []>;
2080
2081multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
2082                             RegisterOperand cls> {
2083  let isCodeGenOnly = 1 in
2084    def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2085  def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2086}
2087
2088class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
2089                          RegisterOperand cls>
2090  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
2091             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2092  let isAsmParserOnly = V.alternate;
2093  let M3 = V.ccmask;
2094}
2095
2096class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2097  : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
2098            mnemonic##"\t$R1, $RI2", []> {
2099  let Constraints = "$R1 = $R1src";
2100  let DisableEncoding = "$R1src";
2101}
2102
2103class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2104  : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
2105             mnemonic##"\t$R1, $RI2", []> {
2106  let Constraints = "$R1 = $R1src";
2107  let DisableEncoding = "$R1src";
2108}
2109
2110class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2111  : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2112           mnemonic##"\t$R1, $R2", []> {
2113  let Constraints = "$R1 = $R1src";
2114  let DisableEncoding = "$R1src";
2115}
2116
2117class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2118  : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2119            mnemonic##"\t$R1, $R2", []> {
2120  let Constraints = "$R1 = $R1src";
2121  let DisableEncoding = "$R1src";
2122}
2123
2124class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2125  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2126            mnemonic##"\t$R1, $XBD2", []> {
2127  let Constraints = "$R1 = $R1src";
2128  let DisableEncoding = "$R1src";
2129}
2130
2131class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2132  : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
2133             mnemonic##"\t$R1, $XBD2", []> {
2134  let Constraints = "$R1 = $R1src";
2135  let DisableEncoding = "$R1src";
2136}
2137
2138class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2139  : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2140            mnemonic##"\t$R1, $R3, $RI2", []> {
2141  let Constraints = "$R1 = $R1src";
2142  let DisableEncoding = "$R1src";
2143}
2144
2145class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2146  : InstRIEe<opcode, (outs cls:$R1),
2147             (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2148             mnemonic##"\t$R1, $R3, $RI2", []> {
2149  let Constraints = "$R1 = $R1src";
2150  let DisableEncoding = "$R1src";
2151}
2152
2153class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2154  : InstRSa<opcode, (outs cls:$R1),
2155            (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
2156            mnemonic##"\t$R1, $R3, $BD2", []> {
2157  let Constraints = "$R1 = $R1src";
2158  let DisableEncoding = "$R1src";
2159}
2160
2161class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2162  : InstRSYa<opcode,
2163             (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
2164             mnemonic##"\t$R1, $R3, $BD2", []> {
2165  let Constraints = "$R1 = $R1src";
2166  let DisableEncoding = "$R1src";
2167}
2168
2169class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2170                     AddressingMode mode = bdaddr12only>
2171  : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2172            mnemonic#"\t$R1, $R3, $BD2", []> {
2173  let mayLoad = 1;
2174}
2175
2176class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2177                      AddressingMode mode = bdaddr20only>
2178  : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2179             mnemonic#"\t$R1, $R3, $BD2", []> {
2180  let mayLoad = 1;
2181}
2182
2183multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2184                              bits<16> rsyOpcode, RegisterOperand cls> {
2185  let DispKey = mnemonic ## #cls in {
2186    let DispSize = "12" in
2187      def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2188    let DispSize = "20" in
2189      def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2190  }
2191}
2192
2193class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2194  : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2195            (ins bdaddr12only:$BD2, bdaddr12only:$BD4),
2196            mnemonic#"\t$R1, $R3, $BD2, $BD4", []> {
2197  let mayLoad = 1;
2198}
2199
2200class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
2201  : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
2202             mnemonic#"\t$V1, $V3, $BD2", []> {
2203  let M4 = 0;
2204  let mayLoad = 1;
2205}
2206
2207class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2208                 RegisterOperand cls>
2209  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2210             mnemonic#"\t$R1, $RI2",
2211             [(operator cls:$R1, pcrel32:$RI2)]> {
2212  let mayStore = 1;
2213  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2214  // However, BDXs have two extra operands and are therefore 6 units more
2215  // complex.
2216  let AddedComplexity = 7;
2217}
2218
2219class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2220              RegisterOperand cls, bits<5> bytes,
2221              AddressingMode mode = bdxaddr12only>
2222  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2223            mnemonic#"\t$R1, $XBD2",
2224            [(operator cls:$R1, mode:$XBD2)]> {
2225  let OpKey = mnemonic#"r"#cls;
2226  let OpType = "mem";
2227  let mayStore = 1;
2228  let AccessBytes = bytes;
2229}
2230
2231class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2232               RegisterOperand cls, bits<5> bytes,
2233               AddressingMode mode = bdxaddr20only>
2234  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2235             mnemonic#"\t$R1, $XBD2",
2236             [(operator cls:$R1, mode:$XBD2)]> {
2237  let OpKey = mnemonic#"r"#cls;
2238  let OpType = "mem";
2239  let mayStore = 1;
2240  let AccessBytes = bytes;
2241}
2242
2243multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2244                       SDPatternOperator operator, RegisterOperand cls,
2245                       bits<5> bytes> {
2246  let DispKey = mnemonic ## #cls in {
2247    let DispSize = "12" in
2248      def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2249    let DispSize = "20" in
2250      def Y  : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2251                        bdxaddr20pair>;
2252  }
2253}
2254
2255class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2256               TypedReg tr, bits<5> bytes, bits<4> type = 0>
2257  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
2258            mnemonic#"\t$V1, $XBD2",
2259            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2260  let M3 = type;
2261  let mayStore = 1;
2262  let AccessBytes = bytes;
2263}
2264
2265class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2266                      SDPatternOperator operator, bits<5> bytes>
2267  : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2268             mnemonic#"\t$V1, $R3, $BD2",
2269             [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2270  let M4 = 0;
2271  let mayStore = 1;
2272  let AccessBytes = bytes;
2273}
2274
2275class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2276                      AddressingMode mode = bdaddr12only>
2277  : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2278            mnemonic#"\t$R1, $R3, $BD2", []> {
2279  let mayStore = 1;
2280}
2281
2282class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2283                       AddressingMode mode = bdaddr20only>
2284  : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2285             mnemonic#"\t$R1, $R3, $BD2", []> {
2286  let mayStore = 1;
2287}
2288
2289multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2290                               bits<16> rsyOpcode, RegisterOperand cls> {
2291  let DispKey = mnemonic ## #cls in {
2292    let DispSize = "12" in
2293      def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2294    let DispSize = "20" in
2295      def Y  : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2296  }
2297}
2298
2299class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
2300  : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
2301             mnemonic#"\t$V1, $V3, $BD2", []> {
2302  let M4 = 0;
2303  let mayStore = 1;
2304}
2305
2306// StoreSI* instructions are used to store an integer to memory, but the
2307// addresses are more restricted than for normal stores.  If we are in the
2308// situation of having to force either the address into a register or the
2309// constant into a register, it's usually better to do the latter.
2310// We therefore match the address in the same way as a normal store and
2311// only use the StoreSI* instruction if the matched address is suitable.
2312class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2313              Immediate imm>
2314  : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2315           mnemonic#"\t$BD1, $I2",
2316           [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2317  let mayStore = 1;
2318}
2319
2320class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2321               Immediate imm>
2322  : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
2323            mnemonic#"\t$BD1, $I2",
2324            [(operator imm:$I2, mviaddr20pair:$BD1)]> {
2325  let mayStore = 1;
2326}
2327
2328class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2329               Immediate imm>
2330  : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2331            mnemonic#"\t$BD1, $I2",
2332            [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2333  let mayStore = 1;
2334}
2335
2336multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2337                       SDPatternOperator operator, Immediate imm> {
2338  let DispKey = mnemonic in {
2339    let DispSize = "12" in
2340      def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
2341    let DispSize = "20" in
2342      def Y  : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
2343  }
2344}
2345
2346class StoreSSE<string mnemonic, bits<16> opcode>
2347  : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2348            mnemonic#"\t$BD1, $BD2", []> {
2349  let mayStore = 1;
2350}
2351
2352class CondStoreRSY<string mnemonic, bits<16> opcode,
2353                   RegisterOperand cls, bits<5> bytes,
2354                   AddressingMode mode = bdaddr20only>
2355  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
2356            mnemonic#"$M3\t$R1, $BD2", []> {
2357  let mayStore = 1;
2358  let AccessBytes = bytes;
2359  let CCMaskLast = 1;
2360}
2361
2362// Like CondStoreRSY, but used for the raw assembly form.  The condition-code
2363// mask is the third operand rather than being part of the mnemonic.
2364class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2365                      RegisterOperand cls, bits<5> bytes,
2366                      AddressingMode mode = bdaddr20only>
2367  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
2368             mnemonic#"\t$R1, $BD2, $M3", []> {
2369  let mayStore = 1;
2370  let AccessBytes = bytes;
2371}
2372
2373// Like CondStoreRSY, but with a fixed CC mask.
2374class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2375                        RegisterOperand cls, bits<5> bytes,
2376                        AddressingMode mode = bdaddr20only>
2377  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
2378             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2379  let mayStore = 1;
2380  let AccessBytes = bytes;
2381  let isAsmParserOnly = V.alternate;
2382  let M3 = V.ccmask;
2383}
2384
2385multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2386                            RegisterOperand cls, bits<5> bytes,
2387                            AddressingMode mode = bdaddr20only> {
2388  let isCodeGenOnly = 1 in
2389    def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2390  def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2391}
2392
2393class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
2394  : InstI<opcode, (outs), (ins imm:$I1),
2395          mnemonic#"\t$I1", []>;
2396
2397class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2398  : InstRR<opcode, (outs), (ins cls:$R1),
2399           mnemonic#"\t$R1", []> {
2400  let R2 = 0;
2401}
2402
2403class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2404                         SDPatternOperator operator>
2405  : InstRRE<opcode, (outs), (ins cls:$R1),
2406            mnemonic#"\t$R1", [(operator cls:$R1)]> {
2407  let R2 = 0;
2408}
2409
2410class SideEffectUnaryS<string mnemonic, bits<16> opcode,
2411                       SDPatternOperator operator, bits<5> bytes,
2412                       AddressingMode mode = bdaddr12only>
2413  : InstS<opcode, (outs), (ins mode:$BD2),
2414          mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
2415  let mayLoad = 1;
2416  let AccessBytes = bytes;
2417}
2418
2419class SideEffectAddressS<string mnemonic, bits<16> opcode,
2420                        SDPatternOperator operator,
2421                        AddressingMode mode = bdaddr12only>
2422  : InstS<opcode, (outs), (ins mode:$BD2),
2423          mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
2424
2425class LoadAddressRX<string mnemonic, bits<8> opcode,
2426                    SDPatternOperator operator, AddressingMode mode>
2427  : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2428            mnemonic#"\t$R1, $XBD2",
2429            [(set GR64:$R1, (operator mode:$XBD2))]>;
2430
2431class LoadAddressRXY<string mnemonic, bits<16> opcode,
2432                     SDPatternOperator operator, AddressingMode mode>
2433  : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2434             mnemonic#"\t$R1, $XBD2",
2435             [(set GR64:$R1, (operator mode:$XBD2))]>;
2436
2437multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
2438                             bits<16> rxyOpcode, SDPatternOperator operator> {
2439  let DispKey = mnemonic in {
2440    let DispSize = "12" in
2441      def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
2442    let DispSize = "20" in
2443      def Y  : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>;
2444  }
2445}
2446
2447class LoadAddressRIL<string mnemonic, bits<12> opcode,
2448                     SDPatternOperator operator>
2449  : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
2450             mnemonic#"\t$R1, $RI2",
2451             [(set GR64:$R1, (operator pcrel32:$RI2))]>;
2452
2453class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2454              RegisterOperand cls1, RegisterOperand cls2>
2455  : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
2456           mnemonic#"\t$R1, $R2",
2457           [(set cls1:$R1, (operator cls2:$R2))]> {
2458  let OpKey = mnemonic#cls1;
2459  let OpType = "reg";
2460}
2461
2462class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2463               RegisterOperand cls1, RegisterOperand cls2>
2464  : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
2465            mnemonic#"\t$R1, $R2",
2466            [(set cls1:$R1, (operator cls2:$R2))]> {
2467  let OpKey = mnemonic#cls1;
2468  let OpType = "reg";
2469}
2470
2471class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2472  : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
2473            mnemonic#"\t$R1", []> {
2474  let Constraints = "$R1 = $R1src";
2475  let DisableEncoding = "$R1src";
2476  let R2 = 0;
2477}
2478
2479class UnaryMemRRFc<string mnemonic, bits<16> opcode,
2480                   RegisterOperand cls1, RegisterOperand cls2>
2481  : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
2482            mnemonic#"\t$R1, $R2", []> {
2483  let Constraints = "$R1 = $R1src";
2484  let DisableEncoding = "$R1src";
2485  let M3 = 0;
2486}
2487
2488class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2489              RegisterOperand cls, Immediate imm>
2490  : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2491            mnemonic#"\t$R1, $I2",
2492            [(set cls:$R1, (operator imm:$I2))]>;
2493
2494class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2495               RegisterOperand cls, Immediate imm>
2496  : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2497             mnemonic#"\t$R1, $I2",
2498             [(set cls:$R1, (operator imm:$I2))]>;
2499
2500class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2501                 RegisterOperand cls>
2502  : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
2503             mnemonic#"\t$R1, $RI2",
2504             [(set cls:$R1, (operator pcrel32:$RI2))]> {
2505  let mayLoad = 1;
2506  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2507  // However, BDXs have two extra operands and are therefore 6 units more
2508  // complex.
2509  let AddedComplexity = 7;
2510}
2511
2512class CondUnaryRSY<string mnemonic, bits<16> opcode,
2513                   SDPatternOperator operator, RegisterOperand cls,
2514                   bits<5> bytes, AddressingMode mode = bdaddr20only>
2515  : InstRSYb<opcode, (outs cls:$R1),
2516             (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
2517             mnemonic#"$M3\t$R1, $BD2",
2518             [(set cls:$R1,
2519                   (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
2520                                    cond4:$valid, cond4:$M3))]> {
2521  let Constraints = "$R1 = $R1src";
2522  let DisableEncoding = "$R1src";
2523  let mayLoad = 1;
2524  let AccessBytes = bytes;
2525  let CCMaskLast = 1;
2526}
2527
2528// Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
2529// mask is the third operand rather than being part of the mnemonic.
2530class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
2531                      RegisterOperand cls, bits<5> bytes,
2532                      AddressingMode mode = bdaddr20only>
2533  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
2534             mnemonic#"\t$R1, $BD2, $M3", []> {
2535  let mayLoad = 1;
2536  let AccessBytes = bytes;
2537  let Constraints = "$R1 = $R1src";
2538  let DisableEncoding = "$R1src";
2539}
2540
2541// Like CondUnaryRSY, but with a fixed CC mask.
2542class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
2543                        RegisterOperand cls, bits<5> bytes,
2544                        AddressingMode mode = bdaddr20only>
2545  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
2546             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2547  let Constraints = "$R1 = $R1src";
2548  let DisableEncoding = "$R1src";
2549  let mayLoad = 1;
2550  let AccessBytes = bytes;
2551  let isAsmParserOnly = V.alternate;
2552  let M3 = V.ccmask;
2553}
2554
2555multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
2556                            SDPatternOperator operator,
2557                            RegisterOperand cls, bits<5> bytes,
2558                            AddressingMode mode = bdaddr20only> {
2559  let isCodeGenOnly = 1 in
2560    def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2561  def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2562}
2563
2564
2565class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2566              RegisterOperand cls, bits<5> bytes,
2567              AddressingMode mode = bdxaddr12only>
2568  : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2569            mnemonic#"\t$R1, $XBD2",
2570            [(set cls:$R1, (operator mode:$XBD2))]> {
2571  let OpKey = mnemonic#"r"#cls;
2572  let OpType = "mem";
2573  let mayLoad = 1;
2574  let AccessBytes = bytes;
2575}
2576
2577class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2578               RegisterOperand cls, bits<5> bytes>
2579  : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
2580            mnemonic#"\t$R1, $XBD2",
2581            [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
2582  let OpKey = mnemonic#"r"#cls;
2583  let OpType = "mem";
2584  let mayLoad = 1;
2585  let AccessBytes = bytes;
2586  let M3 = 0;
2587}
2588
2589class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2590               RegisterOperand cls, bits<5> bytes,
2591               AddressingMode mode = bdxaddr20only>
2592  : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2593             mnemonic#"\t$R1, $XBD2",
2594             [(set cls:$R1, (operator mode:$XBD2))]> {
2595  let OpKey = mnemonic#"r"#cls;
2596  let OpType = "mem";
2597  let mayLoad = 1;
2598  let AccessBytes = bytes;
2599}
2600
2601multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2602                       SDPatternOperator operator, RegisterOperand cls,
2603                       bits<5> bytes> {
2604  let DispKey = mnemonic ## #cls in {
2605    let DispSize = "12" in
2606      def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2607    let DispSize = "20" in
2608      def Y  : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2609                        bdxaddr20pair>;
2610  }
2611}
2612
2613class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2614                TypedReg tr, Immediate imm, bits<4> type = 0>
2615  : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
2616             mnemonic#"\t$V1, $I2",
2617             [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
2618  let M3 = type;
2619}
2620
2621class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, Immediate imm>
2622  : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
2623             mnemonic#"\t$V1, $I2, $M3", []>;
2624
2625class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2626                TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
2627                bits<4> m5 = 0>
2628  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
2629             mnemonic#"\t$V1, $V2",
2630             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
2631  let M3 = type;
2632  let M4 = m4;
2633  let M5 = m5;
2634}
2635
2636class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
2637                       bits<4> m5 = 0>
2638  : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
2639             mnemonic#"\t$V1, $V2, $M3", []> {
2640  let M4 = m4;
2641  let M5 = m5;
2642}
2643
2644class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
2645  : InstVRRa<opcode, (outs VR128:$V1),
2646             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
2647             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
2648  let M5 = m5;
2649}
2650
2651// Declare a pair of instructions, one which sets CC and one which doesn't.
2652// The CC-setting form ends with "S" and sets the low bit of M5.
2653// The form that does not set CC has an extra operand to optionally allow
2654// specifying arbitrary M5 values in assembler.
2655multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
2656                               SDPatternOperator operator,
2657                               SDPatternOperator operator_cc,
2658                               TypedReg tr1, TypedReg tr2, bits<4> type> {
2659  let M3 = type, M4 = 0 in
2660    def "" : InstVRRa<opcode, (outs tr1.op:$V1),
2661                      (ins tr2.op:$V2, imm32zx4:$M5),
2662                      mnemonic#"\t$V1, $V2, $M5", []>;
2663  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
2664            (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
2665  def : InstAlias<mnemonic#"\t$V1, $V2",
2666                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
2667  let Defs = [CC] in
2668    def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
2669                      type, 0, 1>;
2670}
2671
2672multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
2673  let M4 = 0 in
2674    def "" : InstVRRa<opcode, (outs VR128:$V1),
2675                     (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
2676                     mnemonic#"\t$V1, $V2, $M3, $M5", []>;
2677  def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
2678                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
2679                                            imm32zx4:$M3, 0)>;
2680}
2681
2682class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2683               TypedReg tr, bits<5> bytes, bits<4> type = 0>
2684  : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
2685            mnemonic#"\t$V1, $XBD2",
2686            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2687  let M3 = type;
2688  let mayLoad = 1;
2689  let AccessBytes = bytes;
2690}
2691
2692class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
2693  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
2694            mnemonic#"\t$V1, $XBD2, $M3", []> {
2695  let mayLoad = 1;
2696}
2697
2698class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
2699                         RegisterOperand cls>
2700  : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2701            mnemonic##"\t$R1, $XBD2", []>;
2702
2703class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
2704                            RegisterOperand cls>
2705  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2706             mnemonic##"\t$R1, $RI2", []> {
2707  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2708  // However, BDXs have two extra operands and are therefore 6 units more
2709  // complex.
2710  let AddedComplexity = 7;
2711}
2712
2713class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
2714                          RegisterOperand cls1, RegisterOperand cls2>
2715  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2716            mnemonic#"\t$R1, $R2", []>;
2717
2718class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
2719                           RegisterOperand cls1, RegisterOperand cls2>
2720  : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2721             mnemonic#"\t$R1, $R2", []> {
2722  let R3 = 0;
2723  let M4 = 0;
2724}
2725
2726class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
2727                           RegisterOperand cls1, RegisterOperand cls2>
2728  : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2729             mnemonic#"\t$R1, $R2", []> {
2730  let M3 = 0;
2731}
2732
2733class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
2734                         Immediate imm1, Immediate imm2>
2735  : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
2736           mnemonic#"\t$I1, $I2", []>;
2737
2738class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
2739  : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2740           mnemonic#"\t$BD1, $I2", []>;
2741
2742class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
2743                          SDPatternOperator operator, Immediate imm>
2744  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2745            mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
2746
2747class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
2748  : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
2749            mnemonic##"\t$BDL1, $BD2", []>;
2750
2751class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
2752  : InstSSb<opcode,
2753            (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
2754            mnemonic##"\t$BDL1, $BDL2", []>;
2755
2756class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
2757  : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
2758            mnemonic##"\t$BD1, $BDL2", []>;
2759
2760class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
2761  : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2762            mnemonic#"\t$BD1, $BD2", []>;
2763
2764class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
2765                               RegisterOperand cls1, RegisterOperand cls2>
2766  : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
2767           mnemonic#"\t$R1, $R2", []> {
2768    let Constraints = "$R1 = $R1src, $R2 = $R2src";
2769    let DisableEncoding = "$R1src, $R2src";
2770}
2771
2772class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
2773                             RegisterOperand cls1, RegisterOperand cls2>
2774  : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
2775            mnemonic#"\t$R1, $R2", []> {
2776  let Constraints = "$R2 = $R2src";
2777  let DisableEncoding = "$R2src";
2778}
2779
2780class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
2781                                RegisterOperand cls1, RegisterOperand cls2>
2782  : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
2783            mnemonic#"\t$R1, $R2", []> {
2784    let Constraints = "$R1 = $R1src, $R2 = $R2src";
2785    let DisableEncoding = "$R1src, $R2src";
2786}
2787
2788class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
2789                                 RegisterOperand cls1, RegisterOperand cls2>
2790  : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
2791             mnemonic#"\t$R1, $R2", []> {
2792  let Constraints = "$R1 = $R1src, $R2 = $R2src";
2793  let DisableEncoding = "$R1src, $R2src";
2794  let M3 = 0;
2795}
2796
2797class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2798               RegisterOperand cls1, RegisterOperand cls2>
2799  : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2800           mnemonic#"\t$R1, $R2",
2801           [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
2802  let OpKey = mnemonic#cls1;
2803  let OpType = "reg";
2804  let Constraints = "$R1 = $R1src";
2805  let DisableEncoding = "$R1src";
2806}
2807
2808class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2809                RegisterOperand cls1, RegisterOperand cls2>
2810  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2811            mnemonic#"\t$R1, $R2",
2812            [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
2813  let OpKey = mnemonic#cls1;
2814  let OpType = "reg";
2815  let Constraints = "$R1 = $R1src";
2816  let DisableEncoding = "$R1src";
2817}
2818
2819class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2820                RegisterOperand cls1, RegisterOperand cls2>
2821  : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
2822            mnemonic#"\t$R1, $R3, $R2",
2823            [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
2824  let OpKey = mnemonic#cls;
2825  let OpType = "reg";
2826}
2827
2828class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2829                 RegisterOperand cls1, RegisterOperand cls2,
2830                 RegisterOperand cls3>
2831  : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
2832             mnemonic#"\t$R1, $R2, $R3",
2833             [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
2834  let M4 = 0;
2835}
2836
2837multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
2838                        SDPatternOperator operator, RegisterOperand cls1,
2839                        RegisterOperand cls2> {
2840  let NumOpsKey = mnemonic in {
2841    let NumOpsValue = "3" in
2842      def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
2843              Requires<[FeatureDistinctOps]>;
2844    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2845      def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
2846  }
2847}
2848
2849multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
2850                         SDPatternOperator operator, RegisterOperand cls1,
2851                         RegisterOperand cls2> {
2852  let NumOpsKey = mnemonic in {
2853    let NumOpsValue = "3" in
2854      def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
2855              Requires<[FeatureDistinctOps]>;
2856    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2857      def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
2858  }
2859}
2860
2861class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2862                 RegisterOperand cls1, RegisterOperand cls2,
2863                 RegisterOperand cls3>
2864  : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
2865             mnemonic#"\t$R1, $R3, $R2",
2866             [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
2867  let M4 = 0;
2868}
2869
2870class BinaryMemRRFc<string mnemonic, bits<16> opcode,
2871                    RegisterOperand cls1, RegisterOperand cls2, Immediate imm>
2872  : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
2873            mnemonic#"\t$R1, $R2, $M3", []> {
2874  let Constraints = "$R1 = $R1src";
2875  let DisableEncoding = "$R1src";
2876}
2877
2878multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
2879                            RegisterOperand cls1, RegisterOperand cls2> {
2880  def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
2881  def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
2882}
2883
2884class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2885                RegisterOperand cls2>
2886  : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
2887             mnemonic#"\t$R1, $R2, $M4", []>;
2888
2889class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2890                RegisterOperand cls2>
2891  : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
2892             mnemonic#"\t$R1, $M3, $R2", []> {
2893  let M4 = 0;
2894}
2895
2896class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2897                   RegisterOperand cls2>
2898  : InstRRFc<opcode, (outs cls1:$R1),
2899             (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
2900             mnemonic#"$M3\t$R1, $R2", []> {
2901  let Constraints = "$R1 = $R1src";
2902  let DisableEncoding = "$R1src";
2903  let CCMaskLast = 1;
2904}
2905
2906// Like CondBinaryRRF, but used for the raw assembly form.  The condition-code
2907// mask is the third operand rather than being part of the mnemonic.
2908class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2909                       RegisterOperand cls2>
2910  : InstRRFc<opcode, (outs cls1:$R1),
2911             (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
2912             mnemonic#"\t$R1, $R2, $M3", []> {
2913  let Constraints = "$R1 = $R1src";
2914  let DisableEncoding = "$R1src";
2915}
2916
2917// Like CondBinaryRRF, but with a fixed CC mask.
2918class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
2919                         RegisterOperand cls1, RegisterOperand cls2>
2920  : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2921             mnemonic#V.suffix#"\t$R1, $R2", []> {
2922  let Constraints = "$R1 = $R1src";
2923  let DisableEncoding = "$R1src";
2924  let isAsmParserOnly = V.alternate;
2925  let M3 = V.ccmask;
2926}
2927
2928multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
2929                             RegisterOperand cls1, RegisterOperand cls2> {
2930  let isCodeGenOnly = 1 in
2931    def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
2932  def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
2933}
2934
2935class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2936               RegisterOperand cls, Immediate imm>
2937  : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2938            mnemonic#"\t$R1, $I2",
2939            [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2940  let Constraints = "$R1 = $R1src";
2941  let DisableEncoding = "$R1src";
2942}
2943
2944class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2945                RegisterOperand cls, Immediate imm>
2946  : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
2947             mnemonic#"\t$R1, $R3, $I2",
2948             [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2949
2950multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
2951                        SDPatternOperator operator, RegisterOperand cls,
2952                        Immediate imm> {
2953  let NumOpsKey = mnemonic in {
2954    let NumOpsValue = "3" in
2955      def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
2956              Requires<[FeatureDistinctOps]>;
2957    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2958      def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
2959  }
2960}
2961
2962class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2963                    Immediate imm>
2964  : InstRIEg<opcode, (outs cls:$R1),
2965             (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
2966             mnemonic#"$M3\t$R1, $I2",
2967             [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
2968                                             cond4:$valid, cond4:$M3))]> {
2969  let Constraints = "$R1 = $R1src";
2970  let DisableEncoding = "$R1src";
2971  let CCMaskLast = 1;
2972}
2973
2974// Like CondBinaryRIE, but used for the raw assembly form.  The condition-code
2975// mask is the third operand rather than being part of the mnemonic.
2976class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2977                       Immediate imm>
2978  : InstRIEg<opcode, (outs cls:$R1),
2979             (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
2980             mnemonic#"\t$R1, $I2, $M3", []> {
2981  let Constraints = "$R1 = $R1src";
2982  let DisableEncoding = "$R1src";
2983}
2984
2985// Like CondBinaryRIE, but with a fixed CC mask.
2986class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
2987                         RegisterOperand cls, Immediate imm>
2988  : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2989             mnemonic#V.suffix#"\t$R1, $I2", []> {
2990  let Constraints = "$R1 = $R1src";
2991  let DisableEncoding = "$R1src";
2992  let isAsmParserOnly = V.alternate;
2993  let M3 = V.ccmask;
2994}
2995
2996multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
2997                             RegisterOperand cls, Immediate imm> {
2998  let isCodeGenOnly = 1 in
2999    def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3000  def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3001}
3002
3003class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3004                RegisterOperand cls, Immediate imm>
3005  : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3006             mnemonic#"\t$R1, $I2",
3007             [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3008  let Constraints = "$R1 = $R1src";
3009  let DisableEncoding = "$R1src";
3010}
3011
3012class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3013               RegisterOperand cls>
3014  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
3015            mnemonic#"\t$R1, $BD2",
3016            [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
3017  let R3 = 0;
3018  let Constraints = "$R1 = $R1src";
3019  let DisableEncoding = "$R1src";
3020}
3021
3022class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3023                RegisterOperand cls>
3024  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
3025             mnemonic#"\t$R1, $R3, $BD2",
3026             [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
3027
3028multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3029                        SDPatternOperator operator, RegisterOperand cls> {
3030  let NumOpsKey = mnemonic in {
3031    let NumOpsValue = "3" in
3032      def K  : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
3033               Requires<[FeatureDistinctOps]>;
3034    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
3035      def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
3036  }
3037}
3038
3039class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3040  : InstRSLb<opcode, (outs cls:$R1),
3041             (ins bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
3042             mnemonic#"\t$R1, $BDL2, $M3", []> {
3043  let mayLoad = 1;
3044}
3045
3046class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3047               RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3048               AddressingMode mode = bdxaddr12only>
3049  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3050            mnemonic#"\t$R1, $XBD2",
3051            [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3052  let OpKey = mnemonic#"r"#cls;
3053  let OpType = "mem";
3054  let Constraints = "$R1 = $R1src";
3055  let DisableEncoding = "$R1src";
3056  let mayLoad = 1;
3057  let AccessBytes = bytes;
3058}
3059
3060class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3061                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3062  : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
3063            mnemonic#"\t$R1, $XBD2",
3064            [(set cls:$R1, (operator cls:$R1src,
3065                                     (load bdxaddr12only:$XBD2)))]> {
3066  let OpKey = mnemonic#"r"#cls;
3067  let OpType = "mem";
3068  let Constraints = "$R1 = $R1src";
3069  let DisableEncoding = "$R1src";
3070  let mayLoad = 1;
3071  let AccessBytes = bytes;
3072  let M3 = 0;
3073}
3074
3075class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3076                RegisterOperand cls1, RegisterOperand cls2,
3077                SDPatternOperator load, bits<5> bytes>
3078  : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
3079            mnemonic#"\t$R1, $R3, $XBD2",
3080            [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
3081  let OpKey = mnemonic#"r"#cls;
3082  let OpType = "mem";
3083  let mayLoad = 1;
3084  let AccessBytes = bytes;
3085}
3086
3087class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3088                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3089                AddressingMode mode = bdxaddr20only>
3090  : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3091             mnemonic#"\t$R1, $XBD2",
3092             [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3093  let OpKey = mnemonic#"r"#cls;
3094  let OpType = "mem";
3095  let Constraints = "$R1 = $R1src";
3096  let DisableEncoding = "$R1src";
3097  let mayLoad = 1;
3098  let AccessBytes = bytes;
3099}
3100
3101multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3102                        SDPatternOperator operator, RegisterOperand cls,
3103                        SDPatternOperator load, bits<5> bytes> {
3104  let DispKey = mnemonic ## #cls in {
3105    let DispSize = "12" in
3106      def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
3107                        bdxaddr12pair>;
3108    let DispSize = "20" in
3109      def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
3110                         bdxaddr20pair>;
3111  }
3112}
3113
3114class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3115               Operand imm, AddressingMode mode = bdaddr12only>
3116  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3117           mnemonic#"\t$BD1, $I2",
3118           [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3119  let mayLoad = 1;
3120  let mayStore = 1;
3121}
3122
3123class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3124                Operand imm, AddressingMode mode = bdaddr20only>
3125  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3126            mnemonic#"\t$BD1, $I2",
3127            [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3128  let mayLoad = 1;
3129  let mayStore = 1;
3130}
3131
3132multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
3133                        bits<16> siyOpcode, SDPatternOperator operator,
3134                        Operand imm> {
3135  let DispKey = mnemonic ## #cls in {
3136    let DispSize = "12" in
3137      def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
3138    let DispSize = "20" in
3139      def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
3140  }
3141}
3142
3143class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3144  : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
3145            mnemonic#"\t$R3, $BD1, $BD2", []> {
3146  let mayLoad = 1;
3147}
3148
3149class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3150                 TypedReg tr, bits<4> type>
3151  : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
3152             mnemonic#"\t$V1, $I2, $I3",
3153             [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
3154  let M4 = type;
3155}
3156
3157class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
3158  : InstVRIb<opcode, (outs VR128:$V1),
3159             (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
3160             mnemonic#"\t$V1, $I2, $I3, $M4", []>;
3161
3162class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3163                 TypedReg tr1, TypedReg tr2, bits<4> type>
3164  : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3165             mnemonic#"\t$V1, $V3, $I2",
3166             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
3167                                                 imm32zx16:$I2)))]> {
3168  let M4 = type;
3169}
3170
3171class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
3172  : InstVRIc<opcode, (outs VR128:$V1),
3173             (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3174             mnemonic#"\t$V1, $V3, $I2, $M4", []>;
3175
3176class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3177                 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
3178  : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
3179             mnemonic#"\t$V1, $V2, $I3",
3180             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3181                                                 imm32zx12:$I3)))]> {
3182  let M4 = type;
3183  let M5 = m5;
3184}
3185
3186class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
3187  : InstVRIe<opcode, (outs VR128:$V1),
3188             (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3189             mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
3190
3191class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3192                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
3193  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
3194             mnemonic#"\t$V1, $V2, $M5",
3195             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3196                                                 imm32zx12:$M5)))]> {
3197  let M3 = type;
3198  let M4 = m4;
3199}
3200
3201class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3202  : InstVRRa<opcode, (outs VR128:$V1),
3203             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3204             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3205
3206class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3207                 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
3208                 bits<4> modifier = 0>
3209  : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3210             mnemonic#"\t$V1, $V2, $V3",
3211             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3212                                                 (tr2.vt tr2.op:$V3))))]> {
3213  let M4 = type;
3214  let M5 = modifier;
3215}
3216
3217// Declare a pair of instructions, one which sets CC and one which doesn't.
3218// The CC-setting form ends with "S" and sets the low bit of M5.
3219multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
3220                           SDPatternOperator operator,
3221                           SDPatternOperator operator_cc, TypedReg tr1,
3222                           TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
3223  def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3224                      !and (modifier, 14)>;
3225  let Defs = [CC] in
3226    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3227                       !add (!and (modifier, 14), 1)>;
3228}
3229
3230class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
3231  : InstVRRb<opcode, (outs VR128:$V1),
3232             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3233             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3234
3235// Declare a pair of instructions, one which sets CC and one which doesn't.
3236// The CC-setting form ends with "S" and sets the low bit of M5.
3237// The form that does not set CC has an extra operand to optionally allow
3238// specifying arbitrary M5 values in assembler.
3239multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
3240                                SDPatternOperator operator,
3241                                SDPatternOperator operator_cc,
3242                                TypedReg tr1, TypedReg tr2, bits<4> type> {
3243  let M4 = type in
3244    def "" : InstVRRb<opcode, (outs tr1.op:$V1),
3245                      (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
3246                      mnemonic#"\t$V1, $V2, $V3, $M5", []>;
3247  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3248            (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
3249  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3250                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3251                                            tr2.op:$V3, 0)>;
3252  let Defs = [CC] in
3253    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
3254}
3255
3256multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3257  def "" : InstVRRb<opcode, (outs VR128:$V1),
3258                   (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3259                   mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3260  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3261                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3262                                            imm32zx4:$M4, 0)>;
3263}
3264
3265class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3266                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
3267                 bits<4> m6 = 0>
3268  : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3269             mnemonic#"\t$V1, $V2, $V3",
3270             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3271                                                 (tr2.vt tr2.op:$V3))))]> {
3272  let M4 = type;
3273  let M5 = m5;
3274  let M6 = m6;
3275}
3276
3277class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
3278                        bits<4> m6 = 0>
3279  : InstVRRc<opcode, (outs VR128:$V1),
3280             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3281             mnemonic#"\t$V1, $V2, $V3, $M4", []> {
3282  let M5 = m5;
3283  let M6 = m6;
3284}
3285
3286class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
3287  : InstVRRc<opcode, (outs VR128:$V1),
3288             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3289             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3290  let M6 = m6;
3291}
3292
3293// Declare a pair of instructions, one which sets CC and one which doesn't.
3294// The CC-setting form ends with "S" and sets the low bit of M5.
3295multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
3296                           SDPatternOperator operator,
3297                           SDPatternOperator operator_cc, TypedReg tr1,
3298                           TypedReg tr2, bits<4> type, bits<4> m5,
3299                           bits<4> modifier = 0> {
3300  def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
3301                      m5, !and (modifier, 14)>;
3302  let Defs = [CC] in
3303    def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3304                       m5, !add (!and (modifier, 14), 1)>;
3305}
3306
3307class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
3308  : InstVRRc<opcode, (outs VR128:$V1),
3309             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
3310                  imm32zx4:$M6),
3311             mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
3312
3313class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3314                 TypedReg tr>
3315  : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
3316             mnemonic#"\t$V1, $R2, $R3",
3317             [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
3318
3319class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3320                 TypedReg tr1, TypedReg tr2, bits<4> type>
3321  : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
3322             mnemonic#"\t$V1, $V3, $BD2",
3323             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
3324                                                 shift12only:$BD2)))]> {
3325  let M4 = type;
3326}
3327
3328class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
3329  : InstVRSa<opcode, (outs VR128:$V1),
3330             (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
3331             mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
3332
3333class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3334                 bits<5> bytes>
3335  : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3336             mnemonic#"\t$V1, $R3, $BD2",
3337             [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3338  let M4 = 0;
3339  let mayLoad = 1;
3340  let AccessBytes = bytes;
3341}
3342
3343class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3344                 TypedReg tr, bits<4> type>
3345  : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
3346           mnemonic#"\t$R1, $V3, $BD2",
3347           [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
3348  let M4 = type;
3349}
3350
3351class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
3352  : InstVRSc<opcode, (outs GR64:$R1),
3353             (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
3354             mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
3355
3356class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3357                TypedReg tr, bits<5> bytes>
3358  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3359            mnemonic#"\t$V1, $XBD2, $M3",
3360            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
3361                                              imm32zx4:$M3)))]> {
3362  let mayLoad = 1;
3363  let AccessBytes = bytes;
3364}
3365
3366class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3367                    bits<5> bytes, AddressingMode mode = bdaddr12only>
3368  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3369            mnemonic#"\t$R1, $M3, $BD2", []> {
3370  let mayStore = 1;
3371  let AccessBytes = bytes;
3372}
3373
3374class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3375                     bits<5> bytes, AddressingMode mode = bdaddr20only>
3376  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3377             mnemonic#"\t$R1, $M3, $BD2", []> {
3378  let mayStore = 1;
3379  let AccessBytes = bytes;
3380}
3381
3382multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
3383                             bits<16> rsyOpcode, RegisterOperand cls,
3384                             bits<5> bytes> {
3385  let DispKey = mnemonic ## #cls in {
3386    let DispSize = "12" in
3387      def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3388    let DispSize = "20" in
3389      def Y  : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
3390                              bdaddr20pair>;
3391  }
3392}
3393
3394class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3395  : InstRSLb<opcode, (outs),
3396             (ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
3397             mnemonic#"\t$R1, $BDL2, $M3", []> {
3398  let mayStore = 1;
3399}
3400
3401class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3402                     Immediate index>
3403  : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
3404            mnemonic#"\t$V1, $VBD2, $M3", []> {
3405  let mayStore = 1;
3406  let AccessBytes = bytes;
3407}
3408
3409class StoreBinaryVRX<string mnemonic, bits<16> opcode,
3410                     SDPatternOperator operator, TypedReg tr, bits<5> bytes,
3411                     Immediate index>
3412  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
3413            mnemonic#"\t$V1, $XBD2, $M3",
3414            [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
3415  let mayStore = 1;
3416  let AccessBytes = bytes;
3417}
3418
3419class MemoryBinarySSd<string mnemonic, bits<8> opcode,
3420                      RegisterOperand cls>
3421  : InstSSd<opcode, (outs),
3422            (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
3423            mnemonic#"\t$RBD1, $BD2, $R3", []>;
3424
3425class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3426                RegisterOperand cls1, RegisterOperand cls2>
3427  : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3428           mnemonic#"\t$R1, $R2",
3429           [(operator cls1:$R1, cls2:$R2)]> {
3430  let OpKey = mnemonic#cls1;
3431  let OpType = "reg";
3432  let isCompare = 1;
3433}
3434
3435class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3436                 RegisterOperand cls1, RegisterOperand cls2>
3437  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3438            mnemonic#"\t$R1, $R2",
3439            [(operator cls1:$R1, cls2:$R2)]> {
3440  let OpKey = mnemonic#cls1;
3441  let OpType = "reg";
3442  let isCompare = 1;
3443}
3444
3445class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3446                RegisterOperand cls, Immediate imm>
3447  : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
3448            mnemonic#"\t$R1, $I2",
3449            [(operator cls:$R1, imm:$I2)]> {
3450  let isCompare = 1;
3451}
3452
3453class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3454                 RegisterOperand cls, Immediate imm>
3455  : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
3456             mnemonic#"\t$R1, $I2",
3457             [(operator cls:$R1, imm:$I2)]> {
3458  let isCompare = 1;
3459}
3460
3461class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3462                   RegisterOperand cls, SDPatternOperator load>
3463  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3464             mnemonic#"\t$R1, $RI2",
3465             [(operator cls:$R1, (load pcrel32:$RI2))]> {
3466  let isCompare = 1;
3467  let mayLoad = 1;
3468  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3469  // However, BDXs have two extra operands and are therefore 6 units more
3470  // complex.
3471  let AddedComplexity = 7;
3472}
3473
3474class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3475                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3476                AddressingMode mode = bdxaddr12only>
3477  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3478            mnemonic#"\t$R1, $XBD2",
3479            [(operator cls:$R1, (load mode:$XBD2))]> {
3480  let OpKey = mnemonic#"r"#cls;
3481  let OpType = "mem";
3482  let isCompare = 1;
3483  let mayLoad = 1;
3484  let AccessBytes = bytes;
3485}
3486
3487class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3488                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3489  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3490            mnemonic#"\t$R1, $XBD2",
3491            [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
3492  let OpKey = mnemonic#"r"#cls;
3493  let OpType = "mem";
3494  let isCompare = 1;
3495  let mayLoad = 1;
3496  let AccessBytes = bytes;
3497  let M3 = 0;
3498}
3499
3500class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3501                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3502                 AddressingMode mode = bdxaddr20only>
3503  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3504             mnemonic#"\t$R1, $XBD2",
3505             [(operator cls:$R1, (load mode:$XBD2))]> {
3506  let OpKey = mnemonic#"r"#cls;
3507  let OpType = "mem";
3508  let isCompare = 1;
3509  let mayLoad = 1;
3510  let AccessBytes = bytes;
3511}
3512
3513multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3514                         SDPatternOperator operator, RegisterOperand cls,
3515                         SDPatternOperator load, bits<5> bytes> {
3516  let DispKey = mnemonic ## #cls in {
3517    let DispSize = "12" in
3518      def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
3519                         load, bytes, bdxaddr12pair>;
3520    let DispSize = "20" in
3521      def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
3522                          load, bytes, bdxaddr20pair>;
3523  }
3524}
3525
3526class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3527                bits<5> bytes, AddressingMode mode = bdaddr12only>
3528  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3529            mnemonic#"\t$R1, $M3, $BD2", []> {
3530  let mayLoad = 1;
3531  let AccessBytes = bytes;
3532}
3533
3534class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3535                 bits<5> bytes, AddressingMode mode = bdaddr20only>
3536  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3537             mnemonic#"\t$R1, $M3, $BD2", []> {
3538  let mayLoad = 1;
3539  let AccessBytes = bytes;
3540}
3541
3542multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3543                         RegisterOperand cls, bits<5> bytes> {
3544  let DispKey = mnemonic ## #cls in {
3545    let DispSize = "12" in
3546      def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3547    let DispSize = "20" in
3548      def Y  : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
3549  }
3550}
3551
3552class CompareSSb<string mnemonic, bits<8> opcode>
3553  : InstSSb<opcode,
3554            (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
3555            mnemonic##"\t$BDL1, $BDL2", []> {
3556  let isCompare = 1;
3557  let mayLoad = 1;
3558}
3559
3560class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3561                SDPatternOperator load, Immediate imm,
3562                AddressingMode mode = bdaddr12only>
3563  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3564           mnemonic#"\t$BD1, $I2",
3565           [(operator (load mode:$BD1), imm:$I2)]> {
3566  let isCompare = 1;
3567  let mayLoad = 1;
3568}
3569
3570class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3571                 SDPatternOperator load, Immediate imm>
3572  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3573            mnemonic#"\t$BD1, $I2",
3574            [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
3575  let isCompare = 1;
3576  let mayLoad = 1;
3577}
3578
3579class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3580                 SDPatternOperator load, Immediate imm,
3581                 AddressingMode mode = bdaddr20only>
3582  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3583            mnemonic#"\t$BD1, $I2",
3584            [(operator (load mode:$BD1), imm:$I2)]> {
3585  let isCompare = 1;
3586  let mayLoad = 1;
3587}
3588
3589multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
3590                         SDPatternOperator operator, SDPatternOperator load,
3591                         Immediate imm> {
3592  let DispKey = mnemonic in {
3593    let DispSize = "12" in
3594      def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
3595    let DispSize = "20" in
3596      def Y  : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
3597                          bdaddr20pair>;
3598  }
3599}
3600
3601class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3602                  TypedReg tr, bits<4> type>
3603  : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
3604             mnemonic#"\t$V1, $V2",
3605             [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
3606  let isCompare = 1;
3607  let M3 = type;
3608  let M4 = 0;
3609  let M5 = 0;
3610}
3611
3612class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
3613  : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
3614             mnemonic#"\t$V1, $V2, $M3", []> {
3615  let isCompare = 1;
3616  let M4 = 0;
3617  let M5 = 0;
3618}
3619
3620class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3621  : InstVRRa<opcode, (outs),
3622             (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
3623             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3624  let isCompare = 1;
3625  let M5 = 0;
3626}
3627
3628class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3629              RegisterOperand cls>
3630  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3631            mnemonic#"\t$R1, $XBD2",
3632            [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
3633  let M3 = 0;
3634}
3635
3636class TestRSL<string mnemonic, bits<16> opcode>
3637  : InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
3638             mnemonic#"\t$BDL1", []> {
3639  let mayLoad = 1;
3640}
3641
3642class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
3643  : InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
3644                                 shift12only:$BD2, imm32zx4:$I3),
3645            mnemonic##"\t$BDL1, $BD2, $I3", []>;
3646
3647class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
3648                            RegisterOperand cls1, RegisterOperand cls2,
3649                            RegisterOperand cls3>
3650  : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
3651             mnemonic#"\t$R1, $R2, $R3", []> {
3652  let M4 = 0;
3653}
3654
3655class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
3656                            RegisterOperand cls1, RegisterOperand cls2,
3657                            RegisterOperand cls3>
3658  : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
3659             mnemonic#"\t$R1, $R3, $R2", []> {
3660  let M4 = 0;
3661}
3662
3663class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
3664                                     RegisterOperand cls1,
3665                                     RegisterOperand cls2,
3666                                     RegisterOperand cls3>
3667  : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
3668             (ins cls1:$R1src, cls2:$R2src, cls3:$R3src),
3669             mnemonic#"\t$R1, $R3, $R2", []> {
3670  let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
3671  let DisableEncoding = "$R1src, $R2src, $R3src";
3672  let M4 = 0;
3673}
3674
3675class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
3676                            RegisterOperand cls1, RegisterOperand cls2,
3677                            Immediate imm>
3678  : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
3679             mnemonic#"\t$R1, $R2, $M3", []>;
3680
3681multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
3682                                    RegisterOperand cls1,
3683                                    RegisterOperand cls2> {
3684  def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3685  def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
3686}
3687
3688class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
3689                                  RegisterOperand cls1, RegisterOperand cls2,
3690                                  Immediate imm>
3691  : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
3692             (ins cls1:$R1src, cls2:$R2src, imm:$M3),
3693             mnemonic#"\t$R1, $R2, $M3", []> {
3694  let Constraints = "$R1 = $R1src, $R2 = $R2src";
3695  let DisableEncoding = "$R1src, $R2src";
3696}
3697
3698multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
3699                                          RegisterOperand cls1,
3700                                          RegisterOperand cls2> {
3701  def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3702  def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
3703}
3704
3705class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
3706                           RegisterOperand cls>
3707  : InstSSF<opcode, (outs),
3708            (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
3709            mnemonic#"\t$BD1, $BD2, $R3", []>;
3710
3711class TernaryRRFa<string mnemonic, bits<16> opcode,
3712                 RegisterOperand cls1, RegisterOperand cls2,
3713                 RegisterOperand cls3>
3714  : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
3715             mnemonic#"\t$R1, $R2, $R3, $M4", []>;
3716
3717class TernaryRRFb<string mnemonic, bits<16> opcode,
3718                  RegisterOperand cls1, RegisterOperand cls2,
3719                  RegisterOperand cls3>
3720  : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3),
3721             (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4),
3722             mnemonic#"\t$R1, $R3, $R2, $M4", []> {
3723  let Constraints = "$R1 = $R1src";
3724  let DisableEncoding = "$R1src";
3725}
3726
3727class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3728                  RegisterOperand cls2>
3729  : InstRRFe<opcode, (outs cls1:$R1),
3730             (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
3731             mnemonic#"\t$R1, $M3, $R2, $M4", []>;
3732
3733class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3734                 RegisterOperand cls1, RegisterOperand cls2>
3735  : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
3736            mnemonic#"\t$R1, $R3, $R2",
3737            [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
3738  let OpKey = mnemonic#cls;
3739  let OpType = "reg";
3740  let Constraints = "$R1 = $R1src";
3741  let DisableEncoding = "$R1src";
3742}
3743
3744class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3745                bits<5> bytes, AddressingMode mode = bdaddr12only>
3746  : InstRSb<opcode, (outs cls:$R1),
3747            (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
3748            mnemonic#"\t$R1, $M3, $BD2", []> {
3749
3750  let Constraints = "$R1 = $R1src";
3751  let DisableEncoding = "$R1src";
3752  let mayLoad = 1;
3753  let AccessBytes = bytes;
3754}
3755
3756class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3757                bits<5> bytes, AddressingMode mode = bdaddr20only>
3758  : InstRSYb<opcode, (outs cls:$R1),
3759             (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
3760             mnemonic#"\t$R1, $M3, $BD2", []> {
3761
3762  let Constraints = "$R1 = $R1src";
3763  let DisableEncoding = "$R1src";
3764  let mayLoad = 1;
3765  let AccessBytes = bytes;
3766}
3767
3768multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3769                         RegisterOperand cls, bits<5> bytes> {
3770  let DispKey = mnemonic ## #cls in {
3771    let DispSize = "12" in
3772      def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3773    let DispSize = "20" in
3774      def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
3775  }
3776}
3777
3778class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
3779                          RegisterOperand cls1, RegisterOperand cls2>
3780  : InstRSa<opcode, (outs),
3781            (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2),
3782            mnemonic#"\t$R1, $R3, $BD2", []>;
3783
3784class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
3785                           RegisterOperand cls1, RegisterOperand cls2>
3786  : InstRSYa<opcode, (outs),
3787             (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2),
3788             mnemonic#"\t$R1, $R3, $BD2", []>;
3789
3790class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
3791                                RegisterOperand cls1, RegisterOperand cls2>
3792  : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
3793            (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
3794            mnemonic#"\t$R1, $R3, $BD2", []> {
3795    let Constraints = "$R1 = $R1src, $R3 = $R3src";
3796    let DisableEncoding = "$R1src, $R3src";
3797}
3798
3799class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
3800                                 RegisterOperand cls1, RegisterOperand cls2>
3801  : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
3802             (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
3803             mnemonic#"\t$R1, $R3, $BD2", []> {
3804    let Constraints = "$R1 = $R1src, $R3 = $R3src";
3805    let DisableEncoding = "$R1src, $R3src";
3806}
3807
3808class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3809                 RegisterOperand cls1, RegisterOperand cls2,
3810                 SDPatternOperator load, bits<5> bytes>
3811  : InstRXF<opcode, (outs cls1:$R1),
3812            (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
3813            mnemonic#"\t$R1, $R3, $XBD2",
3814            [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
3815                                      (load bdxaddr12only:$XBD2)))]> {
3816  let OpKey = mnemonic#"r"#cls;
3817  let OpType = "mem";
3818  let Constraints = "$R1 = $R1src";
3819  let DisableEncoding = "$R1src";
3820  let mayLoad = 1;
3821  let AccessBytes = bytes;
3822}
3823
3824class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3825                  TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
3826  : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
3827             mnemonic#"\t$V1, $I2, $M3",
3828             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3829                                                 imm:$I2, index:$M3)))]> {
3830  let Constraints = "$V1 = $V1src";
3831  let DisableEncoding = "$V1src";
3832}
3833
3834class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3835                  TypedReg tr1, TypedReg tr2, bits<4> type>
3836  : InstVRId<opcode, (outs tr1.op:$V1),
3837             (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
3838             mnemonic#"\t$V1, $V2, $V3, $I4",
3839             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3840                                                 (tr2.vt tr2.op:$V3),
3841                                                 imm32zx8:$I4)))]> {
3842  let M5 = type;
3843}
3844
3845class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3846                  TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
3847  : InstVRRa<opcode, (outs tr1.op:$V1),
3848             (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
3849             mnemonic#"\t$V1, $V2, $M4, $M5",
3850             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3851                                                 imm32zx4:$M4,
3852                                                 imm32zx4:$M5)))],
3853             m4or> {
3854  let M3 = type;
3855}
3856
3857class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3858  : InstVRRa<opcode, (outs VR128:$V1),
3859             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3860             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3861
3862class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3863                  TypedReg tr1, TypedReg tr2, bits<4> type,
3864                  SDPatternOperator m5mask, bits<4> m5or>
3865  : InstVRRb<opcode, (outs tr1.op:$V1),
3866             (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
3867             mnemonic#"\t$V1, $V2, $V3, $M5",
3868             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3869                                                 (tr2.vt tr2.op:$V3),
3870                                                 m5mask:$M5)))],
3871             m5or> {
3872  let M4 = type;
3873}
3874
3875// Declare a pair of instructions, one which sets CC and one which doesn't.
3876// The CC-setting form ends with "S" and sets the low bit of M5.
3877// Also create aliases to make use of M5 operand optional in assembler.
3878multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
3879                               SDPatternOperator operator,
3880                               SDPatternOperator operator_cc,
3881                               TypedReg tr1, TypedReg tr2, bits<4> type,
3882                               bits<4> modifier = 0> {
3883  def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3884                       imm32zx4even, !and (modifier, 14)>;
3885  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3886                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3887                                            tr2.op:$V3, 0)>;
3888  let Defs = [CC] in
3889    def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3890                        imm32zx4even, !add(!and (modifier, 14), 1)>;
3891  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
3892                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
3893                                                tr2.op:$V3, 0)>;
3894}
3895
3896multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3897  def "" : InstVRRb<opcode, (outs VR128:$V1),
3898                   (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3899                   mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3900  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3901                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3902                                            imm32zx4:$M4, 0)>;
3903}
3904
3905class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3906                  TypedReg tr1, TypedReg tr2>
3907  : InstVRRc<opcode, (outs tr1.op:$V1),
3908             (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
3909             mnemonic#"\t$V1, $V2, $V3, $M4",
3910             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3911                                                 (tr2.vt tr2.op:$V3),
3912                                                 imm32zx4:$M4)))]> {
3913  let M5 = 0;
3914  let M6 = 0;
3915}
3916
3917class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3918                  TypedReg tr1, TypedReg tr2, bits<4> type = 0>
3919  : InstVRRd<opcode, (outs tr1.op:$V1),
3920             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
3921             mnemonic#"\t$V1, $V2, $V3, $V4",
3922             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3923                                                 (tr2.vt tr2.op:$V3),
3924                                                 (tr1.vt tr1.op:$V4))))]> {
3925  let M5 = type;
3926  let M6 = 0;
3927}
3928
3929class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
3930  : InstVRRd<opcode, (outs VR128:$V1),
3931             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
3932             mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
3933  let M6 = 0;
3934}
3935
3936class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3937                  TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
3938  : InstVRRe<opcode, (outs tr1.op:$V1),
3939             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
3940             mnemonic#"\t$V1, $V2, $V3, $V4",
3941             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3942                                                 (tr2.vt tr2.op:$V3),
3943                                                 (tr1.vt tr1.op:$V4))))]> {
3944  let M5 = m5;
3945  let M6 = type;
3946}
3947
3948class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
3949  : InstVRRe<opcode, (outs VR128:$V1),
3950             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
3951             mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
3952
3953class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3954                  TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
3955  : InstVRSb<opcode, (outs tr1.op:$V1),
3956             (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
3957             mnemonic#"\t$V1, $R3, $BD2",
3958             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3959                                                 cls:$R3,
3960                                                 shift12only:$BD2)))]> {
3961  let Constraints = "$V1 = $V1src";
3962  let DisableEncoding = "$V1src";
3963  let M4 = type;
3964}
3965
3966class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
3967  : InstVRSb<opcode, (outs VR128:$V1),
3968             (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
3969             mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
3970  let Constraints = "$V1 = $V1src";
3971  let DisableEncoding = "$V1src";
3972}
3973
3974class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3975                 Immediate index>
3976  : InstVRV<opcode, (outs VR128:$V1),
3977           (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
3978           mnemonic#"\t$V1, $VBD2, $M3", []> {
3979  let Constraints = "$V1 = $V1src";
3980  let DisableEncoding = "$V1src";
3981  let mayLoad = 1;
3982  let AccessBytes = bytes;
3983}
3984
3985class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3986                 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
3987  : InstVRX<opcode, (outs tr1.op:$V1),
3988           (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
3989           mnemonic#"\t$V1, $XBD2, $M3",
3990           [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3991                                               bdxaddr12only:$XBD2,
3992                                               index:$M3)))]> {
3993  let Constraints = "$V1 = $V1src";
3994  let DisableEncoding = "$V1src";
3995  let mayLoad = 1;
3996  let AccessBytes = bytes;
3997}
3998
3999class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4000                     TypedReg tr1, TypedReg tr2, bits<4> type>
4001  : InstVRId<opcode, (outs tr1.op:$V1),
4002             (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4003             mnemonic#"\t$V1, $V2, $V3, $I4",
4004             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
4005                                                 (tr2.vt tr2.op:$V2),
4006                                                 (tr2.vt tr2.op:$V3),
4007                                                 imm32zx8:$I4)))]> {
4008  let Constraints = "$V1 = $V1src";
4009  let DisableEncoding = "$V1src";
4010  let M5 = type;
4011}
4012
4013class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
4014  : InstVRId<opcode, (outs VR128:$V1),
4015             (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4016                  imm32zx8:$I4, imm32zx4:$M5),
4017             mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
4018  let Constraints = "$V1 = $V1src";
4019  let DisableEncoding = "$V1src";
4020}
4021
4022class QuaternaryVRRd<string mnemonic, bits<16> opcode,
4023                     SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
4024                     bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
4025  : InstVRRd<opcode, (outs tr1.op:$V1),
4026             (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
4027             mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
4028             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
4029                                                 (tr2.vt tr2.op:$V3),
4030                                                 (tr2.vt tr2.op:$V4),
4031                                                 m6mask:$M6)))],
4032             m6or> {
4033  let M5 = type;
4034}
4035
4036// Declare a pair of instructions, one which sets CC and one which doesn't.
4037// The CC-setting form ends with "S" and sets the low bit of M6.
4038// Also create aliases to make use of M6 operand optional in assembler.
4039multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
4040                                  SDPatternOperator operator,
4041                                SDPatternOperator operator_cc,
4042                                TypedReg tr1, TypedReg tr2, bits<4> type,
4043                                bits<4> modifier = 0> {
4044  def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
4045                          imm32zx4even, !and (modifier, 14)>;
4046  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4047                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4048                                            tr2.op:$V3, tr2.op:$V4, 0)>;
4049  let Defs = [CC] in
4050    def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
4051                           imm32zx4even, !add (!and (modifier, 14), 1)>;
4052  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4053                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4054                                                tr2.op:$V3, tr2.op:$V4, 0)>;
4055}
4056
4057multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
4058  def "" : InstVRRd<opcode, (outs VR128:$V1),
4059                   (ins VR128:$V2, VR128:$V3, VR128:$V4,
4060                        imm32zx4:$M5, imm32zx4:$M6),
4061                   mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4062  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4063                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4064                                            VR128:$V4, imm32zx4:$M5, 0)>;
4065}
4066
4067class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
4068                               RegisterOperand cls1, RegisterOperand cls2,
4069                               RegisterOperand cls3>
4070  : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4071             mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4072
4073multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
4074                                          RegisterOperand cls1,
4075                                          RegisterOperand cls2,
4076                                          RegisterOperand cls3> {
4077  def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4078  def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4079  def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
4080}
4081
4082class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
4083                               RegisterOperand cls1, RegisterOperand cls2,
4084                               RegisterOperand cls3>
4085  : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4086             mnemonic#"\t$R1, $R3, $R2, $M4", []>;
4087
4088multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
4089                                       RegisterOperand cls1,
4090                                       RegisterOperand cls2,
4091                                       RegisterOperand cls3> {
4092  def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4093  def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4094}
4095
4096class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
4097                              RegisterOperand cls>
4098  : InstSSe<opcode, (outs),
4099            (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
4100            mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
4101
4102class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4103                  RegisterOperand cls, AddressingMode mode = bdaddr20only>
4104  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
4105             mnemonic#"\t$R1, $R3, $BD2",
4106             [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
4107  let mayLoad = 1;
4108  let mayStore = 1;
4109}
4110
4111class CmpSwapRRE<string mnemonic, bits<16> opcode,
4112                 RegisterOperand cls1, RegisterOperand cls2>
4113  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
4114            mnemonic#"\t$R1, $R2", []> {
4115  let Constraints = "$R1 = $R1src";
4116  let DisableEncoding = "$R1src";
4117  let mayLoad = 1;
4118  let mayStore = 1;
4119}
4120
4121class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4122                RegisterOperand cls, AddressingMode mode = bdaddr12only>
4123  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4124            mnemonic#"\t$R1, $R3, $BD2",
4125            [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4126  let Constraints = "$R1 = $R1src";
4127  let DisableEncoding = "$R1src";
4128  let mayLoad = 1;
4129  let mayStore = 1;
4130}
4131
4132class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4133                 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4134  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4135             mnemonic#"\t$R1, $R3, $BD2",
4136             [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4137  let Constraints = "$R1 = $R1src";
4138  let DisableEncoding = "$R1src";
4139  let mayLoad = 1;
4140  let mayStore = 1;
4141}
4142
4143multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4144                         SDPatternOperator operator, RegisterOperand cls> {
4145  let DispKey = mnemonic ## #cls in {
4146    let DispSize = "12" in
4147      def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
4148    let DispSize = "20" in
4149      def Y  : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
4150  }
4151}
4152
4153class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4154                       RegisterOperand cls2>
4155  : InstRIEf<opcode, (outs cls1:$R1),
4156             (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4157                  imm32zx6:$I5),
4158             mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
4159  let Constraints = "$R1 = $R1src";
4160  let DisableEncoding = "$R1src";
4161}
4162
4163class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
4164  : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
4165             mnemonic##"\t$M1, $XBD2",
4166             [(operator imm32zx4:$M1, bdxaddr20only:$XBD2)]>;
4167
4168class PrefetchRILPC<string mnemonic, bits<12> opcode,
4169                    SDPatternOperator operator>
4170  : InstRILc<opcode, (outs), (ins imm32zx4:$M1, pcrel32:$RI2),
4171             mnemonic##"\t$M1, $RI2",
4172             [(operator imm32zx4:$M1, pcrel32:$RI2)]> {
4173  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
4174  // However, BDXs have two extra operands and are therefore 6 units more
4175  // complex.
4176  let AddedComplexity = 7;
4177}
4178
4179class BranchPreloadSMI<string mnemonic, bits<8> opcode>
4180  : InstSMI<opcode, (outs),
4181            (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
4182            mnemonic#"\t$M1, $RI2, $BD3", []>;
4183
4184class BranchPreloadMII<string mnemonic, bits<8> opcode>
4185  : InstMII<opcode, (outs),
4186            (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
4187            mnemonic#"\t$M1, $RI2, $RI3", []>;
4188
4189// A floating-point load-and test operation.  Create both a normal unary
4190// operation and one that acts as a comparison against zero.
4191// Note that the comparison against zero operation is not available if we
4192// have vector support, since load-and-test instructions will partially
4193// clobber the target (vector) register.
4194multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
4195                          RegisterOperand cls> {
4196  def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
4197  let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
4198    def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
4199}
4200
4201//===----------------------------------------------------------------------===//
4202// Pseudo instructions
4203//===----------------------------------------------------------------------===//
4204//
4205// Convenience instructions that get lowered to real instructions
4206// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
4207// or SystemZInstrInfo::expandPostRAPseudo().
4208//
4209//===----------------------------------------------------------------------===//
4210
4211class Pseudo<dag outs, dag ins, list<dag> pattern>
4212  : InstSystemZ<0, outs, ins, "", pattern> {
4213  let isPseudo = 1;
4214  let isCodeGenOnly = 1;
4215}
4216
4217// Like SideEffectBinarySIL, but expanded later.
4218class SideEffectBinarySILPseudo<SDPatternOperator operator, Immediate imm>
4219  : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
4220           [(operator bdaddr12only:$BD1, imm:$I2)]>;
4221
4222// Like UnaryRI, but expanded after RA depending on the choice of register.
4223class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4224                    Immediate imm>
4225  : Pseudo<(outs cls:$R1), (ins imm:$I2),
4226           [(set cls:$R1, (operator imm:$I2))]>;
4227
4228// Like UnaryRXY, but expanded after RA depending on the choice of register.
4229class UnaryRXYPseudo<string key, SDPatternOperator operator,
4230                     RegisterOperand cls, bits<5> bytes,
4231                     AddressingMode mode = bdxaddr20only>
4232  : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
4233           [(set cls:$R1, (operator mode:$XBD2))]> {
4234  let OpKey = key#"r"#cls;
4235  let OpType = "mem";
4236  let mayLoad = 1;
4237  let Has20BitOffset = 1;
4238  let HasIndex = 1;
4239  let AccessBytes = bytes;
4240}
4241
4242// Like UnaryRR, but expanded after RA depending on the choice of registers.
4243class UnaryRRPseudo<string key, SDPatternOperator operator,
4244                    RegisterOperand cls1, RegisterOperand cls2>
4245  : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
4246           [(set cls1:$R1, (operator cls2:$R2))]> {
4247  let OpKey = key#cls1;
4248  let OpType = "reg";
4249}
4250
4251// Like BinaryRI, but expanded after RA depending on the choice of register.
4252class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4253                     Immediate imm>
4254  : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
4255           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4256  let Constraints = "$R1 = $R1src";
4257}
4258
4259// Like BinaryRIE, but expanded after RA depending on the choice of register.
4260class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
4261                      Immediate imm>
4262  : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
4263           [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
4264
4265// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
4266multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
4267                              RegisterOperand cls, Immediate imm> {
4268  let NumOpsKey = key in {
4269    let NumOpsValue = "3" in
4270      def K : BinaryRIEPseudo<null_frag, cls, imm>,
4271              Requires<[FeatureHighWord, FeatureDistinctOps]>;
4272    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
4273      def "" : BinaryRIPseudo<operator, cls, imm>,
4274               Requires<[FeatureHighWord]>;
4275  }
4276}
4277
4278// Like CompareRI, but expanded after RA depending on the choice of register.
4279class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4280                      Immediate imm>
4281  : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
4282  let isCompare = 1;
4283}
4284
4285// Like CompareRXY, but expanded after RA depending on the choice of register.
4286class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
4287                       SDPatternOperator load, bits<5> bytes,
4288                       AddressingMode mode = bdxaddr20only>
4289  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
4290           [(operator cls:$R1, (load mode:$XBD2))]> {
4291  let mayLoad = 1;
4292  let Has20BitOffset = 1;
4293  let HasIndex = 1;
4294  let AccessBytes = bytes;
4295}
4296
4297// Like CondBinaryRRF, but expanded after RA depending on the choice of
4298// register.
4299class CondBinaryRRFPseudo<RegisterOperand cls1, RegisterOperand cls2>
4300  : Pseudo<(outs cls1:$R1),
4301           (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), []> {
4302  let Constraints = "$R1 = $R1src";
4303  let DisableEncoding = "$R1src";
4304  let CCMaskLast = 1;
4305}
4306
4307// Like CondBinaryRIE, but expanded after RA depending on the choice of
4308// register.
4309class CondBinaryRIEPseudo<RegisterOperand cls, Immediate imm>
4310  : Pseudo<(outs cls:$R1),
4311           (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
4312           [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
4313                                           cond4:$valid, cond4:$M3))]> {
4314  let Constraints = "$R1 = $R1src";
4315  let DisableEncoding = "$R1src";
4316  let CCMaskLast = 1;
4317}
4318
4319// Like CondUnaryRSY, but expanded after RA depending on the choice of
4320// register.
4321class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls,
4322                         bits<5> bytes, AddressingMode mode = bdaddr20only>
4323  : Pseudo<(outs cls:$R1),
4324           (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
4325           [(set cls:$R1,
4326                 (z_select_ccmask (operator mode:$BD2), cls:$R1src,
4327                                  cond4:$valid, cond4:$R3))]> {
4328  let Constraints = "$R1 = $R1src";
4329  let DisableEncoding = "$R1src";
4330  let mayLoad = 1;
4331  let AccessBytes = bytes;
4332  let CCMaskLast = 1;
4333}
4334
4335// Like CondStoreRSY, but expanded after RA depending on the choice of
4336// register.
4337class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
4338                         AddressingMode mode = bdaddr20only>
4339  : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
4340  let mayStore = 1;
4341  let AccessBytes = bytes;
4342  let CCMaskLast = 1;
4343}
4344
4345// Like StoreRXY, but expanded after RA depending on the choice of register.
4346class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
4347                     bits<5> bytes, AddressingMode mode = bdxaddr20only>
4348  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
4349           [(operator cls:$R1, mode:$XBD2)]> {
4350  let mayStore = 1;
4351  let Has20BitOffset = 1;
4352  let HasIndex = 1;
4353  let AccessBytes = bytes;
4354}
4355
4356// Like RotateSelectRIEf, but expanded after RA depending on the choice
4357// of registers.
4358class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
4359  : Pseudo<(outs cls1:$R1),
4360           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4361                imm32zx6:$I5),
4362           []> {
4363  let Constraints = "$R1 = $R1src";
4364  let DisableEncoding = "$R1src";
4365}
4366
4367// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
4368// the value of the PSW's 2-bit condition code field.
4369class SelectWrapper<RegisterOperand cls>
4370  : Pseudo<(outs cls:$dst),
4371           (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
4372           [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
4373                                            imm32zx4:$valid, imm32zx4:$cc))]> {
4374  let usesCustomInserter = 1;
4375  // Although the instructions used by these nodes do not in themselves
4376  // change CC, the insertion requires new blocks, and CC cannot be live
4377  // across them.
4378  let Defs = [CC];
4379  let Uses = [CC];
4380}
4381
4382// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
4383multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
4384                      SDPatternOperator load, AddressingMode mode> {
4385  let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
4386    def "" : Pseudo<(outs),
4387                    (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
4388                    [(store (z_select_ccmask cls:$new, (load mode:$addr),
4389                                             imm32zx4:$valid, imm32zx4:$cc),
4390                            mode:$addr)]>;
4391    def Inv : Pseudo<(outs),
4392                     (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
4393                     [(store (z_select_ccmask (load mode:$addr), cls:$new,
4394                                              imm32zx4:$valid, imm32zx4:$cc),
4395                              mode:$addr)]>;
4396  }
4397}
4398
4399// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation.  PAT and OPERAND
4400// describe the second (non-memory) operand.
4401class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
4402                       dag pat, DAGOperand operand>
4403  : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
4404           [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
4405  let Defs = [CC];
4406  let Has20BitOffset = 1;
4407  let mayLoad = 1;
4408  let mayStore = 1;
4409  let usesCustomInserter = 1;
4410  let hasNoSchedulingInfo = 1;
4411}
4412
4413// Specializations of AtomicLoadWBinary.
4414class AtomicLoadBinaryReg32<SDPatternOperator operator>
4415  : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
4416class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
4417  : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
4418class AtomicLoadBinaryReg64<SDPatternOperator operator>
4419  : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
4420class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
4421  : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
4422
4423// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation.  PAT and OPERAND
4424// describe the second (non-memory) operand.
4425class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
4426                        DAGOperand operand>
4427  : Pseudo<(outs GR32:$dst),
4428           (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
4429                ADDR32:$negbitshift, uimm32:$bitsize),
4430           [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
4431                                      ADDR32:$negbitshift, uimm32:$bitsize))]> {
4432  let Defs = [CC];
4433  let Has20BitOffset = 1;
4434  let mayLoad = 1;
4435  let mayStore = 1;
4436  let usesCustomInserter = 1;
4437  let hasNoSchedulingInfo = 1;
4438}
4439
4440// Specializations of AtomicLoadWBinary.
4441class AtomicLoadWBinaryReg<SDPatternOperator operator>
4442  : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
4443class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
4444  : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
4445
4446// Define an instruction that operates on two fixed-length blocks of memory,
4447// and associated pseudo instructions for operating on blocks of any size.
4448// The Sequence form uses a straight-line sequence of instructions and
4449// the Loop form uses a loop of length-256 instructions followed by
4450// another instruction to handle the excess.
4451multiclass MemorySS<string mnemonic, bits<8> opcode,
4452                    SDPatternOperator sequence, SDPatternOperator loop> {
4453  def "" : SideEffectBinarySSa<mnemonic, opcode>;
4454  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
4455    def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
4456                                       imm64:$length),
4457                           [(sequence bdaddr12only:$dest, bdaddr12only:$src,
4458                                      imm64:$length)]>;
4459    def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
4460                                   imm64:$length, GR64:$count256),
4461                      [(loop bdaddr12only:$dest, bdaddr12only:$src,
4462                             imm64:$length, GR64:$count256)]>;
4463  }
4464}
4465
4466// Define an instruction that operates on two strings, both terminated
4467// by the character in R0.  The instruction processes a CPU-determinated
4468// number of bytes at a time and sets CC to 3 if the instruction needs
4469// to be repeated.  Also define a pseudo instruction that represents
4470// the full loop (the main instruction plus the branch on CC==3).
4471multiclass StringRRE<string mnemonic, bits<16> opcode,
4472                     SDPatternOperator operator> {
4473  let Uses = [R0L] in
4474    def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;
4475  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
4476    def Loop : Pseudo<(outs GR64:$end),
4477                      (ins GR64:$start1, GR64:$start2, GR32:$char),
4478                      [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
4479                                                 GR32:$char))]>;
4480}
4481
4482// A pseudo instruction that is a direct alias of a real instruction.
4483// These aliases are used in cases where a particular register operand is
4484// fixed or where the same instruction is used with different register sizes.
4485// The size parameter is the size in bytes of the associated real instruction.
4486class Alias<int size, dag outs, dag ins, list<dag> pattern>
4487  : InstSystemZ<size, outs, ins, "", pattern> {
4488  let isPseudo = 1;
4489  let isCodeGenOnly = 1;
4490}
4491
4492class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
4493 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
4494
4495// An alias of a UnaryVRR*, but with different register sizes.
4496class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
4497  : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
4498          [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
4499
4500// An alias of a UnaryVRX, but with different register sizes.
4501class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
4502                    AddressingMode mode = bdxaddr12only>
4503  : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
4504          [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
4505
4506// An alias of a StoreVRX, but with different register sizes.
4507class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
4508                    AddressingMode mode = bdxaddr12only>
4509  : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
4510          [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
4511
4512// An alias of a BinaryRI, but with different register sizes.
4513class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
4514                    Immediate imm>
4515  : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
4516          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4517  let Constraints = "$R1 = $R1src";
4518}
4519
4520// An alias of a BinaryRIL, but with different register sizes.
4521class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
4522                     Immediate imm>
4523  : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
4524          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4525  let Constraints = "$R1 = $R1src";
4526}
4527
4528// An alias of a BinaryVRRf, but with different register sizes.
4529class BinaryAliasVRRf<RegisterOperand cls>
4530  : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
4531
4532// An alias of a CompareRI, but with different register sizes.
4533class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
4534                     Immediate imm>
4535  : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
4536  let isCompare = 1;
4537}
4538
4539// An alias of a RotateSelectRIEf, but with different register sizes.
4540class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
4541  : Alias<6, (outs cls1:$R1),
4542          (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4543               imm32zx6:$I5), []> {
4544  let Constraints = "$R1 = $R1src";
4545}
4546