1//===- SystemZInstrFormats.td - SystemZ Instruction Formats ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// Format specifies the encoding used by the instruction. This is part of the 11// ad-hoc solution used to emit machine instruction encodings by our machine 12// code emitter. 13class Format<bits<5> val> { 14 bits<5> Value = val; 15} 16 17def Pseudo : Format<0>; 18def EForm : Format<1>; 19def IForm : Format<2>; 20def RIForm : Format<3>; 21def RIEForm : Format<4>; 22def RILForm : Format<5>; 23def RISForm : Format<6>; 24def RRForm : Format<7>; 25def RREForm : Format<8>; 26def RRFForm : Format<9>; 27def RRRForm : Format<10>; 28def RRSForm : Format<11>; 29def RSForm : Format<12>; 30def RSIForm : Format<13>; 31def RSILForm : Format<14>; 32def RSYForm : Format<15>; 33def RXForm : Format<16>; 34def RXEForm : Format<17>; 35def RXFForm : Format<18>; 36def RXYForm : Format<19>; 37def SForm : Format<20>; 38def SIForm : Format<21>; 39def SILForm : Format<22>; 40def SIYForm : Format<23>; 41def SSForm : Format<24>; 42def SSEForm : Format<25>; 43def SSFForm : Format<26>; 44 45class InstSystemZ<bits<16> op, Format f, dag outs, dag ins> : Instruction { 46 let Namespace = "SystemZ"; 47 48 bits<16> Opcode = op; 49 50 Format Form = f; 51 bits<5> FormBits = Form.Value; 52 53 dag OutOperandList = outs; 54 dag InOperandList = ins; 55} 56 57class I8<bits<8> op, Format f, dag outs, dag ins, string asmstr, 58 list<dag> pattern> 59 : InstSystemZ<0, f, outs, ins> { 60 let Opcode{0-7} = op; 61 let Opcode{8-15} = 0; 62 63 let Pattern = pattern; 64 let AsmString = asmstr; 65} 66 67class I12<bits<12> op, Format f, dag outs, dag ins, string asmstr, 68 list<dag> pattern> 69 : InstSystemZ<0, f, outs, ins> { 70 let Opcode{0-11} = op; 71 let Opcode{12-15} = 0; 72 73 let Pattern = pattern; 74 let AsmString = asmstr; 75} 76 77class I16<bits<16> op, Format f, dag outs, dag ins, string asmstr, 78 list<dag> pattern> 79 : InstSystemZ<op, f, outs, ins> { 80 let Pattern = pattern; 81 let AsmString = asmstr; 82} 83 84class RRI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 85 : I8<op, RRForm, outs, ins, asmstr, pattern>; 86 87class RII<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 88 : I12<op, RIForm, outs, ins, asmstr, pattern>; 89 90class RILI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 91 : I12<op, RILForm, outs, ins, asmstr, pattern>; 92 93class RREI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 94 : I16<op, RREForm, outs, ins, asmstr, pattern>; 95 96class RXI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 97 : I8<op, RXForm, outs, ins, asmstr, pattern>; 98 99class RXYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 100 : I16<op, RXYForm, outs, ins, asmstr, pattern>; 101 102class RSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 103 : I8<op, RSForm, outs, ins, asmstr, pattern>; 104 105class RSYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 106 : I16<op, RSYForm, outs, ins, asmstr, pattern>; 107 108class SII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 109 : I8<op, SIForm, outs, ins, asmstr, pattern>; 110 111class SIYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 112 : I16<op, SIYForm, outs, ins, asmstr, pattern>; 113 114class SILI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 115 : I16<op, SILForm, outs, ins, asmstr, pattern>; 116 117 118//===----------------------------------------------------------------------===// 119// Pseudo instructions 120//===----------------------------------------------------------------------===// 121 122class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 123 : InstSystemZ<0, Pseudo, outs, ins> { 124 125 let Pattern = pattern; 126 let AsmString = asmstr; 127} 128