1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Basic SystemZ instruction definition 12//===----------------------------------------------------------------------===// 13 14class InstSystemZ<int size, dag outs, dag ins, string asmstr, 15 list<dag> pattern> : Instruction { 16 let Namespace = "SystemZ"; 17 18 dag OutOperandList = outs; 19 dag InOperandList = ins; 20 let Size = size; 21 let Pattern = pattern; 22 let AsmString = asmstr; 23 24 // Some instructions come in pairs, one having a 12-bit displacement 25 // and the other having a 20-bit displacement. Both instructions in 26 // the pair have the same DispKey and their DispSizes are "12" and "20" 27 // respectively. 28 string DispKey = ""; 29 string DispSize = "none"; 30 31 // Many register-based <INSN>R instructions have a memory-based <INSN> 32 // counterpart. OpKey uniquely identifies <INSN>, while OpType is 33 // "reg" for <INSN>R and "mem" for <INSN>. 34 string OpKey = ""; 35 string OpType = "none"; 36 37 // Many distinct-operands instructions have older 2-operand equivalents. 38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs, 39 // with NumOpsValue being "2" or "3" as appropriate. 40 string NumOpsKey = ""; 41 string NumOpsValue = "none"; 42 43 // True if this instruction is a simple D(X,B) load of a register 44 // (with no sign or zero extension). 45 bit SimpleBDXLoad = 0; 46 47 // True if this instruction is a simple D(X,B) store of a register 48 // (with no truncation). 49 bit SimpleBDXStore = 0; 50 51 // True if this instruction has a 20-bit displacement field. 52 bit Has20BitOffset = 0; 53 54 // True if addresses in this instruction have an index register. 55 bit HasIndex = 0; 56 57 // True if this is a 128-bit pseudo instruction that combines two 64-bit 58 // operations. 59 bit Is128Bit = 0; 60 61 // The access size of all memory operands in bytes, or 0 if not known. 62 bits<5> AccessBytes = 0; 63 64 // If the instruction sets CC to a useful value, this gives the mask 65 // of all possible CC results. The mask has the same form as 66 // SystemZ::CCMASK_*. 67 bits<4> CCValues = 0; 68 69 // The subset of CCValues that have the same meaning as they would after 70 // a comparison of the first operand against zero. 71 bits<4> CompareZeroCCMask = 0; 72 73 // True if the instruction is conditional and if the CC mask operand 74 // comes first (as for BRC, etc.). 75 bit CCMaskFirst = 0; 76 77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.). 78 bit CCMaskLast = 0; 79 80 // True if the instruction is the "logical" rather than "arithmetic" form, 81 // in cases where a distinction exists. 82 bit IsLogical = 0; 83 84 let TSFlags{0} = SimpleBDXLoad; 85 let TSFlags{1} = SimpleBDXStore; 86 let TSFlags{2} = Has20BitOffset; 87 let TSFlags{3} = HasIndex; 88 let TSFlags{4} = Is128Bit; 89 let TSFlags{9-5} = AccessBytes; 90 let TSFlags{13-10} = CCValues; 91 let TSFlags{17-14} = CompareZeroCCMask; 92 let TSFlags{18} = CCMaskFirst; 93 let TSFlags{19} = CCMaskLast; 94 let TSFlags{20} = IsLogical; 95} 96 97//===----------------------------------------------------------------------===// 98// Mappings between instructions 99//===----------------------------------------------------------------------===// 100 101// Return the version of an instruction that has an unsigned 12-bit 102// displacement. 103def getDisp12Opcode : InstrMapping { 104 let FilterClass = "InstSystemZ"; 105 let RowFields = ["DispKey"]; 106 let ColFields = ["DispSize"]; 107 let KeyCol = ["20"]; 108 let ValueCols = [["12"]]; 109} 110 111// Return the version of an instruction that has a signed 20-bit displacement. 112def getDisp20Opcode : InstrMapping { 113 let FilterClass = "InstSystemZ"; 114 let RowFields = ["DispKey"]; 115 let ColFields = ["DispSize"]; 116 let KeyCol = ["12"]; 117 let ValueCols = [["20"]]; 118} 119 120// Return the memory form of a register instruction. 121def getMemOpcode : InstrMapping { 122 let FilterClass = "InstSystemZ"; 123 let RowFields = ["OpKey"]; 124 let ColFields = ["OpType"]; 125 let KeyCol = ["reg"]; 126 let ValueCols = [["mem"]]; 127} 128 129// Return the 3-operand form of a 2-operand instruction. 130def getThreeOperandOpcode : InstrMapping { 131 let FilterClass = "InstSystemZ"; 132 let RowFields = ["NumOpsKey"]; 133 let ColFields = ["NumOpsValue"]; 134 let KeyCol = ["2"]; 135 let ValueCols = [["3"]]; 136} 137 138//===----------------------------------------------------------------------===// 139// Instruction formats 140//===----------------------------------------------------------------------===// 141// 142// Formats are specified using operand field declarations of the form: 143// 144// bits<4> Rn : register input or output for operand n 145// bits<5> Vn : vector register input or output for operand n 146// bits<m> In : immediate value of width m for operand n 147// bits<4> BDn : address operand n, which has a base and a displacement 148// bits<m> XBDn : address operand n, which has an index, a base and a 149// displacement 150// bits<m> VBDn : address operand n, which has a vector index, a base and a 151// displacement 152// bits<4> Xn : index register for address operand n 153// bits<4> Mn : mode value for operand n 154// 155// The operand numbers ("n" in the list above) follow the architecture manual. 156// Assembly operands sometimes have a different order; in particular, R3 often 157// is often written between operands 1 and 2. 158// 159//===----------------------------------------------------------------------===// 160 161class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 162 : InstSystemZ<2, outs, ins, asmstr, pattern> { 163 field bits<16> Inst; 164 field bits<16> SoftFail = 0; 165 166 bits<8> I1; 167 168 let Inst{15-8} = op; 169 let Inst{7-0} = I1; 170} 171 172class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 173 : InstSystemZ<4, outs, ins, asmstr, pattern> { 174 field bits<32> Inst; 175 field bits<32> SoftFail = 0; 176 177 bits<4> R1; 178 bits<16> I2; 179 180 let Inst{31-24} = op{11-4}; 181 let Inst{23-20} = R1; 182 let Inst{19-16} = op{3-0}; 183 let Inst{15-0} = I2; 184} 185 186class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 187 : InstSystemZ<6, outs, ins, asmstr, pattern> { 188 field bits<48> Inst; 189 field bits<48> SoftFail = 0; 190 191 bits<4> R1; 192 bits<4> R2; 193 bits<4> M3; 194 bits<16> RI4; 195 196 let Inst{47-40} = op{15-8}; 197 let Inst{39-36} = R1; 198 let Inst{35-32} = R2; 199 let Inst{31-16} = RI4; 200 let Inst{15-12} = M3; 201 let Inst{11-8} = 0; 202 let Inst{7-0} = op{7-0}; 203} 204 205class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 206 : InstSystemZ<6, outs, ins, asmstr, pattern> { 207 field bits<48> Inst; 208 field bits<48> SoftFail = 0; 209 210 bits<4> R1; 211 bits<8> I2; 212 bits<4> M3; 213 bits<16> RI4; 214 215 let Inst{47-40} = op{15-8}; 216 let Inst{39-36} = R1; 217 let Inst{35-32} = M3; 218 let Inst{31-16} = RI4; 219 let Inst{15-8} = I2; 220 let Inst{7-0} = op{7-0}; 221} 222 223class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 224 : InstSystemZ<6, outs, ins, asmstr, pattern> { 225 field bits<48> Inst; 226 field bits<48> SoftFail = 0; 227 228 bits<4> R1; 229 bits<4> R3; 230 bits<16> I2; 231 232 let Inst{47-40} = op{15-8}; 233 let Inst{39-36} = R1; 234 let Inst{35-32} = R3; 235 let Inst{31-16} = I2; 236 let Inst{15-8} = 0; 237 let Inst{7-0} = op{7-0}; 238} 239 240class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 241 : InstSystemZ<6, outs, ins, asmstr, pattern> { 242 field bits<48> Inst; 243 field bits<48> SoftFail = 0; 244 245 bits<4> R1; 246 bits<4> R2; 247 bits<8> I3; 248 bits<8> I4; 249 bits<8> I5; 250 251 let Inst{47-40} = op{15-8}; 252 let Inst{39-36} = R1; 253 let Inst{35-32} = R2; 254 let Inst{31-24} = I3; 255 let Inst{23-16} = I4; 256 let Inst{15-8} = I5; 257 let Inst{7-0} = op{7-0}; 258} 259 260class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 261 : InstSystemZ<6, outs, ins, asmstr, pattern> { 262 field bits<48> Inst; 263 field bits<48> SoftFail = 0; 264 265 bits<4> R1; 266 bits<32> I2; 267 268 let Inst{47-40} = op{11-4}; 269 let Inst{39-36} = R1; 270 let Inst{35-32} = op{3-0}; 271 let Inst{31-0} = I2; 272} 273 274class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 275 : InstSystemZ<6, outs, ins, asmstr, pattern> { 276 field bits<48> Inst; 277 field bits<48> SoftFail = 0; 278 279 bits<4> R1; 280 bits<8> I2; 281 bits<4> M3; 282 bits<16> BD4; 283 284 let Inst{47-40} = op{15-8}; 285 let Inst{39-36} = R1; 286 let Inst{35-32} = M3; 287 let Inst{31-16} = BD4; 288 let Inst{15-8} = I2; 289 let Inst{7-0} = op{7-0}; 290} 291 292class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 293 : InstSystemZ<2, outs, ins, asmstr, pattern> { 294 field bits<16> Inst; 295 field bits<16> SoftFail = 0; 296 297 bits<4> R1; 298 bits<4> R2; 299 300 let Inst{15-8} = op; 301 let Inst{7-4} = R1; 302 let Inst{3-0} = R2; 303} 304 305class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 306 : InstSystemZ<4, outs, ins, asmstr, pattern> { 307 field bits<32> Inst; 308 field bits<32> SoftFail = 0; 309 310 bits<4> R1; 311 bits<4> R3; 312 bits<4> R2; 313 314 let Inst{31-16} = op; 315 let Inst{15-12} = R1; 316 let Inst{11-8} = 0; 317 let Inst{7-4} = R3; 318 let Inst{3-0} = R2; 319} 320 321class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 322 : InstSystemZ<4, outs, ins, asmstr, pattern> { 323 field bits<32> Inst; 324 field bits<32> SoftFail = 0; 325 326 bits<4> R1; 327 bits<4> R2; 328 329 let Inst{31-16} = op; 330 let Inst{15-8} = 0; 331 let Inst{7-4} = R1; 332 let Inst{3-0} = R2; 333} 334 335class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 336 : InstSystemZ<4, outs, ins, asmstr, pattern> { 337 field bits<32> Inst; 338 field bits<32> SoftFail = 0; 339 340 bits<4> R1; 341 bits<4> R2; 342 bits<4> R3; 343 bits<4> R4; 344 345 let Inst{31-16} = op; 346 let Inst{15-12} = R3; 347 let Inst{11-8} = R4; 348 let Inst{7-4} = R1; 349 let Inst{3-0} = R2; 350} 351 352class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 353 : InstSystemZ<6, outs, ins, asmstr, pattern> { 354 field bits<48> Inst; 355 field bits<48> SoftFail = 0; 356 357 bits<4> R1; 358 bits<4> R2; 359 bits<4> M3; 360 bits<16> BD4; 361 362 let Inst{47-40} = op{15-8}; 363 let Inst{39-36} = R1; 364 let Inst{35-32} = R2; 365 let Inst{31-16} = BD4; 366 let Inst{15-12} = M3; 367 let Inst{11-8} = 0; 368 let Inst{7-0} = op{7-0}; 369} 370 371class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 372 : InstSystemZ<4, outs, ins, asmstr, pattern> { 373 field bits<32> Inst; 374 field bits<32> SoftFail = 0; 375 376 bits<4> R1; 377 bits<20> XBD2; 378 379 let Inst{31-24} = op; 380 let Inst{23-20} = R1; 381 let Inst{19-0} = XBD2; 382 383 let HasIndex = 1; 384} 385 386class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 387 : InstSystemZ<6, outs, ins, asmstr, pattern> { 388 field bits<48> Inst; 389 field bits<48> SoftFail = 0; 390 391 bits<4> R1; 392 bits<20> XBD2; 393 bits<4> M3; 394 395 let Inst{47-40} = op{15-8}; 396 let Inst{39-36} = R1; 397 let Inst{35-16} = XBD2; 398 let Inst{15-12} = M3; 399 let Inst{11-8} = 0; 400 let Inst{7-0} = op{7-0}; 401 402 let HasIndex = 1; 403} 404 405class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 406 : InstSystemZ<6, outs, ins, asmstr, pattern> { 407 field bits<48> Inst; 408 field bits<48> SoftFail = 0; 409 410 bits<4> R1; 411 bits<4> R3; 412 bits<20> XBD2; 413 414 let Inst{47-40} = op{15-8}; 415 let Inst{39-36} = R3; 416 let Inst{35-16} = XBD2; 417 let Inst{15-12} = R1; 418 let Inst{11-8} = 0; 419 let Inst{7-0} = op{7-0}; 420 421 let HasIndex = 1; 422} 423 424class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 425 : InstSystemZ<6, outs, ins, asmstr, pattern> { 426 field bits<48> Inst; 427 field bits<48> SoftFail = 0; 428 429 bits<4> R1; 430 bits<28> XBD2; 431 432 let Inst{47-40} = op{15-8}; 433 let Inst{39-36} = R1; 434 let Inst{35-8} = XBD2; 435 let Inst{7-0} = op{7-0}; 436 437 let Has20BitOffset = 1; 438 let HasIndex = 1; 439} 440 441class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 442 : InstSystemZ<4, outs, ins, asmstr, pattern> { 443 field bits<32> Inst; 444 field bits<32> SoftFail = 0; 445 446 bits<4> R1; 447 bits<4> R3; 448 bits<16> BD2; 449 450 let Inst{31-24} = op; 451 let Inst{23-20} = R1; 452 let Inst{19-16} = R3; 453 let Inst{15-0} = BD2; 454} 455 456class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 457 : InstSystemZ<6, outs, ins, asmstr, pattern> { 458 field bits<48> Inst; 459 field bits<48> SoftFail = 0; 460 461 bits<4> R1; 462 bits<4> R3; 463 bits<24> BD2; 464 465 let Inst{47-40} = op{15-8}; 466 let Inst{39-36} = R1; 467 let Inst{35-32} = R3; 468 let Inst{31-8} = BD2; 469 let Inst{7-0} = op{7-0}; 470 471 let Has20BitOffset = 1; 472} 473 474class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 475 : InstSystemZ<4, outs, ins, asmstr, pattern> { 476 field bits<32> Inst; 477 field bits<32> SoftFail = 0; 478 479 bits<16> BD1; 480 bits<8> I2; 481 482 let Inst{31-24} = op; 483 let Inst{23-16} = I2; 484 let Inst{15-0} = BD1; 485} 486 487class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 488 : InstSystemZ<6, outs, ins, asmstr, pattern> { 489 field bits<48> Inst; 490 field bits<48> SoftFail = 0; 491 492 bits<16> BD1; 493 bits<16> I2; 494 495 let Inst{47-32} = op; 496 let Inst{31-16} = BD1; 497 let Inst{15-0} = I2; 498} 499 500class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 501 : InstSystemZ<6, outs, ins, asmstr, pattern> { 502 field bits<48> Inst; 503 field bits<48> SoftFail = 0; 504 505 bits<24> BD1; 506 bits<8> I2; 507 508 let Inst{47-40} = op{15-8}; 509 let Inst{39-32} = I2; 510 let Inst{31-8} = BD1; 511 let Inst{7-0} = op{7-0}; 512 513 let Has20BitOffset = 1; 514} 515 516class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 517 : InstSystemZ<6, outs, ins, asmstr, pattern> { 518 field bits<48> Inst; 519 field bits<48> SoftFail = 0; 520 521 bits<24> BDL1; 522 bits<16> BD2; 523 524 let Inst{47-40} = op; 525 let Inst{39-16} = BDL1; 526 let Inst{15-0} = BD2; 527} 528 529class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 530 : InstSystemZ<4, outs, ins, asmstr, pattern> { 531 field bits<32> Inst; 532 field bits<32> SoftFail = 0; 533 534 bits<16> BD2; 535 536 let Inst{31-16} = op; 537 let Inst{15-0} = BD2; 538} 539 540class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 541 : InstSystemZ<6, outs, ins, asmstr, pattern> { 542 field bits<48> Inst; 543 field bits<48> SoftFail = 0; 544 545 bits<5> V1; 546 bits<16> I2; 547 bits<4> M3; 548 549 let Inst{47-40} = op{15-8}; 550 let Inst{39-36} = V1{3-0}; 551 let Inst{35-32} = 0; 552 let Inst{31-16} = I2; 553 let Inst{15-12} = M3; 554 let Inst{11} = V1{4}; 555 let Inst{10-8} = 0; 556 let Inst{7-0} = op{7-0}; 557} 558 559class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 560 : InstSystemZ<6, outs, ins, asmstr, pattern> { 561 field bits<48> Inst; 562 field bits<48> SoftFail = 0; 563 564 bits<5> V1; 565 bits<8> I2; 566 bits<8> I3; 567 bits<4> M4; 568 569 let Inst{47-40} = op{15-8}; 570 let Inst{39-36} = V1{3-0}; 571 let Inst{35-32} = 0; 572 let Inst{31-24} = I2; 573 let Inst{23-16} = I3; 574 let Inst{15-12} = M4; 575 let Inst{11} = V1{4}; 576 let Inst{10-8} = 0; 577 let Inst{7-0} = op{7-0}; 578} 579 580class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 581 : InstSystemZ<6, outs, ins, asmstr, pattern> { 582 field bits<48> Inst; 583 field bits<48> SoftFail = 0; 584 585 bits<5> V1; 586 bits<5> V3; 587 bits<16> I2; 588 bits<4> M4; 589 590 let Inst{47-40} = op{15-8}; 591 let Inst{39-36} = V1{3-0}; 592 let Inst{35-32} = V3{3-0}; 593 let Inst{31-16} = I2; 594 let Inst{15-12} = M4; 595 let Inst{11} = V1{4}; 596 let Inst{10} = V3{4}; 597 let Inst{9-8} = 0; 598 let Inst{7-0} = op{7-0}; 599} 600 601class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 602 : InstSystemZ<6, outs, ins, asmstr, pattern> { 603 field bits<48> Inst; 604 field bits<48> SoftFail = 0; 605 606 bits<5> V1; 607 bits<5> V2; 608 bits<5> V3; 609 bits<8> I4; 610 bits<4> M5; 611 612 let Inst{47-40} = op{15-8}; 613 let Inst{39-36} = V1{3-0}; 614 let Inst{35-32} = V2{3-0}; 615 let Inst{31-28} = V3{3-0}; 616 let Inst{27-24} = 0; 617 let Inst{23-16} = I4; 618 let Inst{15-12} = M5; 619 let Inst{11} = V1{4}; 620 let Inst{10} = V2{4}; 621 let Inst{9} = V3{4}; 622 let Inst{8} = 0; 623 let Inst{7-0} = op{7-0}; 624} 625 626class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 627 : InstSystemZ<6, outs, ins, asmstr, pattern> { 628 field bits<48> Inst; 629 field bits<48> SoftFail = 0; 630 631 bits<5> V1; 632 bits<5> V2; 633 bits<12> I3; 634 bits<4> M4; 635 bits<4> M5; 636 637 let Inst{47-40} = op{15-8}; 638 let Inst{39-36} = V1{3-0}; 639 let Inst{35-32} = V2{3-0}; 640 let Inst{31-20} = I3; 641 let Inst{19-16} = M5; 642 let Inst{15-12} = M4; 643 let Inst{11} = V1{4}; 644 let Inst{10} = V2{4}; 645 let Inst{9-8} = 0; 646 let Inst{7-0} = op{7-0}; 647} 648 649// Depending on the instruction mnemonic, certain bits may be or-ed into 650// the M4 value provided as explicit operand. These are passed as m4or. 651class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 652 bits<4> m4or = 0> 653 : InstSystemZ<6, outs, ins, asmstr, pattern> { 654 field bits<48> Inst; 655 field bits<48> SoftFail = 0; 656 657 bits<5> V1; 658 bits<5> V2; 659 bits<4> M3; 660 bits<4> M4; 661 bits<4> M5; 662 663 let Inst{47-40} = op{15-8}; 664 let Inst{39-36} = V1{3-0}; 665 let Inst{35-32} = V2{3-0}; 666 let Inst{31-24} = 0; 667 let Inst{23-20} = M5; 668 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3}); 669 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2}); 670 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1}); 671 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0}); 672 let Inst{15-12} = M3; 673 let Inst{11} = V1{4}; 674 let Inst{10} = V2{4}; 675 let Inst{9-8} = 0; 676 let Inst{7-0} = op{7-0}; 677} 678 679// Depending on the instruction mnemonic, certain bits may be or-ed into 680// the M5 value provided as explicit operand. These are passed as m5or. 681class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 682 bits<4> m5or = 0> 683 : InstSystemZ<6, outs, ins, asmstr, pattern> { 684 field bits<48> Inst; 685 field bits<48> SoftFail = 0; 686 687 bits<5> V1; 688 bits<5> V2; 689 bits<5> V3; 690 bits<4> M4; 691 bits<4> M5; 692 693 let Inst{47-40} = op{15-8}; 694 let Inst{39-36} = V1{3-0}; 695 let Inst{35-32} = V2{3-0}; 696 let Inst{31-28} = V3{3-0}; 697 let Inst{27-24} = 0; 698 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3}); 699 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2}); 700 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1}); 701 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0}); 702 let Inst{19-16} = 0; 703 let Inst{15-12} = M4; 704 let Inst{11} = V1{4}; 705 let Inst{10} = V2{4}; 706 let Inst{9} = V3{4}; 707 let Inst{8} = 0; 708 let Inst{7-0} = op{7-0}; 709} 710 711class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 712 : InstSystemZ<6, outs, ins, asmstr, pattern> { 713 field bits<48> Inst; 714 field bits<48> SoftFail = 0; 715 716 bits<5> V1; 717 bits<5> V2; 718 bits<5> V3; 719 bits<4> M4; 720 bits<4> M5; 721 bits<4> M6; 722 723 let Inst{47-40} = op{15-8}; 724 let Inst{39-36} = V1{3-0}; 725 let Inst{35-32} = V2{3-0}; 726 let Inst{31-28} = V3{3-0}; 727 let Inst{27-24} = 0; 728 let Inst{23-20} = M6; 729 let Inst{19-16} = M5; 730 let Inst{15-12} = M4; 731 let Inst{11} = V1{4}; 732 let Inst{10} = V2{4}; 733 let Inst{9} = V3{4}; 734 let Inst{8} = 0; 735 let Inst{7-0} = op{7-0}; 736} 737 738// Depending on the instruction mnemonic, certain bits may be or-ed into 739// the M6 value provided as explicit operand. These are passed as m6or. 740class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 741 bits<4> m6or = 0> 742 : InstSystemZ<6, outs, ins, asmstr, pattern> { 743 field bits<48> Inst; 744 field bits<48> SoftFail = 0; 745 746 bits<5> V1; 747 bits<5> V2; 748 bits<5> V3; 749 bits<5> V4; 750 bits<4> M5; 751 bits<4> M6; 752 753 let Inst{47-40} = op{15-8}; 754 let Inst{39-36} = V1{3-0}; 755 let Inst{35-32} = V2{3-0}; 756 let Inst{31-28} = V3{3-0}; 757 let Inst{27-24} = M5; 758 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3}); 759 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2}); 760 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1}); 761 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0}); 762 let Inst{19-16} = 0; 763 let Inst{15-12} = V4{3-0}; 764 let Inst{11} = V1{4}; 765 let Inst{10} = V2{4}; 766 let Inst{9} = V3{4}; 767 let Inst{8} = V4{4}; 768 let Inst{7-0} = op{7-0}; 769} 770 771class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 772 : InstSystemZ<6, outs, ins, asmstr, pattern> { 773 field bits<48> Inst; 774 field bits<48> SoftFail = 0; 775 776 bits<5> V1; 777 bits<5> V2; 778 bits<5> V3; 779 bits<5> V4; 780 bits<4> M5; 781 bits<4> M6; 782 783 let Inst{47-40} = op{15-8}; 784 let Inst{39-36} = V1{3-0}; 785 let Inst{35-32} = V2{3-0}; 786 let Inst{31-28} = V3{3-0}; 787 let Inst{27-24} = M6; 788 let Inst{23-20} = 0; 789 let Inst{19-16} = M5; 790 let Inst{15-12} = V4{3-0}; 791 let Inst{11} = V1{4}; 792 let Inst{10} = V2{4}; 793 let Inst{9} = V3{4}; 794 let Inst{8} = V4{4}; 795 let Inst{7-0} = op{7-0}; 796} 797 798class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 799 : InstSystemZ<6, outs, ins, asmstr, pattern> { 800 field bits<48> Inst; 801 field bits<48> SoftFail = 0; 802 803 bits<5> V1; 804 bits<4> R2; 805 bits<4> R3; 806 807 let Inst{47-40} = op{15-8}; 808 let Inst{39-36} = V1{3-0}; 809 let Inst{35-32} = R2; 810 let Inst{31-28} = R3; 811 let Inst{27-12} = 0; 812 let Inst{11} = V1{4}; 813 let Inst{10-8} = 0; 814 let Inst{7-0} = op{7-0}; 815} 816 817class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 818 : InstSystemZ<6, outs, ins, asmstr, pattern> { 819 field bits<48> Inst; 820 field bits<48> SoftFail = 0; 821 822 bits<5> V1; 823 bits<16> BD2; 824 bits<5> V3; 825 bits<4> M4; 826 827 let Inst{47-40} = op{15-8}; 828 let Inst{39-36} = V1{3-0}; 829 let Inst{35-32} = V3{3-0}; 830 let Inst{31-16} = BD2; 831 let Inst{15-12} = M4; 832 let Inst{11} = V1{4}; 833 let Inst{10} = V3{4}; 834 let Inst{9-8} = 0; 835 let Inst{7-0} = op{7-0}; 836} 837 838class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 839 : InstSystemZ<6, outs, ins, asmstr, pattern> { 840 field bits<48> Inst; 841 field bits<48> SoftFail = 0; 842 843 bits<5> V1; 844 bits<16> BD2; 845 bits<4> R3; 846 bits<4> M4; 847 848 let Inst{47-40} = op{15-8}; 849 let Inst{39-36} = V1{3-0}; 850 let Inst{35-32} = R3; 851 let Inst{31-16} = BD2; 852 let Inst{15-12} = M4; 853 let Inst{11} = V1{4}; 854 let Inst{10-8} = 0; 855 let Inst{7-0} = op{7-0}; 856} 857 858class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 859 : InstSystemZ<6, outs, ins, asmstr, pattern> { 860 field bits<48> Inst; 861 field bits<48> SoftFail = 0; 862 863 bits<4> R1; 864 bits<16> BD2; 865 bits<5> V3; 866 bits<4> M4; 867 868 let Inst{47-40} = op{15-8}; 869 let Inst{39-36} = R1; 870 let Inst{35-32} = V3{3-0}; 871 let Inst{31-16} = BD2; 872 let Inst{15-12} = M4; 873 let Inst{11} = 0; 874 let Inst{10} = V3{4}; 875 let Inst{9-8} = 0; 876 let Inst{7-0} = op{7-0}; 877} 878 879class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 880 : InstSystemZ<6, outs, ins, asmstr, pattern> { 881 field bits<48> Inst; 882 field bits<48> SoftFail = 0; 883 884 bits<5> V1; 885 bits<21> VBD2; 886 bits<4> M3; 887 888 let Inst{47-40} = op{15-8}; 889 let Inst{39-36} = V1{3-0}; 890 let Inst{35-16} = VBD2{19-0}; 891 let Inst{15-12} = M3; 892 let Inst{11} = V1{4}; 893 let Inst{10} = VBD2{20}; 894 let Inst{9-8} = 0; 895 let Inst{7-0} = op{7-0}; 896} 897 898class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 899 : InstSystemZ<6, outs, ins, asmstr, pattern> { 900 field bits<48> Inst; 901 field bits<48> SoftFail = 0; 902 903 bits<5> V1; 904 bits<20> XBD2; 905 bits<4> M3; 906 907 let Inst{47-40} = op{15-8}; 908 let Inst{39-36} = V1{3-0}; 909 let Inst{35-16} = XBD2; 910 let Inst{15-12} = M3; 911 let Inst{11} = V1{4}; 912 let Inst{10-8} = 0; 913 let Inst{7-0} = op{7-0}; 914} 915 916//===----------------------------------------------------------------------===// 917// Instruction definitions with semantics 918//===----------------------------------------------------------------------===// 919// 920// These classes have the form [Cond]<Category><Format>, where <Format> is one 921// of the formats defined above and where <Category> describes the inputs 922// and outputs. "Cond" is used if the instruction is conditional, 923// in which case the 4-bit condition-code mask is added as a final operand. 924// <Category> can be one of: 925// 926// Inherent: 927// One register output operand and no input operands. 928// 929// BranchUnary: 930// One register output operand, one register input operand and 931// one branch displacement. The instructions stores a modified 932// form of the source register in the destination register and 933// branches on the result. 934// 935// LoadMultiple: 936// One address input operand and two explicit output operands. 937// The instruction loads a range of registers from the address, 938// with the explicit operands giving the first and last register 939// to load. Other loaded registers are added as implicit definitions. 940// 941// StoreMultiple: 942// Two explicit input register operands and an address operand. 943// The instruction stores a range of registers to the address, 944// with the explicit operands giving the first and last register 945// to store. Other stored registers are added as implicit uses. 946// 947// StoreLength: 948// One value operand, one length operand and one address operand. 949// The instruction stores the value operand to the address but 950// doesn't write more than the number of bytes specified by the 951// length operand. 952// 953// Unary: 954// One register output operand and one input operand. 955// 956// Store: 957// One address operand and one other input operand. The instruction 958// stores to the address. 959// 960// Binary: 961// One register output operand and two input operands. 962// 963// StoreBinary: 964// One address operand and two other input operands. The instruction 965// stores to the address. 966// 967// Compare: 968// Two input operands and an implicit CC output operand. 969// 970// Ternary: 971// One register output operand and three input operands. 972// 973// Quaternary: 974// One register output operand and four input operands. 975// 976// LoadAndOp: 977// One output operand and two input operands, one of which is an address. 978// The instruction both reads from and writes to the address. 979// 980// CmpSwap: 981// One output operand and three input operands, one of which is an address. 982// The instruction both reads from and writes to the address. 983// 984// RotateSelect: 985// One output operand and five input operands. The first two operands 986// are registers and the other three are immediates. 987// 988// Prefetch: 989// One 4-bit immediate operand and one address operand. The immediate 990// operand is 1 for a load prefetch and 2 for a store prefetch. 991// 992// The format determines which input operands are tied to output operands, 993// and also determines the shape of any address operand. 994// 995// Multiclasses of the form <Category><Format>Pair define two instructions, 996// one with <Category><Format> and one with <Category><Format>Y. The name 997// of the first instruction has no suffix, the name of the second has 998// an extra "y". 999// 1000//===----------------------------------------------------------------------===// 1001 1002class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 1003 dag src> 1004 : InstRRE<opcode, (outs cls:$R1), (ins), 1005 mnemonic#"\t$R1", 1006 [(set cls:$R1, src)]> { 1007 let R2 = 0; 1008} 1009 1010class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value> 1011 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> { 1012 let I2 = value; 1013 let M3 = 0; 1014} 1015 1016class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls> 1017 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2), 1018 mnemonic##"\t$R1, $I2", []> { 1019 let isBranch = 1; 1020 let isTerminator = 1; 1021 let Constraints = "$R1 = $R1src"; 1022 let DisableEncoding = "$R1src"; 1023} 1024 1025class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 1026 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2), 1027 mnemonic#"\t$R1, $R3, $BD2", []> { 1028 let mayLoad = 1; 1029} 1030 1031class LoadMultipleVRSa<string mnemonic, bits<16> opcode> 1032 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2), 1033 mnemonic#"\t$V1, $V3, $BD2", []> { 1034 let M4 = 0; 1035 let mayLoad = 1; 1036} 1037 1038class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1039 RegisterOperand cls> 1040 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 1041 mnemonic#"\t$R1, $I2", 1042 [(operator cls:$R1, pcrel32:$I2)]> { 1043 let mayStore = 1; 1044 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 1045 // However, BDXs have two extra operands and are therefore 6 units more 1046 // complex. 1047 let AddedComplexity = 7; 1048} 1049 1050class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1051 RegisterOperand cls, bits<5> bytes, 1052 AddressingMode mode = bdxaddr12only> 1053 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1054 mnemonic#"\t$R1, $XBD2", 1055 [(operator cls:$R1, mode:$XBD2)]> { 1056 let OpKey = mnemonic ## cls; 1057 let OpType = "mem"; 1058 let mayStore = 1; 1059 let AccessBytes = bytes; 1060} 1061 1062class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1063 RegisterOperand cls, bits<5> bytes, 1064 AddressingMode mode = bdxaddr20only> 1065 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1066 mnemonic#"\t$R1, $XBD2", 1067 [(operator cls:$R1, mode:$XBD2)]> { 1068 let OpKey = mnemonic ## cls; 1069 let OpType = "mem"; 1070 let mayStore = 1; 1071 let AccessBytes = bytes; 1072} 1073 1074multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1075 SDPatternOperator operator, RegisterOperand cls, 1076 bits<5> bytes> { 1077 let DispKey = mnemonic ## #cls in { 1078 let DispSize = "12" in 1079 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 1080 let DispSize = "20" in 1081 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 1082 bdxaddr20pair>; 1083 } 1084} 1085 1086class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1087 TypedReg tr, bits<5> bytes, bits<4> type = 0> 1088 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2), 1089 mnemonic#"\t$V1, $XBD2", 1090 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> { 1091 let M3 = type; 1092 let mayStore = 1; 1093 let AccessBytes = bytes; 1094} 1095 1096class StoreLengthVRSb<string mnemonic, bits<16> opcode, 1097 SDPatternOperator operator, bits<5> bytes> 1098 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2), 1099 mnemonic#"\t$V1, $R3, $BD2", 1100 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 1101 let M4 = 0; 1102 let mayStore = 1; 1103 let AccessBytes = bytes; 1104} 1105 1106class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 1107 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2), 1108 mnemonic#"\t$R1, $R3, $BD2", []> { 1109 let mayStore = 1; 1110} 1111 1112class StoreMultipleVRSa<string mnemonic, bits<16> opcode> 1113 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2), 1114 mnemonic#"\t$V1, $V3, $BD2", []> { 1115 let M4 = 0; 1116 let mayStore = 1; 1117} 1118 1119// StoreSI* instructions are used to store an integer to memory, but the 1120// addresses are more restricted than for normal stores. If we are in the 1121// situation of having to force either the address into a register or the 1122// constant into a register, it's usually better to do the latter. 1123// We therefore match the address in the same way as a normal store and 1124// only use the StoreSI* instruction if the matched address is suitable. 1125class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1126 Immediate imm> 1127 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2), 1128 mnemonic#"\t$BD1, $I2", 1129 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 1130 let mayStore = 1; 1131} 1132 1133class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1134 Immediate imm> 1135 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2), 1136 mnemonic#"\t$BD1, $I2", 1137 [(operator imm:$I2, mviaddr20pair:$BD1)]> { 1138 let mayStore = 1; 1139} 1140 1141class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1142 Immediate imm> 1143 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2), 1144 mnemonic#"\t$BD1, $I2", 1145 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 1146 let mayStore = 1; 1147} 1148 1149multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 1150 SDPatternOperator operator, Immediate imm> { 1151 let DispKey = mnemonic in { 1152 let DispSize = "12" in 1153 def "" : StoreSI<mnemonic, siOpcode, operator, imm>; 1154 let DispSize = "20" in 1155 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>; 1156 } 1157} 1158 1159class CondStoreRSY<string mnemonic, bits<16> opcode, 1160 RegisterOperand cls, bits<5> bytes, 1161 AddressingMode mode = bdaddr20only> 1162 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), 1163 mnemonic#"$R3\t$R1, $BD2", []>, 1164 Requires<[FeatureLoadStoreOnCond]> { 1165 let mayStore = 1; 1166 let AccessBytes = bytes; 1167 let CCMaskLast = 1; 1168} 1169 1170// Like CondStoreRSY, but used for the raw assembly form. The condition-code 1171// mask is the third operand rather than being part of the mnemonic. 1172class AsmCondStoreRSY<string mnemonic, bits<16> opcode, 1173 RegisterOperand cls, bits<5> bytes, 1174 AddressingMode mode = bdaddr20only> 1175 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3), 1176 mnemonic#"\t$R1, $BD2, $R3", []>, 1177 Requires<[FeatureLoadStoreOnCond]> { 1178 let mayStore = 1; 1179 let AccessBytes = bytes; 1180} 1181 1182// Like CondStoreRSY, but with a fixed CC mask. 1183class FixedCondStoreRSY<string mnemonic, bits<16> opcode, 1184 RegisterOperand cls, bits<4> ccmask, bits<5> bytes, 1185 AddressingMode mode = bdaddr20only> 1186 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2), 1187 mnemonic#"\t$R1, $BD2", []>, 1188 Requires<[FeatureLoadStoreOnCond]> { 1189 let mayStore = 1; 1190 let AccessBytes = bytes; 1191 let R3 = ccmask; 1192} 1193 1194class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1195 RegisterOperand cls1, RegisterOperand cls2> 1196 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2), 1197 mnemonic#"r\t$R1, $R2", 1198 [(set cls1:$R1, (operator cls2:$R2))]> { 1199 let OpKey = mnemonic ## cls1; 1200 let OpType = "reg"; 1201} 1202 1203class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1204 RegisterOperand cls1, RegisterOperand cls2> 1205 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2), 1206 mnemonic#"r\t$R1, $R2", 1207 [(set cls1:$R1, (operator cls2:$R2))]> { 1208 let OpKey = mnemonic ## cls1; 1209 let OpType = "reg"; 1210} 1211 1212class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1213 RegisterOperand cls2> 1214 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2), 1215 mnemonic#"r\t$R1, $R3, $R2", []> { 1216 let OpKey = mnemonic ## cls1; 1217 let OpType = "reg"; 1218 let R4 = 0; 1219} 1220 1221class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1222 RegisterOperand cls2> 1223 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4), 1224 mnemonic#"\t$R1, $R3, $R2, $R4", []>; 1225 1226// These instructions are generated by if conversion. The old value of R1 1227// is added as an implicit use. 1228class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1229 RegisterOperand cls2> 1230 : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3), 1231 mnemonic#"r$R3\t$R1, $R2", []>, 1232 Requires<[FeatureLoadStoreOnCond]> { 1233 let CCMaskLast = 1; 1234 let R4 = 0; 1235} 1236 1237// Like CondUnaryRRF, but used for the raw assembly form. The condition-code 1238// mask is the third operand rather than being part of the mnemonic. 1239class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1240 RegisterOperand cls2> 1241 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3), 1242 mnemonic#"r\t$R1, $R2, $R3", []>, 1243 Requires<[FeatureLoadStoreOnCond]> { 1244 let Constraints = "$R1 = $R1src"; 1245 let DisableEncoding = "$R1src"; 1246 let R4 = 0; 1247} 1248 1249// Like CondUnaryRRF, but with a fixed CC mask. 1250class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1251 RegisterOperand cls2, bits<4> ccmask> 1252 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 1253 mnemonic#"\t$R1, $R2", []>, 1254 Requires<[FeatureLoadStoreOnCond]> { 1255 let Constraints = "$R1 = $R1src"; 1256 let DisableEncoding = "$R1src"; 1257 let R3 = ccmask; 1258 let R4 = 0; 1259} 1260 1261class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1262 RegisterOperand cls, Immediate imm> 1263 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2), 1264 mnemonic#"\t$R1, $I2", 1265 [(set cls:$R1, (operator imm:$I2))]>; 1266 1267class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1268 RegisterOperand cls, Immediate imm> 1269 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2), 1270 mnemonic#"\t$R1, $I2", 1271 [(set cls:$R1, (operator imm:$I2))]>; 1272 1273class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1274 RegisterOperand cls> 1275 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2), 1276 mnemonic#"\t$R1, $I2", 1277 [(set cls:$R1, (operator pcrel32:$I2))]> { 1278 let mayLoad = 1; 1279 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 1280 // However, BDXs have two extra operands and are therefore 6 units more 1281 // complex. 1282 let AddedComplexity = 7; 1283} 1284 1285class CondUnaryRSY<string mnemonic, bits<16> opcode, 1286 SDPatternOperator operator, RegisterOperand cls, 1287 bits<5> bytes, AddressingMode mode = bdaddr20only> 1288 : InstRSY<opcode, (outs cls:$R1), 1289 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3), 1290 mnemonic#"$R3\t$R1, $BD2", 1291 [(set cls:$R1, 1292 (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src, 1293 cond4:$valid, cond4:$R3))]>, 1294 Requires<[FeatureLoadStoreOnCond]> { 1295 let Constraints = "$R1 = $R1src"; 1296 let DisableEncoding = "$R1src"; 1297 let mayLoad = 1; 1298 let AccessBytes = bytes; 1299 let CCMaskLast = 1; 1300} 1301 1302// Like CondUnaryRSY, but used for the raw assembly form. The condition-code 1303// mask is the third operand rather than being part of the mnemonic. 1304class AsmCondUnaryRSY<string mnemonic, bits<16> opcode, 1305 RegisterOperand cls, bits<5> bytes, 1306 AddressingMode mode = bdaddr20only> 1307 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3), 1308 mnemonic#"\t$R1, $BD2, $R3", []>, 1309 Requires<[FeatureLoadStoreOnCond]> { 1310 let mayLoad = 1; 1311 let AccessBytes = bytes; 1312 let Constraints = "$R1 = $R1src"; 1313 let DisableEncoding = "$R1src"; 1314} 1315 1316// Like CondUnaryRSY, but with a fixed CC mask. 1317class FixedCondUnaryRSY<string mnemonic, bits<16> opcode, 1318 RegisterOperand cls, bits<4> ccmask, bits<5> bytes, 1319 AddressingMode mode = bdaddr20only> 1320 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2), 1321 mnemonic#"\t$R1, $BD2", []>, 1322 Requires<[FeatureLoadStoreOnCond]> { 1323 let Constraints = "$R1 = $R1src"; 1324 let DisableEncoding = "$R1src"; 1325 let R3 = ccmask; 1326 let mayLoad = 1; 1327 let AccessBytes = bytes; 1328} 1329 1330class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1331 RegisterOperand cls, bits<5> bytes, 1332 AddressingMode mode = bdxaddr12only> 1333 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2), 1334 mnemonic#"\t$R1, $XBD2", 1335 [(set cls:$R1, (operator mode:$XBD2))]> { 1336 let OpKey = mnemonic ## cls; 1337 let OpType = "mem"; 1338 let mayLoad = 1; 1339 let AccessBytes = bytes; 1340} 1341 1342class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1343 RegisterOperand cls, bits<5> bytes> 1344 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2), 1345 mnemonic#"\t$R1, $XBD2", 1346 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> { 1347 let OpKey = mnemonic ## cls; 1348 let OpType = "mem"; 1349 let mayLoad = 1; 1350 let AccessBytes = bytes; 1351 let M3 = 0; 1352} 1353 1354class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1355 RegisterOperand cls, bits<5> bytes, 1356 AddressingMode mode = bdxaddr20only> 1357 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2), 1358 mnemonic#"\t$R1, $XBD2", 1359 [(set cls:$R1, (operator mode:$XBD2))]> { 1360 let OpKey = mnemonic ## cls; 1361 let OpType = "mem"; 1362 let mayLoad = 1; 1363 let AccessBytes = bytes; 1364} 1365 1366multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1367 SDPatternOperator operator, RegisterOperand cls, 1368 bits<5> bytes> { 1369 let DispKey = mnemonic ## #cls in { 1370 let DispSize = "12" in 1371 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 1372 let DispSize = "20" in 1373 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 1374 bdxaddr20pair>; 1375 } 1376} 1377 1378class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1379 TypedReg tr, Immediate imm, bits<4> type = 0> 1380 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2), 1381 mnemonic#"\t$V1, $I2", 1382 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> { 1383 let M3 = type; 1384} 1385 1386class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1387 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0, 1388 bits<4> m5 = 0> 1389 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2), 1390 mnemonic#"\t$V1, $V2", 1391 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> { 1392 let M3 = type; 1393 let M4 = m4; 1394 let M5 = m5; 1395} 1396 1397multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode, 1398 SDPatternOperator operator, 1399 SDPatternOperator operator_cc, TypedReg tr1, 1400 TypedReg tr2, bits<4> type, bits<4> modifier = 0, 1401 bits<4> modifier_cc = 1> { 1402 def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>; 1403 let Defs = [CC] in 1404 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0, 1405 modifier_cc>; 1406} 1407 1408class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1409 TypedReg tr, bits<5> bytes, bits<4> type = 0> 1410 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2), 1411 mnemonic#"\t$V1, $XBD2", 1412 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> { 1413 let M3 = type; 1414 let mayLoad = 1; 1415 let AccessBytes = bytes; 1416} 1417 1418class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1419 RegisterOperand cls1, RegisterOperand cls2> 1420 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 1421 mnemonic#"r\t$R1, $R2", 1422 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 1423 let OpKey = mnemonic ## cls1; 1424 let OpType = "reg"; 1425 let Constraints = "$R1 = $R1src"; 1426 let DisableEncoding = "$R1src"; 1427} 1428 1429class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1430 RegisterOperand cls1, RegisterOperand cls2> 1431 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 1432 mnemonic#"r\t$R1, $R2", 1433 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 1434 let OpKey = mnemonic ## cls1; 1435 let OpType = "reg"; 1436 let Constraints = "$R1 = $R1src"; 1437 let DisableEncoding = "$R1src"; 1438} 1439 1440class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1441 RegisterOperand cls1, RegisterOperand cls2> 1442 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2), 1443 mnemonic#"r\t$R1, $R3, $R2", 1444 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> { 1445 let OpKey = mnemonic ## cls1; 1446 let OpType = "reg"; 1447 let R4 = 0; 1448} 1449 1450class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1451 RegisterOperand cls1, RegisterOperand cls2> 1452 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3), 1453 mnemonic#"rk\t$R1, $R2, $R3", 1454 [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> { 1455 let R4 = 0; 1456} 1457 1458multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 1459 SDPatternOperator operator, RegisterOperand cls1, 1460 RegisterOperand cls2> { 1461 let NumOpsKey = mnemonic in { 1462 let NumOpsValue = "3" in 1463 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>, 1464 Requires<[FeatureDistinctOps]>; 1465 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1466 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>; 1467 } 1468} 1469 1470multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2, 1471 SDPatternOperator operator, RegisterOperand cls1, 1472 RegisterOperand cls2> { 1473 let NumOpsKey = mnemonic in { 1474 let NumOpsValue = "3" in 1475 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>, 1476 Requires<[FeatureDistinctOps]>; 1477 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1478 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>; 1479 } 1480} 1481 1482class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1483 RegisterOperand cls, Immediate imm> 1484 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 1485 mnemonic#"\t$R1, $I2", 1486 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 1487 let Constraints = "$R1 = $R1src"; 1488 let DisableEncoding = "$R1src"; 1489} 1490 1491class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1492 RegisterOperand cls, Immediate imm> 1493 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2), 1494 mnemonic#"\t$R1, $R3, $I2", 1495 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 1496 1497multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2, 1498 SDPatternOperator operator, RegisterOperand cls, 1499 Immediate imm> { 1500 let NumOpsKey = mnemonic in { 1501 let NumOpsValue = "3" in 1502 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>, 1503 Requires<[FeatureDistinctOps]>; 1504 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1505 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>; 1506 } 1507} 1508 1509class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1510 RegisterOperand cls, Immediate imm> 1511 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 1512 mnemonic#"\t$R1, $I2", 1513 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 1514 let Constraints = "$R1 = $R1src"; 1515 let DisableEncoding = "$R1src"; 1516} 1517 1518class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1519 RegisterOperand cls> 1520 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2), 1521 mnemonic#"\t$R1, $BD2", 1522 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> { 1523 let R3 = 0; 1524 let Constraints = "$R1 = $R1src"; 1525 let DisableEncoding = "$R1src"; 1526} 1527 1528class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1529 RegisterOperand cls> 1530 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2), 1531 mnemonic#"\t$R1, $R3, $BD2", 1532 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>; 1533 1534multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 1535 SDPatternOperator operator, RegisterOperand cls> { 1536 let NumOpsKey = mnemonic in { 1537 let NumOpsValue = "3" in 1538 def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>, 1539 Requires<[FeatureDistinctOps]>; 1540 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1541 def "" : BinaryRS<mnemonic, opcode1, operator, cls>; 1542 } 1543} 1544 1545class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1546 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1547 AddressingMode mode = bdxaddr12only> 1548 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 1549 mnemonic#"\t$R1, $XBD2", 1550 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 1551 let OpKey = mnemonic ## cls; 1552 let OpType = "mem"; 1553 let Constraints = "$R1 = $R1src"; 1554 let DisableEncoding = "$R1src"; 1555 let mayLoad = 1; 1556 let AccessBytes = bytes; 1557} 1558 1559class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1560 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1561 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2), 1562 mnemonic#"\t$R1, $XBD2", 1563 [(set cls:$R1, (operator cls:$R1src, 1564 (load bdxaddr12only:$XBD2)))]> { 1565 let OpKey = mnemonic ## cls; 1566 let OpType = "mem"; 1567 let Constraints = "$R1 = $R1src"; 1568 let DisableEncoding = "$R1src"; 1569 let mayLoad = 1; 1570 let AccessBytes = bytes; 1571 let M3 = 0; 1572} 1573 1574class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1575 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1576 AddressingMode mode = bdxaddr20only> 1577 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 1578 mnemonic#"\t$R1, $XBD2", 1579 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 1580 let OpKey = mnemonic ## cls; 1581 let OpType = "mem"; 1582 let Constraints = "$R1 = $R1src"; 1583 let DisableEncoding = "$R1src"; 1584 let mayLoad = 1; 1585 let AccessBytes = bytes; 1586} 1587 1588multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1589 SDPatternOperator operator, RegisterOperand cls, 1590 SDPatternOperator load, bits<5> bytes> { 1591 let DispKey = mnemonic ## #cls in { 1592 let DispSize = "12" in 1593 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 1594 bdxaddr12pair>; 1595 let DispSize = "20" in 1596 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes, 1597 bdxaddr20pair>; 1598 } 1599} 1600 1601class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1602 Operand imm, AddressingMode mode = bdaddr12only> 1603 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 1604 mnemonic#"\t$BD1, $I2", 1605 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 1606 let mayLoad = 1; 1607 let mayStore = 1; 1608} 1609 1610class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1611 Operand imm, AddressingMode mode = bdaddr20only> 1612 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 1613 mnemonic#"\t$BD1, $I2", 1614 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 1615 let mayLoad = 1; 1616 let mayStore = 1; 1617} 1618 1619multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, 1620 bits<16> siyOpcode, SDPatternOperator operator, 1621 Operand imm> { 1622 let DispKey = mnemonic ## #cls in { 1623 let DispSize = "12" in 1624 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 1625 let DispSize = "20" in 1626 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 1627 } 1628} 1629 1630class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1631 TypedReg tr, bits<4> type> 1632 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3), 1633 mnemonic#"\t$V1, $I2, $I3", 1634 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> { 1635 let M4 = type; 1636} 1637 1638class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1639 TypedReg tr1, TypedReg tr2, bits<4> type> 1640 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2), 1641 mnemonic#"\t$V1, $V3, $I2", 1642 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3), 1643 imm32zx16:$I2)))]> { 1644 let M4 = type; 1645} 1646 1647class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1648 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5> 1649 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3), 1650 mnemonic#"\t$V1, $V2, $I3", 1651 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1652 imm32zx12:$I3)))]> { 1653 let M4 = type; 1654 let M5 = m5; 1655} 1656 1657class BinaryVRRa<string mnemonic, bits<16> opcode> 1658 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), 1659 mnemonic#"\t$V1, $V2, $M3", []> { 1660 let M4 = 0; 1661 let M5 = 0; 1662} 1663 1664class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1665 TypedReg tr1, TypedReg tr2, bits<4> type = 0, 1666 bits<4> modifier = 0> 1667 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 1668 mnemonic#"\t$V1, $V2, $V3", 1669 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1670 (tr2.vt tr2.op:$V3))))]> { 1671 let M4 = type; 1672 let M5 = modifier; 1673} 1674 1675// Declare a pair of instructions, one which sets CC and one which doesn't. 1676// The CC-setting form ends with "S" and sets the low bit of M5. 1677multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode, 1678 SDPatternOperator operator, 1679 SDPatternOperator operator_cc, TypedReg tr1, 1680 TypedReg tr2, bits<4> type, 1681 bits<4> modifier = 0, bits<4> modifier_cc = 1> { 1682 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>; 1683 let Defs = [CC] in 1684 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1685 modifier_cc>; 1686} 1687 1688class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1689 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0, 1690 bits<4> m6 = 0> 1691 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 1692 mnemonic#"\t$V1, $V2, $V3", 1693 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1694 (tr2.vt tr2.op:$V3))))]> { 1695 let M4 = type; 1696 let M5 = m5; 1697 let M6 = m6; 1698} 1699 1700multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode, 1701 SDPatternOperator operator, 1702 SDPatternOperator operator_cc, TypedReg tr1, 1703 TypedReg tr2, bits<4> type, bits<4> m5, 1704 bits<4> modifier = 0, bits<4> modifier_cc = 1> { 1705 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>; 1706 let Defs = [CC] in 1707 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1708 m5, modifier_cc>; 1709} 1710 1711class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1712 TypedReg tr> 1713 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3), 1714 mnemonic#"\t$V1, $R2, $R3", 1715 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>; 1716 1717class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1718 TypedReg tr1, TypedReg tr2, bits<4> type> 1719 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2), 1720 mnemonic#"\t$V1, $V3, $BD2", 1721 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3), 1722 shift12only:$BD2)))]> { 1723 let M4 = type; 1724} 1725 1726class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1727 bits<5> bytes> 1728 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2), 1729 mnemonic#"\t$V1, $R3, $BD2", 1730 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 1731 let M4 = 0; 1732 let mayLoad = 1; 1733 let AccessBytes = bytes; 1734} 1735 1736class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1737 TypedReg tr, bits<4> type> 1738 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2), 1739 mnemonic#"\t$R1, $V3, $BD2", 1740 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> { 1741 let M4 = type; 1742} 1743 1744class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1745 TypedReg tr, bits<5> bytes> 1746 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 1747 mnemonic#"\t$V1, $XBD2, $M3", 1748 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2, 1749 imm32zx4:$M3)))]> { 1750 let mayLoad = 1; 1751 let AccessBytes = bytes; 1752} 1753 1754class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 1755 Immediate index> 1756 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3), 1757 mnemonic#"\t$V1, $VBD2, $M3", []> { 1758 let mayStore = 1; 1759 let AccessBytes = bytes; 1760} 1761 1762class StoreBinaryVRX<string mnemonic, bits<16> opcode, 1763 SDPatternOperator operator, TypedReg tr, bits<5> bytes, 1764 Immediate index> 1765 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3), 1766 mnemonic#"\t$V1, $XBD2, $M3", 1767 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> { 1768 let mayStore = 1; 1769 let AccessBytes = bytes; 1770} 1771 1772class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1773 RegisterOperand cls1, RegisterOperand cls2> 1774 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), 1775 mnemonic#"r\t$R1, $R2", 1776 [(operator cls1:$R1, cls2:$R2)]> { 1777 let OpKey = mnemonic ## cls1; 1778 let OpType = "reg"; 1779 let isCompare = 1; 1780} 1781 1782class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1783 RegisterOperand cls1, RegisterOperand cls2> 1784 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 1785 mnemonic#"r\t$R1, $R2", 1786 [(operator cls1:$R1, cls2:$R2)]> { 1787 let OpKey = mnemonic ## cls1; 1788 let OpType = "reg"; 1789 let isCompare = 1; 1790} 1791 1792class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1793 RegisterOperand cls, Immediate imm> 1794 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2), 1795 mnemonic#"\t$R1, $I2", 1796 [(operator cls:$R1, imm:$I2)]> { 1797 let isCompare = 1; 1798} 1799 1800class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1801 RegisterOperand cls, Immediate imm> 1802 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2), 1803 mnemonic#"\t$R1, $I2", 1804 [(operator cls:$R1, imm:$I2)]> { 1805 let isCompare = 1; 1806} 1807 1808class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1809 RegisterOperand cls, SDPatternOperator load> 1810 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 1811 mnemonic#"\t$R1, $I2", 1812 [(operator cls:$R1, (load pcrel32:$I2))]> { 1813 let isCompare = 1; 1814 let mayLoad = 1; 1815 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 1816 // However, BDXs have two extra operands and are therefore 6 units more 1817 // complex. 1818 let AddedComplexity = 7; 1819} 1820 1821class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1822 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1823 AddressingMode mode = bdxaddr12only> 1824 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1825 mnemonic#"\t$R1, $XBD2", 1826 [(operator cls:$R1, (load mode:$XBD2))]> { 1827 let OpKey = mnemonic ## cls; 1828 let OpType = "mem"; 1829 let isCompare = 1; 1830 let mayLoad = 1; 1831 let AccessBytes = bytes; 1832} 1833 1834class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1835 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1836 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2), 1837 mnemonic#"\t$R1, $XBD2", 1838 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> { 1839 let OpKey = mnemonic ## cls; 1840 let OpType = "mem"; 1841 let isCompare = 1; 1842 let mayLoad = 1; 1843 let AccessBytes = bytes; 1844 let M3 = 0; 1845} 1846 1847class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1848 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1849 AddressingMode mode = bdxaddr20only> 1850 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1851 mnemonic#"\t$R1, $XBD2", 1852 [(operator cls:$R1, (load mode:$XBD2))]> { 1853 let OpKey = mnemonic ## cls; 1854 let OpType = "mem"; 1855 let isCompare = 1; 1856 let mayLoad = 1; 1857 let AccessBytes = bytes; 1858} 1859 1860multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1861 SDPatternOperator operator, RegisterOperand cls, 1862 SDPatternOperator load, bits<5> bytes> { 1863 let DispKey = mnemonic ## #cls in { 1864 let DispSize = "12" in 1865 def "" : CompareRX<mnemonic, rxOpcode, operator, cls, 1866 load, bytes, bdxaddr12pair>; 1867 let DispSize = "20" in 1868 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls, 1869 load, bytes, bdxaddr20pair>; 1870 } 1871} 1872 1873class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1874 SDPatternOperator load, Immediate imm, 1875 AddressingMode mode = bdaddr12only> 1876 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 1877 mnemonic#"\t$BD1, $I2", 1878 [(operator (load mode:$BD1), imm:$I2)]> { 1879 let isCompare = 1; 1880 let mayLoad = 1; 1881} 1882 1883class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1884 SDPatternOperator load, Immediate imm> 1885 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 1886 mnemonic#"\t$BD1, $I2", 1887 [(operator (load bdaddr12only:$BD1), imm:$I2)]> { 1888 let isCompare = 1; 1889 let mayLoad = 1; 1890} 1891 1892class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1893 SDPatternOperator load, Immediate imm, 1894 AddressingMode mode = bdaddr20only> 1895 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 1896 mnemonic#"\t$BD1, $I2", 1897 [(operator (load mode:$BD1), imm:$I2)]> { 1898 let isCompare = 1; 1899 let mayLoad = 1; 1900} 1901 1902multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 1903 SDPatternOperator operator, SDPatternOperator load, 1904 Immediate imm> { 1905 let DispKey = mnemonic in { 1906 let DispSize = "12" in 1907 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>; 1908 let DispSize = "20" in 1909 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm, 1910 bdaddr20pair>; 1911 } 1912} 1913 1914class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1915 TypedReg tr, bits<4> type> 1916 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2), 1917 mnemonic#"\t$V1, $V2", 1918 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> { 1919 let isCompare = 1; 1920 let M3 = type; 1921 let M4 = 0; 1922 let M5 = 0; 1923} 1924 1925class TernaryRRD<string mnemonic, bits<16> opcode, 1926 SDPatternOperator operator, RegisterOperand cls> 1927 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2), 1928 mnemonic#"r\t$R1, $R3, $R2", 1929 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> { 1930 let OpKey = mnemonic ## cls; 1931 let OpType = "reg"; 1932 let Constraints = "$R1 = $R1src"; 1933 let DisableEncoding = "$R1src"; 1934} 1935 1936class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1937 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1938 : InstRXF<opcode, (outs cls:$R1), 1939 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2), 1940 mnemonic#"\t$R1, $R3, $XBD2", 1941 [(set cls:$R1, (operator cls:$R1src, cls:$R3, 1942 (load bdxaddr12only:$XBD2)))]> { 1943 let OpKey = mnemonic ## cls; 1944 let OpType = "mem"; 1945 let Constraints = "$R1 = $R1src"; 1946 let DisableEncoding = "$R1src"; 1947 let mayLoad = 1; 1948 let AccessBytes = bytes; 1949} 1950 1951class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1952 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index> 1953 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3), 1954 mnemonic#"\t$V1, $I2, $M3", 1955 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 1956 imm:$I2, index:$M3)))]> { 1957 let Constraints = "$V1 = $V1src"; 1958 let DisableEncoding = "$V1src"; 1959} 1960 1961class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1962 TypedReg tr1, TypedReg tr2, bits<4> type> 1963 : InstVRId<opcode, (outs tr1.op:$V1), 1964 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 1965 mnemonic#"\t$V1, $V2, $V3, $I4", 1966 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1967 (tr2.vt tr2.op:$V3), 1968 imm32zx8:$I4)))]> { 1969 let M5 = type; 1970} 1971 1972class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1973 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or> 1974 : InstVRRa<opcode, (outs tr1.op:$V1), 1975 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5), 1976 mnemonic#"\t$V1, $V2, $M4, $M5", 1977 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1978 imm32zx4:$M4, 1979 imm32zx4:$M5)))], 1980 m4or> { 1981 let M3 = type; 1982} 1983 1984class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1985 TypedReg tr1, TypedReg tr2, bits<4> type, 1986 SDPatternOperator m5mask, bits<4> m5or> 1987 : InstVRRb<opcode, (outs tr1.op:$V1), 1988 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5), 1989 mnemonic#"\t$V1, $V2, $V3, $M5", 1990 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1991 (tr2.vt tr2.op:$V3), 1992 m5mask:$M5)))], 1993 m5or> { 1994 let M4 = type; 1995} 1996 1997multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode, 1998 SDPatternOperator operator, 1999 SDPatternOperator operator_cc, TypedReg tr1, 2000 TypedReg tr2, bits<4> type, bits<4> m5or> { 2001 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 2002 imm32zx4even, !and (m5or, 14)>; 2003 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 2004 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 2005 tr2.op:$V3, 0)>; 2006 let Defs = [CC] in 2007 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 2008 imm32zx4even, !add(!and (m5or, 14), 1)>; 2009 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3", 2010 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 2011 tr2.op:$V3, 0)>; 2012} 2013 2014class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2015 TypedReg tr1, TypedReg tr2> 2016 : InstVRRc<opcode, (outs tr1.op:$V1), 2017 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4), 2018 mnemonic#"\t$V1, $V2, $V3, $M4", 2019 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 2020 (tr2.vt tr2.op:$V3), 2021 imm32zx4:$M4)))]> { 2022 let M5 = 0; 2023 let M6 = 0; 2024} 2025 2026class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2027 TypedReg tr1, TypedReg tr2, bits<4> type = 0> 2028 : InstVRRd<opcode, (outs tr1.op:$V1), 2029 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 2030 mnemonic#"\t$V1, $V2, $V3, $V4", 2031 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 2032 (tr2.vt tr2.op:$V3), 2033 (tr1.vt tr1.op:$V4))))]> { 2034 let M5 = type; 2035 let M6 = 0; 2036} 2037 2038class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2039 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0> 2040 : InstVRRe<opcode, (outs tr1.op:$V1), 2041 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 2042 mnemonic#"\t$V1, $V2, $V3, $V4", 2043 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 2044 (tr2.vt tr2.op:$V3), 2045 (tr1.vt tr1.op:$V4))))]> { 2046 let M5 = m5; 2047 let M6 = type; 2048} 2049 2050class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2051 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type> 2052 : InstVRSb<opcode, (outs tr1.op:$V1), 2053 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2), 2054 mnemonic#"\t$V1, $R3, $BD2", 2055 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 2056 cls:$R3, 2057 shift12only:$BD2)))]> { 2058 let Constraints = "$V1 = $V1src"; 2059 let DisableEncoding = "$V1src"; 2060 let M4 = type; 2061} 2062 2063class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 2064 Immediate index> 2065 : InstVRV<opcode, (outs VR128:$V1), 2066 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3), 2067 mnemonic#"\t$V1, $VBD2, $M3", []> { 2068 let Constraints = "$V1 = $V1src"; 2069 let DisableEncoding = "$V1src"; 2070 let mayLoad = 1; 2071 let AccessBytes = bytes; 2072} 2073 2074class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2075 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index> 2076 : InstVRX<opcode, (outs tr1.op:$V1), 2077 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3), 2078 mnemonic#"\t$V1, $XBD2, $M3", 2079 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 2080 bdxaddr12only:$XBD2, 2081 index:$M3)))]> { 2082 let Constraints = "$V1 = $V1src"; 2083 let DisableEncoding = "$V1src"; 2084 let mayLoad = 1; 2085 let AccessBytes = bytes; 2086} 2087 2088class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2089 TypedReg tr1, TypedReg tr2, bits<4> type> 2090 : InstVRId<opcode, (outs tr1.op:$V1), 2091 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 2092 mnemonic#"\t$V1, $V2, $V3, $I4", 2093 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 2094 (tr2.vt tr2.op:$V2), 2095 (tr2.vt tr2.op:$V3), 2096 imm32zx8:$I4)))]> { 2097 let Constraints = "$V1 = $V1src"; 2098 let DisableEncoding = "$V1src"; 2099 let M5 = type; 2100} 2101 2102class QuaternaryVRRd<string mnemonic, bits<16> opcode, 2103 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 2104 bits<4> type, SDPatternOperator m6mask, bits<4> m6or> 2105 : InstVRRd<opcode, (outs tr1.op:$V1), 2106 (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6), 2107 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", 2108 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 2109 (tr2.vt tr2.op:$V3), 2110 (tr2.vt tr2.op:$V4), 2111 m6mask:$M6)))], 2112 m6or> { 2113 let M5 = type; 2114} 2115 2116multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode, 2117 SDPatternOperator operator, 2118 SDPatternOperator operator_cc, TypedReg tr1, 2119 TypedReg tr2, bits<4> type, bits<4> m6or> { 2120 def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type, 2121 imm32zx4even, !and (m6or, 14)>; 2122 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 2123 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 2124 tr2.op:$V3, tr2.op:$V4, 0)>; 2125 let Defs = [CC] in 2126 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 2127 imm32zx4even, !add (!and (m6or, 14), 1)>; 2128 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4", 2129 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 2130 tr2.op:$V3, tr2.op:$V4, 0)>; 2131} 2132 2133class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2134 RegisterOperand cls, AddressingMode mode = bdaddr20only> 2135 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2), 2136 mnemonic#"\t$R1, $R3, $BD2", 2137 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> { 2138 let mayLoad = 1; 2139 let mayStore = 1; 2140} 2141 2142class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2143 RegisterOperand cls, AddressingMode mode = bdaddr12only> 2144 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 2145 mnemonic#"\t$R1, $R3, $BD2", 2146 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 2147 let Constraints = "$R1 = $R1src"; 2148 let DisableEncoding = "$R1src"; 2149 let mayLoad = 1; 2150 let mayStore = 1; 2151} 2152 2153class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2154 RegisterOperand cls, AddressingMode mode = bdaddr20only> 2155 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 2156 mnemonic#"\t$R1, $R3, $BD2", 2157 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 2158 let Constraints = "$R1 = $R1src"; 2159 let DisableEncoding = "$R1src"; 2160 let mayLoad = 1; 2161 let mayStore = 1; 2162} 2163 2164multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 2165 SDPatternOperator operator, RegisterOperand cls> { 2166 let DispKey = mnemonic ## #cls in { 2167 let DispSize = "12" in 2168 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>; 2169 let DispSize = "20" in 2170 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>; 2171 } 2172} 2173 2174class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1, 2175 RegisterOperand cls2> 2176 : InstRIEf<opcode, (outs cls1:$R1), 2177 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 2178 imm32zx6:$I5), 2179 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> { 2180 let Constraints = "$R1 = $R1src"; 2181 let DisableEncoding = "$R1src"; 2182} 2183 2184class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator> 2185 : InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2), 2186 mnemonic##"\t$R1, $XBD2", 2187 [(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>; 2188 2189class PrefetchRILPC<string mnemonic, bits<12> opcode, 2190 SDPatternOperator operator> 2191 : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2), 2192 mnemonic##"\t$R1, $I2", 2193 [(operator imm32zx4:$R1, pcrel32:$I2)]> { 2194 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 2195 // However, BDXs have two extra operands and are therefore 6 units more 2196 // complex. 2197 let AddedComplexity = 7; 2198} 2199 2200// A floating-point load-and test operation. Create both a normal unary 2201// operation and one that acts as a comparison against zero. 2202// Note that the comparison against zero operation is not available if we 2203// have vector support, since load-and-test instructions will partially 2204// clobber the target (vector) register. 2205multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode, 2206 RegisterOperand cls> { 2207 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>; 2208 let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in 2209 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>; 2210} 2211 2212//===----------------------------------------------------------------------===// 2213// Pseudo instructions 2214//===----------------------------------------------------------------------===// 2215// 2216// Convenience instructions that get lowered to real instructions 2217// by either SystemZTargetLowering::EmitInstrWithCustomInserter() 2218// or SystemZInstrInfo::expandPostRAPseudo(). 2219// 2220//===----------------------------------------------------------------------===// 2221 2222class Pseudo<dag outs, dag ins, list<dag> pattern> 2223 : InstSystemZ<0, outs, ins, "", pattern> { 2224 let isPseudo = 1; 2225 let isCodeGenOnly = 1; 2226} 2227 2228// Like UnaryRI, but expanded after RA depending on the choice of register. 2229class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 2230 Immediate imm> 2231 : Pseudo<(outs cls:$R1), (ins imm:$I2), 2232 [(set cls:$R1, (operator imm:$I2))]>; 2233 2234// Like UnaryRXY, but expanded after RA depending on the choice of register. 2235class UnaryRXYPseudo<string key, SDPatternOperator operator, 2236 RegisterOperand cls, bits<5> bytes, 2237 AddressingMode mode = bdxaddr20only> 2238 : Pseudo<(outs cls:$R1), (ins mode:$XBD2), 2239 [(set cls:$R1, (operator mode:$XBD2))]> { 2240 let OpKey = key ## cls; 2241 let OpType = "mem"; 2242 let mayLoad = 1; 2243 let Has20BitOffset = 1; 2244 let HasIndex = 1; 2245 let AccessBytes = bytes; 2246} 2247 2248// Like UnaryRR, but expanded after RA depending on the choice of registers. 2249class UnaryRRPseudo<string key, SDPatternOperator operator, 2250 RegisterOperand cls1, RegisterOperand cls2> 2251 : Pseudo<(outs cls1:$R1), (ins cls2:$R2), 2252 [(set cls1:$R1, (operator cls2:$R2))]> { 2253 let OpKey = key ## cls1; 2254 let OpType = "reg"; 2255} 2256 2257// Like BinaryRI, but expanded after RA depending on the choice of register. 2258class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 2259 Immediate imm> 2260 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2), 2261 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 2262 let Constraints = "$R1 = $R1src"; 2263} 2264 2265// Like BinaryRIE, but expanded after RA depending on the choice of register. 2266class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls, 2267 Immediate imm> 2268 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2), 2269 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 2270 2271// Like BinaryRIAndK, but expanded after RA depending on the choice of register. 2272multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator, 2273 RegisterOperand cls, Immediate imm> { 2274 let NumOpsKey = key in { 2275 let NumOpsValue = "3" in 2276 def K : BinaryRIEPseudo<null_frag, cls, imm>, 2277 Requires<[FeatureHighWord, FeatureDistinctOps]>; 2278 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 2279 def "" : BinaryRIPseudo<operator, cls, imm>, 2280 Requires<[FeatureHighWord]>; 2281 } 2282} 2283 2284// Like CompareRI, but expanded after RA depending on the choice of register. 2285class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls, 2286 Immediate imm> 2287 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>; 2288 2289// Like CompareRXY, but expanded after RA depending on the choice of register. 2290class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 2291 SDPatternOperator load, bits<5> bytes, 2292 AddressingMode mode = bdxaddr20only> 2293 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2), 2294 [(operator cls:$R1, (load mode:$XBD2))]> { 2295 let mayLoad = 1; 2296 let Has20BitOffset = 1; 2297 let HasIndex = 1; 2298 let AccessBytes = bytes; 2299} 2300 2301// Like StoreRXY, but expanded after RA depending on the choice of register. 2302class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 2303 bits<5> bytes, AddressingMode mode = bdxaddr20only> 2304 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2), 2305 [(operator cls:$R1, mode:$XBD2)]> { 2306 let mayStore = 1; 2307 let Has20BitOffset = 1; 2308 let HasIndex = 1; 2309 let AccessBytes = bytes; 2310} 2311 2312// Like RotateSelectRIEf, but expanded after RA depending on the choice 2313// of registers. 2314class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2> 2315 : Pseudo<(outs cls1:$R1), 2316 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 2317 imm32zx6:$I5), 2318 []> { 2319 let Constraints = "$R1 = $R1src"; 2320 let DisableEncoding = "$R1src"; 2321} 2322 2323// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is 2324// the value of the PSW's 2-bit condition code field. 2325class SelectWrapper<RegisterOperand cls> 2326 : Pseudo<(outs cls:$dst), 2327 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc), 2328 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, 2329 imm32zx4:$valid, imm32zx4:$cc))]> { 2330 let usesCustomInserter = 1; 2331 // Although the instructions used by these nodes do not in themselves 2332 // change CC, the insertion requires new blocks, and CC cannot be live 2333 // across them. 2334 let Defs = [CC]; 2335 let Uses = [CC]; 2336} 2337 2338// Stores $new to $addr if $cc is true ("" case) or false (Inv case). 2339multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 2340 SDPatternOperator load, AddressingMode mode> { 2341 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in { 2342 def "" : Pseudo<(outs), 2343 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 2344 [(store (z_select_ccmask cls:$new, (load mode:$addr), 2345 imm32zx4:$valid, imm32zx4:$cc), 2346 mode:$addr)]>; 2347 def Inv : Pseudo<(outs), 2348 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 2349 [(store (z_select_ccmask (load mode:$addr), cls:$new, 2350 imm32zx4:$valid, imm32zx4:$cc), 2351 mode:$addr)]>; 2352 } 2353} 2354 2355// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND 2356// describe the second (non-memory) operand. 2357class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls, 2358 dag pat, DAGOperand operand> 2359 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2), 2360 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> { 2361 let Defs = [CC]; 2362 let Has20BitOffset = 1; 2363 let mayLoad = 1; 2364 let mayStore = 1; 2365 let usesCustomInserter = 1; 2366} 2367 2368// Specializations of AtomicLoadWBinary. 2369class AtomicLoadBinaryReg32<SDPatternOperator operator> 2370 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>; 2371class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm> 2372 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>; 2373class AtomicLoadBinaryReg64<SDPatternOperator operator> 2374 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>; 2375class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm> 2376 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>; 2377 2378// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND 2379// describe the second (non-memory) operand. 2380class AtomicLoadWBinary<SDPatternOperator operator, dag pat, 2381 DAGOperand operand> 2382 : Pseudo<(outs GR32:$dst), 2383 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift, 2384 ADDR32:$negbitshift, uimm32:$bitsize), 2385 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift, 2386 ADDR32:$negbitshift, uimm32:$bitsize))]> { 2387 let Defs = [CC]; 2388 let Has20BitOffset = 1; 2389 let mayLoad = 1; 2390 let mayStore = 1; 2391 let usesCustomInserter = 1; 2392} 2393 2394// Specializations of AtomicLoadWBinary. 2395class AtomicLoadWBinaryReg<SDPatternOperator operator> 2396 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>; 2397class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm> 2398 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>; 2399 2400// Define an instruction that operates on two fixed-length blocks of memory, 2401// and associated pseudo instructions for operating on blocks of any size. 2402// The Sequence form uses a straight-line sequence of instructions and 2403// the Loop form uses a loop of length-256 instructions followed by 2404// another instruction to handle the excess. 2405multiclass MemorySS<string mnemonic, bits<8> opcode, 2406 SDPatternOperator sequence, SDPatternOperator loop> { 2407 def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, 2408 bdaddr12only:$BD2), 2409 mnemonic##"\t$BDL1, $BD2", []>; 2410 let usesCustomInserter = 1 in { 2411 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 2412 imm64:$length), 2413 [(sequence bdaddr12only:$dest, bdaddr12only:$src, 2414 imm64:$length)]>; 2415 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 2416 imm64:$length, GR64:$count256), 2417 [(loop bdaddr12only:$dest, bdaddr12only:$src, 2418 imm64:$length, GR64:$count256)]>; 2419 } 2420} 2421 2422// Define an instruction that operates on two strings, both terminated 2423// by the character in R0. The instruction processes a CPU-determinated 2424// number of bytes at a time and sets CC to 3 if the instruction needs 2425// to be repeated. Also define a pseudo instruction that represents 2426// the full loop (the main instruction plus the branch on CC==3). 2427multiclass StringRRE<string mnemonic, bits<16> opcode, 2428 SDPatternOperator operator> { 2429 def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2), 2430 (ins GR64:$R1src, GR64:$R2src), 2431 mnemonic#"\t$R1, $R2", []> { 2432 let Uses = [R0L]; 2433 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 2434 let DisableEncoding = "$R1src, $R2src"; 2435 } 2436 let usesCustomInserter = 1 in 2437 def Loop : Pseudo<(outs GR64:$end), 2438 (ins GR64:$start1, GR64:$start2, GR32:$char), 2439 [(set GR64:$end, (operator GR64:$start1, GR64:$start2, 2440 GR32:$char))]>; 2441} 2442 2443// A pseudo instruction that is a direct alias of a real instruction. 2444// These aliases are used in cases where a particular register operand is 2445// fixed or where the same instruction is used with different register sizes. 2446// The size parameter is the size in bytes of the associated real instruction. 2447class Alias<int size, dag outs, dag ins, list<dag> pattern> 2448 : InstSystemZ<size, outs, ins, "", pattern> { 2449 let isPseudo = 1; 2450 let isCodeGenOnly = 1; 2451} 2452 2453class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2> 2454 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>; 2455 2456// An alias of a UnaryVRR*, but with different register sizes. 2457class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2> 2458 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2), 2459 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>; 2460 2461// An alias of a UnaryVRX, but with different register sizes. 2462class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr, 2463 AddressingMode mode = bdxaddr12only> 2464 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2), 2465 [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>; 2466 2467// An alias of a StoreVRX, but with different register sizes. 2468class StoreAliasVRX<SDPatternOperator operator, TypedReg tr, 2469 AddressingMode mode = bdxaddr12only> 2470 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2), 2471 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>; 2472 2473// An alias of a BinaryRI, but with different register sizes. 2474class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls, 2475 Immediate imm> 2476 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 2477 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 2478 let Constraints = "$R1 = $R1src"; 2479} 2480 2481// An alias of a BinaryRIL, but with different register sizes. 2482class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls, 2483 Immediate imm> 2484 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 2485 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 2486 let Constraints = "$R1 = $R1src"; 2487} 2488 2489// An alias of a BinaryVRRf, but with different register sizes. 2490class BinaryAliasVRRf<RegisterOperand cls> 2491 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>; 2492 2493// An alias of a CompareRI, but with different register sizes. 2494class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls, 2495 Immediate imm> 2496 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> { 2497 let isCompare = 1; 2498} 2499 2500// An alias of a RotateSelectRIEf, but with different register sizes. 2501class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2> 2502 : Alias<6, (outs cls1:$R1), 2503 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 2504 imm32zx6:$I5), []> { 2505 let Constraints = "$R1 = $R1src"; 2506} 2507