1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Basic SystemZ instruction definition
12//===----------------------------------------------------------------------===//
13
14class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15                  list<dag> pattern> : Instruction {
16  let Namespace = "SystemZ";
17
18  dag OutOperandList = outs;
19  dag InOperandList = ins;
20  let Size = size;
21  let Pattern = pattern;
22  let AsmString = asmstr;
23
24  // Some instructions come in pairs, one having a 12-bit displacement
25  // and the other having a 20-bit displacement.  Both instructions in
26  // the pair have the same DispKey and their DispSizes are "12" and "20"
27  // respectively.
28  string DispKey = "";
29  string DispSize = "none";
30
31  // Many register-based <INSN>R instructions have a memory-based <INSN>
32  // counterpart.  OpKey uniquely identifies <INSN>R, while OpType is
33  // "reg" for <INSN>R and "mem" for <INSN>.
34  string OpKey = "";
35  string OpType = "none";
36
37  // Many distinct-operands instructions have older 2-operand equivalents.
38  // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39  // with NumOpsValue being "2" or "3" as appropriate.
40  string NumOpsKey = "";
41  string NumOpsValue = "none";
42
43  // True if this instruction is a simple D(X,B) load of a register
44  // (with no sign or zero extension).
45  bit SimpleBDXLoad = 0;
46
47  // True if this instruction is a simple D(X,B) store of a register
48  // (with no truncation).
49  bit SimpleBDXStore = 0;
50
51  // True if this instruction has a 20-bit displacement field.
52  bit Has20BitOffset = 0;
53
54  // True if addresses in this instruction have an index register.
55  bit HasIndex = 0;
56
57  // True if this is a 128-bit pseudo instruction that combines two 64-bit
58  // operations.
59  bit Is128Bit = 0;
60
61  // The access size of all memory operands in bytes, or 0 if not known.
62  bits<5> AccessBytes = 0;
63
64  // If the instruction sets CC to a useful value, this gives the mask
65  // of all possible CC results.  The mask has the same form as
66  // SystemZ::CCMASK_*.
67  bits<4> CCValues = 0;
68
69  // The subset of CCValues that have the same meaning as they would after
70  // a comparison of the first operand against zero.
71  bits<4> CompareZeroCCMask = 0;
72
73  // True if the instruction is conditional and if the CC mask operand
74  // comes first (as for BRC, etc.).
75  bit CCMaskFirst = 0;
76
77  // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
78  bit CCMaskLast = 0;
79
80  // True if the instruction is the "logical" rather than "arithmetic" form,
81  // in cases where a distinction exists.
82  bit IsLogical = 0;
83
84  let TSFlags{0}     = SimpleBDXLoad;
85  let TSFlags{1}     = SimpleBDXStore;
86  let TSFlags{2}     = Has20BitOffset;
87  let TSFlags{3}     = HasIndex;
88  let TSFlags{4}     = Is128Bit;
89  let TSFlags{9-5}   = AccessBytes;
90  let TSFlags{13-10} = CCValues;
91  let TSFlags{17-14} = CompareZeroCCMask;
92  let TSFlags{18}    = CCMaskFirst;
93  let TSFlags{19}    = CCMaskLast;
94  let TSFlags{20}    = IsLogical;
95}
96
97//===----------------------------------------------------------------------===//
98// Mappings between instructions
99//===----------------------------------------------------------------------===//
100
101// Return the version of an instruction that has an unsigned 12-bit
102// displacement.
103def getDisp12Opcode : InstrMapping {
104  let FilterClass = "InstSystemZ";
105  let RowFields = ["DispKey"];
106  let ColFields = ["DispSize"];
107  let KeyCol = ["20"];
108  let ValueCols = [["12"]];
109}
110
111// Return the version of an instruction that has a signed 20-bit displacement.
112def getDisp20Opcode : InstrMapping {
113  let FilterClass = "InstSystemZ";
114  let RowFields = ["DispKey"];
115  let ColFields = ["DispSize"];
116  let KeyCol = ["12"];
117  let ValueCols = [["20"]];
118}
119
120// Return the memory form of a register instruction.
121def getMemOpcode : InstrMapping {
122  let FilterClass = "InstSystemZ";
123  let RowFields = ["OpKey"];
124  let ColFields = ["OpType"];
125  let KeyCol = ["reg"];
126  let ValueCols = [["mem"]];
127}
128
129// Return the 3-operand form of a 2-operand instruction.
130def getThreeOperandOpcode : InstrMapping {
131  let FilterClass = "InstSystemZ";
132  let RowFields = ["NumOpsKey"];
133  let ColFields = ["NumOpsValue"];
134  let KeyCol = ["2"];
135  let ValueCols = [["3"]];
136}
137
138//===----------------------------------------------------------------------===//
139// Instruction formats
140//===----------------------------------------------------------------------===//
141//
142// Formats are specified using operand field declarations of the form:
143//
144//   bits<4> Rn   : register input or output for operand n
145//   bits<5> Vn   : vector register input or output for operand n
146//   bits<m> In   : immediate value of width m for operand n
147//   bits<4> BDn  : address operand n, which has a base and a displacement
148//   bits<m> XBDn : address operand n, which has an index, a base and a
149//                  displacement
150//   bits<m> VBDn : address operand n, which has a vector index, a base and a
151//                  displacement
152//   bits<4> Xn   : index register for address operand n
153//   bits<4> Mn   : mode value for operand n
154//
155// The operand numbers ("n" in the list above) follow the architecture manual.
156// Assembly operands sometimes have a different order; in particular, R3 often
157// is often written between operands 1 and 2.
158//
159//===----------------------------------------------------------------------===//
160
161class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162  : InstSystemZ<2, outs, ins, asmstr, pattern> {
163  field bits<16> Inst;
164  field bits<16> SoftFail = 0;
165
166  let Inst = op;
167}
168
169class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
170  : InstSystemZ<2, outs, ins, asmstr, pattern> {
171  field bits<16> Inst;
172  field bits<16> SoftFail = 0;
173
174  bits<8> I1;
175
176  let Inst{15-8} = op;
177  let Inst{7-0}  = I1;
178}
179
180class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
181  : InstSystemZ<4, outs, ins, asmstr, pattern> {
182  field bits<32> Inst;
183  field bits<32> SoftFail = 0;
184
185  bits<4> R1;
186  bits<16> I2;
187
188  let Inst{31-24} = op{11-4};
189  let Inst{23-20} = R1;
190  let Inst{19-16} = op{3-0};
191  let Inst{15-0}  = I2;
192}
193
194class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195  : InstSystemZ<4, outs, ins, asmstr, pattern> {
196  field bits<32> Inst;
197  field bits<32> SoftFail = 0;
198
199  bits<4> R1;
200  bits<16> RI2;
201
202  let Inst{31-24} = op{11-4};
203  let Inst{23-20} = R1;
204  let Inst{19-16} = op{3-0};
205  let Inst{15-0}  = RI2;
206}
207
208class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
209  : InstSystemZ<4, outs, ins, asmstr, pattern> {
210  field bits<32> Inst;
211  field bits<32> SoftFail = 0;
212
213  bits<4> M1;
214  bits<16> RI2;
215
216  let Inst{31-24} = op{11-4};
217  let Inst{23-20} = M1;
218  let Inst{19-16} = op{3-0};
219  let Inst{15-0}  = RI2;
220}
221
222class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
223  : InstSystemZ<6, outs, ins, asmstr, pattern> {
224  field bits<48> Inst;
225  field bits<48> SoftFail = 0;
226
227  bits<4> R1;
228  bits<16> I2;
229  bits<4> M3;
230
231  let Inst{47-40} = op{15-8};
232  let Inst{39-36} = R1;
233  let Inst{35-32} = 0;
234  let Inst{31-16} = I2;
235  let Inst{15-12} = M3;
236  let Inst{11-8}  = 0;
237  let Inst{7-0}   = op{7-0};
238}
239
240class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
241  : InstSystemZ<6, outs, ins, asmstr, pattern> {
242  field bits<48> Inst;
243  field bits<48> SoftFail = 0;
244
245  bits<4> R1;
246  bits<4> R2;
247  bits<4> M3;
248  bits<16> RI4;
249
250  let Inst{47-40} = op{15-8};
251  let Inst{39-36} = R1;
252  let Inst{35-32} = R2;
253  let Inst{31-16} = RI4;
254  let Inst{15-12} = M3;
255  let Inst{11-8}  = 0;
256  let Inst{7-0}   = op{7-0};
257}
258
259class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
260  : InstSystemZ<6, outs, ins, asmstr, pattern> {
261  field bits<48> Inst;
262  field bits<48> SoftFail = 0;
263
264  bits<4> R1;
265  bits<8> I2;
266  bits<4> M3;
267  bits<16> RI4;
268
269  let Inst{47-40} = op{15-8};
270  let Inst{39-36} = R1;
271  let Inst{35-32} = M3;
272  let Inst{31-16} = RI4;
273  let Inst{15-8}  = I2;
274  let Inst{7-0}   = op{7-0};
275}
276
277class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
278  : InstSystemZ<6, outs, ins, asmstr, pattern> {
279  field bits<48> Inst;
280  field bits<48> SoftFail = 0;
281
282  bits<4> R1;
283  bits<4> R3;
284  bits<16> I2;
285
286  let Inst{47-40} = op{15-8};
287  let Inst{39-36} = R1;
288  let Inst{35-32} = R3;
289  let Inst{31-16} = I2;
290  let Inst{15-8}  = 0;
291  let Inst{7-0}   = op{7-0};
292}
293
294class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
295  : InstSystemZ<6, outs, ins, asmstr, pattern> {
296  field bits<48> Inst;
297  field bits<48> SoftFail = 0;
298
299  bits<4> R1;
300  bits<4> R2;
301  bits<8> I3;
302  bits<8> I4;
303  bits<8> I5;
304
305  let Inst{47-40} = op{15-8};
306  let Inst{39-36} = R1;
307  let Inst{35-32} = R2;
308  let Inst{31-24} = I3;
309  let Inst{23-16} = I4;
310  let Inst{15-8}  = I5;
311  let Inst{7-0}   = op{7-0};
312}
313
314class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
315  : InstSystemZ<6, outs, ins, asmstr, pattern> {
316  field bits<48> Inst;
317  field bits<48> SoftFail = 0;
318
319  bits<4> R1;
320  bits<4> M3;
321  bits<16> I2;
322
323  let Inst{47-40} = op{15-8};
324  let Inst{39-36} = R1;
325  let Inst{35-32} = M3;
326  let Inst{31-16} = I2;
327  let Inst{15-8}  = 0;
328  let Inst{7-0}   = op{7-0};
329}
330
331class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
332  : InstSystemZ<6, outs, ins, asmstr, pattern> {
333  field bits<48> Inst;
334  field bits<48> SoftFail = 0;
335
336  bits<4> R1;
337  bits<32> I2;
338
339  let Inst{47-40} = op{11-4};
340  let Inst{39-36} = R1;
341  let Inst{35-32} = op{3-0};
342  let Inst{31-0}  = I2;
343}
344
345class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
346  : InstSystemZ<6, outs, ins, asmstr, pattern> {
347  field bits<48> Inst;
348  field bits<48> SoftFail = 0;
349
350  bits<4> R1;
351  bits<32> RI2;
352
353  let Inst{47-40} = op{11-4};
354  let Inst{39-36} = R1;
355  let Inst{35-32} = op{3-0};
356  let Inst{31-0}  = RI2;
357}
358
359class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
360  : InstSystemZ<6, outs, ins, asmstr, pattern> {
361  field bits<48> Inst;
362  field bits<48> SoftFail = 0;
363
364  bits<4> M1;
365  bits<32> RI2;
366
367  let Inst{47-40} = op{11-4};
368  let Inst{39-36} = M1;
369  let Inst{35-32} = op{3-0};
370  let Inst{31-0}  = RI2;
371}
372
373class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
374  : InstSystemZ<6, outs, ins, asmstr, pattern> {
375  field bits<48> Inst;
376  field bits<48> SoftFail = 0;
377
378  bits<4> R1;
379  bits<8> I2;
380  bits<4> M3;
381  bits<16> BD4;
382
383  let Inst{47-40} = op{15-8};
384  let Inst{39-36} = R1;
385  let Inst{35-32} = M3;
386  let Inst{31-16} = BD4;
387  let Inst{15-8}  = I2;
388  let Inst{7-0}   = op{7-0};
389}
390
391class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
392  : InstSystemZ<2, outs, ins, asmstr, pattern> {
393  field bits<16> Inst;
394  field bits<16> SoftFail = 0;
395
396  bits<4> R1;
397  bits<4> R2;
398
399  let Inst{15-8} = op;
400  let Inst{7-4}  = R1;
401  let Inst{3-0}  = R2;
402}
403
404class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
405  : InstSystemZ<4, outs, ins, asmstr, pattern> {
406  field bits<32> Inst;
407  field bits<32> SoftFail = 0;
408
409  bits<4> R1;
410  bits<4> R3;
411  bits<4> R2;
412
413  let Inst{31-16} = op;
414  let Inst{15-12} = R1;
415  let Inst{11-8}  = 0;
416  let Inst{7-4}   = R3;
417  let Inst{3-0}   = R2;
418}
419
420class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
421  : InstSystemZ<4, outs, ins, asmstr, pattern> {
422  field bits<32> Inst;
423  field bits<32> SoftFail = 0;
424
425  bits<4> R1;
426  bits<4> R2;
427
428  let Inst{31-16} = op;
429  let Inst{15-8}  = 0;
430  let Inst{7-4}   = R1;
431  let Inst{3-0}   = R2;
432}
433
434class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
435  : InstSystemZ<4, outs, ins, asmstr, pattern> {
436  field bits<32> Inst;
437  field bits<32> SoftFail = 0;
438
439  bits<4> R1;
440  bits<4> R2;
441  bits<4> R3;
442  bits<4> M4;
443
444  let Inst{31-16} = op;
445  let Inst{15-12} = R3;
446  let Inst{11-8}  = M4;
447  let Inst{7-4}   = R1;
448  let Inst{3-0}   = R2;
449}
450
451class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
452  : InstSystemZ<4, outs, ins, asmstr, pattern> {
453  field bits<32> Inst;
454  field bits<32> SoftFail = 0;
455
456  bits<4> R1;
457  bits<4> R2;
458  bits<4> R3;
459  bits<4> M4;
460
461  let Inst{31-16} = op;
462  let Inst{15-12} = R3;
463  let Inst{11-8}  = M4;
464  let Inst{7-4}   = R1;
465  let Inst{3-0}   = R2;
466}
467
468class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
469  : InstSystemZ<4, outs, ins, asmstr, pattern> {
470  field bits<32> Inst;
471  field bits<32> SoftFail = 0;
472
473  bits<4> R1;
474  bits<4> R2;
475  bits<4> M3;
476
477  let Inst{31-16} = op;
478  let Inst{15-12} = M3;
479  let Inst{11-8}  = 0;
480  let Inst{7-4}   = R1;
481  let Inst{3-0}   = R2;
482}
483
484class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
485  : InstSystemZ<4, outs, ins, asmstr, pattern> {
486  field bits<32> Inst;
487  field bits<32> SoftFail = 0;
488
489  bits<4> R1;
490  bits<4> R2;
491  bits<4> M3;
492  bits<4> M4;
493
494  let Inst{31-16} = op;
495  let Inst{15-12} = M3;
496  let Inst{11-8}  = M4;
497  let Inst{7-4}   = R1;
498  let Inst{3-0}   = R2;
499}
500
501class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
502  : InstSystemZ<6, outs, ins, asmstr, pattern> {
503  field bits<48> Inst;
504  field bits<48> SoftFail = 0;
505
506  bits<4> R1;
507  bits<4> R2;
508  bits<4> M3;
509  bits<16> BD4;
510
511  let Inst{47-40} = op{15-8};
512  let Inst{39-36} = R1;
513  let Inst{35-32} = R2;
514  let Inst{31-16} = BD4;
515  let Inst{15-12} = M3;
516  let Inst{11-8}  = 0;
517  let Inst{7-0}   = op{7-0};
518}
519
520class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
521  : InstSystemZ<4, outs, ins, asmstr, pattern> {
522  field bits<32> Inst;
523  field bits<32> SoftFail = 0;
524
525  bits<4> R1;
526  bits<20> XBD2;
527
528  let Inst{31-24} = op;
529  let Inst{23-20} = R1;
530  let Inst{19-0}  = XBD2;
531
532  let HasIndex = 1;
533}
534
535class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
536  : InstSystemZ<4, outs, ins, asmstr, pattern> {
537  field bits<32> Inst;
538  field bits<32> SoftFail = 0;
539
540  bits<4> M1;
541  bits<20> XBD2;
542
543  let Inst{31-24} = op;
544  let Inst{23-20} = M1;
545  let Inst{19-0}  = XBD2;
546
547  let HasIndex = 1;
548}
549
550class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
551  : InstSystemZ<6, outs, ins, asmstr, pattern> {
552  field bits<48> Inst;
553  field bits<48> SoftFail = 0;
554
555  bits<4> R1;
556  bits<20> XBD2;
557  bits<4> M3;
558
559  let Inst{47-40} = op{15-8};
560  let Inst{39-36} = R1;
561  let Inst{35-16} = XBD2;
562  let Inst{15-12} = M3;
563  let Inst{11-8}  = 0;
564  let Inst{7-0}   = op{7-0};
565
566  let HasIndex = 1;
567}
568
569class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
570  : InstSystemZ<6, outs, ins, asmstr, pattern> {
571  field bits<48> Inst;
572  field bits<48> SoftFail = 0;
573
574  bits<4> R1;
575  bits<4> R3;
576  bits<20> XBD2;
577
578  let Inst{47-40} = op{15-8};
579  let Inst{39-36} = R3;
580  let Inst{35-16} = XBD2;
581  let Inst{15-12} = R1;
582  let Inst{11-8}  = 0;
583  let Inst{7-0}   = op{7-0};
584
585  let HasIndex = 1;
586}
587
588class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
589  : InstSystemZ<6, outs, ins, asmstr, pattern> {
590  field bits<48> Inst;
591  field bits<48> SoftFail = 0;
592
593  bits<4> R1;
594  bits<28> XBD2;
595
596  let Inst{47-40} = op{15-8};
597  let Inst{39-36} = R1;
598  let Inst{35-8}  = XBD2;
599  let Inst{7-0}   = op{7-0};
600
601  let Has20BitOffset = 1;
602  let HasIndex = 1;
603}
604
605class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
606  : InstSystemZ<6, outs, ins, asmstr, pattern> {
607  field bits<48> Inst;
608  field bits<48> SoftFail = 0;
609
610  bits<4> M1;
611  bits<28> XBD2;
612
613  let Inst{47-40} = op{15-8};
614  let Inst{39-36} = M1;
615  let Inst{35-8}  = XBD2;
616  let Inst{7-0}   = op{7-0};
617
618  let Has20BitOffset = 1;
619  let HasIndex = 1;
620}
621
622class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
623  : InstSystemZ<4, outs, ins, asmstr, pattern> {
624  field bits<32> Inst;
625  field bits<32> SoftFail = 0;
626
627  bits<4> R1;
628  bits<4> R3;
629  bits<16> BD2;
630
631  let Inst{31-24} = op;
632  let Inst{23-20} = R1;
633  let Inst{19-16} = R3;
634  let Inst{15-0}  = BD2;
635}
636
637class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
638  : InstSystemZ<4, outs, ins, asmstr, pattern> {
639  field bits<32> Inst;
640  field bits<32> SoftFail = 0;
641
642  bits<4> R1;
643  bits<4> M3;
644  bits<16> BD2;
645
646  let Inst{31-24} = op;
647  let Inst{23-20} = R1;
648  let Inst{19-16} = M3;
649  let Inst{15-0}  = BD2;
650}
651
652class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
653  : InstSystemZ<4, outs, ins, asmstr, pattern> {
654  field bits<32> Inst;
655  field bits<32> SoftFail = 0;
656
657  bits<4> R1;
658  bits<4> R3;
659  bits<16> RI2;
660
661  let Inst{31-24} = op;
662  let Inst{23-20} = R1;
663  let Inst{19-16} = R3;
664  let Inst{15-0}  = RI2;
665}
666
667class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
668  : InstSystemZ<6, outs, ins, asmstr, pattern> {
669  field bits<48> Inst;
670  field bits<48> SoftFail = 0;
671
672  bits<4> R1;
673  bits<4> R3;
674  bits<24> BD2;
675
676  let Inst{47-40} = op{15-8};
677  let Inst{39-36} = R1;
678  let Inst{35-32} = R3;
679  let Inst{31-8}  = BD2;
680  let Inst{7-0}   = op{7-0};
681
682  let Has20BitOffset = 1;
683}
684
685class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
686  : InstSystemZ<6, outs, ins, asmstr, pattern> {
687  field bits<48> Inst;
688  field bits<48> SoftFail = 0;
689
690  bits<4> R1;
691  bits<4> M3;
692  bits<24> BD2;
693
694  let Inst{47-40} = op{15-8};
695  let Inst{39-36} = R1;
696  let Inst{35-32} = M3;
697  let Inst{31-8}  = BD2;
698  let Inst{7-0}   = op{7-0};
699
700  let Has20BitOffset = 1;
701}
702
703class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
704  : InstSystemZ<4, outs, ins, asmstr, pattern> {
705  field bits<32> Inst;
706  field bits<32> SoftFail = 0;
707
708  bits<16> BD1;
709  bits<8> I2;
710
711  let Inst{31-24} = op;
712  let Inst{23-16} = I2;
713  let Inst{15-0}  = BD1;
714}
715
716class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
717  : InstSystemZ<6, outs, ins, asmstr, pattern> {
718  field bits<48> Inst;
719  field bits<48> SoftFail = 0;
720
721  bits<16> BD1;
722  bits<16> I2;
723
724  let Inst{47-32} = op;
725  let Inst{31-16} = BD1;
726  let Inst{15-0}  = I2;
727}
728
729class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
730  : InstSystemZ<6, outs, ins, asmstr, pattern> {
731  field bits<48> Inst;
732  field bits<48> SoftFail = 0;
733
734  bits<24> BD1;
735  bits<8> I2;
736
737  let Inst{47-40} = op{15-8};
738  let Inst{39-32} = I2;
739  let Inst{31-8}  = BD1;
740  let Inst{7-0}   = op{7-0};
741
742  let Has20BitOffset = 1;
743}
744
745class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
746  : InstSystemZ<6, outs, ins, asmstr, pattern> {
747  field bits<48> Inst;
748  field bits<48> SoftFail = 0;
749
750  bits<24> BDL1;
751  bits<16> BD2;
752
753  let Inst{47-40} = op;
754  let Inst{39-16} = BDL1;
755  let Inst{15-0}  = BD2;
756}
757
758class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
759  : InstSystemZ<6, outs, ins, asmstr, pattern> {
760  field bits<48> Inst;
761  field bits<48> SoftFail = 0;
762
763  bits<20> RBD1;
764  bits<16> BD2;
765  bits<4> R3;
766
767  let Inst{47-40} = op;
768  let Inst{39-36} = RBD1{19-16};
769  let Inst{35-32} = R3;
770  let Inst{31-16} = RBD1{15-0};
771  let Inst{15-0}  = BD2;
772}
773
774class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
775  : InstSystemZ<6, outs, ins, asmstr, pattern> {
776  field bits<48> Inst;
777  field bits<48> SoftFail = 0;
778
779  bits<16> BD1;
780  bits<16> BD2;
781
782  let Inst{47-32} = op;
783  let Inst{31-16} = BD1;
784  let Inst{15-0}  = BD2;
785}
786
787class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
788  : InstSystemZ<6, outs, ins, asmstr, pattern> {
789  field bits<48> Inst;
790  field bits<48> SoftFail = 0;
791
792  bits<16> BD1;
793  bits<16> BD2;
794  bits<4>  R3;
795
796  let Inst{47-40} = op{11-4};
797  let Inst{39-36} = R3;
798  let Inst{35-32} = op{3-0};
799  let Inst{31-16} = BD1;
800  let Inst{15-0}  = BD2;
801}
802
803class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
804  : InstSystemZ<4, outs, ins, asmstr, pattern> {
805  field bits<32> Inst;
806  field bits<32> SoftFail = 0;
807
808  bits<16> BD2;
809
810  let Inst{31-16} = op;
811  let Inst{15-0}  = BD2;
812}
813
814class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
815  : InstSystemZ<6, outs, ins, asmstr, pattern> {
816  field bits<48> Inst;
817  field bits<48> SoftFail = 0;
818
819  bits<5> V1;
820  bits<16> I2;
821  bits<4> M3;
822
823  let Inst{47-40} = op{15-8};
824  let Inst{39-36} = V1{3-0};
825  let Inst{35-32} = 0;
826  let Inst{31-16} = I2;
827  let Inst{15-12} = M3;
828  let Inst{11}    = V1{4};
829  let Inst{10-8}  = 0;
830  let Inst{7-0}   = op{7-0};
831}
832
833class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
834  : InstSystemZ<6, outs, ins, asmstr, pattern> {
835  field bits<48> Inst;
836  field bits<48> SoftFail = 0;
837
838  bits<5> V1;
839  bits<8> I2;
840  bits<8> I3;
841  bits<4> M4;
842
843  let Inst{47-40} = op{15-8};
844  let Inst{39-36} = V1{3-0};
845  let Inst{35-32} = 0;
846  let Inst{31-24} = I2;
847  let Inst{23-16} = I3;
848  let Inst{15-12} = M4;
849  let Inst{11}    = V1{4};
850  let Inst{10-8}  = 0;
851  let Inst{7-0}   = op{7-0};
852}
853
854class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
855  : InstSystemZ<6, outs, ins, asmstr, pattern> {
856  field bits<48> Inst;
857  field bits<48> SoftFail = 0;
858
859  bits<5> V1;
860  bits<5> V3;
861  bits<16> I2;
862  bits<4> M4;
863
864  let Inst{47-40} = op{15-8};
865  let Inst{39-36} = V1{3-0};
866  let Inst{35-32} = V3{3-0};
867  let Inst{31-16} = I2;
868  let Inst{15-12} = M4;
869  let Inst{11}    = V1{4};
870  let Inst{10}    = V3{4};
871  let Inst{9-8}   = 0;
872  let Inst{7-0}   = op{7-0};
873}
874
875class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
876  : InstSystemZ<6, outs, ins, asmstr, pattern> {
877  field bits<48> Inst;
878  field bits<48> SoftFail = 0;
879
880  bits<5> V1;
881  bits<5> V2;
882  bits<5> V3;
883  bits<8> I4;
884  bits<4> M5;
885
886  let Inst{47-40} = op{15-8};
887  let Inst{39-36} = V1{3-0};
888  let Inst{35-32} = V2{3-0};
889  let Inst{31-28} = V3{3-0};
890  let Inst{27-24} = 0;
891  let Inst{23-16} = I4;
892  let Inst{15-12} = M5;
893  let Inst{11}    = V1{4};
894  let Inst{10}    = V2{4};
895  let Inst{9}     = V3{4};
896  let Inst{8}     = 0;
897  let Inst{7-0}   = op{7-0};
898}
899
900class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
901  : InstSystemZ<6, outs, ins, asmstr, pattern> {
902  field bits<48> Inst;
903  field bits<48> SoftFail = 0;
904
905  bits<5> V1;
906  bits<5> V2;
907  bits<12> I3;
908  bits<4> M4;
909  bits<4> M5;
910
911  let Inst{47-40} = op{15-8};
912  let Inst{39-36} = V1{3-0};
913  let Inst{35-32} = V2{3-0};
914  let Inst{31-20} = I3;
915  let Inst{19-16} = M5;
916  let Inst{15-12} = M4;
917  let Inst{11}    = V1{4};
918  let Inst{10}    = V2{4};
919  let Inst{9-8}   = 0;
920  let Inst{7-0}   = op{7-0};
921}
922
923// Depending on the instruction mnemonic, certain bits may be or-ed into
924// the M4 value provided as explicit operand.  These are passed as m4or.
925class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
926               bits<4> m4or = 0>
927  : InstSystemZ<6, outs, ins, asmstr, pattern> {
928  field bits<48> Inst;
929  field bits<48> SoftFail = 0;
930
931  bits<5> V1;
932  bits<5> V2;
933  bits<4> M3;
934  bits<4> M4;
935  bits<4> M5;
936
937  let Inst{47-40} = op{15-8};
938  let Inst{39-36} = V1{3-0};
939  let Inst{35-32} = V2{3-0};
940  let Inst{31-24} = 0;
941  let Inst{23-20} = M5;
942  let Inst{19}    = !if (!eq (m4or{3}, 1), 1, M4{3});
943  let Inst{18}    = !if (!eq (m4or{2}, 1), 1, M4{2});
944  let Inst{17}    = !if (!eq (m4or{1}, 1), 1, M4{1});
945  let Inst{16}    = !if (!eq (m4or{0}, 1), 1, M4{0});
946  let Inst{15-12} = M3;
947  let Inst{11}    = V1{4};
948  let Inst{10}    = V2{4};
949  let Inst{9-8}   = 0;
950  let Inst{7-0}   = op{7-0};
951}
952
953// Depending on the instruction mnemonic, certain bits may be or-ed into
954// the M5 value provided as explicit operand.  These are passed as m5or.
955class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
956               bits<4> m5or = 0>
957  : InstSystemZ<6, outs, ins, asmstr, pattern> {
958  field bits<48> Inst;
959  field bits<48> SoftFail = 0;
960
961  bits<5> V1;
962  bits<5> V2;
963  bits<5> V3;
964  bits<4> M4;
965  bits<4> M5;
966
967  let Inst{47-40} = op{15-8};
968  let Inst{39-36} = V1{3-0};
969  let Inst{35-32} = V2{3-0};
970  let Inst{31-28} = V3{3-0};
971  let Inst{27-24} = 0;
972  let Inst{23}    = !if (!eq (m5or{3}, 1), 1, M5{3});
973  let Inst{22}    = !if (!eq (m5or{2}, 1), 1, M5{2});
974  let Inst{21}    = !if (!eq (m5or{1}, 1), 1, M5{1});
975  let Inst{20}    = !if (!eq (m5or{0}, 1), 1, M5{0});
976  let Inst{19-16} = 0;
977  let Inst{15-12} = M4;
978  let Inst{11}    = V1{4};
979  let Inst{10}    = V2{4};
980  let Inst{9}     = V3{4};
981  let Inst{8}     = 0;
982  let Inst{7-0}   = op{7-0};
983}
984
985class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
986  : InstSystemZ<6, outs, ins, asmstr, pattern> {
987  field bits<48> Inst;
988  field bits<48> SoftFail = 0;
989
990  bits<5> V1;
991  bits<5> V2;
992  bits<5> V3;
993  bits<4> M4;
994  bits<4> M5;
995  bits<4> M6;
996
997  let Inst{47-40} = op{15-8};
998  let Inst{39-36} = V1{3-0};
999  let Inst{35-32} = V2{3-0};
1000  let Inst{31-28} = V3{3-0};
1001  let Inst{27-24} = 0;
1002  let Inst{23-20} = M6;
1003  let Inst{19-16} = M5;
1004  let Inst{15-12} = M4;
1005  let Inst{11}    = V1{4};
1006  let Inst{10}    = V2{4};
1007  let Inst{9}     = V3{4};
1008  let Inst{8}     = 0;
1009  let Inst{7-0}   = op{7-0};
1010}
1011
1012// Depending on the instruction mnemonic, certain bits may be or-ed into
1013// the M6 value provided as explicit operand.  These are passed as m6or.
1014class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1015               bits<4> m6or = 0>
1016  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1017  field bits<48> Inst;
1018  field bits<48> SoftFail = 0;
1019
1020  bits<5> V1;
1021  bits<5> V2;
1022  bits<5> V3;
1023  bits<5> V4;
1024  bits<4> M5;
1025  bits<4> M6;
1026
1027  let Inst{47-40} = op{15-8};
1028  let Inst{39-36} = V1{3-0};
1029  let Inst{35-32} = V2{3-0};
1030  let Inst{31-28} = V3{3-0};
1031  let Inst{27-24} = M5;
1032  let Inst{23}    = !if (!eq (m6or{3}, 1), 1, M6{3});
1033  let Inst{22}    = !if (!eq (m6or{2}, 1), 1, M6{2});
1034  let Inst{21}    = !if (!eq (m6or{1}, 1), 1, M6{1});
1035  let Inst{20}    = !if (!eq (m6or{0}, 1), 1, M6{0});
1036  let Inst{19-16} = 0;
1037  let Inst{15-12} = V4{3-0};
1038  let Inst{11}    = V1{4};
1039  let Inst{10}    = V2{4};
1040  let Inst{9}     = V3{4};
1041  let Inst{8}     = V4{4};
1042  let Inst{7-0}   = op{7-0};
1043}
1044
1045class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1046  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1047  field bits<48> Inst;
1048  field bits<48> SoftFail = 0;
1049
1050  bits<5> V1;
1051  bits<5> V2;
1052  bits<5> V3;
1053  bits<5> V4;
1054  bits<4> M5;
1055  bits<4> M6;
1056
1057  let Inst{47-40} = op{15-8};
1058  let Inst{39-36} = V1{3-0};
1059  let Inst{35-32} = V2{3-0};
1060  let Inst{31-28} = V3{3-0};
1061  let Inst{27-24} = M6;
1062  let Inst{23-20} = 0;
1063  let Inst{19-16} = M5;
1064  let Inst{15-12} = V4{3-0};
1065  let Inst{11}    = V1{4};
1066  let Inst{10}    = V2{4};
1067  let Inst{9}     = V3{4};
1068  let Inst{8}     = V4{4};
1069  let Inst{7-0}   = op{7-0};
1070}
1071
1072class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1073  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1074  field bits<48> Inst;
1075  field bits<48> SoftFail = 0;
1076
1077  bits<5> V1;
1078  bits<4> R2;
1079  bits<4> R3;
1080
1081  let Inst{47-40} = op{15-8};
1082  let Inst{39-36} = V1{3-0};
1083  let Inst{35-32} = R2;
1084  let Inst{31-28} = R3;
1085  let Inst{27-12} = 0;
1086  let Inst{11}    = V1{4};
1087  let Inst{10-8}  = 0;
1088  let Inst{7-0}   = op{7-0};
1089}
1090
1091class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1092  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1093  field bits<48> Inst;
1094  field bits<48> SoftFail = 0;
1095
1096  bits<5> V1;
1097  bits<16> BD2;
1098  bits<5> V3;
1099  bits<4> M4;
1100
1101  let Inst{47-40} = op{15-8};
1102  let Inst{39-36} = V1{3-0};
1103  let Inst{35-32} = V3{3-0};
1104  let Inst{31-16} = BD2;
1105  let Inst{15-12} = M4;
1106  let Inst{11}    = V1{4};
1107  let Inst{10}    = V3{4};
1108  let Inst{9-8}   = 0;
1109  let Inst{7-0}   = op{7-0};
1110}
1111
1112class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1113  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1114  field bits<48> Inst;
1115  field bits<48> SoftFail = 0;
1116
1117  bits<5> V1;
1118  bits<16> BD2;
1119  bits<4> R3;
1120  bits<4> M4;
1121
1122  let Inst{47-40} = op{15-8};
1123  let Inst{39-36} = V1{3-0};
1124  let Inst{35-32} = R3;
1125  let Inst{31-16} = BD2;
1126  let Inst{15-12} = M4;
1127  let Inst{11}    = V1{4};
1128  let Inst{10-8}  = 0;
1129  let Inst{7-0}   = op{7-0};
1130}
1131
1132class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1133  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1134  field bits<48> Inst;
1135  field bits<48> SoftFail = 0;
1136
1137  bits<4> R1;
1138  bits<16> BD2;
1139  bits<5> V3;
1140  bits<4> M4;
1141
1142  let Inst{47-40} = op{15-8};
1143  let Inst{39-36} = R1;
1144  let Inst{35-32} = V3{3-0};
1145  let Inst{31-16} = BD2;
1146  let Inst{15-12} = M4;
1147  let Inst{11}    = 0;
1148  let Inst{10}    = V3{4};
1149  let Inst{9-8}   = 0;
1150  let Inst{7-0}   = op{7-0};
1151}
1152
1153class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1154  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1155  field bits<48> Inst;
1156  field bits<48> SoftFail = 0;
1157
1158  bits<5> V1;
1159  bits<21> VBD2;
1160  bits<4> M3;
1161
1162  let Inst{47-40} = op{15-8};
1163  let Inst{39-36} = V1{3-0};
1164  let Inst{35-16} = VBD2{19-0};
1165  let Inst{15-12} = M3;
1166  let Inst{11}    = V1{4};
1167  let Inst{10}    = VBD2{20};
1168  let Inst{9-8}   = 0;
1169  let Inst{7-0}   = op{7-0};
1170}
1171
1172class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1173  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1174  field bits<48> Inst;
1175  field bits<48> SoftFail = 0;
1176
1177  bits<5> V1;
1178  bits<20> XBD2;
1179  bits<4> M3;
1180
1181  let Inst{47-40} = op{15-8};
1182  let Inst{39-36} = V1{3-0};
1183  let Inst{35-16} = XBD2;
1184  let Inst{15-12} = M3;
1185  let Inst{11}    = V1{4};
1186  let Inst{10-8}  = 0;
1187  let Inst{7-0}   = op{7-0};
1188}
1189
1190//===----------------------------------------------------------------------===//
1191// Instruction classes for .insn directives
1192//===----------------------------------------------------------------------===//
1193
1194class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
1195  : InstE<0, outs, ins, asmstr, pattern> {
1196  bits<16> enc;
1197
1198  let Inst = enc;
1199}
1200
1201class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1202  : InstRIa<0, outs, ins, asmstr, pattern> {
1203  bits<32> enc;
1204
1205  let Inst{31-24} = enc{31-24};
1206  let Inst{19-16} = enc{19-16};
1207}
1208
1209class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
1210  : InstRIEd<0, outs, ins, asmstr, pattern> {
1211  bits<48> enc;
1212
1213  let Inst{47-40} = enc{47-40};
1214  let Inst{7-0}   = enc{7-0};
1215}
1216
1217class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1218  : InstRILa<0, outs, ins, asmstr, pattern> {
1219  bits<48> enc;
1220  string type;
1221
1222  let Inst{47-40} = enc{47-40};
1223  let Inst{35-32} = enc{35-32};
1224}
1225
1226class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
1227  : InstRIS<0, outs, ins, asmstr, pattern> {
1228  bits<48> enc;
1229
1230  let Inst{47-40} = enc{47-40};
1231  let Inst{7-0}   = enc{7-0};
1232}
1233
1234class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1235  : InstRR<0, outs, ins, asmstr, pattern> {
1236  bits<16> enc;
1237
1238  let Inst{15-8} = enc{15-8};
1239}
1240
1241class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
1242  : InstRRE<0, outs, ins, asmstr, pattern> {
1243  bits<32> enc;
1244
1245  let Inst{31-16} = enc{31-16};
1246}
1247
1248class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
1249  : InstRRFa<0, outs, ins, asmstr, pattern> {
1250  bits<32> enc;
1251
1252  let Inst{31-16} = enc{31-16};
1253}
1254
1255class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1256  : InstRRS<0, outs, ins, asmstr, pattern> {
1257  bits<48> enc;
1258
1259  let Inst{47-40} = enc{47-40};
1260  let Inst{7-0}   = enc{7-0};
1261}
1262
1263class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1264  : InstRSa<0, outs, ins, asmstr, pattern> {
1265  bits<32> enc;
1266
1267  let Inst{31-24} = enc{31-24};
1268}
1269
1270// RSE is like RSY except with a 12 bit displacement (instead of 20).
1271class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1272  : InstRSYa<6, outs, ins, asmstr, pattern> {
1273  bits <48> enc;
1274
1275  let Inst{47-40} = enc{47-40};
1276  let Inst{31-16} = BD2{15-0};
1277  let Inst{15-8}  = 0;
1278  let Inst{7-0}   = enc{7-0};
1279}
1280
1281class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1282  : InstRSI<0, outs, ins, asmstr, pattern> {
1283  bits<32> enc;
1284
1285  let Inst{31-24} = enc{31-24};
1286}
1287
1288class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
1289  : InstRSYa<0, outs, ins, asmstr, pattern> {
1290  bits<48> enc;
1291
1292  let Inst{47-40} = enc{47-40};
1293  let Inst{7-0}   = enc{7-0};
1294}
1295
1296class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1297  : InstRXa<0, outs, ins, asmstr, pattern> {
1298  bits<32> enc;
1299
1300  let Inst{31-24} = enc{31-24};
1301}
1302
1303class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
1304  : InstRXE<0, outs, ins, asmstr, pattern> {
1305  bits<48> enc;
1306
1307  let M3 = 0;
1308
1309  let Inst{47-40} = enc{47-40};
1310  let Inst{7-0}   = enc{7-0};
1311}
1312
1313class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
1314  : InstRXF<0, outs, ins, asmstr, pattern> {
1315  bits<48> enc;
1316
1317  let Inst{47-40} = enc{47-40};
1318  let Inst{7-0}   = enc{7-0};
1319}
1320
1321class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
1322  : InstRXYa<0, outs, ins, asmstr, pattern> {
1323  bits<48> enc;
1324
1325  let Inst{47-40} = enc{47-40};
1326  let Inst{7-0}   = enc{7-0};
1327}
1328
1329class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
1330  : InstS<0, outs, ins, asmstr, pattern> {
1331  bits<32> enc;
1332
1333  let Inst{31-16} = enc{31-16};
1334}
1335
1336class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1337  : InstSI<0, outs, ins, asmstr, pattern> {
1338  bits<32> enc;
1339
1340  let Inst{31-24} = enc{31-24};
1341}
1342
1343class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
1344  : InstSIY<0, outs, ins, asmstr, pattern> {
1345  bits<48> enc;
1346
1347  let Inst{47-40} = enc{47-40};
1348  let Inst{7-0}   = enc{7-0};
1349}
1350
1351class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1352  : InstSIL<0, outs, ins, asmstr, pattern> {
1353  bits<48> enc;
1354
1355  let Inst{47-32} = enc{47-32};
1356}
1357
1358class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
1359  : InstSSd<0, outs, ins, asmstr, pattern> {
1360  bits<48> enc;
1361
1362  let Inst{47-40} = enc{47-40};
1363}
1364
1365class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1366  : InstSSE<0, outs, ins, asmstr, pattern> {
1367  bits<48> enc;
1368
1369  let Inst{47-32} = enc{47-32};
1370}
1371
1372class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
1373  : InstSSF<0, outs, ins, asmstr, pattern> {
1374  bits<48> enc;
1375
1376  let Inst{47-40} = enc{47-40};
1377  let Inst{35-32} = enc{35-32};
1378}
1379
1380//===----------------------------------------------------------------------===//
1381// Variants of instructions with condition mask
1382//===----------------------------------------------------------------------===//
1383//
1384// For instructions using a condition mask (e.g. conditional branches,
1385// compare-and-branch instructions, or conditional move instructions),
1386// we generally need to create multiple instruction patterns:
1387//
1388// - One used for code generation, which encodes the condition mask as an
1389//   MI operand, but writes out an extended mnemonic for better readability.
1390// - One pattern for the base form of the instruction with an explicit
1391//   condition mask (encoded as a plain integer MI operand).
1392// - Specific patterns for each extended mnemonic, where the condition mask
1393//   is implied by the pattern name and not otherwise encoded at all.
1394//
1395// We need the latter primarily for the assembler and disassembler, since the
1396// assembler parser is not able to decode part of an instruction mnemonic
1397// into an operand.  Thus we provide separate patterns for each mnemonic.
1398//
1399// Note that in some cases there are two different mnemonics for the same
1400// condition mask.  In this case we cannot have both instructions available
1401// to the disassembler at the same time since the encodings are not distinct.
1402// Therefore the alternate forms are marked isAsmParserOnly.
1403//
1404// We don't make one of the two names an alias of the other because
1405// we need the custom parsing routines to select the correct register class.
1406//
1407// This section provides helpers for generating the specific forms.
1408//
1409//===----------------------------------------------------------------------===//
1410
1411// A class to describe a variant of an instruction with condition mask.
1412class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
1413  // The fixed condition mask to use.
1414  bits<4> ccmask = ccmaskin;
1415
1416  // The suffix to use for the extended assembler mnemonic.
1417  string suffix = suffixin;
1418
1419  // Whether this is an alternate that needs to be marked isAsmParserOnly.
1420  bit alternate = alternatein;
1421}
1422
1423// Condition mask 15 means "always true", which is used to define
1424// unconditional branches as a variant of conditional branches.
1425def CondAlways : CondVariant<15, "", 0>;
1426
1427// Condition masks for general instructions that can set all 4 bits.
1428def CondVariantO   : CondVariant<1,  "o",   0>;
1429def CondVariantH   : CondVariant<2,  "h",   0>;
1430def CondVariantP   : CondVariant<2,  "p",   1>;
1431def CondVariantNLE : CondVariant<3,  "nle", 0>;
1432def CondVariantL   : CondVariant<4,  "l",   0>;
1433def CondVariantM   : CondVariant<4,  "m",   1>;
1434def CondVariantNHE : CondVariant<5,  "nhe", 0>;
1435def CondVariantLH  : CondVariant<6,  "lh",  0>;
1436def CondVariantNE  : CondVariant<7,  "ne",  0>;
1437def CondVariantNZ  : CondVariant<7,  "nz",  1>;
1438def CondVariantE   : CondVariant<8,  "e",   0>;
1439def CondVariantZ   : CondVariant<8,  "z",   1>;
1440def CondVariantNLH : CondVariant<9,  "nlh", 0>;
1441def CondVariantHE  : CondVariant<10, "he",  0>;
1442def CondVariantNL  : CondVariant<11, "nl",  0>;
1443def CondVariantNM  : CondVariant<11, "nm",  1>;
1444def CondVariantLE  : CondVariant<12, "le",  0>;
1445def CondVariantNH  : CondVariant<13, "nh",  0>;
1446def CondVariantNP  : CondVariant<13, "np",  1>;
1447def CondVariantNO  : CondVariant<14, "no",  0>;
1448
1449// A helper class to look up one of the above by name.
1450class CV<string name>
1451  : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
1452                !cast<CondVariant>("CondVariant"#name).suffix,
1453                !cast<CondVariant>("CondVariant"#name).alternate>;
1454
1455// Condition masks for integer instructions (e.g. compare-and-branch).
1456// This is like the list above, except that condition 3 is not possible
1457// and that the low bit of the mask is therefore always 0.  This means
1458// that each condition has two names.  Conditions "o" and "no" are not used.
1459def IntCondVariantH   : CondVariant<2,  "h",   0>;
1460def IntCondVariantNLE : CondVariant<2,  "nle", 1>;
1461def IntCondVariantL   : CondVariant<4,  "l",   0>;
1462def IntCondVariantNHE : CondVariant<4,  "nhe", 1>;
1463def IntCondVariantLH  : CondVariant<6,  "lh",  0>;
1464def IntCondVariantNE  : CondVariant<6,  "ne",  1>;
1465def IntCondVariantE   : CondVariant<8,  "e",   0>;
1466def IntCondVariantNLH : CondVariant<8,  "nlh", 1>;
1467def IntCondVariantHE  : CondVariant<10, "he",  0>;
1468def IntCondVariantNL  : CondVariant<10, "nl",  1>;
1469def IntCondVariantLE  : CondVariant<12, "le",  0>;
1470def IntCondVariantNH  : CondVariant<12, "nh",  1>;
1471
1472// A helper class to look up one of the above by name.
1473class ICV<string name>
1474  : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
1475                !cast<CondVariant>("IntCondVariant"#name).suffix,
1476                !cast<CondVariant>("IntCondVariant"#name).alternate>;
1477
1478//===----------------------------------------------------------------------===//
1479// Instruction definitions with semantics
1480//===----------------------------------------------------------------------===//
1481//
1482// These classes have the form [Cond]<Category><Format>, where <Format> is one
1483// of the formats defined above and where <Category> describes the inputs
1484// and outputs.  "Cond" is used if the instruction is conditional,
1485// in which case the 4-bit condition-code mask is added as a final operand.
1486// <Category> can be one of:
1487//
1488//   Inherent:
1489//     One register output operand and no input operands.
1490//
1491//   StoreInherent:
1492//     One address operand.  The instruction stores to the address.
1493//
1494//   SideEffectInherent:
1495//     No input or output operands, but causes some side effect.
1496//
1497//   Branch:
1498//     One branch target.  The instruction branches to the target.
1499//
1500//   Call:
1501//     One output operand and one branch target.  The instruction stores
1502//     the return address to the output operand and branches to the target.
1503//
1504//   CmpBranch:
1505//     Two input operands and one optional branch target.  The instruction
1506//     compares the two input operands and branches or traps on the result.
1507//
1508//   BranchUnary:
1509//     One register output operand, one register input operand and
1510//     one branch displacement.  The instructions stores a modified
1511//     form of the source register in the destination register and
1512//     branches on the result.
1513//
1514//   BranchBinary:
1515//     One register output operand, two register input operands and one branch
1516//     displacement. The instructions stores a modified form of one of the
1517//     source registers in the destination register and branches on the result.
1518//
1519//   LoadMultiple:
1520//     One address input operand and two explicit output operands.
1521//     The instruction loads a range of registers from the address,
1522//     with the explicit operands giving the first and last register
1523//     to load.  Other loaded registers are added as implicit definitions.
1524//
1525//   StoreMultiple:
1526//     Two explicit input register operands and an address operand.
1527//     The instruction stores a range of registers to the address,
1528//     with the explicit operands giving the first and last register
1529//     to store.  Other stored registers are added as implicit uses.
1530//
1531//   StoreLength:
1532//     One value operand, one length operand and one address operand.
1533//     The instruction stores the value operand to the address but
1534//     doesn't write more than the number of bytes specified by the
1535//     length operand.
1536//
1537//   LoadAddress:
1538//     One register output operand and one address operand.
1539//
1540//   Unary:
1541//     One register output operand and one input operand.
1542//
1543//   Store:
1544//     One address operand and one other input operand.  The instruction
1545//     stores to the address.
1546//
1547//   SideEffectUnary:
1548//     One input operand.  No output operands, but causes some side effect.
1549//
1550//   Binary:
1551//     One register output operand and two input operands.
1552//
1553//   StoreBinary:
1554//     One address operand and two other input operands.  The instruction
1555//     stores to the address.
1556//
1557//   SideEffectBinary:
1558//     Two input operands.  No output operands, but causes some side effect.
1559//
1560//   Compare:
1561//     Two input operands and an implicit CC output operand.
1562//
1563//   Test:
1564//     Two input operands and an implicit CC output operand.  The second
1565//     input operand is an "address" operand used as a test class mask.
1566//
1567//   Ternary:
1568//     One register output operand and three input operands.
1569//
1570//   SideEffectTernary:
1571//     Three input operands.  No output operands, but causes some side effect.
1572//
1573//   Quaternary:
1574//     One register output operand and four input operands.
1575//
1576//   LoadAndOp:
1577//     One output operand and two input operands, one of which is an address.
1578//     The instruction both reads from and writes to the address.
1579//
1580//   CmpSwap:
1581//     One output operand and three input operands, one of which is an address.
1582//     The instruction both reads from and writes to the address.
1583//
1584//   RotateSelect:
1585//     One output operand and five input operands.  The first two operands
1586//     are registers and the other three are immediates.
1587//
1588//   Prefetch:
1589//     One 4-bit immediate operand and one address operand.  The immediate
1590//     operand is 1 for a load prefetch and 2 for a store prefetch.
1591//
1592// The format determines which input operands are tied to output operands,
1593// and also determines the shape of any address operand.
1594//
1595// Multiclasses of the form <Category><Format>Pair define two instructions,
1596// one with <Category><Format> and one with <Category><Format>Y.  The name
1597// of the first instruction has no suffix, the name of the second has
1598// an extra "y".
1599//
1600//===----------------------------------------------------------------------===//
1601
1602class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1603                  SDPatternOperator operator>
1604  : InstRRE<opcode, (outs cls:$R1), (ins),
1605            mnemonic#"\t$R1",
1606            [(set cls:$R1, (operator))]> {
1607  let R2 = 0;
1608}
1609
1610class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1611  : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1612  let I2 = value;
1613  let M3 = 0;
1614}
1615
1616class StoreInherentS<string mnemonic, bits<16> opcode>
1617  : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
1618          mnemonic#"\t$BD2", []> {
1619  let mayStore = 1;
1620}
1621
1622class SideEffectInherentE<string mnemonic, bits<16>opcode>
1623  : InstE<opcode, (outs), (ins), mnemonic, []> {
1624  let hasSideEffects = 1;
1625}
1626
1627class SideEffectInherentS<string mnemonic, bits<16> opcode,
1628                          SDPatternOperator operator>
1629  : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
1630  let hasSideEffects = 1;
1631  let BD2 = 0;
1632}
1633
1634// Allow an optional TLS marker symbol to generate TLS call relocations.
1635class CallRI<string mnemonic, bits<12> opcode>
1636  : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
1637            mnemonic#"\t$R1, $RI2", []>;
1638
1639// Allow an optional TLS marker symbol to generate TLS call relocations.
1640class CallRIL<string mnemonic, bits<12> opcode>
1641  : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
1642             mnemonic#"\t$R1, $RI2", []>;
1643
1644class CallRR<string mnemonic, bits<8> opcode>
1645  : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
1646           mnemonic#"\t$R1, $R2", []>;
1647
1648class CallRX<string mnemonic, bits<8> opcode>
1649  : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
1650            mnemonic#"\t$R1, $XBD2", []>;
1651
1652class CondBranchRI<string mnemonic, bits<12> opcode,
1653                   SDPatternOperator operator = null_frag>
1654  : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
1655            !subst("#", "${M1}", mnemonic)#"\t$RI2",
1656            [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
1657  let CCMaskFirst = 1;
1658}
1659
1660class AsmCondBranchRI<string mnemonic, bits<12> opcode>
1661  : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
1662            mnemonic#"\t$M1, $RI2", []>;
1663
1664class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
1665                        SDPatternOperator operator = null_frag>
1666  : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
1667            !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
1668  let isAsmParserOnly = V.alternate;
1669  let M1 = V.ccmask;
1670}
1671
1672class CondBranchRIL<string mnemonic, bits<12> opcode>
1673  : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
1674             !subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
1675  let CCMaskFirst = 1;
1676}
1677
1678class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
1679  : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
1680             mnemonic#"\t$M1, $RI2", []>;
1681
1682class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
1683  : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
1684             !subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
1685  let isAsmParserOnly = V.alternate;
1686  let M1 = V.ccmask;
1687}
1688
1689class CondBranchRR<string mnemonic, bits<8> opcode>
1690  : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
1691           !subst("#", "${R1}", mnemonic)#"\t$R2", []> {
1692  let CCMaskFirst = 1;
1693}
1694
1695class AsmCondBranchRR<string mnemonic, bits<8> opcode>
1696  : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
1697           mnemonic#"\t$R1, $R2", []>;
1698
1699class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
1700                      SDPatternOperator operator = null_frag>
1701  : InstRR<opcode, (outs), (ins ADDR64:$R2),
1702           !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
1703  let isAsmParserOnly = V.alternate;
1704  let R1 = V.ccmask;
1705}
1706
1707class CondBranchRX<string mnemonic, bits<8> opcode>
1708  : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
1709            !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
1710  let CCMaskFirst = 1;
1711}
1712
1713class AsmCondBranchRX<string mnemonic, bits<8> opcode>
1714  : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
1715            mnemonic#"\t$M1, $XBD2", []>;
1716
1717class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
1718  : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
1719            !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
1720  let isAsmParserOnly = V.alternate;
1721  let M1 = V.ccmask;
1722}
1723
1724class CmpBranchRIEa<string mnemonic, bits<16> opcode,
1725                    RegisterOperand cls, Immediate imm>
1726  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
1727             mnemonic#"$M3\t$R1, $I2", []>;
1728
1729class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
1730                       RegisterOperand cls, Immediate imm>
1731  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
1732             mnemonic#"\t$R1, $I2, $M3", []>;
1733
1734class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
1735                          RegisterOperand cls, Immediate imm>
1736  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
1737             mnemonic#V.suffix#"\t$R1, $I2", []> {
1738  let isAsmParserOnly = V.alternate;
1739  let M3 = V.ccmask;
1740}
1741
1742multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
1743                             RegisterOperand cls, Immediate imm> {
1744  let isCodeGenOnly = 1 in
1745    def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
1746  def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
1747}
1748
1749class CmpBranchRIEb<string mnemonic, bits<16> opcode,
1750                    RegisterOperand cls>
1751  : InstRIEb<opcode, (outs),
1752             (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
1753             mnemonic#"$M3\t$R1, $R2, $RI4", []>;
1754
1755class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
1756                       RegisterOperand cls>
1757  : InstRIEb<opcode, (outs),
1758             (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
1759             mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
1760
1761class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
1762                         RegisterOperand cls>
1763  : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
1764             mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
1765  let isAsmParserOnly = V.alternate;
1766  let M3 = V.ccmask;
1767}
1768
1769multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
1770                             RegisterOperand cls> {
1771  let isCodeGenOnly = 1 in
1772    def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
1773  def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
1774}
1775
1776class CmpBranchRIEc<string mnemonic, bits<16> opcode,
1777                    RegisterOperand cls, Immediate imm>
1778  : InstRIEc<opcode, (outs),
1779             (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
1780             mnemonic#"$M3\t$R1, $I2, $RI4", []>;
1781
1782class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
1783                       RegisterOperand cls, Immediate imm>
1784  : InstRIEc<opcode, (outs),
1785             (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
1786             mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
1787
1788class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
1789                         RegisterOperand cls, Immediate imm>
1790  : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
1791             mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
1792  let isAsmParserOnly = V.alternate;
1793  let M3 = V.ccmask;
1794}
1795
1796multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
1797                            RegisterOperand cls, Immediate imm> {
1798  let isCodeGenOnly = 1 in
1799    def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
1800  def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
1801}
1802
1803class CmpBranchRRFc<string mnemonic, bits<16> opcode,
1804                    RegisterOperand cls>
1805  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
1806             mnemonic#"$M3\t$R1, $R2", []>;
1807
1808class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
1809                       RegisterOperand cls>
1810  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
1811             mnemonic#"\t$R1, $R2, $M3", []>;
1812
1813multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
1814                             RegisterOperand cls> {
1815  let isCodeGenOnly = 1 in
1816    def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
1817  def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
1818}
1819
1820class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
1821                          RegisterOperand cls>
1822  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
1823             mnemonic#V.suffix#"\t$R1, $R2", []> {
1824  let isAsmParserOnly = V.alternate;
1825  let M3 = V.ccmask;
1826}
1827
1828class CmpBranchRRS<string mnemonic, bits<16> opcode,
1829                   RegisterOperand cls>
1830  : InstRRS<opcode, (outs),
1831            (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
1832            mnemonic#"$M3\t$R1, $R2, $BD4", []>;
1833
1834class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
1835                      RegisterOperand cls>
1836  : InstRRS<opcode, (outs),
1837            (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
1838            mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
1839
1840class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
1841                        RegisterOperand cls>
1842  : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
1843            mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
1844  let isAsmParserOnly = V.alternate;
1845  let M3 = V.ccmask;
1846}
1847
1848multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
1849                            RegisterOperand cls> {
1850  let isCodeGenOnly = 1 in
1851    def "" : CmpBranchRRS<mnemonic, opcode, cls>;
1852  def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
1853}
1854
1855class CmpBranchRIS<string mnemonic, bits<16> opcode,
1856                   RegisterOperand cls, Immediate imm>
1857  : InstRIS<opcode, (outs),
1858            (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
1859            mnemonic#"$M3\t$R1, $I2, $BD4", []>;
1860
1861class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
1862                      RegisterOperand cls, Immediate imm>
1863  : InstRIS<opcode, (outs),
1864            (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
1865            mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
1866
1867class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
1868                        RegisterOperand cls, Immediate imm>
1869  : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
1870            mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
1871  let isAsmParserOnly = V.alternate;
1872  let M3 = V.ccmask;
1873}
1874
1875multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
1876                            RegisterOperand cls, Immediate imm> {
1877  let isCodeGenOnly = 1 in
1878    def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
1879  def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
1880}
1881
1882class CmpBranchRSYb<string mnemonic, bits<16> opcode,
1883                    RegisterOperand cls>
1884  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
1885             mnemonic#"$M3\t$R1, $BD2", []>;
1886
1887class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
1888                       RegisterOperand cls>
1889  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
1890             mnemonic#"\t$R1, $M3, $BD2", []>;
1891
1892multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
1893                             RegisterOperand cls> {
1894  let isCodeGenOnly = 1 in
1895    def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
1896  def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
1897}
1898
1899class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
1900                          RegisterOperand cls>
1901  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
1902             mnemonic#V.suffix#"\t$R1, $BD2", []> {
1903  let isAsmParserOnly = V.alternate;
1904  let M3 = V.ccmask;
1905}
1906
1907class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
1908  : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
1909            mnemonic##"\t$R1, $RI2", []> {
1910  let Constraints = "$R1 = $R1src";
1911  let DisableEncoding = "$R1src";
1912}
1913
1914class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
1915  : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
1916            mnemonic##"\t$R1, $R3, $RI2", []> {
1917  let Constraints = "$R1 = $R1src";
1918  let DisableEncoding = "$R1src";
1919}
1920
1921class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1922                     AddressingMode mode = bdaddr12only>
1923  : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1924            mnemonic#"\t$R1, $R3, $BD2", []> {
1925  let mayLoad = 1;
1926}
1927
1928class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1929                      AddressingMode mode = bdaddr20only>
1930  : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1931             mnemonic#"\t$R1, $R3, $BD2", []> {
1932  let mayLoad = 1;
1933}
1934
1935multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1936                              bits<16> rsyOpcode, RegisterOperand cls> {
1937  let DispKey = mnemonic ## #cls in {
1938    let DispSize = "12" in
1939      def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1940    let DispSize = "20" in
1941      def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1942  }
1943}
1944
1945class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
1946  : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
1947             mnemonic#"\t$V1, $V3, $BD2", []> {
1948  let M4 = 0;
1949  let mayLoad = 1;
1950}
1951
1952class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1953                 RegisterOperand cls>
1954  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
1955             mnemonic#"\t$R1, $RI2",
1956             [(operator cls:$R1, pcrel32:$RI2)]> {
1957  let mayStore = 1;
1958  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1959  // However, BDXs have two extra operands and are therefore 6 units more
1960  // complex.
1961  let AddedComplexity = 7;
1962}
1963
1964class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1965              RegisterOperand cls, bits<5> bytes,
1966              AddressingMode mode = bdxaddr12only>
1967  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1968            mnemonic#"\t$R1, $XBD2",
1969            [(operator cls:$R1, mode:$XBD2)]> {
1970  let OpKey = mnemonic#"r"#cls;
1971  let OpType = "mem";
1972  let mayStore = 1;
1973  let AccessBytes = bytes;
1974}
1975
1976class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1977               RegisterOperand cls, bits<5> bytes,
1978               AddressingMode mode = bdxaddr20only>
1979  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1980             mnemonic#"\t$R1, $XBD2",
1981             [(operator cls:$R1, mode:$XBD2)]> {
1982  let OpKey = mnemonic#"r"#cls;
1983  let OpType = "mem";
1984  let mayStore = 1;
1985  let AccessBytes = bytes;
1986}
1987
1988multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1989                       SDPatternOperator operator, RegisterOperand cls,
1990                       bits<5> bytes> {
1991  let DispKey = mnemonic ## #cls in {
1992    let DispSize = "12" in
1993      def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1994    let DispSize = "20" in
1995      def Y  : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1996                        bdxaddr20pair>;
1997  }
1998}
1999
2000class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2001               TypedReg tr, bits<5> bytes, bits<4> type = 0>
2002  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
2003            mnemonic#"\t$V1, $XBD2",
2004            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2005  let M3 = type;
2006  let mayStore = 1;
2007  let AccessBytes = bytes;
2008}
2009
2010class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2011                      SDPatternOperator operator, bits<5> bytes>
2012  : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2013             mnemonic#"\t$V1, $R3, $BD2",
2014             [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2015  let M4 = 0;
2016  let mayStore = 1;
2017  let AccessBytes = bytes;
2018}
2019
2020class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2021                      AddressingMode mode = bdaddr12only>
2022  : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2023            mnemonic#"\t$R1, $R3, $BD2", []> {
2024  let mayStore = 1;
2025}
2026
2027class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2028                       AddressingMode mode = bdaddr20only>
2029  : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2030             mnemonic#"\t$R1, $R3, $BD2", []> {
2031  let mayStore = 1;
2032}
2033
2034multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2035                               bits<16> rsyOpcode, RegisterOperand cls> {
2036  let DispKey = mnemonic ## #cls in {
2037    let DispSize = "12" in
2038      def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2039    let DispSize = "20" in
2040      def Y  : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2041  }
2042}
2043
2044class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
2045  : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
2046             mnemonic#"\t$V1, $V3, $BD2", []> {
2047  let M4 = 0;
2048  let mayStore = 1;
2049}
2050
2051// StoreSI* instructions are used to store an integer to memory, but the
2052// addresses are more restricted than for normal stores.  If we are in the
2053// situation of having to force either the address into a register or the
2054// constant into a register, it's usually better to do the latter.
2055// We therefore match the address in the same way as a normal store and
2056// only use the StoreSI* instruction if the matched address is suitable.
2057class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2058              Immediate imm>
2059  : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2060           mnemonic#"\t$BD1, $I2",
2061           [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2062  let mayStore = 1;
2063}
2064
2065class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2066               Immediate imm>
2067  : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
2068            mnemonic#"\t$BD1, $I2",
2069            [(operator imm:$I2, mviaddr20pair:$BD1)]> {
2070  let mayStore = 1;
2071}
2072
2073class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2074               Immediate imm>
2075  : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2076            mnemonic#"\t$BD1, $I2",
2077            [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2078  let mayStore = 1;
2079}
2080
2081multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2082                       SDPatternOperator operator, Immediate imm> {
2083  let DispKey = mnemonic in {
2084    let DispSize = "12" in
2085      def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
2086    let DispSize = "20" in
2087      def Y  : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
2088  }
2089}
2090
2091class StoreSSE<string mnemonic, bits<16> opcode>
2092  : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2093            mnemonic#"\t$BD1, $BD2", []> {
2094  let mayStore = 1;
2095}
2096
2097class CondStoreRSY<string mnemonic, bits<16> opcode,
2098                   RegisterOperand cls, bits<5> bytes,
2099                   AddressingMode mode = bdaddr20only>
2100  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
2101            mnemonic#"$M3\t$R1, $BD2", []> {
2102  let mayStore = 1;
2103  let AccessBytes = bytes;
2104  let CCMaskLast = 1;
2105}
2106
2107// Like CondStoreRSY, but used for the raw assembly form.  The condition-code
2108// mask is the third operand rather than being part of the mnemonic.
2109class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2110                      RegisterOperand cls, bits<5> bytes,
2111                      AddressingMode mode = bdaddr20only>
2112  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
2113             mnemonic#"\t$R1, $BD2, $M3", []> {
2114  let mayStore = 1;
2115  let AccessBytes = bytes;
2116}
2117
2118// Like CondStoreRSY, but with a fixed CC mask.
2119class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2120                        RegisterOperand cls, bits<5> bytes,
2121                        AddressingMode mode = bdaddr20only>
2122  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
2123             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2124  let mayStore = 1;
2125  let AccessBytes = bytes;
2126  let isAsmParserOnly = V.alternate;
2127  let M3 = V.ccmask;
2128}
2129
2130multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2131                            RegisterOperand cls, bits<5> bytes,
2132                            AddressingMode mode = bdaddr20only> {
2133  let isCodeGenOnly = 1 in
2134    def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2135  def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2136}
2137
2138class SideEffectUnaryI<string mnemonic, bits<8> opcode, Immediate imm>
2139  : InstI<opcode, (outs), (ins imm:$I1),
2140          mnemonic#"\t$I1", []> {
2141  let hasSideEffects = 1;
2142}
2143
2144class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2145  : InstRR<opcode, (outs), (ins cls:$R1),
2146           mnemonic#"\t$R1", []> {
2147  let hasSideEffects = 1;
2148  let R2 = 0;
2149}
2150
2151class SideEffectUnaryS<string mnemonic, bits<16> opcode,
2152                       SDPatternOperator operator>
2153  : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
2154          mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
2155  let hasSideEffects = 1;
2156}
2157
2158class LoadAddressRX<string mnemonic, bits<8> opcode,
2159                    SDPatternOperator operator, AddressingMode mode>
2160  : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2161            mnemonic#"\t$R1, $XBD2",
2162            [(set GR64:$R1, (operator mode:$XBD2))]>;
2163
2164class LoadAddressRXY<string mnemonic, bits<16> opcode,
2165                     SDPatternOperator operator, AddressingMode mode>
2166  : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2167             mnemonic#"\t$R1, $XBD2",
2168             [(set GR64:$R1, (operator mode:$XBD2))]>;
2169
2170multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
2171                             bits<16> rxyOpcode, SDPatternOperator operator> {
2172  let DispKey = mnemonic in {
2173    let DispSize = "12" in
2174      def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
2175    let DispSize = "20" in
2176      def Y  : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>;
2177  }
2178}
2179
2180class LoadAddressRIL<string mnemonic, bits<12> opcode,
2181                     SDPatternOperator operator>
2182  : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
2183             mnemonic#"\t$R1, $RI2",
2184             [(set GR64:$R1, (operator pcrel32:$RI2))]>;
2185
2186class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2187              RegisterOperand cls1, RegisterOperand cls2>
2188  : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
2189           mnemonic#"\t$R1, $R2",
2190           [(set cls1:$R1, (operator cls2:$R2))]> {
2191  let OpKey = mnemonic#cls1;
2192  let OpType = "reg";
2193}
2194
2195class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2196               RegisterOperand cls1, RegisterOperand cls2>
2197  : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
2198            mnemonic#"\t$R1, $R2",
2199            [(set cls1:$R1, (operator cls2:$R2))]> {
2200  let OpKey = mnemonic#cls1;
2201  let OpType = "reg";
2202}
2203
2204// These instructions are generated by if conversion.  The old value of R1
2205// is added as an implicit use.
2206class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2207                   RegisterOperand cls2>
2208  : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$M3),
2209             mnemonic#"$M3\t$R1, $R2", []> {
2210  let CCMaskLast = 1;
2211}
2212
2213class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2214                   Immediate imm>
2215  : InstRIEg<opcode, (outs cls:$R1), (ins imm:$I2, cond4:$valid, cond4:$M3),
2216             mnemonic#"$M3\t$R1, $I2", []> {
2217  let CCMaskLast = 1;
2218}
2219
2220// Like CondUnaryRRF, but used for the raw assembly form.  The condition-code
2221// mask is the third operand rather than being part of the mnemonic.
2222class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2223                      RegisterOperand cls2>
2224  : InstRRFc<opcode, (outs cls1:$R1),
2225             (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
2226             mnemonic#"\t$R1, $R2, $M3", []> {
2227  let Constraints = "$R1 = $R1src";
2228  let DisableEncoding = "$R1src";
2229}
2230
2231class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2232                   Immediate imm>
2233  : InstRIEg<opcode, (outs cls:$R1),
2234             (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
2235             mnemonic#"\t$R1, $I2, $M3", []> {
2236  let Constraints = "$R1 = $R1src";
2237  let DisableEncoding = "$R1src";
2238}
2239
2240// Like CondUnaryRRF, but with a fixed CC mask.
2241class FixedCondUnaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
2242                        RegisterOperand cls1, RegisterOperand cls2>
2243  : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2244             mnemonic#V.suffix#"\t$R1, $R2", []> {
2245  let Constraints = "$R1 = $R1src";
2246  let DisableEncoding = "$R1src";
2247  let isAsmParserOnly = V.alternate;
2248  let M3 = V.ccmask;
2249}
2250
2251class FixedCondUnaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
2252                        RegisterOperand cls, Immediate imm>
2253  : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2254             mnemonic#V.suffix#"\t$R1, $I2", []> {
2255  let Constraints = "$R1 = $R1src";
2256  let DisableEncoding = "$R1src";
2257  let isAsmParserOnly = V.alternate;
2258  let M3 = V.ccmask;
2259}
2260
2261multiclass CondUnaryRRFPair<string mnemonic, bits<16> opcode,
2262                            RegisterOperand cls1, RegisterOperand cls2> {
2263  let isCodeGenOnly = 1 in
2264    def "" : CondUnaryRRF<mnemonic, opcode, cls1, cls2>;
2265  def Asm : AsmCondUnaryRRF<mnemonic, opcode, cls1, cls2>;
2266}
2267
2268multiclass CondUnaryRIEPair<string mnemonic, bits<16> opcode,
2269                            RegisterOperand cls, Immediate imm> {
2270  let isCodeGenOnly = 1 in
2271    def "" : CondUnaryRIE<mnemonic, opcode, cls, imm>;
2272  def Asm : AsmCondUnaryRIE<mnemonic, opcode, cls, imm>;
2273}
2274
2275class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2276              RegisterOperand cls, Immediate imm>
2277  : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2278            mnemonic#"\t$R1, $I2",
2279            [(set cls:$R1, (operator imm:$I2))]>;
2280
2281class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2282               RegisterOperand cls, Immediate imm>
2283  : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2284             mnemonic#"\t$R1, $I2",
2285             [(set cls:$R1, (operator imm:$I2))]>;
2286
2287class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2288                 RegisterOperand cls>
2289  : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
2290             mnemonic#"\t$R1, $RI2",
2291             [(set cls:$R1, (operator pcrel32:$RI2))]> {
2292  let mayLoad = 1;
2293  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2294  // However, BDXs have two extra operands and are therefore 6 units more
2295  // complex.
2296  let AddedComplexity = 7;
2297}
2298
2299class CondUnaryRSY<string mnemonic, bits<16> opcode,
2300                   SDPatternOperator operator, RegisterOperand cls,
2301                   bits<5> bytes, AddressingMode mode = bdaddr20only>
2302  : InstRSYb<opcode, (outs cls:$R1),
2303             (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
2304             mnemonic#"$M3\t$R1, $BD2",
2305             [(set cls:$R1,
2306                   (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
2307                                    cond4:$valid, cond4:$M3))]> {
2308  let Constraints = "$R1 = $R1src";
2309  let DisableEncoding = "$R1src";
2310  let mayLoad = 1;
2311  let AccessBytes = bytes;
2312  let CCMaskLast = 1;
2313}
2314
2315// Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
2316// mask is the third operand rather than being part of the mnemonic.
2317class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
2318                      RegisterOperand cls, bits<5> bytes,
2319                      AddressingMode mode = bdaddr20only>
2320  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
2321             mnemonic#"\t$R1, $BD2, $M3", []> {
2322  let mayLoad = 1;
2323  let AccessBytes = bytes;
2324  let Constraints = "$R1 = $R1src";
2325  let DisableEncoding = "$R1src";
2326}
2327
2328// Like CondUnaryRSY, but with a fixed CC mask.
2329class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
2330                        RegisterOperand cls, bits<5> bytes,
2331                        AddressingMode mode = bdaddr20only>
2332  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
2333             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2334  let Constraints = "$R1 = $R1src";
2335  let DisableEncoding = "$R1src";
2336  let mayLoad = 1;
2337  let AccessBytes = bytes;
2338  let isAsmParserOnly = V.alternate;
2339  let M3 = V.ccmask;
2340}
2341
2342multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
2343                            SDPatternOperator operator,
2344                            RegisterOperand cls, bits<5> bytes,
2345                            AddressingMode mode = bdaddr20only> {
2346  let isCodeGenOnly = 1 in
2347    def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2348  def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2349}
2350
2351
2352class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2353              RegisterOperand cls, bits<5> bytes,
2354              AddressingMode mode = bdxaddr12only>
2355  : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2356            mnemonic#"\t$R1, $XBD2",
2357            [(set cls:$R1, (operator mode:$XBD2))]> {
2358  let OpKey = mnemonic#"r"#cls;
2359  let OpType = "mem";
2360  let mayLoad = 1;
2361  let AccessBytes = bytes;
2362}
2363
2364class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2365               RegisterOperand cls, bits<5> bytes>
2366  : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
2367            mnemonic#"\t$R1, $XBD2",
2368            [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
2369  let OpKey = mnemonic#"r"#cls;
2370  let OpType = "mem";
2371  let mayLoad = 1;
2372  let AccessBytes = bytes;
2373  let M3 = 0;
2374}
2375
2376class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2377               RegisterOperand cls, bits<5> bytes,
2378               AddressingMode mode = bdxaddr20only>
2379  : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2380             mnemonic#"\t$R1, $XBD2",
2381             [(set cls:$R1, (operator mode:$XBD2))]> {
2382  let OpKey = mnemonic#"r"#cls;
2383  let OpType = "mem";
2384  let mayLoad = 1;
2385  let AccessBytes = bytes;
2386}
2387
2388multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2389                       SDPatternOperator operator, RegisterOperand cls,
2390                       bits<5> bytes> {
2391  let DispKey = mnemonic ## #cls in {
2392    let DispSize = "12" in
2393      def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2394    let DispSize = "20" in
2395      def Y  : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2396                        bdxaddr20pair>;
2397  }
2398}
2399
2400class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2401                TypedReg tr, Immediate imm, bits<4> type = 0>
2402  : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
2403             mnemonic#"\t$V1, $I2",
2404             [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
2405  let M3 = type;
2406}
2407
2408class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, Immediate imm>
2409  : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
2410             mnemonic#"\t$V1, $I2, $M3", []>;
2411
2412class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2413                TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
2414                bits<4> m5 = 0>
2415  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
2416             mnemonic#"\t$V1, $V2",
2417             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
2418  let M3 = type;
2419  let M4 = m4;
2420  let M5 = m5;
2421}
2422
2423class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
2424                       bits<4> m5 = 0>
2425  : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
2426             mnemonic#"\t$V1, $V2, $M3", []> {
2427  let M4 = m4;
2428  let M5 = m5;
2429}
2430
2431class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
2432  : InstVRRa<opcode, (outs VR128:$V1),
2433             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
2434             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
2435  let M5 = m5;
2436}
2437
2438// Declare a pair of instructions, one which sets CC and one which doesn't.
2439// The CC-setting form ends with "S" and sets the low bit of M5.
2440// The form that does not set CC has an extra operand to optionally allow
2441// specifying arbitrary M5 values in assembler.
2442multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
2443                               SDPatternOperator operator,
2444                               SDPatternOperator operator_cc,
2445                               TypedReg tr1, TypedReg tr2, bits<4> type> {
2446  let M3 = type, M4 = 0 in
2447    def "" : InstVRRa<opcode, (outs tr1.op:$V1),
2448                      (ins tr2.op:$V2, imm32zx4:$M5),
2449                      mnemonic#"\t$V1, $V2, $M5", []>;
2450  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
2451            (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
2452  def : InstAlias<mnemonic#"\t$V1, $V2",
2453                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
2454  let Defs = [CC] in
2455    def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2,
2456                      type, 0, 1>;
2457}
2458
2459multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
2460  let M4 = 0 in
2461    def "" : InstVRRa<opcode, (outs VR128:$V1),
2462                     (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
2463                     mnemonic#"\t$V1, $V2, $M3, $M5", []>;
2464  def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
2465                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
2466                                            imm32zx4:$M3, 0)>;
2467}
2468
2469class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2470               TypedReg tr, bits<5> bytes, bits<4> type = 0>
2471  : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
2472            mnemonic#"\t$V1, $XBD2",
2473            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
2474  let M3 = type;
2475  let mayLoad = 1;
2476  let AccessBytes = bytes;
2477}
2478
2479class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
2480  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
2481            mnemonic#"\t$V1, $XBD2, $M3", []> {
2482  let mayLoad = 1;
2483}
2484
2485class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
2486                         RegisterOperand cls>
2487  : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2488            mnemonic##"\t$R1, $XBD2", []> {
2489  let hasSideEffects = 1;
2490}
2491
2492class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
2493                            RegisterOperand cls>
2494  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2495             mnemonic##"\t$R1, $RI2", []> {
2496  let hasSideEffects = 1;
2497  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2498  // However, BDXs have two extra operands and are therefore 6 units more
2499  // complex.
2500  let AddedComplexity = 7;
2501}
2502
2503class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
2504                          SDPatternOperator operator, Immediate imm>
2505  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2506            mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]> {
2507  let hasSideEffects = 1;
2508}
2509
2510class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2511               RegisterOperand cls1, RegisterOperand cls2>
2512  : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2513           mnemonic#"\t$R1, $R2",
2514           [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
2515  let OpKey = mnemonic#cls1;
2516  let OpType = "reg";
2517  let Constraints = "$R1 = $R1src";
2518  let DisableEncoding = "$R1src";
2519}
2520
2521class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2522                RegisterOperand cls1, RegisterOperand cls2>
2523  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
2524            mnemonic#"\t$R1, $R2",
2525            [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
2526  let OpKey = mnemonic#cls1;
2527  let OpType = "reg";
2528  let Constraints = "$R1 = $R1src";
2529  let DisableEncoding = "$R1src";
2530}
2531
2532class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2533                 RegisterOperand cls1, RegisterOperand cls2,
2534                 RegisterOperand cls3>
2535  : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
2536             mnemonic#"\t$R1, $R2, $R3",
2537             [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
2538  let M4 = 0;
2539}
2540
2541multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
2542                        SDPatternOperator operator, RegisterOperand cls1,
2543                        RegisterOperand cls2> {
2544  let NumOpsKey = mnemonic in {
2545    let NumOpsValue = "3" in
2546      def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
2547              Requires<[FeatureDistinctOps]>;
2548    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2549      def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
2550  }
2551}
2552
2553multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
2554                         SDPatternOperator operator, RegisterOperand cls1,
2555                         RegisterOperand cls2> {
2556  let NumOpsKey = mnemonic in {
2557    let NumOpsValue = "3" in
2558      def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
2559              Requires<[FeatureDistinctOps]>;
2560    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2561      def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
2562  }
2563}
2564
2565class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2566                 RegisterOperand cls1, RegisterOperand cls2,
2567                 RegisterOperand cls3>
2568  : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
2569             mnemonic#"\t$R1, $R3, $R2",
2570             [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
2571  let M4 = 0;
2572}
2573
2574class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2575                RegisterOperand cls2>
2576  : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
2577             mnemonic#"\t$R1, $M3, $R2", []> {
2578  let M4 = 0;
2579}
2580
2581class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2582               RegisterOperand cls, Immediate imm>
2583  : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2584            mnemonic#"\t$R1, $I2",
2585            [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2586  let Constraints = "$R1 = $R1src";
2587  let DisableEncoding = "$R1src";
2588}
2589
2590class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2591                RegisterOperand cls, Immediate imm>
2592  : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
2593             mnemonic#"\t$R1, $R3, $I2",
2594             [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2595
2596multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
2597                        SDPatternOperator operator, RegisterOperand cls,
2598                        Immediate imm> {
2599  let NumOpsKey = mnemonic in {
2600    let NumOpsValue = "3" in
2601      def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
2602              Requires<[FeatureDistinctOps]>;
2603    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2604      def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
2605  }
2606}
2607
2608class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2609                RegisterOperand cls, Immediate imm>
2610  : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2611             mnemonic#"\t$R1, $I2",
2612             [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2613  let Constraints = "$R1 = $R1src";
2614  let DisableEncoding = "$R1src";
2615}
2616
2617class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2618               RegisterOperand cls>
2619  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
2620            mnemonic#"\t$R1, $BD2",
2621            [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
2622  let R3 = 0;
2623  let Constraints = "$R1 = $R1src";
2624  let DisableEncoding = "$R1src";
2625}
2626
2627class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2628                RegisterOperand cls>
2629  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
2630             mnemonic#"\t$R1, $R3, $BD2",
2631             [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
2632
2633multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
2634                        SDPatternOperator operator, RegisterOperand cls> {
2635  let NumOpsKey = mnemonic in {
2636    let NumOpsValue = "3" in
2637      def K  : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
2638               Requires<[FeatureDistinctOps]>;
2639    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2640      def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
2641  }
2642}
2643
2644class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2645               RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2646               AddressingMode mode = bdxaddr12only>
2647  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
2648            mnemonic#"\t$R1, $XBD2",
2649            [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
2650  let OpKey = mnemonic#"r"#cls;
2651  let OpType = "mem";
2652  let Constraints = "$R1 = $R1src";
2653  let DisableEncoding = "$R1src";
2654  let mayLoad = 1;
2655  let AccessBytes = bytes;
2656}
2657
2658class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2659                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2660  : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2661            mnemonic#"\t$R1, $XBD2",
2662            [(set cls:$R1, (operator cls:$R1src,
2663                                     (load bdxaddr12only:$XBD2)))]> {
2664  let OpKey = mnemonic#"r"#cls;
2665  let OpType = "mem";
2666  let Constraints = "$R1 = $R1src";
2667  let DisableEncoding = "$R1src";
2668  let mayLoad = 1;
2669  let AccessBytes = bytes;
2670  let M3 = 0;
2671}
2672
2673class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2674                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2675                AddressingMode mode = bdxaddr20only>
2676  : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
2677             mnemonic#"\t$R1, $XBD2",
2678             [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
2679  let OpKey = mnemonic#"r"#cls;
2680  let OpType = "mem";
2681  let Constraints = "$R1 = $R1src";
2682  let DisableEncoding = "$R1src";
2683  let mayLoad = 1;
2684  let AccessBytes = bytes;
2685}
2686
2687multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2688                        SDPatternOperator operator, RegisterOperand cls,
2689                        SDPatternOperator load, bits<5> bytes> {
2690  let DispKey = mnemonic ## #cls in {
2691    let DispSize = "12" in
2692      def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
2693                        bdxaddr12pair>;
2694    let DispSize = "20" in
2695      def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
2696                         bdxaddr20pair>;
2697  }
2698}
2699
2700class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2701               Operand imm, AddressingMode mode = bdaddr12only>
2702  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
2703           mnemonic#"\t$BD1, $I2",
2704           [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
2705  let mayLoad = 1;
2706  let mayStore = 1;
2707}
2708
2709class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2710                Operand imm, AddressingMode mode = bdaddr20only>
2711  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
2712            mnemonic#"\t$BD1, $I2",
2713            [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
2714  let mayLoad = 1;
2715  let mayStore = 1;
2716}
2717
2718multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
2719                        bits<16> siyOpcode, SDPatternOperator operator,
2720                        Operand imm> {
2721  let DispKey = mnemonic ## #cls in {
2722    let DispSize = "12" in
2723      def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
2724    let DispSize = "20" in
2725      def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
2726  }
2727}
2728
2729class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2730                 TypedReg tr, bits<4> type>
2731  : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
2732             mnemonic#"\t$V1, $I2, $I3",
2733             [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
2734  let M4 = type;
2735}
2736
2737class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
2738  : InstVRIb<opcode, (outs VR128:$V1),
2739             (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
2740             mnemonic#"\t$V1, $I2, $I3, $M4", []>;
2741
2742class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2743                 TypedReg tr1, TypedReg tr2, bits<4> type>
2744  : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
2745             mnemonic#"\t$V1, $V3, $I2",
2746             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2747                                                 imm32zx16:$I2)))]> {
2748  let M4 = type;
2749}
2750
2751class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
2752  : InstVRIc<opcode, (outs VR128:$V1),
2753             (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
2754             mnemonic#"\t$V1, $V3, $I2, $M4", []>;
2755
2756class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2757                 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
2758  : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
2759             mnemonic#"\t$V1, $V2, $I3",
2760             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2761                                                 imm32zx12:$I3)))]> {
2762  let M4 = type;
2763  let M5 = m5;
2764}
2765
2766class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
2767  : InstVRIe<opcode, (outs VR128:$V1),
2768             (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
2769             mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
2770
2771class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2772                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
2773  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
2774             mnemonic#"\t$V1, $V2, $M5",
2775             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2776                                                 imm32zx12:$M5)))]> {
2777  let M3 = type;
2778  let M4 = m4;
2779}
2780
2781class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
2782  : InstVRRa<opcode, (outs VR128:$V1),
2783             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
2784             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
2785
2786class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2787                 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
2788                 bits<4> modifier = 0>
2789  : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
2790             mnemonic#"\t$V1, $V2, $V3",
2791             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2792                                                 (tr2.vt tr2.op:$V3))))]> {
2793  let M4 = type;
2794  let M5 = modifier;
2795}
2796
2797// Declare a pair of instructions, one which sets CC and one which doesn't.
2798// The CC-setting form ends with "S" and sets the low bit of M5.
2799multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
2800                           SDPatternOperator operator,
2801                           SDPatternOperator operator_cc, TypedReg tr1,
2802                           TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
2803  def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2804                      !and (modifier, 14)>;
2805  let Defs = [CC] in
2806    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2807                       !add (!and (modifier, 14), 1)>;
2808}
2809
2810class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
2811  : InstVRRb<opcode, (outs VR128:$V1),
2812             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2813             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
2814
2815// Declare a pair of instructions, one which sets CC and one which doesn't.
2816// The CC-setting form ends with "S" and sets the low bit of M5.
2817// The form that does not set CC has an extra operand to optionally allow
2818// specifying arbitrary M5 values in assembler.
2819multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
2820                                SDPatternOperator operator,
2821                                SDPatternOperator operator_cc,
2822                                TypedReg tr1, TypedReg tr2, bits<4> type> {
2823  let M4 = type in
2824    def "" : InstVRRb<opcode, (outs tr1.op:$V1),
2825                      (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
2826                      mnemonic#"\t$V1, $V2, $V3, $M5", []>;
2827  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
2828            (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
2829  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2830                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2831                                            tr2.op:$V3, 0)>;
2832  let Defs = [CC] in
2833    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>;
2834}
2835
2836multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
2837  def "" : InstVRRb<opcode, (outs VR128:$V1),
2838                   (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2839                   mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
2840  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
2841                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
2842                                            imm32zx4:$M4, 0)>;
2843}
2844
2845class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2846                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
2847                 bits<4> m6 = 0>
2848  : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
2849             mnemonic#"\t$V1, $V2, $V3",
2850             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2851                                                 (tr2.vt tr2.op:$V3))))]> {
2852  let M4 = type;
2853  let M5 = m5;
2854  let M6 = m6;
2855}
2856
2857class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
2858                        bits<4> m6 = 0>
2859  : InstVRRc<opcode, (outs VR128:$V1),
2860             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
2861             mnemonic#"\t$V1, $V2, $V3, $M4", []> {
2862  let M5 = m5;
2863  let M6 = m6;
2864}
2865
2866class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
2867  : InstVRRc<opcode, (outs VR128:$V1),
2868             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
2869             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
2870  let M6 = m6;
2871}
2872
2873// Declare a pair of instructions, one which sets CC and one which doesn't.
2874// The CC-setting form ends with "S" and sets the low bit of M5.
2875multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
2876                           SDPatternOperator operator,
2877                           SDPatternOperator operator_cc, TypedReg tr1,
2878                           TypedReg tr2, bits<4> type, bits<4> m5,
2879                           bits<4> modifier = 0> {
2880  def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
2881                      m5, !and (modifier, 14)>;
2882  let Defs = [CC] in
2883    def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2884                       m5, !add (!and (modifier, 14), 1)>;
2885}
2886
2887class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
2888  : InstVRRc<opcode, (outs VR128:$V1),
2889             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
2890                  imm32zx4:$M6),
2891             mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
2892
2893class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2894                 TypedReg tr>
2895  : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
2896             mnemonic#"\t$V1, $R2, $R3",
2897             [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
2898
2899class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2900                 TypedReg tr1, TypedReg tr2, bits<4> type>
2901  : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
2902             mnemonic#"\t$V1, $V3, $BD2",
2903             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2904                                                 shift12only:$BD2)))]> {
2905  let M4 = type;
2906}
2907
2908class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
2909  : InstVRSa<opcode, (outs VR128:$V1),
2910             (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
2911             mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2912
2913class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2914                 bits<5> bytes>
2915  : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
2916             mnemonic#"\t$V1, $R3, $BD2",
2917             [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
2918  let M4 = 0;
2919  let mayLoad = 1;
2920  let AccessBytes = bytes;
2921}
2922
2923class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2924                 TypedReg tr, bits<4> type>
2925  : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
2926           mnemonic#"\t$R1, $V3, $BD2",
2927           [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
2928  let M4 = type;
2929}
2930
2931class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
2932  : InstVRSc<opcode, (outs GR64:$R1),
2933             (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
2934             mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
2935
2936class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2937                TypedReg tr, bits<5> bytes>
2938  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
2939            mnemonic#"\t$V1, $XBD2, $M3",
2940            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
2941                                              imm32zx4:$M3)))]> {
2942  let mayLoad = 1;
2943  let AccessBytes = bytes;
2944}
2945
2946class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2947                     Immediate index>
2948  : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
2949            mnemonic#"\t$V1, $VBD2, $M3", []> {
2950  let mayStore = 1;
2951  let AccessBytes = bytes;
2952}
2953
2954class StoreBinaryVRX<string mnemonic, bits<16> opcode,
2955                     SDPatternOperator operator, TypedReg tr, bits<5> bytes,
2956                     Immediate index>
2957  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
2958            mnemonic#"\t$V1, $XBD2, $M3",
2959            [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
2960  let mayStore = 1;
2961  let AccessBytes = bytes;
2962}
2963
2964class MemoryBinarySSd<string mnemonic, bits<8> opcode,
2965                      RegisterOperand cls>
2966  : InstSSd<opcode, (outs),
2967            (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
2968            mnemonic#"\t$RBD1, $BD2, $R3", []>;
2969
2970class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2971                RegisterOperand cls1, RegisterOperand cls2>
2972  : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2973           mnemonic#"\t$R1, $R2",
2974           [(operator cls1:$R1, cls2:$R2)]> {
2975  let OpKey = mnemonic#cls1;
2976  let OpType = "reg";
2977  let isCompare = 1;
2978}
2979
2980class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2981                 RegisterOperand cls1, RegisterOperand cls2>
2982  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2983            mnemonic#"\t$R1, $R2",
2984            [(operator cls1:$R1, cls2:$R2)]> {
2985  let OpKey = mnemonic#cls1;
2986  let OpType = "reg";
2987  let isCompare = 1;
2988}
2989
2990class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2991                RegisterOperand cls, Immediate imm>
2992  : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
2993            mnemonic#"\t$R1, $I2",
2994            [(operator cls:$R1, imm:$I2)]> {
2995  let isCompare = 1;
2996}
2997
2998class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2999                 RegisterOperand cls, Immediate imm>
3000  : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
3001             mnemonic#"\t$R1, $I2",
3002             [(operator cls:$R1, imm:$I2)]> {
3003  let isCompare = 1;
3004}
3005
3006class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3007                   RegisterOperand cls, SDPatternOperator load>
3008  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3009             mnemonic#"\t$R1, $RI2",
3010             [(operator cls:$R1, (load pcrel32:$RI2))]> {
3011  let isCompare = 1;
3012  let mayLoad = 1;
3013  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3014  // However, BDXs have two extra operands and are therefore 6 units more
3015  // complex.
3016  let AddedComplexity = 7;
3017}
3018
3019class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3020                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3021                AddressingMode mode = bdxaddr12only>
3022  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3023            mnemonic#"\t$R1, $XBD2",
3024            [(operator cls:$R1, (load mode:$XBD2))]> {
3025  let OpKey = mnemonic#"r"#cls;
3026  let OpType = "mem";
3027  let isCompare = 1;
3028  let mayLoad = 1;
3029  let AccessBytes = bytes;
3030}
3031
3032class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3033                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3034  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3035            mnemonic#"\t$R1, $XBD2",
3036            [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
3037  let OpKey = mnemonic#"r"#cls;
3038  let OpType = "mem";
3039  let isCompare = 1;
3040  let mayLoad = 1;
3041  let AccessBytes = bytes;
3042  let M3 = 0;
3043}
3044
3045class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3046                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3047                 AddressingMode mode = bdxaddr20only>
3048  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3049             mnemonic#"\t$R1, $XBD2",
3050             [(operator cls:$R1, (load mode:$XBD2))]> {
3051  let OpKey = mnemonic#"r"#cls;
3052  let OpType = "mem";
3053  let isCompare = 1;
3054  let mayLoad = 1;
3055  let AccessBytes = bytes;
3056}
3057
3058multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3059                         SDPatternOperator operator, RegisterOperand cls,
3060                         SDPatternOperator load, bits<5> bytes> {
3061  let DispKey = mnemonic ## #cls in {
3062    let DispSize = "12" in
3063      def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
3064                         load, bytes, bdxaddr12pair>;
3065    let DispSize = "20" in
3066      def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
3067                          load, bytes, bdxaddr20pair>;
3068  }
3069}
3070
3071class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3072                SDPatternOperator load, Immediate imm,
3073                AddressingMode mode = bdaddr12only>
3074  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3075           mnemonic#"\t$BD1, $I2",
3076           [(operator (load mode:$BD1), imm:$I2)]> {
3077  let isCompare = 1;
3078  let mayLoad = 1;
3079}
3080
3081class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3082                 SDPatternOperator load, Immediate imm>
3083  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3084            mnemonic#"\t$BD1, $I2",
3085            [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
3086  let isCompare = 1;
3087  let mayLoad = 1;
3088}
3089
3090class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3091                 SDPatternOperator load, Immediate imm,
3092                 AddressingMode mode = bdaddr20only>
3093  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3094            mnemonic#"\t$BD1, $I2",
3095            [(operator (load mode:$BD1), imm:$I2)]> {
3096  let isCompare = 1;
3097  let mayLoad = 1;
3098}
3099
3100multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
3101                         SDPatternOperator operator, SDPatternOperator load,
3102                         Immediate imm> {
3103  let DispKey = mnemonic in {
3104    let DispSize = "12" in
3105      def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
3106    let DispSize = "20" in
3107      def Y  : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
3108                          bdaddr20pair>;
3109  }
3110}
3111
3112class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3113                  TypedReg tr, bits<4> type>
3114  : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
3115             mnemonic#"\t$V1, $V2",
3116             [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
3117  let isCompare = 1;
3118  let M3 = type;
3119  let M4 = 0;
3120  let M5 = 0;
3121}
3122
3123class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
3124  : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
3125             mnemonic#"\t$V1, $V2, $M3", []> {
3126  let isCompare = 1;
3127  let M4 = 0;
3128  let M5 = 0;
3129}
3130
3131class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3132  : InstVRRa<opcode, (outs),
3133             (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
3134             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3135  let isCompare = 1;
3136  let M5 = 0;
3137}
3138
3139class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3140              RegisterOperand cls>
3141  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3142            mnemonic#"\t$R1, $XBD2",
3143            [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
3144  let M3 = 0;
3145}
3146
3147class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
3148                            RegisterOperand cls1, RegisterOperand cls2,
3149                            Immediate imm>
3150  : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
3151             mnemonic#"\t$R1, $R2, $M3", []> {
3152  let hasSideEffects = 1;
3153}
3154
3155class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
3156                           RegisterOperand cls>
3157  : InstSSF<opcode, (outs),
3158            (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
3159            mnemonic#"\t$BD1, $BD2, $R3", []> {
3160  let hasSideEffects = 1;
3161}
3162
3163class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3164                  RegisterOperand cls2>
3165  : InstRRFe<opcode, (outs cls1:$R1),
3166             (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
3167             mnemonic#"\t$R1, $M3, $R2, $M4", []>;
3168
3169class TernaryRRD<string mnemonic, bits<16> opcode,
3170                 SDPatternOperator operator, RegisterOperand cls>
3171  : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
3172            mnemonic#"\t$R1, $R3, $R2",
3173            [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
3174  let OpKey = mnemonic#cls;
3175  let OpType = "reg";
3176  let Constraints = "$R1 = $R1src";
3177  let DisableEncoding = "$R1src";
3178}
3179
3180class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3181                bits<5> bytes, AddressingMode mode = bdaddr12only>
3182  : InstRSb<opcode, (outs cls:$R1),
3183            (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
3184            mnemonic#"\t$R1, $M3, $BD2", []> {
3185
3186  let Constraints = "$R1 = $R1src";
3187  let DisableEncoding = "$R1src";
3188  let mayLoad = 1;
3189  let AccessBytes = bytes;
3190}
3191
3192class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3193                bits<5> bytes, AddressingMode mode = bdaddr20only>
3194  : InstRSYb<opcode, (outs cls:$R1),
3195             (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
3196             mnemonic#"\t$R1, $M3, $BD2", []> {
3197
3198  let Constraints = "$R1 = $R1src";
3199  let DisableEncoding = "$R1src";
3200  let mayLoad = 1;
3201  let AccessBytes = bytes;
3202}
3203
3204multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3205                         RegisterOperand cls, bits<5> bytes> {
3206  let DispKey = mnemonic ## #cls in {
3207    let DispSize = "12" in
3208      def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3209    let DispSize = "20" in
3210      def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
3211  }
3212}
3213
3214class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3215                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3216  : InstRXF<opcode, (outs cls:$R1),
3217            (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
3218            mnemonic#"\t$R1, $R3, $XBD2",
3219            [(set cls:$R1, (operator cls:$R1src, cls:$R3,
3220                                     (load bdxaddr12only:$XBD2)))]> {
3221  let OpKey = mnemonic#"r"#cls;
3222  let OpType = "mem";
3223  let Constraints = "$R1 = $R1src";
3224  let DisableEncoding = "$R1src";
3225  let mayLoad = 1;
3226  let AccessBytes = bytes;
3227}
3228
3229class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3230                  TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
3231  : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
3232             mnemonic#"\t$V1, $I2, $M3",
3233             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3234                                                 imm:$I2, index:$M3)))]> {
3235  let Constraints = "$V1 = $V1src";
3236  let DisableEncoding = "$V1src";
3237}
3238
3239class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3240                  TypedReg tr1, TypedReg tr2, bits<4> type>
3241  : InstVRId<opcode, (outs tr1.op:$V1),
3242             (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
3243             mnemonic#"\t$V1, $V2, $V3, $I4",
3244             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3245                                                 (tr2.vt tr2.op:$V3),
3246                                                 imm32zx8:$I4)))]> {
3247  let M5 = type;
3248}
3249
3250class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3251                  TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
3252  : InstVRRa<opcode, (outs tr1.op:$V1),
3253             (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
3254             mnemonic#"\t$V1, $V2, $M4, $M5",
3255             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3256                                                 imm32zx4:$M4,
3257                                                 imm32zx4:$M5)))],
3258             m4or> {
3259  let M3 = type;
3260}
3261
3262class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3263  : InstVRRa<opcode, (outs VR128:$V1),
3264             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3265             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3266
3267class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3268                  TypedReg tr1, TypedReg tr2, bits<4> type,
3269                  SDPatternOperator m5mask, bits<4> m5or>
3270  : InstVRRb<opcode, (outs tr1.op:$V1),
3271             (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
3272             mnemonic#"\t$V1, $V2, $V3, $M5",
3273             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3274                                                 (tr2.vt tr2.op:$V3),
3275                                                 m5mask:$M5)))],
3276             m5or> {
3277  let M4 = type;
3278}
3279
3280// Declare a pair of instructions, one which sets CC and one which doesn't.
3281// The CC-setting form ends with "S" and sets the low bit of M5.
3282// Also create aliases to make use of M5 operand optional in assembler.
3283multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
3284                               SDPatternOperator operator,
3285                               SDPatternOperator operator_cc,
3286                               TypedReg tr1, TypedReg tr2, bits<4> type,
3287                               bits<4> modifier = 0> {
3288  def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3289                       imm32zx4even, !and (modifier, 14)>;
3290  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3291                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3292                                            tr2.op:$V3, 0)>;
3293  let Defs = [CC] in
3294    def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3295                        imm32zx4even, !add(!and (modifier, 14), 1)>;
3296  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
3297                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
3298                                                tr2.op:$V3, 0)>;
3299}
3300
3301multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3302  def "" : InstVRRb<opcode, (outs VR128:$V1),
3303                   (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3304                   mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3305  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3306                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3307                                            imm32zx4:$M4, 0)>;
3308}
3309
3310class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3311                  TypedReg tr1, TypedReg tr2>
3312  : InstVRRc<opcode, (outs tr1.op:$V1),
3313             (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
3314             mnemonic#"\t$V1, $V2, $V3, $M4",
3315             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3316                                                 (tr2.vt tr2.op:$V3),
3317                                                 imm32zx4:$M4)))]> {
3318  let M5 = 0;
3319  let M6 = 0;
3320}
3321
3322class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3323                  TypedReg tr1, TypedReg tr2, bits<4> type = 0>
3324  : InstVRRd<opcode, (outs tr1.op:$V1),
3325             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
3326             mnemonic#"\t$V1, $V2, $V3, $V4",
3327             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3328                                                 (tr2.vt tr2.op:$V3),
3329                                                 (tr1.vt tr1.op:$V4))))]> {
3330  let M5 = type;
3331  let M6 = 0;
3332}
3333
3334class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
3335  : InstVRRd<opcode, (outs VR128:$V1),
3336             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
3337             mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
3338  let M6 = 0;
3339}
3340
3341class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3342                  TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
3343  : InstVRRe<opcode, (outs tr1.op:$V1),
3344             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
3345             mnemonic#"\t$V1, $V2, $V3, $V4",
3346             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3347                                                 (tr2.vt tr2.op:$V3),
3348                                                 (tr1.vt tr1.op:$V4))))]> {
3349  let M5 = m5;
3350  let M6 = type;
3351}
3352
3353class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
3354  : InstVRRe<opcode, (outs VR128:$V1),
3355             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
3356             mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
3357
3358class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3359                  TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
3360  : InstVRSb<opcode, (outs tr1.op:$V1),
3361             (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
3362             mnemonic#"\t$V1, $R3, $BD2",
3363             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3364                                                 cls:$R3,
3365                                                 shift12only:$BD2)))]> {
3366  let Constraints = "$V1 = $V1src";
3367  let DisableEncoding = "$V1src";
3368  let M4 = type;
3369}
3370
3371class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
3372  : InstVRSb<opcode, (outs VR128:$V1),
3373             (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
3374             mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
3375  let Constraints = "$V1 = $V1src";
3376  let DisableEncoding = "$V1src";
3377}
3378
3379class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3380                 Immediate index>
3381  : InstVRV<opcode, (outs VR128:$V1),
3382           (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
3383           mnemonic#"\t$V1, $VBD2, $M3", []> {
3384  let Constraints = "$V1 = $V1src";
3385  let DisableEncoding = "$V1src";
3386  let mayLoad = 1;
3387  let AccessBytes = bytes;
3388}
3389
3390class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3391                 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
3392  : InstVRX<opcode, (outs tr1.op:$V1),
3393           (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
3394           mnemonic#"\t$V1, $XBD2, $M3",
3395           [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3396                                               bdxaddr12only:$XBD2,
3397                                               index:$M3)))]> {
3398  let Constraints = "$V1 = $V1src";
3399  let DisableEncoding = "$V1src";
3400  let mayLoad = 1;
3401  let AccessBytes = bytes;
3402}
3403
3404class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3405                     TypedReg tr1, TypedReg tr2, bits<4> type>
3406  : InstVRId<opcode, (outs tr1.op:$V1),
3407             (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
3408             mnemonic#"\t$V1, $V2, $V3, $I4",
3409             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
3410                                                 (tr2.vt tr2.op:$V2),
3411                                                 (tr2.vt tr2.op:$V3),
3412                                                 imm32zx8:$I4)))]> {
3413  let Constraints = "$V1 = $V1src";
3414  let DisableEncoding = "$V1src";
3415  let M5 = type;
3416}
3417
3418class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
3419  : InstVRId<opcode, (outs VR128:$V1),
3420             (ins VR128:$V1src, VR128:$V2, VR128:$V3,
3421                  imm32zx8:$I4, imm32zx4:$M5),
3422             mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
3423  let Constraints = "$V1 = $V1src";
3424  let DisableEncoding = "$V1src";
3425}
3426
3427class QuaternaryVRRd<string mnemonic, bits<16> opcode,
3428                     SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
3429                     bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
3430  : InstVRRd<opcode, (outs tr1.op:$V1),
3431             (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
3432             mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
3433             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
3434                                                 (tr2.vt tr2.op:$V3),
3435                                                 (tr2.vt tr2.op:$V4),
3436                                                 m6mask:$M6)))],
3437             m6or> {
3438  let M5 = type;
3439}
3440
3441// Declare a pair of instructions, one which sets CC and one which doesn't.
3442// The CC-setting form ends with "S" and sets the low bit of M6.
3443// Also create aliases to make use of M6 operand optional in assembler.
3444multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
3445                                  SDPatternOperator operator,
3446                                SDPatternOperator operator_cc,
3447                                TypedReg tr1, TypedReg tr2, bits<4> type,
3448                                bits<4> modifier = 0> {
3449  def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
3450                          imm32zx4even, !and (modifier, 14)>;
3451  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
3452                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3453                                            tr2.op:$V3, tr2.op:$V4, 0)>;
3454  let Defs = [CC] in
3455    def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
3456                           imm32zx4even, !add (!and (modifier, 14), 1)>;
3457  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
3458                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
3459                                                tr2.op:$V3, tr2.op:$V4, 0)>;
3460}
3461
3462multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
3463  def "" : InstVRRd<opcode, (outs VR128:$V1),
3464                   (ins VR128:$V2, VR128:$V3, VR128:$V4,
3465                        imm32zx4:$M5, imm32zx4:$M6),
3466                   mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
3467  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
3468                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3469                                            VR128:$V4, imm32zx4:$M5, 0)>;
3470}
3471
3472class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3473                  RegisterOperand cls, AddressingMode mode = bdaddr20only>
3474  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
3475             mnemonic#"\t$R1, $R3, $BD2",
3476             [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
3477  let mayLoad = 1;
3478  let mayStore = 1;
3479}
3480
3481class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3482                RegisterOperand cls, AddressingMode mode = bdaddr12only>
3483  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
3484            mnemonic#"\t$R1, $R3, $BD2",
3485            [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
3486  let Constraints = "$R1 = $R1src";
3487  let DisableEncoding = "$R1src";
3488  let mayLoad = 1;
3489  let mayStore = 1;
3490}
3491
3492class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3493                 RegisterOperand cls, AddressingMode mode = bdaddr20only>
3494  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
3495             mnemonic#"\t$R1, $R3, $BD2",
3496             [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
3497  let Constraints = "$R1 = $R1src";
3498  let DisableEncoding = "$R1src";
3499  let mayLoad = 1;
3500  let mayStore = 1;
3501}
3502
3503multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3504                         SDPatternOperator operator, RegisterOperand cls> {
3505  let DispKey = mnemonic ## #cls in {
3506    let DispSize = "12" in
3507      def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
3508    let DispSize = "20" in
3509      def Y  : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
3510  }
3511}
3512
3513class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3514                       RegisterOperand cls2>
3515  : InstRIEf<opcode, (outs cls1:$R1),
3516             (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
3517                  imm32zx6:$I5),
3518             mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
3519  let Constraints = "$R1 = $R1src";
3520  let DisableEncoding = "$R1src";
3521}
3522
3523class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
3524  : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
3525             mnemonic##"\t$M1, $XBD2",
3526             [(operator imm32zx4:$M1, bdxaddr20only:$XBD2)]>;
3527
3528class PrefetchRILPC<string mnemonic, bits<12> opcode,
3529                    SDPatternOperator operator>
3530  : InstRILc<opcode, (outs), (ins imm32zx4:$M1, pcrel32:$RI2),
3531             mnemonic##"\t$M1, $RI2",
3532             [(operator imm32zx4:$M1, pcrel32:$RI2)]> {
3533  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3534  // However, BDXs have two extra operands and are therefore 6 units more
3535  // complex.
3536  let AddedComplexity = 7;
3537}
3538
3539// A floating-point load-and test operation.  Create both a normal unary
3540// operation and one that acts as a comparison against zero.
3541// Note that the comparison against zero operation is not available if we
3542// have vector support, since load-and-test instructions will partially
3543// clobber the target (vector) register.
3544multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
3545                          RegisterOperand cls> {
3546  def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
3547  let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
3548    def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
3549}
3550
3551//===----------------------------------------------------------------------===//
3552// Pseudo instructions
3553//===----------------------------------------------------------------------===//
3554//
3555// Convenience instructions that get lowered to real instructions
3556// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
3557// or SystemZInstrInfo::expandPostRAPseudo().
3558//
3559//===----------------------------------------------------------------------===//
3560
3561class Pseudo<dag outs, dag ins, list<dag> pattern>
3562  : InstSystemZ<0, outs, ins, "", pattern> {
3563  let isPseudo = 1;
3564  let isCodeGenOnly = 1;
3565}
3566
3567// Like SideEffectBinarySIL, but expanded later.
3568class SideEffectBinarySILPseudo<SDPatternOperator operator, Immediate imm>
3569  : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
3570           [(operator bdaddr12only:$BD1, imm:$I2)]> {
3571  let hasSideEffects = 1;
3572}
3573
3574// Like UnaryRI, but expanded after RA depending on the choice of register.
3575class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
3576                    Immediate imm>
3577  : Pseudo<(outs cls:$R1), (ins imm:$I2),
3578           [(set cls:$R1, (operator imm:$I2))]>;
3579
3580// Like UnaryRXY, but expanded after RA depending on the choice of register.
3581class UnaryRXYPseudo<string key, SDPatternOperator operator,
3582                     RegisterOperand cls, bits<5> bytes,
3583                     AddressingMode mode = bdxaddr20only>
3584  : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
3585           [(set cls:$R1, (operator mode:$XBD2))]> {
3586  let OpKey = key#"r"#cls;
3587  let OpType = "mem";
3588  let mayLoad = 1;
3589  let Has20BitOffset = 1;
3590  let HasIndex = 1;
3591  let AccessBytes = bytes;
3592}
3593
3594// Like UnaryRR, but expanded after RA depending on the choice of registers.
3595class UnaryRRPseudo<string key, SDPatternOperator operator,
3596                    RegisterOperand cls1, RegisterOperand cls2>
3597  : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
3598           [(set cls1:$R1, (operator cls2:$R2))]> {
3599  let OpKey = key#cls1;
3600  let OpType = "reg";
3601}
3602
3603// Like BinaryRI, but expanded after RA depending on the choice of register.
3604class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
3605                     Immediate imm>
3606  : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
3607           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3608  let Constraints = "$R1 = $R1src";
3609}
3610
3611// Like BinaryRIE, but expanded after RA depending on the choice of register.
3612class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
3613                      Immediate imm>
3614  : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
3615           [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3616
3617// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
3618multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
3619                              RegisterOperand cls, Immediate imm> {
3620  let NumOpsKey = key in {
3621    let NumOpsValue = "3" in
3622      def K : BinaryRIEPseudo<null_frag, cls, imm>,
3623              Requires<[FeatureHighWord, FeatureDistinctOps]>;
3624    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
3625      def "" : BinaryRIPseudo<operator, cls, imm>,
3626               Requires<[FeatureHighWord]>;
3627  }
3628}
3629
3630// Like CompareRI, but expanded after RA depending on the choice of register.
3631class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
3632                      Immediate imm>
3633  : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
3634
3635// Like CompareRXY, but expanded after RA depending on the choice of register.
3636class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
3637                       SDPatternOperator load, bits<5> bytes,
3638                       AddressingMode mode = bdxaddr20only>
3639  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
3640           [(operator cls:$R1, (load mode:$XBD2))]> {
3641  let mayLoad = 1;
3642  let Has20BitOffset = 1;
3643  let HasIndex = 1;
3644  let AccessBytes = bytes;
3645}
3646
3647// Like StoreRXY, but expanded after RA depending on the choice of register.
3648class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
3649                     bits<5> bytes, AddressingMode mode = bdxaddr20only>
3650  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
3651           [(operator cls:$R1, mode:$XBD2)]> {
3652  let mayStore = 1;
3653  let Has20BitOffset = 1;
3654  let HasIndex = 1;
3655  let AccessBytes = bytes;
3656}
3657
3658// Like RotateSelectRIEf, but expanded after RA depending on the choice
3659// of registers.
3660class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
3661  : Pseudo<(outs cls1:$R1),
3662           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
3663                imm32zx6:$I5),
3664           []> {
3665  let Constraints = "$R1 = $R1src";
3666  let DisableEncoding = "$R1src";
3667}
3668
3669// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
3670// the value of the PSW's 2-bit condition code field.
3671class SelectWrapper<RegisterOperand cls>
3672  : Pseudo<(outs cls:$dst),
3673           (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
3674           [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
3675                                            imm32zx4:$valid, imm32zx4:$cc))]> {
3676  let usesCustomInserter = 1;
3677  // Although the instructions used by these nodes do not in themselves
3678  // change CC, the insertion requires new blocks, and CC cannot be live
3679  // across them.
3680  let Defs = [CC];
3681  let Uses = [CC];
3682}
3683
3684// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
3685multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
3686                      SDPatternOperator load, AddressingMode mode> {
3687  let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
3688    def "" : Pseudo<(outs),
3689                    (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
3690                    [(store (z_select_ccmask cls:$new, (load mode:$addr),
3691                                             imm32zx4:$valid, imm32zx4:$cc),
3692                            mode:$addr)]>;
3693    def Inv : Pseudo<(outs),
3694                     (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
3695                     [(store (z_select_ccmask (load mode:$addr), cls:$new,
3696                                              imm32zx4:$valid, imm32zx4:$cc),
3697                              mode:$addr)]>;
3698  }
3699}
3700
3701// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation.  PAT and OPERAND
3702// describe the second (non-memory) operand.
3703class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
3704                       dag pat, DAGOperand operand>
3705  : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
3706           [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
3707  let Defs = [CC];
3708  let Has20BitOffset = 1;
3709  let mayLoad = 1;
3710  let mayStore = 1;
3711  let usesCustomInserter = 1;
3712  let hasNoSchedulingInfo = 1;
3713}
3714
3715// Specializations of AtomicLoadWBinary.
3716class AtomicLoadBinaryReg32<SDPatternOperator operator>
3717  : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
3718class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
3719  : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
3720class AtomicLoadBinaryReg64<SDPatternOperator operator>
3721  : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
3722class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
3723  : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
3724
3725// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation.  PAT and OPERAND
3726// describe the second (non-memory) operand.
3727class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
3728                        DAGOperand operand>
3729  : Pseudo<(outs GR32:$dst),
3730           (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
3731                ADDR32:$negbitshift, uimm32:$bitsize),
3732           [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
3733                                      ADDR32:$negbitshift, uimm32:$bitsize))]> {
3734  let Defs = [CC];
3735  let Has20BitOffset = 1;
3736  let mayLoad = 1;
3737  let mayStore = 1;
3738  let usesCustomInserter = 1;
3739  let hasNoSchedulingInfo = 1;
3740}
3741
3742// Specializations of AtomicLoadWBinary.
3743class AtomicLoadWBinaryReg<SDPatternOperator operator>
3744  : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
3745class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
3746  : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
3747
3748// Define an instruction that operates on two fixed-length blocks of memory,
3749// and associated pseudo instructions for operating on blocks of any size.
3750// The Sequence form uses a straight-line sequence of instructions and
3751// the Loop form uses a loop of length-256 instructions followed by
3752// another instruction to handle the excess.
3753multiclass MemorySS<string mnemonic, bits<8> opcode,
3754                    SDPatternOperator sequence, SDPatternOperator loop> {
3755  def "" : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
3756                                        bdaddr12only:$BD2),
3757                   mnemonic##"\t$BDL1, $BD2", []>;
3758  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
3759    def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
3760                                       imm64:$length),
3761                           [(sequence bdaddr12only:$dest, bdaddr12only:$src,
3762                                      imm64:$length)]>;
3763    def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
3764                                   imm64:$length, GR64:$count256),
3765                      [(loop bdaddr12only:$dest, bdaddr12only:$src,
3766                             imm64:$length, GR64:$count256)]>;
3767  }
3768}
3769
3770// Define an instruction that operates on two strings, both terminated
3771// by the character in R0.  The instruction processes a CPU-determinated
3772// number of bytes at a time and sets CC to 3 if the instruction needs
3773// to be repeated.  Also define a pseudo instruction that represents
3774// the full loop (the main instruction plus the branch on CC==3).
3775multiclass StringRRE<string mnemonic, bits<16> opcode,
3776                     SDPatternOperator operator> {
3777  def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
3778                   (ins GR64:$R1src, GR64:$R2src),
3779                   mnemonic#"\t$R1, $R2", []> {
3780    let Uses = [R0L];
3781    let Constraints = "$R1 = $R1src, $R2 = $R2src";
3782    let DisableEncoding = "$R1src, $R2src";
3783  }
3784  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
3785    def Loop : Pseudo<(outs GR64:$end),
3786                      (ins GR64:$start1, GR64:$start2, GR32:$char),
3787                      [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
3788                                                 GR32:$char))]>;
3789}
3790
3791// A pseudo instruction that is a direct alias of a real instruction.
3792// These aliases are used in cases where a particular register operand is
3793// fixed or where the same instruction is used with different register sizes.
3794// The size parameter is the size in bytes of the associated real instruction.
3795class Alias<int size, dag outs, dag ins, list<dag> pattern>
3796  : InstSystemZ<size, outs, ins, "", pattern> {
3797  let isPseudo = 1;
3798  let isCodeGenOnly = 1;
3799}
3800
3801class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
3802 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
3803
3804// An alias of a UnaryVRR*, but with different register sizes.
3805class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
3806  : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
3807          [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
3808
3809// An alias of a UnaryVRX, but with different register sizes.
3810class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
3811                    AddressingMode mode = bdxaddr12only>
3812  : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
3813          [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
3814
3815// An alias of a StoreVRX, but with different register sizes.
3816class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
3817                    AddressingMode mode = bdxaddr12only>
3818  : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
3819          [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
3820
3821// An alias of a BinaryRI, but with different register sizes.
3822class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
3823                    Immediate imm>
3824  : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3825          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3826  let Constraints = "$R1 = $R1src";
3827}
3828
3829// An alias of a BinaryRIL, but with different register sizes.
3830class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
3831                     Immediate imm>
3832  : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3833          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3834  let Constraints = "$R1 = $R1src";
3835}
3836
3837// An alias of a BinaryVRRf, but with different register sizes.
3838class BinaryAliasVRRf<RegisterOperand cls>
3839  : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
3840
3841// An alias of a CompareRI, but with different register sizes.
3842class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
3843                     Immediate imm>
3844  : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
3845  let isCompare = 1;
3846}
3847
3848// An alias of a RotateSelectRIEf, but with different register sizes.
3849class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
3850  : Alias<6, (outs cls1:$R1),
3851          (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
3852               imm32zx6:$I5), []> {
3853  let Constraints = "$R1 = $R1src";
3854}
3855