1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Basic SystemZ instruction definition
12//===----------------------------------------------------------------------===//
13
14class InstSystemZ<int size, dag outs, dag ins, string asmstr,
15                  list<dag> pattern> : Instruction {
16  let Namespace = "SystemZ";
17
18  dag OutOperandList = outs;
19  dag InOperandList = ins;
20  let Size = size;
21  let Pattern = pattern;
22  let AsmString = asmstr;
23
24  // Some instructions come in pairs, one having a 12-bit displacement
25  // and the other having a 20-bit displacement.  Both instructions in
26  // the pair have the same DispKey and their DispSizes are "12" and "20"
27  // respectively.
28  string DispKey = "";
29  string DispSize = "none";
30
31  // Many register-based <INSN>R instructions have a memory-based <INSN>
32  // counterpart.  OpKey uniquely identifies <INSN>, while OpType is
33  // "reg" for <INSN>R and "mem" for <INSN>.
34  string OpKey = "";
35  string OpType = "none";
36
37  // Many distinct-operands instructions have older 2-operand equivalents.
38  // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
39  // with NumOpsValue being "2" or "3" as appropriate.
40  string NumOpsKey = "";
41  string NumOpsValue = "none";
42
43  // True if this instruction is a simple D(X,B) load of a register
44  // (with no sign or zero extension).
45  bit SimpleBDXLoad = 0;
46
47  // True if this instruction is a simple D(X,B) store of a register
48  // (with no truncation).
49  bit SimpleBDXStore = 0;
50
51  // True if this instruction has a 20-bit displacement field.
52  bit Has20BitOffset = 0;
53
54  // True if addresses in this instruction have an index register.
55  bit HasIndex = 0;
56
57  // True if this is a 128-bit pseudo instruction that combines two 64-bit
58  // operations.
59  bit Is128Bit = 0;
60
61  // The access size of all memory operands in bytes, or 0 if not known.
62  bits<5> AccessBytes = 0;
63
64  // If the instruction sets CC to a useful value, this gives the mask
65  // of all possible CC results.  The mask has the same form as
66  // SystemZ::CCMASK_*.
67  bits<4> CCValues = 0;
68
69  // The subset of CCValues that have the same meaning as they would after
70  // a comparison of the first operand against zero.
71  bits<4> CompareZeroCCMask = 0;
72
73  // True if the instruction is conditional and if the CC mask operand
74  // comes first (as for BRC, etc.).
75  bit CCMaskFirst = 0;
76
77  // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
78  bit CCMaskLast = 0;
79
80  // True if the instruction is the "logical" rather than "arithmetic" form,
81  // in cases where a distinction exists.
82  bit IsLogical = 0;
83
84  let TSFlags{0}     = SimpleBDXLoad;
85  let TSFlags{1}     = SimpleBDXStore;
86  let TSFlags{2}     = Has20BitOffset;
87  let TSFlags{3}     = HasIndex;
88  let TSFlags{4}     = Is128Bit;
89  let TSFlags{9-5}   = AccessBytes;
90  let TSFlags{13-10} = CCValues;
91  let TSFlags{17-14} = CompareZeroCCMask;
92  let TSFlags{18}    = CCMaskFirst;
93  let TSFlags{19}    = CCMaskLast;
94  let TSFlags{20}    = IsLogical;
95}
96
97//===----------------------------------------------------------------------===//
98// Mappings between instructions
99//===----------------------------------------------------------------------===//
100
101// Return the version of an instruction that has an unsigned 12-bit
102// displacement.
103def getDisp12Opcode : InstrMapping {
104  let FilterClass = "InstSystemZ";
105  let RowFields = ["DispKey"];
106  let ColFields = ["DispSize"];
107  let KeyCol = ["20"];
108  let ValueCols = [["12"]];
109}
110
111// Return the version of an instruction that has a signed 20-bit displacement.
112def getDisp20Opcode : InstrMapping {
113  let FilterClass = "InstSystemZ";
114  let RowFields = ["DispKey"];
115  let ColFields = ["DispSize"];
116  let KeyCol = ["12"];
117  let ValueCols = [["20"]];
118}
119
120// Return the memory form of a register instruction.
121def getMemOpcode : InstrMapping {
122  let FilterClass = "InstSystemZ";
123  let RowFields = ["OpKey"];
124  let ColFields = ["OpType"];
125  let KeyCol = ["reg"];
126  let ValueCols = [["mem"]];
127}
128
129// Return the 3-operand form of a 2-operand instruction.
130def getThreeOperandOpcode : InstrMapping {
131  let FilterClass = "InstSystemZ";
132  let RowFields = ["NumOpsKey"];
133  let ColFields = ["NumOpsValue"];
134  let KeyCol = ["2"];
135  let ValueCols = [["3"]];
136}
137
138//===----------------------------------------------------------------------===//
139// Instruction formats
140//===----------------------------------------------------------------------===//
141//
142// Formats are specified using operand field declarations of the form:
143//
144//   bits<4> Rn   : register input or output for operand n
145//   bits<5> Vn   : vector register input or output for operand n
146//   bits<m> In   : immediate value of width m for operand n
147//   bits<4> BDn  : address operand n, which has a base and a displacement
148//   bits<m> XBDn : address operand n, which has an index, a base and a
149//                  displacement
150//   bits<m> VBDn : address operand n, which has a vector index, a base and a
151//                  displacement
152//   bits<4> Xn   : index register for address operand n
153//   bits<4> Mn   : mode value for operand n
154//
155// The operand numbers ("n" in the list above) follow the architecture manual.
156// Assembly operands sometimes have a different order; in particular, R3 often
157// is often written between operands 1 and 2.
158//
159//===----------------------------------------------------------------------===//
160
161class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162  : InstSystemZ<2, outs, ins, asmstr, pattern> {
163  field bits<16> Inst;
164  field bits<16> SoftFail = 0;
165
166  let Inst = op;
167}
168
169class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
170  : InstSystemZ<2, outs, ins, asmstr, pattern> {
171  field bits<16> Inst;
172  field bits<16> SoftFail = 0;
173
174  bits<8> I1;
175
176  let Inst{15-8} = op;
177  let Inst{7-0}  = I1;
178}
179
180class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
181  : InstSystemZ<4, outs, ins, asmstr, pattern> {
182  field bits<32> Inst;
183  field bits<32> SoftFail = 0;
184
185  bits<4> R1;
186  bits<16> I2;
187
188  let Inst{31-24} = op{11-4};
189  let Inst{23-20} = R1;
190  let Inst{19-16} = op{3-0};
191  let Inst{15-0}  = I2;
192}
193
194class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195  : InstSystemZ<6, outs, ins, asmstr, pattern> {
196  field bits<48> Inst;
197  field bits<48> SoftFail = 0;
198
199  bits<4> R1;
200  bits<16> I2;
201  bits<4> M3;
202
203  let Inst{47-40} = op{15-8};
204  let Inst{39-36} = R1;
205  let Inst{35-32} = 0;
206  let Inst{31-16} = I2;
207  let Inst{15-12} = M3;
208  let Inst{11-8}  = 0;
209  let Inst{7-0}   = op{7-0};
210}
211
212class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
213  : InstSystemZ<6, outs, ins, asmstr, pattern> {
214  field bits<48> Inst;
215  field bits<48> SoftFail = 0;
216
217  bits<4> R1;
218  bits<4> R2;
219  bits<4> M3;
220  bits<16> RI4;
221
222  let Inst{47-40} = op{15-8};
223  let Inst{39-36} = R1;
224  let Inst{35-32} = R2;
225  let Inst{31-16} = RI4;
226  let Inst{15-12} = M3;
227  let Inst{11-8}  = 0;
228  let Inst{7-0}   = op{7-0};
229}
230
231class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
232  : InstSystemZ<6, outs, ins, asmstr, pattern> {
233  field bits<48> Inst;
234  field bits<48> SoftFail = 0;
235
236  bits<4> R1;
237  bits<8> I2;
238  bits<4> M3;
239  bits<16> RI4;
240
241  let Inst{47-40} = op{15-8};
242  let Inst{39-36} = R1;
243  let Inst{35-32} = M3;
244  let Inst{31-16} = RI4;
245  let Inst{15-8}  = I2;
246  let Inst{7-0}   = op{7-0};
247}
248
249class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
250  : InstSystemZ<6, outs, ins, asmstr, pattern> {
251  field bits<48> Inst;
252  field bits<48> SoftFail = 0;
253
254  bits<4> R1;
255  bits<4> R3;
256  bits<16> I2;
257
258  let Inst{47-40} = op{15-8};
259  let Inst{39-36} = R1;
260  let Inst{35-32} = R3;
261  let Inst{31-16} = I2;
262  let Inst{15-8}  = 0;
263  let Inst{7-0}   = op{7-0};
264}
265
266class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
267  : InstSystemZ<6, outs, ins, asmstr, pattern> {
268  field bits<48> Inst;
269  field bits<48> SoftFail = 0;
270
271  bits<4> R1;
272  bits<4> R2;
273  bits<8> I3;
274  bits<8> I4;
275  bits<8> I5;
276
277  let Inst{47-40} = op{15-8};
278  let Inst{39-36} = R1;
279  let Inst{35-32} = R2;
280  let Inst{31-24} = I3;
281  let Inst{23-16} = I4;
282  let Inst{15-8}  = I5;
283  let Inst{7-0}   = op{7-0};
284}
285
286class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
287  : InstSystemZ<6, outs, ins, asmstr, pattern> {
288  field bits<48> Inst;
289  field bits<48> SoftFail = 0;
290
291  bits<4> R1;
292  bits<32> I2;
293
294  let Inst{47-40} = op{11-4};
295  let Inst{39-36} = R1;
296  let Inst{35-32} = op{3-0};
297  let Inst{31-0}  = I2;
298}
299
300class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
301  : InstSystemZ<6, outs, ins, asmstr, pattern> {
302  field bits<48> Inst;
303  field bits<48> SoftFail = 0;
304
305  bits<4> R1;
306  bits<8> I2;
307  bits<4> M3;
308  bits<16> BD4;
309
310  let Inst{47-40} = op{15-8};
311  let Inst{39-36} = R1;
312  let Inst{35-32} = M3;
313  let Inst{31-16} = BD4;
314  let Inst{15-8}  = I2;
315  let Inst{7-0}   = op{7-0};
316}
317
318class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
319  : InstSystemZ<2, outs, ins, asmstr, pattern> {
320  field bits<16> Inst;
321  field bits<16> SoftFail = 0;
322
323  bits<4> R1;
324  bits<4> R2;
325
326  let Inst{15-8} = op;
327  let Inst{7-4}  = R1;
328  let Inst{3-0}  = R2;
329}
330
331class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
332  : InstSystemZ<4, outs, ins, asmstr, pattern> {
333  field bits<32> Inst;
334  field bits<32> SoftFail = 0;
335
336  bits<4> R1;
337  bits<4> R3;
338  bits<4> R2;
339
340  let Inst{31-16} = op;
341  let Inst{15-12} = R1;
342  let Inst{11-8}  = 0;
343  let Inst{7-4}   = R3;
344  let Inst{3-0}   = R2;
345}
346
347class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
348  : InstSystemZ<4, outs, ins, asmstr, pattern> {
349  field bits<32> Inst;
350  field bits<32> SoftFail = 0;
351
352  bits<4> R1;
353  bits<4> R2;
354
355  let Inst{31-16} = op;
356  let Inst{15-8}  = 0;
357  let Inst{7-4}   = R1;
358  let Inst{3-0}   = R2;
359}
360
361class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
362  : InstSystemZ<4, outs, ins, asmstr, pattern> {
363  field bits<32> Inst;
364  field bits<32> SoftFail = 0;
365
366  bits<4> R1;
367  bits<4> R2;
368  bits<4> R3;
369  bits<4> R4;
370
371  let Inst{31-16} = op;
372  let Inst{15-12} = R3;
373  let Inst{11-8}  = R4;
374  let Inst{7-4}   = R1;
375  let Inst{3-0}   = R2;
376}
377
378class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
379  : InstSystemZ<4, outs, ins, asmstr, pattern> {
380  field bits<32> Inst;
381  field bits<32> SoftFail = 0;
382
383  bits<4> R1;
384  bits<4> R2;
385  bits<4> M3;
386
387  let Inst{31-16} = op;
388  let Inst{15-12} = M3;
389  let Inst{11-8}  = 0;
390  let Inst{7-4}   = R1;
391  let Inst{3-0}   = R2;
392}
393
394class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
395  : InstSystemZ<6, outs, ins, asmstr, pattern> {
396  field bits<48> Inst;
397  field bits<48> SoftFail = 0;
398
399  bits<4> R1;
400  bits<4> R2;
401  bits<4> M3;
402  bits<16> BD4;
403
404  let Inst{47-40} = op{15-8};
405  let Inst{39-36} = R1;
406  let Inst{35-32} = R2;
407  let Inst{31-16} = BD4;
408  let Inst{15-12} = M3;
409  let Inst{11-8}  = 0;
410  let Inst{7-0}   = op{7-0};
411}
412
413class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
414  : InstSystemZ<4, outs, ins, asmstr, pattern> {
415  field bits<32> Inst;
416  field bits<32> SoftFail = 0;
417
418  bits<4> R1;
419  bits<20> XBD2;
420
421  let Inst{31-24} = op;
422  let Inst{23-20} = R1;
423  let Inst{19-0}  = XBD2;
424
425  let HasIndex = 1;
426}
427
428class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
429  : InstSystemZ<6, outs, ins, asmstr, pattern> {
430  field bits<48> Inst;
431  field bits<48> SoftFail = 0;
432
433  bits<4> R1;
434  bits<20> XBD2;
435  bits<4> M3;
436
437  let Inst{47-40} = op{15-8};
438  let Inst{39-36} = R1;
439  let Inst{35-16} = XBD2;
440  let Inst{15-12} = M3;
441  let Inst{11-8}  = 0;
442  let Inst{7-0}   = op{7-0};
443
444  let HasIndex = 1;
445}
446
447class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
448  : InstSystemZ<6, outs, ins, asmstr, pattern> {
449  field bits<48> Inst;
450  field bits<48> SoftFail = 0;
451
452  bits<4> R1;
453  bits<4> R3;
454  bits<20> XBD2;
455
456  let Inst{47-40} = op{15-8};
457  let Inst{39-36} = R3;
458  let Inst{35-16} = XBD2;
459  let Inst{15-12} = R1;
460  let Inst{11-8}  = 0;
461  let Inst{7-0}   = op{7-0};
462
463  let HasIndex = 1;
464}
465
466class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
467  : InstSystemZ<6, outs, ins, asmstr, pattern> {
468  field bits<48> Inst;
469  field bits<48> SoftFail = 0;
470
471  bits<4> R1;
472  bits<28> XBD2;
473
474  let Inst{47-40} = op{15-8};
475  let Inst{39-36} = R1;
476  let Inst{35-8}  = XBD2;
477  let Inst{7-0}   = op{7-0};
478
479  let Has20BitOffset = 1;
480  let HasIndex = 1;
481}
482
483class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
484  : InstSystemZ<4, outs, ins, asmstr, pattern> {
485  field bits<32> Inst;
486  field bits<32> SoftFail = 0;
487
488  bits<4> R1;
489  bits<4> R3;
490  bits<16> BD2;
491
492  let Inst{31-24} = op;
493  let Inst{23-20} = R1;
494  let Inst{19-16} = R3;
495  let Inst{15-0}  = BD2;
496}
497
498class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
499  : InstSystemZ<4, outs, ins, asmstr, pattern> {
500  field bits<32> Inst;
501  field bits<32> SoftFail = 0;
502
503  bits<4> R1;
504  bits<4> R3;
505  bits<16> RI2;
506
507  let Inst{31-24} = op;
508  let Inst{23-20} = R1;
509  let Inst{19-16} = R3;
510  let Inst{15-0}  = RI2;
511}
512
513class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
514  : InstSystemZ<6, outs, ins, asmstr, pattern> {
515  field bits<48> Inst;
516  field bits<48> SoftFail = 0;
517
518  bits<4> R1;
519  bits<4> R3;
520  bits<24> BD2;
521
522  let Inst{47-40} = op{15-8};
523  let Inst{39-36} = R1;
524  let Inst{35-32} = R3;
525  let Inst{31-8}  = BD2;
526  let Inst{7-0}   = op{7-0};
527
528  let Has20BitOffset = 1;
529}
530
531class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
532  : InstSystemZ<4, outs, ins, asmstr, pattern> {
533  field bits<32> Inst;
534  field bits<32> SoftFail = 0;
535
536  bits<16> BD1;
537  bits<8> I2;
538
539  let Inst{31-24} = op;
540  let Inst{23-16} = I2;
541  let Inst{15-0}  = BD1;
542}
543
544class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
545  : InstSystemZ<6, outs, ins, asmstr, pattern> {
546  field bits<48> Inst;
547  field bits<48> SoftFail = 0;
548
549  bits<16> BD1;
550  bits<16> I2;
551
552  let Inst{47-32} = op;
553  let Inst{31-16} = BD1;
554  let Inst{15-0}  = I2;
555}
556
557class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
558  : InstSystemZ<6, outs, ins, asmstr, pattern> {
559  field bits<48> Inst;
560  field bits<48> SoftFail = 0;
561
562  bits<24> BD1;
563  bits<8> I2;
564
565  let Inst{47-40} = op{15-8};
566  let Inst{39-32} = I2;
567  let Inst{31-8}  = BD1;
568  let Inst{7-0}   = op{7-0};
569
570  let Has20BitOffset = 1;
571}
572
573class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
574  : InstSystemZ<6, outs, ins, asmstr, pattern> {
575  field bits<48> Inst;
576  field bits<48> SoftFail = 0;
577
578  bits<24> BDL1;
579  bits<16> BD2;
580
581  let Inst{47-40} = op;
582  let Inst{39-16} = BDL1;
583  let Inst{15-0}  = BD2;
584}
585
586class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
587  : InstSystemZ<6, outs, ins, asmstr, pattern> {
588  field bits<48> Inst;
589  field bits<48> SoftFail = 0;
590
591  bits<20> XBD1;
592  bits<16> BD2;
593  bits<4> R3;
594
595  let Inst{47-40} = op;
596  let Inst{39-36} = XBD1{19-16};
597  let Inst{35-32} = R3;
598  let Inst{31-16} = XBD1{15-0};
599  let Inst{15-0}  = BD2;
600}
601
602class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
603  : InstSystemZ<6, outs, ins, asmstr, pattern> {
604  field bits<48> Inst;
605  field bits<48> SoftFail = 0;
606
607  bits<16> BD1;
608  bits<16> BD2;
609
610  let Inst{47-32} = op;
611  let Inst{31-16} = BD1;
612  let Inst{15-0}  = BD2;
613}
614
615class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
616  : InstSystemZ<6, outs, ins, asmstr, pattern> {
617  field bits<48> Inst;
618  field bits<48> SoftFail = 0;
619
620  bits<16> BD1;
621  bits<16> BD2;
622  bits<4>  R3;
623
624  let Inst{47-40} = op{11-4};
625  let Inst{39-36} = R3;
626  let Inst{35-32} = op{3-0};
627  let Inst{31-16} = BD1;
628  let Inst{15-0}  = BD2;
629}
630
631class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
632  : InstSystemZ<4, outs, ins, asmstr, pattern> {
633  field bits<32> Inst;
634  field bits<32> SoftFail = 0;
635
636  bits<16> BD2;
637
638  let Inst{31-16} = op;
639  let Inst{15-0}  = BD2;
640}
641
642class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
643  : InstSystemZ<6, outs, ins, asmstr, pattern> {
644  field bits<48> Inst;
645  field bits<48> SoftFail = 0;
646
647  bits<5> V1;
648  bits<16> I2;
649  bits<4> M3;
650
651  let Inst{47-40} = op{15-8};
652  let Inst{39-36} = V1{3-0};
653  let Inst{35-32} = 0;
654  let Inst{31-16} = I2;
655  let Inst{15-12} = M3;
656  let Inst{11}    = V1{4};
657  let Inst{10-8}  = 0;
658  let Inst{7-0}   = op{7-0};
659}
660
661class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
662  : InstSystemZ<6, outs, ins, asmstr, pattern> {
663  field bits<48> Inst;
664  field bits<48> SoftFail = 0;
665
666  bits<5> V1;
667  bits<8> I2;
668  bits<8> I3;
669  bits<4> M4;
670
671  let Inst{47-40} = op{15-8};
672  let Inst{39-36} = V1{3-0};
673  let Inst{35-32} = 0;
674  let Inst{31-24} = I2;
675  let Inst{23-16} = I3;
676  let Inst{15-12} = M4;
677  let Inst{11}    = V1{4};
678  let Inst{10-8}  = 0;
679  let Inst{7-0}   = op{7-0};
680}
681
682class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
683  : InstSystemZ<6, outs, ins, asmstr, pattern> {
684  field bits<48> Inst;
685  field bits<48> SoftFail = 0;
686
687  bits<5> V1;
688  bits<5> V3;
689  bits<16> I2;
690  bits<4> M4;
691
692  let Inst{47-40} = op{15-8};
693  let Inst{39-36} = V1{3-0};
694  let Inst{35-32} = V3{3-0};
695  let Inst{31-16} = I2;
696  let Inst{15-12} = M4;
697  let Inst{11}    = V1{4};
698  let Inst{10}    = V3{4};
699  let Inst{9-8}   = 0;
700  let Inst{7-0}   = op{7-0};
701}
702
703class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
704  : InstSystemZ<6, outs, ins, asmstr, pattern> {
705  field bits<48> Inst;
706  field bits<48> SoftFail = 0;
707
708  bits<5> V1;
709  bits<5> V2;
710  bits<5> V3;
711  bits<8> I4;
712  bits<4> M5;
713
714  let Inst{47-40} = op{15-8};
715  let Inst{39-36} = V1{3-0};
716  let Inst{35-32} = V2{3-0};
717  let Inst{31-28} = V3{3-0};
718  let Inst{27-24} = 0;
719  let Inst{23-16} = I4;
720  let Inst{15-12} = M5;
721  let Inst{11}    = V1{4};
722  let Inst{10}    = V2{4};
723  let Inst{9}     = V3{4};
724  let Inst{8}     = 0;
725  let Inst{7-0}   = op{7-0};
726}
727
728class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
729  : InstSystemZ<6, outs, ins, asmstr, pattern> {
730  field bits<48> Inst;
731  field bits<48> SoftFail = 0;
732
733  bits<5> V1;
734  bits<5> V2;
735  bits<12> I3;
736  bits<4> M4;
737  bits<4> M5;
738
739  let Inst{47-40} = op{15-8};
740  let Inst{39-36} = V1{3-0};
741  let Inst{35-32} = V2{3-0};
742  let Inst{31-20} = I3;
743  let Inst{19-16} = M5;
744  let Inst{15-12} = M4;
745  let Inst{11}    = V1{4};
746  let Inst{10}    = V2{4};
747  let Inst{9-8}   = 0;
748  let Inst{7-0}   = op{7-0};
749}
750
751// Depending on the instruction mnemonic, certain bits may be or-ed into
752// the M4 value provided as explicit operand.  These are passed as m4or.
753class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
754               bits<4> m4or = 0>
755  : InstSystemZ<6, outs, ins, asmstr, pattern> {
756  field bits<48> Inst;
757  field bits<48> SoftFail = 0;
758
759  bits<5> V1;
760  bits<5> V2;
761  bits<4> M3;
762  bits<4> M4;
763  bits<4> M5;
764
765  let Inst{47-40} = op{15-8};
766  let Inst{39-36} = V1{3-0};
767  let Inst{35-32} = V2{3-0};
768  let Inst{31-24} = 0;
769  let Inst{23-20} = M5;
770  let Inst{19}    = !if (!eq (m4or{3}, 1), 1, M4{3});
771  let Inst{18}    = !if (!eq (m4or{2}, 1), 1, M4{2});
772  let Inst{17}    = !if (!eq (m4or{1}, 1), 1, M4{1});
773  let Inst{16}    = !if (!eq (m4or{0}, 1), 1, M4{0});
774  let Inst{15-12} = M3;
775  let Inst{11}    = V1{4};
776  let Inst{10}    = V2{4};
777  let Inst{9-8}   = 0;
778  let Inst{7-0}   = op{7-0};
779}
780
781// Depending on the instruction mnemonic, certain bits may be or-ed into
782// the M5 value provided as explicit operand.  These are passed as m5or.
783class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
784               bits<4> m5or = 0>
785  : InstSystemZ<6, outs, ins, asmstr, pattern> {
786  field bits<48> Inst;
787  field bits<48> SoftFail = 0;
788
789  bits<5> V1;
790  bits<5> V2;
791  bits<5> V3;
792  bits<4> M4;
793  bits<4> M5;
794
795  let Inst{47-40} = op{15-8};
796  let Inst{39-36} = V1{3-0};
797  let Inst{35-32} = V2{3-0};
798  let Inst{31-28} = V3{3-0};
799  let Inst{27-24} = 0;
800  let Inst{23}    = !if (!eq (m5or{3}, 1), 1, M5{3});
801  let Inst{22}    = !if (!eq (m5or{2}, 1), 1, M5{2});
802  let Inst{21}    = !if (!eq (m5or{1}, 1), 1, M5{1});
803  let Inst{20}    = !if (!eq (m5or{0}, 1), 1, M5{0});
804  let Inst{19-16} = 0;
805  let Inst{15-12} = M4;
806  let Inst{11}    = V1{4};
807  let Inst{10}    = V2{4};
808  let Inst{9}     = V3{4};
809  let Inst{8}     = 0;
810  let Inst{7-0}   = op{7-0};
811}
812
813class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
814  : InstSystemZ<6, outs, ins, asmstr, pattern> {
815  field bits<48> Inst;
816  field bits<48> SoftFail = 0;
817
818  bits<5> V1;
819  bits<5> V2;
820  bits<5> V3;
821  bits<4> M4;
822  bits<4> M5;
823  bits<4> M6;
824
825  let Inst{47-40} = op{15-8};
826  let Inst{39-36} = V1{3-0};
827  let Inst{35-32} = V2{3-0};
828  let Inst{31-28} = V3{3-0};
829  let Inst{27-24} = 0;
830  let Inst{23-20} = M6;
831  let Inst{19-16} = M5;
832  let Inst{15-12} = M4;
833  let Inst{11}    = V1{4};
834  let Inst{10}    = V2{4};
835  let Inst{9}     = V3{4};
836  let Inst{8}     = 0;
837  let Inst{7-0}   = op{7-0};
838}
839
840// Depending on the instruction mnemonic, certain bits may be or-ed into
841// the M6 value provided as explicit operand.  These are passed as m6or.
842class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
843               bits<4> m6or = 0>
844  : InstSystemZ<6, outs, ins, asmstr, pattern> {
845  field bits<48> Inst;
846  field bits<48> SoftFail = 0;
847
848  bits<5> V1;
849  bits<5> V2;
850  bits<5> V3;
851  bits<5> V4;
852  bits<4> M5;
853  bits<4> M6;
854
855  let Inst{47-40} = op{15-8};
856  let Inst{39-36} = V1{3-0};
857  let Inst{35-32} = V2{3-0};
858  let Inst{31-28} = V3{3-0};
859  let Inst{27-24} = M5;
860  let Inst{23}    = !if (!eq (m6or{3}, 1), 1, M6{3});
861  let Inst{22}    = !if (!eq (m6or{2}, 1), 1, M6{2});
862  let Inst{21}    = !if (!eq (m6or{1}, 1), 1, M6{1});
863  let Inst{20}    = !if (!eq (m6or{0}, 1), 1, M6{0});
864  let Inst{19-16} = 0;
865  let Inst{15-12} = V4{3-0};
866  let Inst{11}    = V1{4};
867  let Inst{10}    = V2{4};
868  let Inst{9}     = V3{4};
869  let Inst{8}     = V4{4};
870  let Inst{7-0}   = op{7-0};
871}
872
873class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
874  : InstSystemZ<6, outs, ins, asmstr, pattern> {
875  field bits<48> Inst;
876  field bits<48> SoftFail = 0;
877
878  bits<5> V1;
879  bits<5> V2;
880  bits<5> V3;
881  bits<5> V4;
882  bits<4> M5;
883  bits<4> M6;
884
885  let Inst{47-40} = op{15-8};
886  let Inst{39-36} = V1{3-0};
887  let Inst{35-32} = V2{3-0};
888  let Inst{31-28} = V3{3-0};
889  let Inst{27-24} = M6;
890  let Inst{23-20} = 0;
891  let Inst{19-16} = M5;
892  let Inst{15-12} = V4{3-0};
893  let Inst{11}    = V1{4};
894  let Inst{10}    = V2{4};
895  let Inst{9}     = V3{4};
896  let Inst{8}     = V4{4};
897  let Inst{7-0}   = op{7-0};
898}
899
900class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
901  : InstSystemZ<6, outs, ins, asmstr, pattern> {
902  field bits<48> Inst;
903  field bits<48> SoftFail = 0;
904
905  bits<5> V1;
906  bits<4> R2;
907  bits<4> R3;
908
909  let Inst{47-40} = op{15-8};
910  let Inst{39-36} = V1{3-0};
911  let Inst{35-32} = R2;
912  let Inst{31-28} = R3;
913  let Inst{27-12} = 0;
914  let Inst{11}    = V1{4};
915  let Inst{10-8}  = 0;
916  let Inst{7-0}   = op{7-0};
917}
918
919class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
920  : InstSystemZ<6, outs, ins, asmstr, pattern> {
921  field bits<48> Inst;
922  field bits<48> SoftFail = 0;
923
924  bits<5> V1;
925  bits<16> BD2;
926  bits<5> V3;
927  bits<4> M4;
928
929  let Inst{47-40} = op{15-8};
930  let Inst{39-36} = V1{3-0};
931  let Inst{35-32} = V3{3-0};
932  let Inst{31-16} = BD2;
933  let Inst{15-12} = M4;
934  let Inst{11}    = V1{4};
935  let Inst{10}    = V3{4};
936  let Inst{9-8}   = 0;
937  let Inst{7-0}   = op{7-0};
938}
939
940class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
941  : InstSystemZ<6, outs, ins, asmstr, pattern> {
942  field bits<48> Inst;
943  field bits<48> SoftFail = 0;
944
945  bits<5> V1;
946  bits<16> BD2;
947  bits<4> R3;
948  bits<4> M4;
949
950  let Inst{47-40} = op{15-8};
951  let Inst{39-36} = V1{3-0};
952  let Inst{35-32} = R3;
953  let Inst{31-16} = BD2;
954  let Inst{15-12} = M4;
955  let Inst{11}    = V1{4};
956  let Inst{10-8}  = 0;
957  let Inst{7-0}   = op{7-0};
958}
959
960class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
961  : InstSystemZ<6, outs, ins, asmstr, pattern> {
962  field bits<48> Inst;
963  field bits<48> SoftFail = 0;
964
965  bits<4> R1;
966  bits<16> BD2;
967  bits<5> V3;
968  bits<4> M4;
969
970  let Inst{47-40} = op{15-8};
971  let Inst{39-36} = R1;
972  let Inst{35-32} = V3{3-0};
973  let Inst{31-16} = BD2;
974  let Inst{15-12} = M4;
975  let Inst{11}    = 0;
976  let Inst{10}    = V3{4};
977  let Inst{9-8}   = 0;
978  let Inst{7-0}   = op{7-0};
979}
980
981class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
982  : InstSystemZ<6, outs, ins, asmstr, pattern> {
983  field bits<48> Inst;
984  field bits<48> SoftFail = 0;
985
986  bits<5> V1;
987  bits<21> VBD2;
988  bits<4> M3;
989
990  let Inst{47-40} = op{15-8};
991  let Inst{39-36} = V1{3-0};
992  let Inst{35-16} = VBD2{19-0};
993  let Inst{15-12} = M3;
994  let Inst{11}    = V1{4};
995  let Inst{10}    = VBD2{20};
996  let Inst{9-8}   = 0;
997  let Inst{7-0}   = op{7-0};
998}
999
1000class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1001  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1002  field bits<48> Inst;
1003  field bits<48> SoftFail = 0;
1004
1005  bits<5> V1;
1006  bits<20> XBD2;
1007  bits<4> M3;
1008
1009  let Inst{47-40} = op{15-8};
1010  let Inst{39-36} = V1{3-0};
1011  let Inst{35-16} = XBD2;
1012  let Inst{15-12} = M3;
1013  let Inst{11}    = V1{4};
1014  let Inst{10-8}  = 0;
1015  let Inst{7-0}   = op{7-0};
1016}
1017
1018//===----------------------------------------------------------------------===//
1019// Instruction classes for .insn directives
1020//===----------------------------------------------------------------------===//
1021
1022class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
1023  : InstE<0, outs, ins, asmstr, pattern> {
1024  bits<16> enc;
1025
1026  let Inst = enc;
1027}
1028
1029class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1030  : InstRI<0, outs, ins, asmstr, pattern> {
1031  bits<32> enc;
1032
1033  let Inst{31-24} = enc{31-24};
1034  let Inst{19-16} = enc{19-16};
1035}
1036
1037class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
1038  : InstRIEd<0, outs, ins, asmstr, pattern> {
1039  bits<48> enc;
1040
1041  let Inst{47-40} = enc{47-40};
1042  let Inst{7-0}   = enc{7-0};
1043}
1044
1045class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1046  : InstRIL<0, outs, ins, asmstr, pattern> {
1047  bits<48> enc;
1048  string type;
1049
1050  let Inst{47-40} = enc{47-40};
1051  let Inst{35-32} = enc{35-32};
1052}
1053
1054class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
1055  : InstRIS<0, outs, ins, asmstr, pattern> {
1056  bits<48> enc;
1057
1058  let Inst{47-40} = enc{47-40};
1059  let Inst{7-0}   = enc{7-0};
1060}
1061
1062class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1063  : InstRR<0, outs, ins, asmstr, pattern> {
1064  bits<16> enc;
1065
1066  let Inst{15-8} = enc{15-8};
1067}
1068
1069class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
1070  : InstRRE<0, outs, ins, asmstr, pattern> {
1071  bits<32> enc;
1072
1073  let Inst{31-16} = enc{31-16};
1074}
1075
1076class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
1077  : InstRRF<0, outs, ins, asmstr, pattern> {
1078  bits<32> enc;
1079
1080  let Inst{31-16} = enc{31-16};
1081}
1082
1083class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1084  : InstRRS<0, outs, ins, asmstr, pattern> {
1085  bits<48> enc;
1086
1087  let Inst{47-40} = enc{47-40};
1088  let Inst{7-0}   = enc{7-0};
1089}
1090
1091class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1092  : InstRS<0, outs, ins, asmstr, pattern> {
1093  bits<32> enc;
1094
1095  let Inst{31-24} = enc{31-24};
1096}
1097
1098// RSE is like RSY except with a 12 bit displacement (instead of 20).
1099class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1100  : InstRSY<6, outs, ins, asmstr, pattern> {
1101  bits <48> enc;
1102
1103  let Inst{47-40} = enc{47-40};
1104  let Inst{31-16} = BD2{15-0};
1105  let Inst{15-8}  = 0;
1106  let Inst{7-0}   = enc{7-0};
1107}
1108
1109class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1110  : InstRSI<0, outs, ins, asmstr, pattern> {
1111  bits<32> enc;
1112
1113  let Inst{31-24} = enc{31-24};
1114}
1115
1116class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
1117  : InstRSY<0, outs, ins, asmstr, pattern> {
1118  bits<48> enc;
1119
1120  let Inst{47-40} = enc{47-40};
1121  let Inst{7-0}   = enc{7-0};
1122}
1123
1124class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1125  : InstRX<0, outs, ins, asmstr, pattern> {
1126  bits<32> enc;
1127
1128  let Inst{31-24} = enc{31-24};
1129}
1130
1131class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
1132  : InstRXE<0, outs, ins, asmstr, pattern> {
1133  bits<48> enc;
1134
1135  let M3 = 0;
1136
1137  let Inst{47-40} = enc{47-40};
1138  let Inst{7-0}   = enc{7-0};
1139}
1140
1141class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
1142  : InstRXF<0, outs, ins, asmstr, pattern> {
1143  bits<48> enc;
1144
1145  let Inst{47-40} = enc{47-40};
1146  let Inst{7-0}   = enc{7-0};
1147}
1148
1149class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
1150  : InstRXY<0, outs, ins, asmstr, pattern> {
1151  bits<48> enc;
1152
1153  let Inst{47-40} = enc{47-40};
1154  let Inst{7-0}   = enc{7-0};
1155}
1156
1157class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
1158  : InstS<0, outs, ins, asmstr, pattern> {
1159  bits<32> enc;
1160
1161  let Inst{31-16} = enc{31-16};
1162}
1163
1164class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1165  : InstSI<0, outs, ins, asmstr, pattern> {
1166  bits<32> enc;
1167
1168  let Inst{31-24} = enc{31-24};
1169}
1170
1171class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
1172  : InstSIY<0, outs, ins, asmstr, pattern> {
1173  bits<48> enc;
1174
1175  let Inst{47-40} = enc{47-40};
1176  let Inst{7-0}   = enc{7-0};
1177}
1178
1179class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1180  : InstSIL<0, outs, ins, asmstr, pattern> {
1181  bits<48> enc;
1182
1183  let Inst{47-32} = enc{47-32};
1184}
1185
1186class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
1187  : InstSSd<0, outs, ins, asmstr, pattern> {
1188  bits<48> enc;
1189
1190  let Inst{47-40} = enc{47-40};
1191}
1192
1193class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1194  : InstSSE<0, outs, ins, asmstr, pattern> {
1195  bits<48> enc;
1196
1197  let Inst{47-32} = enc{47-32};
1198}
1199
1200class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
1201  : InstSSF<0, outs, ins, asmstr, pattern> {
1202  bits<48> enc;
1203
1204  let Inst{47-40} = enc{47-40};
1205  let Inst{35-32} = enc{35-32};
1206}
1207
1208//===----------------------------------------------------------------------===//
1209// Instruction definitions with semantics
1210//===----------------------------------------------------------------------===//
1211//
1212// These classes have the form [Cond]<Category><Format>, where <Format> is one
1213// of the formats defined above and where <Category> describes the inputs
1214// and outputs.  "Cond" is used if the instruction is conditional,
1215// in which case the 4-bit condition-code mask is added as a final operand.
1216// <Category> can be one of:
1217//
1218//   Inherent:
1219//     One register output operand and no input operands.
1220//
1221//   BranchUnary:
1222//     One register output operand, one register input operand and
1223//     one branch displacement.  The instructions stores a modified
1224//     form of the source register in the destination register and
1225//     branches on the result.
1226//
1227//   BranchBinary:
1228//     One register output operand, two register input operands and one branch
1229//     displacement. The instructions stores a modified form of one of the
1230//     source registers in the destination register and branches on the result.
1231//
1232//   LoadMultiple:
1233//     One address input operand and two explicit output operands.
1234//     The instruction loads a range of registers from the address,
1235//     with the explicit operands giving the first and last register
1236//     to load.  Other loaded registers are added as implicit definitions.
1237//
1238//   StoreMultiple:
1239//     Two explicit input register operands and an address operand.
1240//     The instruction stores a range of registers to the address,
1241//     with the explicit operands giving the first and last register
1242//     to store.  Other stored registers are added as implicit uses.
1243//
1244//   StoreLength:
1245//     One value operand, one length operand and one address operand.
1246//     The instruction stores the value operand to the address but
1247//     doesn't write more than the number of bytes specified by the
1248//     length operand.
1249//
1250//   Unary:
1251//     One register output operand and one input operand.
1252//
1253//   Store:
1254//     One address operand and one other input operand.  The instruction
1255//     stores to the address.
1256//
1257//   Binary:
1258//     One register output operand and two input operands.
1259//
1260//   StoreBinary:
1261//     One address operand and two other input operands.  The instruction
1262//     stores to the address.
1263//
1264//   Compare:
1265//     Two input operands and an implicit CC output operand.
1266//
1267//   Test:
1268//     Two input operands and an implicit CC output operand.  The second
1269//     input operand is an "address" operand used as a test class mask.
1270//
1271//   Ternary:
1272//     One register output operand and three input operands.
1273//
1274//   Quaternary:
1275//     One register output operand and four input operands.
1276//
1277//   LoadAndOp:
1278//     One output operand and two input operands, one of which is an address.
1279//     The instruction both reads from and writes to the address.
1280//
1281//   CmpSwap:
1282//     One output operand and three input operands, one of which is an address.
1283//     The instruction both reads from and writes to the address.
1284//
1285//   RotateSelect:
1286//     One output operand and five input operands.  The first two operands
1287//     are registers and the other three are immediates.
1288//
1289//   Prefetch:
1290//     One 4-bit immediate operand and one address operand.  The immediate
1291//     operand is 1 for a load prefetch and 2 for a store prefetch.
1292//
1293// The format determines which input operands are tied to output operands,
1294// and also determines the shape of any address operand.
1295//
1296// Multiclasses of the form <Category><Format>Pair define two instructions,
1297// one with <Category><Format> and one with <Category><Format>Y.  The name
1298// of the first instruction has no suffix, the name of the second has
1299// an extra "y".
1300//
1301//===----------------------------------------------------------------------===//
1302
1303class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1304                  dag src>
1305  : InstRRE<opcode, (outs cls:$R1), (ins),
1306            mnemonic#"\t$R1",
1307            [(set cls:$R1, src)]> {
1308  let R2 = 0;
1309}
1310
1311class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
1312  : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
1313  let I2 = value;
1314  let M3 = 0;
1315}
1316
1317class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
1318  : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
1319           mnemonic##"\t$R1, $I2", []> {
1320  let isBranch = 1;
1321  let isTerminator = 1;
1322  let Constraints = "$R1 = $R1src";
1323  let DisableEncoding = "$R1src";
1324}
1325
1326class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
1327  : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
1328            mnemonic##"\t$R1, $R3, $RI2", []> {
1329  let isBranch = 1;
1330  let isTerminator = 1;
1331  let Constraints = "$R1 = $R1src";
1332  let DisableEncoding = "$R1src";
1333}
1334
1335class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1336                     AddressingMode mode = bdaddr12only>
1337  : InstRS<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1338           mnemonic#"\t$R1, $R3, $BD2", []> {
1339  let mayLoad = 1;
1340}
1341
1342class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1343                      AddressingMode mode = bdaddr20only>
1344  : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
1345            mnemonic#"\t$R1, $R3, $BD2", []> {
1346  let mayLoad = 1;
1347}
1348
1349multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1350                              bits<16> rsyOpcode, RegisterOperand cls> {
1351  let DispKey = mnemonic ## #cls in {
1352    let DispSize = "12" in
1353      def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1354    let DispSize = "20" in
1355      def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1356  }
1357}
1358
1359class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
1360  : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
1361             mnemonic#"\t$V1, $V3, $BD2", []> {
1362  let M4 = 0;
1363  let mayLoad = 1;
1364}
1365
1366class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1367                 RegisterOperand cls>
1368  : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1369            mnemonic#"\t$R1, $I2",
1370            [(operator cls:$R1, pcrel32:$I2)]> {
1371  let mayStore = 1;
1372  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1373  // However, BDXs have two extra operands and are therefore 6 units more
1374  // complex.
1375  let AddedComplexity = 7;
1376}
1377
1378class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1379              RegisterOperand cls, bits<5> bytes,
1380              AddressingMode mode = bdxaddr12only>
1381  : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1382           mnemonic#"\t$R1, $XBD2",
1383           [(operator cls:$R1, mode:$XBD2)]> {
1384  let OpKey = mnemonic ## cls;
1385  let OpType = "mem";
1386  let mayStore = 1;
1387  let AccessBytes = bytes;
1388}
1389
1390class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1391               RegisterOperand cls, bits<5> bytes,
1392               AddressingMode mode = bdxaddr20only>
1393  : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
1394            mnemonic#"\t$R1, $XBD2",
1395            [(operator cls:$R1, mode:$XBD2)]> {
1396  let OpKey = mnemonic ## cls;
1397  let OpType = "mem";
1398  let mayStore = 1;
1399  let AccessBytes = bytes;
1400}
1401
1402multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1403                       SDPatternOperator operator, RegisterOperand cls,
1404                       bits<5> bytes> {
1405  let DispKey = mnemonic ## #cls in {
1406    let DispSize = "12" in
1407      def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1408    let DispSize = "20" in
1409      def Y  : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1410                        bdxaddr20pair>;
1411  }
1412}
1413
1414class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1415               TypedReg tr, bits<5> bytes, bits<4> type = 0>
1416  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
1417            mnemonic#"\t$V1, $XBD2",
1418            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1419  let M3 = type;
1420  let mayStore = 1;
1421  let AccessBytes = bytes;
1422}
1423
1424class StoreLengthVRSb<string mnemonic, bits<16> opcode,
1425                      SDPatternOperator operator, bits<5> bytes>
1426  : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
1427             mnemonic#"\t$V1, $R3, $BD2",
1428             [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
1429  let M4 = 0;
1430  let mayStore = 1;
1431  let AccessBytes = bytes;
1432}
1433
1434class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
1435                      AddressingMode mode = bdaddr12only>
1436  : InstRS<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1437           mnemonic#"\t$R1, $R3, $BD2", []> {
1438  let mayStore = 1;
1439}
1440
1441class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
1442                       AddressingMode mode = bdaddr20only>
1443  : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
1444            mnemonic#"\t$R1, $R3, $BD2", []> {
1445  let mayStore = 1;
1446}
1447
1448multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
1449                               bits<16> rsyOpcode, RegisterOperand cls> {
1450  let DispKey = mnemonic ## #cls in {
1451    let DispSize = "12" in
1452      def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
1453    let DispSize = "20" in
1454      def Y  : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
1455  }
1456}
1457
1458class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
1459  : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
1460             mnemonic#"\t$V1, $V3, $BD2", []> {
1461  let M4 = 0;
1462  let mayStore = 1;
1463}
1464
1465// StoreSI* instructions are used to store an integer to memory, but the
1466// addresses are more restricted than for normal stores.  If we are in the
1467// situation of having to force either the address into a register or the
1468// constant into a register, it's usually better to do the latter.
1469// We therefore match the address in the same way as a normal store and
1470// only use the StoreSI* instruction if the matched address is suitable.
1471class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1472              Immediate imm>
1473  : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1474           mnemonic#"\t$BD1, $I2",
1475           [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1476  let mayStore = 1;
1477}
1478
1479class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1480               Immediate imm>
1481  : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
1482            mnemonic#"\t$BD1, $I2",
1483            [(operator imm:$I2, mviaddr20pair:$BD1)]> {
1484  let mayStore = 1;
1485}
1486
1487class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1488               Immediate imm>
1489  : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1490            mnemonic#"\t$BD1, $I2",
1491            [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1492  let mayStore = 1;
1493}
1494
1495multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1496                       SDPatternOperator operator, Immediate imm> {
1497  let DispKey = mnemonic in {
1498    let DispSize = "12" in
1499      def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
1500    let DispSize = "20" in
1501      def Y  : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
1502  }
1503}
1504
1505class CondStoreRSY<string mnemonic, bits<16> opcode,
1506                   RegisterOperand cls, bits<5> bytes,
1507                   AddressingMode mode = bdaddr20only>
1508  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3),
1509            mnemonic#"$R3\t$R1, $BD2", []>,
1510    Requires<[FeatureLoadStoreOnCond]> {
1511  let mayStore = 1;
1512  let AccessBytes = bytes;
1513  let CCMaskLast = 1;
1514}
1515
1516// Like CondStoreRSY, but used for the raw assembly form.  The condition-code
1517// mask is the third operand rather than being part of the mnemonic.
1518class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
1519                      RegisterOperand cls, bits<5> bytes,
1520                      AddressingMode mode = bdaddr20only>
1521  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3),
1522            mnemonic#"\t$R1, $BD2, $R3", []>,
1523    Requires<[FeatureLoadStoreOnCond]> {
1524  let mayStore = 1;
1525  let AccessBytes = bytes;
1526}
1527
1528// Like CondStoreRSY, but with a fixed CC mask.
1529class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
1530                        RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1531                        AddressingMode mode = bdaddr20only>
1532  : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2),
1533            mnemonic#"\t$R1, $BD2", []>,
1534    Requires<[FeatureLoadStoreOnCond]> {
1535  let mayStore = 1;
1536  let AccessBytes = bytes;
1537  let R3 = ccmask;
1538}
1539
1540class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1541              RegisterOperand cls1, RegisterOperand cls2>
1542  : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
1543           mnemonic#"r\t$R1, $R2",
1544           [(set cls1:$R1, (operator cls2:$R2))]> {
1545  let OpKey = mnemonic ## cls1;
1546  let OpType = "reg";
1547}
1548
1549class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1550               RegisterOperand cls1, RegisterOperand cls2>
1551  : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
1552            mnemonic#"r\t$R1, $R2",
1553            [(set cls1:$R1, (operator cls2:$R2))]> {
1554  let OpKey = mnemonic ## cls1;
1555  let OpType = "reg";
1556}
1557
1558class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1559               RegisterOperand cls2>
1560  : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
1561            mnemonic#"r\t$R1, $R3, $R2", []> {
1562  let OpKey = mnemonic ## cls1;
1563  let OpType = "reg";
1564  let R4 = 0;
1565}
1566
1567class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1568                RegisterOperand cls2>
1569  : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
1570            mnemonic#"\t$R1, $R3, $R2, $R4", []>;
1571
1572// These instructions are generated by if conversion.  The old value of R1
1573// is added as an implicit use.
1574class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1575                   RegisterOperand cls2>
1576  : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3),
1577            mnemonic#"r$R3\t$R1, $R2", []>,
1578    Requires<[FeatureLoadStoreOnCond]> {
1579  let CCMaskLast = 1;
1580  let R4 = 0;
1581}
1582
1583class CondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1584                   Immediate imm>
1585  : InstRIEd<opcode, (outs cls:$R1),
1586                     (ins imm:$I2, cond4:$valid, cond4:$R3),
1587             mnemonic#"$R3\t$R1, $I2", []>,
1588    Requires<[FeatureLoadStoreOnCond2]> {
1589  let CCMaskLast = 1;
1590}
1591
1592// Like CondUnaryRRF, but used for the raw assembly form.  The condition-code
1593// mask is the third operand rather than being part of the mnemonic.
1594class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1595                      RegisterOperand cls2>
1596  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3),
1597            mnemonic#"r\t$R1, $R2, $R3", []>,
1598    Requires<[FeatureLoadStoreOnCond]> {
1599  let Constraints = "$R1 = $R1src";
1600  let DisableEncoding = "$R1src";
1601  let R4 = 0;
1602}
1603
1604class AsmCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1605                   Immediate imm>
1606  : InstRIEd<opcode, (outs cls:$R1),
1607                     (ins cls:$R1src, imm:$I2, imm32zx4:$R3),
1608             mnemonic#"\t$R1, $I2, $R3", []>,
1609    Requires<[FeatureLoadStoreOnCond2]> {
1610  let Constraints = "$R1 = $R1src";
1611  let DisableEncoding = "$R1src";
1612}
1613
1614// Like CondUnaryRRF, but with a fixed CC mask.
1615class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1616                        RegisterOperand cls2, bits<4> ccmask>
1617  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1618            mnemonic#"\t$R1, $R2", []>,
1619    Requires<[FeatureLoadStoreOnCond]> {
1620  let Constraints = "$R1 = $R1src";
1621  let DisableEncoding = "$R1src";
1622  let R3 = ccmask;
1623  let R4 = 0;
1624}
1625
1626class FixedCondUnaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
1627                   Immediate imm, bits<4> ccmask>
1628  : InstRIEd<opcode, (outs cls:$R1),
1629                     (ins cls:$R1src, imm:$I2),
1630             mnemonic#"\t$R1, $I2", []>,
1631    Requires<[FeatureLoadStoreOnCond2]> {
1632  let Constraints = "$R1 = $R1src";
1633  let DisableEncoding = "$R1src";
1634  let R3 = ccmask;
1635}
1636
1637class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1638              RegisterOperand cls, Immediate imm>
1639  : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
1640           mnemonic#"\t$R1, $I2",
1641           [(set cls:$R1, (operator imm:$I2))]>;
1642
1643class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1644               RegisterOperand cls, Immediate imm>
1645  : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
1646            mnemonic#"\t$R1, $I2",
1647            [(set cls:$R1, (operator imm:$I2))]>;
1648
1649class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1650                 RegisterOperand cls>
1651  : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
1652            mnemonic#"\t$R1, $I2",
1653            [(set cls:$R1, (operator pcrel32:$I2))]> {
1654  let mayLoad = 1;
1655  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
1656  // However, BDXs have two extra operands and are therefore 6 units more
1657  // complex.
1658  let AddedComplexity = 7;
1659}
1660
1661class CondUnaryRSY<string mnemonic, bits<16> opcode,
1662                   SDPatternOperator operator, RegisterOperand cls,
1663                   bits<5> bytes, AddressingMode mode = bdaddr20only>
1664  : InstRSY<opcode, (outs cls:$R1),
1665            (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
1666            mnemonic#"$R3\t$R1, $BD2",
1667            [(set cls:$R1,
1668                  (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src,
1669                                   cond4:$valid, cond4:$R3))]>,
1670    Requires<[FeatureLoadStoreOnCond]> {
1671  let Constraints = "$R1 = $R1src";
1672  let DisableEncoding = "$R1src";
1673  let mayLoad = 1;
1674  let AccessBytes = bytes;
1675  let CCMaskLast = 1;
1676}
1677
1678// Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
1679// mask is the third operand rather than being part of the mnemonic.
1680class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
1681                      RegisterOperand cls, bits<5> bytes,
1682                      AddressingMode mode = bdaddr20only>
1683  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3),
1684            mnemonic#"\t$R1, $BD2, $R3", []>,
1685    Requires<[FeatureLoadStoreOnCond]> {
1686  let mayLoad = 1;
1687  let AccessBytes = bytes;
1688  let Constraints = "$R1 = $R1src";
1689  let DisableEncoding = "$R1src";
1690}
1691
1692// Like CondUnaryRSY, but with a fixed CC mask.
1693class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
1694                        RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
1695                        AddressingMode mode = bdaddr20only>
1696  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
1697            mnemonic#"\t$R1, $BD2", []>,
1698    Requires<[FeatureLoadStoreOnCond]> {
1699  let Constraints = "$R1 = $R1src";
1700  let DisableEncoding = "$R1src";
1701  let R3 = ccmask;
1702  let mayLoad = 1;
1703  let AccessBytes = bytes;
1704}
1705
1706class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1707              RegisterOperand cls, bits<5> bytes,
1708              AddressingMode mode = bdxaddr12only>
1709  : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2),
1710           mnemonic#"\t$R1, $XBD2",
1711           [(set cls:$R1, (operator mode:$XBD2))]> {
1712  let OpKey = mnemonic ## cls;
1713  let OpType = "mem";
1714  let mayLoad = 1;
1715  let AccessBytes = bytes;
1716}
1717
1718class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1719               RegisterOperand cls, bits<5> bytes>
1720  : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
1721            mnemonic#"\t$R1, $XBD2",
1722            [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
1723  let OpKey = mnemonic ## cls;
1724  let OpType = "mem";
1725  let mayLoad = 1;
1726  let AccessBytes = bytes;
1727  let M3 = 0;
1728}
1729
1730class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1731               RegisterOperand cls, bits<5> bytes,
1732               AddressingMode mode = bdxaddr20only>
1733  : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2),
1734            mnemonic#"\t$R1, $XBD2",
1735            [(set cls:$R1, (operator mode:$XBD2))]> {
1736  let OpKey = mnemonic ## cls;
1737  let OpType = "mem";
1738  let mayLoad = 1;
1739  let AccessBytes = bytes;
1740}
1741
1742multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1743                       SDPatternOperator operator, RegisterOperand cls,
1744                       bits<5> bytes> {
1745  let DispKey = mnemonic ## #cls in {
1746    let DispSize = "12" in
1747      def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
1748    let DispSize = "20" in
1749      def Y  : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
1750                        bdxaddr20pair>;
1751  }
1752}
1753
1754class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1755                TypedReg tr, Immediate imm, bits<4> type = 0>
1756  : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1757             mnemonic#"\t$V1, $I2",
1758             [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1759  let M3 = type;
1760}
1761
1762class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1763                TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
1764                bits<4> m5 = 0>
1765  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1766             mnemonic#"\t$V1, $V2",
1767             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1768  let M3 = type;
1769  let M4 = m4;
1770  let M5 = m5;
1771}
1772
1773multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode,
1774                          SDPatternOperator operator,
1775                          SDPatternOperator operator_cc, TypedReg tr1,
1776                          TypedReg tr2, bits<4> type, bits<4> modifier = 0,
1777                          bits<4> modifier_cc = 1> {
1778  def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>;
1779  let Defs = [CC] in
1780    def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0,
1781                      modifier_cc>;
1782}
1783
1784class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1785               TypedReg tr, bits<5> bytes, bits<4> type = 0>
1786  : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
1787            mnemonic#"\t$V1, $XBD2",
1788            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> {
1789  let M3 = type;
1790  let mayLoad = 1;
1791  let AccessBytes = bytes;
1792}
1793
1794class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1795               RegisterOperand cls1, RegisterOperand cls2>
1796  : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1797           mnemonic#"r\t$R1, $R2",
1798           [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1799  let OpKey = mnemonic ## cls1;
1800  let OpType = "reg";
1801  let Constraints = "$R1 = $R1src";
1802  let DisableEncoding = "$R1src";
1803}
1804
1805class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1806                RegisterOperand cls1, RegisterOperand cls2>
1807  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
1808            mnemonic#"r\t$R1, $R2",
1809            [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
1810  let OpKey = mnemonic ## cls1;
1811  let OpType = "reg";
1812  let Constraints = "$R1 = $R1src";
1813  let DisableEncoding = "$R1src";
1814}
1815
1816class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1817                RegisterOperand cls1, RegisterOperand cls2>
1818  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1819            mnemonic#"r\t$R1, $R3, $R2",
1820            [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1821  let OpKey = mnemonic ## cls1;
1822  let OpType = "reg";
1823  let R4 = 0;
1824}
1825
1826class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1827                 RegisterOperand cls1, RegisterOperand cls2>
1828  : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
1829            mnemonic#"rk\t$R1, $R2, $R3",
1830            [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
1831  let R4 = 0;
1832}
1833
1834multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1835                        SDPatternOperator operator, RegisterOperand cls1,
1836                        RegisterOperand cls2> {
1837  let NumOpsKey = mnemonic in {
1838    let NumOpsValue = "3" in
1839      def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1840              Requires<[FeatureDistinctOps]>;
1841    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1842      def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
1843  }
1844}
1845
1846multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
1847                         SDPatternOperator operator, RegisterOperand cls1,
1848                         RegisterOperand cls2> {
1849  let NumOpsKey = mnemonic in {
1850    let NumOpsValue = "3" in
1851      def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
1852              Requires<[FeatureDistinctOps]>;
1853    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1854      def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
1855  }
1856}
1857
1858class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1859               RegisterOperand cls, Immediate imm>
1860  : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1861           mnemonic#"\t$R1, $I2",
1862           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1863  let Constraints = "$R1 = $R1src";
1864  let DisableEncoding = "$R1src";
1865}
1866
1867class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1868                RegisterOperand cls, Immediate imm>
1869  : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
1870             mnemonic#"\t$R1, $R3, $I2",
1871             [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
1872
1873multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
1874                        SDPatternOperator operator, RegisterOperand cls,
1875                        Immediate imm> {
1876  let NumOpsKey = mnemonic in {
1877    let NumOpsValue = "3" in
1878      def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>,
1879              Requires<[FeatureDistinctOps]>;
1880    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1881      def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
1882  }
1883}
1884
1885class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1886                RegisterOperand cls, Immediate imm>
1887  : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1888            mnemonic#"\t$R1, $I2",
1889            [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1890  let Constraints = "$R1 = $R1src";
1891  let DisableEncoding = "$R1src";
1892}
1893
1894class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1895               RegisterOperand cls>
1896  : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
1897           mnemonic#"\t$R1, $BD2",
1898           [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
1899  let R3 = 0;
1900  let Constraints = "$R1 = $R1src";
1901  let DisableEncoding = "$R1src";
1902}
1903
1904class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1905                RegisterOperand cls>
1906  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
1907            mnemonic#"\t$R1, $R3, $BD2",
1908            [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
1909
1910multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1911                        SDPatternOperator operator, RegisterOperand cls> {
1912  let NumOpsKey = mnemonic in {
1913    let NumOpsValue = "3" in
1914      def K  : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>,
1915               Requires<[FeatureDistinctOps]>;
1916    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
1917      def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
1918  }
1919}
1920
1921class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1922               RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1923               AddressingMode mode = bdxaddr12only>
1924  : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1925           mnemonic#"\t$R1, $XBD2",
1926           [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1927  let OpKey = mnemonic ## cls;
1928  let OpType = "mem";
1929  let Constraints = "$R1 = $R1src";
1930  let DisableEncoding = "$R1src";
1931  let mayLoad = 1;
1932  let AccessBytes = bytes;
1933}
1934
1935class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1936                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1937  : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
1938            mnemonic#"\t$R1, $XBD2",
1939            [(set cls:$R1, (operator cls:$R1src,
1940                                     (load bdxaddr12only:$XBD2)))]> {
1941  let OpKey = mnemonic ## cls;
1942  let OpType = "mem";
1943  let Constraints = "$R1 = $R1src";
1944  let DisableEncoding = "$R1src";
1945  let mayLoad = 1;
1946  let AccessBytes = bytes;
1947  let M3 = 0;
1948}
1949
1950class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1951                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1952                AddressingMode mode = bdxaddr20only>
1953  : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
1954            mnemonic#"\t$R1, $XBD2",
1955            [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
1956  let OpKey = mnemonic ## cls;
1957  let OpType = "mem";
1958  let Constraints = "$R1 = $R1src";
1959  let DisableEncoding = "$R1src";
1960  let mayLoad = 1;
1961  let AccessBytes = bytes;
1962}
1963
1964multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1965                        SDPatternOperator operator, RegisterOperand cls,
1966                        SDPatternOperator load, bits<5> bytes> {
1967  let DispKey = mnemonic ## #cls in {
1968    let DispSize = "12" in
1969      def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
1970                        bdxaddr12pair>;
1971    let DispSize = "20" in
1972      def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
1973                         bdxaddr20pair>;
1974  }
1975}
1976
1977class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1978               Operand imm, AddressingMode mode = bdaddr12only>
1979  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1980           mnemonic#"\t$BD1, $I2",
1981           [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1982  let mayLoad = 1;
1983  let mayStore = 1;
1984}
1985
1986class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1987                Operand imm, AddressingMode mode = bdaddr20only>
1988  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1989            mnemonic#"\t$BD1, $I2",
1990            [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1991  let mayLoad = 1;
1992  let mayStore = 1;
1993}
1994
1995multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
1996                        bits<16> siyOpcode, SDPatternOperator operator,
1997                        Operand imm> {
1998  let DispKey = mnemonic ## #cls in {
1999    let DispSize = "12" in
2000      def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
2001    let DispSize = "20" in
2002      def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
2003  }
2004}
2005
2006class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2007                 TypedReg tr, bits<4> type>
2008  : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
2009             mnemonic#"\t$V1, $I2, $I3",
2010             [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
2011  let M4 = type;
2012}
2013
2014class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2015                 TypedReg tr1, TypedReg tr2, bits<4> type>
2016  : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
2017             mnemonic#"\t$V1, $V3, $I2",
2018             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2019                                                 imm32zx16:$I2)))]> {
2020  let M4 = type;
2021}
2022
2023class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2024                 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
2025  : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
2026             mnemonic#"\t$V1, $V2, $I3",
2027             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2028                                                 imm32zx12:$I3)))]> {
2029  let M4 = type;
2030  let M5 = m5;
2031}
2032
2033class BinaryVRRa<string mnemonic, bits<16> opcode>
2034  : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
2035             mnemonic#"\t$V1, $V2, $M3", []> {
2036  let M4 = 0;
2037  let M5 = 0;
2038}
2039
2040class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2041                 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
2042                 bits<4> modifier = 0>
2043  : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
2044             mnemonic#"\t$V1, $V2, $V3",
2045             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2046                                                 (tr2.vt tr2.op:$V3))))]> {
2047  let M4 = type;
2048  let M5 = modifier;
2049}
2050
2051// Declare a pair of instructions, one which sets CC and one which doesn't.
2052// The CC-setting form ends with "S" and sets the low bit of M5.
2053multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
2054                           SDPatternOperator operator,
2055                           SDPatternOperator operator_cc, TypedReg tr1,
2056                           TypedReg tr2, bits<4> type,
2057                           bits<4> modifier = 0, bits<4> modifier_cc = 1> {
2058  def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>;
2059  let Defs = [CC] in
2060    def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2061                       modifier_cc>;
2062}
2063
2064class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2065                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
2066                 bits<4> m6 = 0>
2067  : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
2068             mnemonic#"\t$V1, $V2, $V3",
2069             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2070                                                 (tr2.vt tr2.op:$V3))))]> {
2071  let M4 = type;
2072  let M5 = m5;
2073  let M6 = m6;
2074}
2075
2076multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
2077                           SDPatternOperator operator,
2078                           SDPatternOperator operator_cc, TypedReg tr1,
2079                           TypedReg tr2, bits<4> type, bits<4> m5,
2080                           bits<4> modifier = 0, bits<4> modifier_cc = 1> {
2081  def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>;
2082  let Defs = [CC] in
2083    def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2084                       m5, modifier_cc>;
2085}
2086
2087class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2088                 TypedReg tr>
2089  : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
2090             mnemonic#"\t$V1, $R2, $R3",
2091             [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>;
2092
2093class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2094                 TypedReg tr1, TypedReg tr2, bits<4> type>
2095  : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
2096             mnemonic#"\t$V1, $V3, $BD2",
2097             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
2098                                                 shift12only:$BD2)))]> {
2099  let M4 = type;
2100}
2101
2102class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2103                 bits<5> bytes>
2104  : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
2105             mnemonic#"\t$V1, $R3, $BD2",
2106             [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
2107  let M4 = 0;
2108  let mayLoad = 1;
2109  let AccessBytes = bytes;
2110}
2111
2112class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2113                 TypedReg tr, bits<4> type>
2114  : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
2115           mnemonic#"\t$R1, $V3, $BD2",
2116           [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
2117  let M4 = type;
2118}
2119
2120class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2121                TypedReg tr, bits<5> bytes>
2122  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
2123            mnemonic#"\t$V1, $XBD2, $M3",
2124            [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2,
2125                                              imm32zx4:$M3)))]> {
2126  let mayLoad = 1;
2127  let AccessBytes = bytes;
2128}
2129
2130class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2131                     Immediate index>
2132  : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
2133            mnemonic#"\t$V1, $VBD2, $M3", []> {
2134  let mayStore = 1;
2135  let AccessBytes = bytes;
2136}
2137
2138class StoreBinaryVRX<string mnemonic, bits<16> opcode,
2139                     SDPatternOperator operator, TypedReg tr, bits<5> bytes,
2140                     Immediate index>
2141  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
2142            mnemonic#"\t$V1, $XBD2, $M3",
2143            [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
2144  let mayStore = 1;
2145  let AccessBytes = bytes;
2146}
2147
2148class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2149                RegisterOperand cls1, RegisterOperand cls2>
2150  : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2151           mnemonic#"r\t$R1, $R2",
2152           [(operator cls1:$R1, cls2:$R2)]> {
2153  let OpKey = mnemonic ## cls1;
2154  let OpType = "reg";
2155  let isCompare = 1;
2156}
2157
2158class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2159                 RegisterOperand cls1, RegisterOperand cls2>
2160  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
2161            mnemonic#"r\t$R1, $R2",
2162            [(operator cls1:$R1, cls2:$R2)]> {
2163  let OpKey = mnemonic ## cls1;
2164  let OpType = "reg";
2165  let isCompare = 1;
2166}
2167
2168class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2169                RegisterOperand cls, Immediate imm>
2170  : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
2171           mnemonic#"\t$R1, $I2",
2172           [(operator cls:$R1, imm:$I2)]> {
2173  let isCompare = 1;
2174}
2175
2176class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2177                 RegisterOperand cls, Immediate imm>
2178  : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
2179            mnemonic#"\t$R1, $I2",
2180            [(operator cls:$R1, imm:$I2)]> {
2181  let isCompare = 1;
2182}
2183
2184class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2185                   RegisterOperand cls, SDPatternOperator load>
2186  : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
2187            mnemonic#"\t$R1, $I2",
2188            [(operator cls:$R1, (load pcrel32:$I2))]> {
2189  let isCompare = 1;
2190  let mayLoad = 1;
2191  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2192  // However, BDXs have two extra operands and are therefore 6 units more
2193  // complex.
2194  let AddedComplexity = 7;
2195}
2196
2197class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2198                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2199                AddressingMode mode = bdxaddr12only>
2200  : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2201           mnemonic#"\t$R1, $XBD2",
2202           [(operator cls:$R1, (load mode:$XBD2))]> {
2203  let OpKey = mnemonic ## cls;
2204  let OpType = "mem";
2205  let isCompare = 1;
2206  let mayLoad = 1;
2207  let AccessBytes = bytes;
2208}
2209
2210class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2211                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2212  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2213            mnemonic#"\t$R1, $XBD2",
2214            [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
2215  let OpKey = mnemonic ## cls;
2216  let OpType = "mem";
2217  let isCompare = 1;
2218  let mayLoad = 1;
2219  let AccessBytes = bytes;
2220  let M3 = 0;
2221}
2222
2223class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2224                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
2225                 AddressingMode mode = bdxaddr20only>
2226  : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2227            mnemonic#"\t$R1, $XBD2",
2228            [(operator cls:$R1, (load mode:$XBD2))]> {
2229  let OpKey = mnemonic ## cls;
2230  let OpType = "mem";
2231  let isCompare = 1;
2232  let mayLoad = 1;
2233  let AccessBytes = bytes;
2234}
2235
2236multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2237                         SDPatternOperator operator, RegisterOperand cls,
2238                         SDPatternOperator load, bits<5> bytes> {
2239  let DispKey = mnemonic ## #cls in {
2240    let DispSize = "12" in
2241      def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
2242                         load, bytes, bdxaddr12pair>;
2243    let DispSize = "20" in
2244      def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
2245                          load, bytes, bdxaddr20pair>;
2246  }
2247}
2248
2249class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2250                SDPatternOperator load, Immediate imm,
2251                AddressingMode mode = bdaddr12only>
2252  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
2253           mnemonic#"\t$BD1, $I2",
2254           [(operator (load mode:$BD1), imm:$I2)]> {
2255  let isCompare = 1;
2256  let mayLoad = 1;
2257}
2258
2259class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2260                 SDPatternOperator load, Immediate imm>
2261  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
2262            mnemonic#"\t$BD1, $I2",
2263            [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
2264  let isCompare = 1;
2265  let mayLoad = 1;
2266}
2267
2268class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2269                 SDPatternOperator load, Immediate imm,
2270                 AddressingMode mode = bdaddr20only>
2271  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
2272            mnemonic#"\t$BD1, $I2",
2273            [(operator (load mode:$BD1), imm:$I2)]> {
2274  let isCompare = 1;
2275  let mayLoad = 1;
2276}
2277
2278multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2279                         SDPatternOperator operator, SDPatternOperator load,
2280                         Immediate imm> {
2281  let DispKey = mnemonic in {
2282    let DispSize = "12" in
2283      def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
2284    let DispSize = "20" in
2285      def Y  : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
2286                          bdaddr20pair>;
2287  }
2288}
2289
2290class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2291                  TypedReg tr, bits<4> type>
2292  : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
2293             mnemonic#"\t$V1, $V2",
2294             [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> {
2295  let isCompare = 1;
2296  let M3 = type;
2297  let M4 = 0;
2298  let M5 = 0;
2299}
2300
2301class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2302              RegisterOperand cls>
2303  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
2304            mnemonic#"\t$R1, $XBD2",
2305            [(operator cls:$R1, bdxaddr12only:$XBD2)]> {
2306  let M3 = 0;
2307}
2308
2309class TernaryRRD<string mnemonic, bits<16> opcode,
2310                 SDPatternOperator operator, RegisterOperand cls>
2311  : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
2312            mnemonic#"r\t$R1, $R3, $R2",
2313            [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
2314  let OpKey = mnemonic ## cls;
2315  let OpType = "reg";
2316  let Constraints = "$R1 = $R1src";
2317  let DisableEncoding = "$R1src";
2318}
2319
2320class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2321                bits<5> bytes, AddressingMode mode = bdaddr12only>
2322  : InstRS<opcode, (outs cls:$R1),
2323          (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2324           mnemonic#"\t$R1, $R3, $BD2", []> {
2325
2326  let Constraints = "$R1 = $R1src";
2327  let DisableEncoding = "$R1src";
2328  let mayLoad = 1;
2329  let AccessBytes = bytes;
2330}
2331
2332class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2333                bits<5> bytes, AddressingMode mode = bdaddr20only>
2334  : InstRSY<opcode, (outs cls:$R1),
2335           (ins cls:$R1src, imm32zx4:$R3, mode:$BD2),
2336            mnemonic#"\t$R1, $R3, $BD2", []> {
2337
2338  let Constraints = "$R1 = $R1src";
2339  let DisableEncoding = "$R1src";
2340  let mayLoad = 1;
2341  let AccessBytes = bytes;
2342}
2343
2344multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2345                         RegisterOperand cls, bits<5> bytes> {
2346  let DispKey = mnemonic ## #cls in {
2347    let DispSize = "12" in
2348      def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
2349    let DispSize = "20" in
2350      def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
2351  }
2352}
2353
2354class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2355                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
2356  : InstRXF<opcode, (outs cls:$R1),
2357            (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2),
2358            mnemonic#"\t$R1, $R3, $XBD2",
2359            [(set cls:$R1, (operator cls:$R1src, cls:$R3,
2360                                     (load bdxaddr12only:$XBD2)))]> {
2361  let OpKey = mnemonic ## cls;
2362  let OpType = "mem";
2363  let Constraints = "$R1 = $R1src";
2364  let DisableEncoding = "$R1src";
2365  let mayLoad = 1;
2366  let AccessBytes = bytes;
2367}
2368
2369class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2370                  TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
2371  : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
2372             mnemonic#"\t$V1, $I2, $M3",
2373             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2374                                                 imm:$I2, index:$M3)))]> {
2375  let Constraints = "$V1 = $V1src";
2376  let DisableEncoding = "$V1src";
2377}
2378
2379class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2380                  TypedReg tr1, TypedReg tr2, bits<4> type>
2381  : InstVRId<opcode, (outs tr1.op:$V1),
2382             (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2383             mnemonic#"\t$V1, $V2, $V3, $I4",
2384             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2385                                                 (tr2.vt tr2.op:$V3),
2386                                                 imm32zx8:$I4)))]> {
2387  let M5 = type;
2388}
2389
2390class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2391                  TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
2392  : InstVRRa<opcode, (outs tr1.op:$V1),
2393             (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
2394             mnemonic#"\t$V1, $V2, $M4, $M5",
2395             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2396                                                 imm32zx4:$M4,
2397                                                 imm32zx4:$M5)))],
2398             m4or> {
2399  let M3 = type;
2400}
2401
2402class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2403                  TypedReg tr1, TypedReg tr2, bits<4> type,
2404                  SDPatternOperator m5mask, bits<4> m5or>
2405  : InstVRRb<opcode, (outs tr1.op:$V1),
2406             (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
2407             mnemonic#"\t$V1, $V2, $V3, $M5",
2408             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2409                                                 (tr2.vt tr2.op:$V3),
2410                                                 m5mask:$M5)))],
2411             m5or> {
2412  let M4 = type;
2413}
2414
2415multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode,
2416                            SDPatternOperator operator,
2417                            SDPatternOperator operator_cc, TypedReg tr1,
2418                            TypedReg tr2, bits<4> type, bits<4> m5or> {
2419  def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
2420                       imm32zx4even, !and (m5or, 14)>;
2421  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
2422                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2423                                            tr2.op:$V3, 0)>;
2424  let Defs = [CC] in
2425    def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2426                        imm32zx4even, !add(!and (m5or, 14), 1)>;
2427  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
2428                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2429                                                tr2.op:$V3, 0)>;
2430}
2431
2432class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2433                  TypedReg tr1, TypedReg tr2>
2434  : InstVRRc<opcode, (outs tr1.op:$V1),
2435             (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
2436             mnemonic#"\t$V1, $V2, $V3, $M4",
2437             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2438                                                 (tr2.vt tr2.op:$V3),
2439                                                 imm32zx4:$M4)))]> {
2440  let M5 = 0;
2441  let M6 = 0;
2442}
2443
2444class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2445                  TypedReg tr1, TypedReg tr2, bits<4> type = 0>
2446  : InstVRRd<opcode, (outs tr1.op:$V1),
2447             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2448             mnemonic#"\t$V1, $V2, $V3, $V4",
2449             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2450                                                 (tr2.vt tr2.op:$V3),
2451                                                 (tr1.vt tr1.op:$V4))))]> {
2452  let M5 = type;
2453  let M6 = 0;
2454}
2455
2456class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2457                  TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
2458  : InstVRRe<opcode, (outs tr1.op:$V1),
2459             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
2460             mnemonic#"\t$V1, $V2, $V3, $V4",
2461             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2462                                                 (tr2.vt tr2.op:$V3),
2463                                                 (tr1.vt tr1.op:$V4))))]> {
2464  let M5 = m5;
2465  let M6 = type;
2466}
2467
2468class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2469                  TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
2470  : InstVRSb<opcode, (outs tr1.op:$V1),
2471             (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
2472             mnemonic#"\t$V1, $R3, $BD2",
2473             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2474                                                 cls:$R3,
2475                                                 shift12only:$BD2)))]> {
2476  let Constraints = "$V1 = $V1src";
2477  let DisableEncoding = "$V1src";
2478  let M4 = type;
2479}
2480
2481class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
2482                 Immediate index>
2483  : InstVRV<opcode, (outs VR128:$V1),
2484           (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
2485           mnemonic#"\t$V1, $VBD2, $M3", []> {
2486  let Constraints = "$V1 = $V1src";
2487  let DisableEncoding = "$V1src";
2488  let mayLoad = 1;
2489  let AccessBytes = bytes;
2490}
2491
2492class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2493                 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
2494  : InstVRX<opcode, (outs tr1.op:$V1),
2495           (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
2496           mnemonic#"\t$V1, $XBD2, $M3",
2497           [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2498                                               bdxaddr12only:$XBD2,
2499                                               index:$M3)))]> {
2500  let Constraints = "$V1 = $V1src";
2501  let DisableEncoding = "$V1src";
2502  let mayLoad = 1;
2503  let AccessBytes = bytes;
2504}
2505
2506class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2507                     TypedReg tr1, TypedReg tr2, bits<4> type>
2508  : InstVRId<opcode, (outs tr1.op:$V1),
2509             (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
2510             mnemonic#"\t$V1, $V2, $V3, $I4",
2511             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2512                                                 (tr2.vt tr2.op:$V2),
2513                                                 (tr2.vt tr2.op:$V3),
2514                                                 imm32zx8:$I4)))]> {
2515  let Constraints = "$V1 = $V1src";
2516  let DisableEncoding = "$V1src";
2517  let M5 = type;
2518}
2519
2520class QuaternaryVRRd<string mnemonic, bits<16> opcode,
2521                     SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
2522                     bits<4> type, SDPatternOperator m6mask, bits<4> m6or>
2523  : InstVRRd<opcode, (outs tr1.op:$V1),
2524             (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6),
2525             mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
2526             [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2527                                                 (tr2.vt tr2.op:$V3),
2528                                                 (tr2.vt tr2.op:$V4),
2529                                                 m6mask:$M6)))],
2530             m6or> {
2531  let M5 = type;
2532}
2533
2534multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode,
2535                               SDPatternOperator operator,
2536                               SDPatternOperator operator_cc, TypedReg tr1,
2537                               TypedReg tr2, bits<4> type, bits<4> m6or> {
2538  def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
2539                          imm32zx4even, !and (m6or, 14)>;
2540  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
2541                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2542                                            tr2.op:$V3, tr2.op:$V4, 0)>;
2543  let Defs = [CC] in
2544    def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2545                           imm32zx4even, !add (!and (m6or, 14), 1)>;
2546  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
2547                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2548                                                tr2.op:$V3, tr2.op:$V4, 0)>;
2549}
2550
2551class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2552                  RegisterOperand cls, AddressingMode mode = bdaddr20only>
2553  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
2554            mnemonic#"\t$R1, $R3, $BD2",
2555            [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
2556  let mayLoad = 1;
2557  let mayStore = 1;
2558}
2559
2560class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2561                RegisterOperand cls, AddressingMode mode = bdaddr12only>
2562  : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2563           mnemonic#"\t$R1, $R3, $BD2",
2564           [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2565  let Constraints = "$R1 = $R1src";
2566  let DisableEncoding = "$R1src";
2567  let mayLoad = 1;
2568  let mayStore = 1;
2569}
2570
2571class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2572                 RegisterOperand cls, AddressingMode mode = bdaddr20only>
2573  : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
2574            mnemonic#"\t$R1, $R3, $BD2",
2575            [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
2576  let Constraints = "$R1 = $R1src";
2577  let DisableEncoding = "$R1src";
2578  let mayLoad = 1;
2579  let mayStore = 1;
2580}
2581
2582multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
2583                         SDPatternOperator operator, RegisterOperand cls> {
2584  let DispKey = mnemonic ## #cls in {
2585    let DispSize = "12" in
2586      def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
2587    let DispSize = "20" in
2588      def Y  : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
2589  }
2590}
2591
2592class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
2593                       RegisterOperand cls2>
2594  : InstRIEf<opcode, (outs cls1:$R1),
2595             (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2596                  imm32zx6:$I5),
2597             mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
2598  let Constraints = "$R1 = $R1src";
2599  let DisableEncoding = "$R1src";
2600}
2601
2602class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
2603  : InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2),
2604            mnemonic##"\t$R1, $XBD2",
2605            [(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>;
2606
2607class PrefetchRILPC<string mnemonic, bits<12> opcode,
2608                    SDPatternOperator operator>
2609  : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2),
2610            mnemonic##"\t$R1, $I2",
2611            [(operator imm32zx4:$R1, pcrel32:$I2)]> {
2612  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2613  // However, BDXs have two extra operands and are therefore 6 units more
2614  // complex.
2615  let AddedComplexity = 7;
2616}
2617
2618// A floating-point load-and test operation.  Create both a normal unary
2619// operation and one that acts as a comparison against zero.
2620// Note that the comparison against zero operation is not available if we
2621// have vector support, since load-and-test instructions will partially
2622// clobber the target (vector) register.
2623multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
2624                          RegisterOperand cls> {
2625  def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
2626  let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
2627    def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
2628}
2629
2630//===----------------------------------------------------------------------===//
2631// Pseudo instructions
2632//===----------------------------------------------------------------------===//
2633//
2634// Convenience instructions that get lowered to real instructions
2635// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
2636// or SystemZInstrInfo::expandPostRAPseudo().
2637//
2638//===----------------------------------------------------------------------===//
2639
2640class Pseudo<dag outs, dag ins, list<dag> pattern>
2641  : InstSystemZ<0, outs, ins, "", pattern> {
2642  let isPseudo = 1;
2643  let isCodeGenOnly = 1;
2644}
2645
2646// Like UnaryRI, but expanded after RA depending on the choice of register.
2647class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2648                    Immediate imm>
2649  : Pseudo<(outs cls:$R1), (ins imm:$I2),
2650           [(set cls:$R1, (operator imm:$I2))]>;
2651
2652// Like UnaryRXY, but expanded after RA depending on the choice of register.
2653class UnaryRXYPseudo<string key, SDPatternOperator operator,
2654                     RegisterOperand cls, bits<5> bytes,
2655                     AddressingMode mode = bdxaddr20only>
2656  : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
2657           [(set cls:$R1, (operator mode:$XBD2))]> {
2658  let OpKey = key ## cls;
2659  let OpType = "mem";
2660  let mayLoad = 1;
2661  let Has20BitOffset = 1;
2662  let HasIndex = 1;
2663  let AccessBytes = bytes;
2664}
2665
2666// Like UnaryRR, but expanded after RA depending on the choice of registers.
2667class UnaryRRPseudo<string key, SDPatternOperator operator,
2668                    RegisterOperand cls1, RegisterOperand cls2>
2669  : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
2670           [(set cls1:$R1, (operator cls2:$R2))]> {
2671  let OpKey = key ## cls1;
2672  let OpType = "reg";
2673}
2674
2675// Like BinaryRI, but expanded after RA depending on the choice of register.
2676class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2677                     Immediate imm>
2678  : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
2679           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2680  let Constraints = "$R1 = $R1src";
2681}
2682
2683// Like BinaryRIE, but expanded after RA depending on the choice of register.
2684class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
2685                      Immediate imm>
2686  : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
2687           [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2688
2689// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
2690multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
2691                              RegisterOperand cls, Immediate imm> {
2692  let NumOpsKey = key in {
2693    let NumOpsValue = "3" in
2694      def K : BinaryRIEPseudo<null_frag, cls, imm>,
2695              Requires<[FeatureHighWord, FeatureDistinctOps]>;
2696    let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
2697      def "" : BinaryRIPseudo<operator, cls, imm>,
2698               Requires<[FeatureHighWord]>;
2699  }
2700}
2701
2702// Like CompareRI, but expanded after RA depending on the choice of register.
2703class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
2704                      Immediate imm>
2705  : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
2706
2707// Like CompareRXY, but expanded after RA depending on the choice of register.
2708class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2709                       SDPatternOperator load, bits<5> bytes,
2710                       AddressingMode mode = bdxaddr20only>
2711  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2712           [(operator cls:$R1, (load mode:$XBD2))]> {
2713  let mayLoad = 1;
2714  let Has20BitOffset = 1;
2715  let HasIndex = 1;
2716  let AccessBytes = bytes;
2717}
2718
2719// Like StoreRXY, but expanded after RA depending on the choice of register.
2720class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
2721                     bits<5> bytes, AddressingMode mode = bdxaddr20only>
2722  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
2723           [(operator cls:$R1, mode:$XBD2)]> {
2724  let mayStore = 1;
2725  let Has20BitOffset = 1;
2726  let HasIndex = 1;
2727  let AccessBytes = bytes;
2728}
2729
2730// Like RotateSelectRIEf, but expanded after RA depending on the choice
2731// of registers.
2732class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
2733  : Pseudo<(outs cls1:$R1),
2734           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2735                imm32zx6:$I5),
2736           []> {
2737  let Constraints = "$R1 = $R1src";
2738  let DisableEncoding = "$R1src";
2739}
2740
2741// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
2742// the value of the PSW's 2-bit condition code field.
2743class SelectWrapper<RegisterOperand cls>
2744  : Pseudo<(outs cls:$dst),
2745           (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
2746           [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2,
2747                                            imm32zx4:$valid, imm32zx4:$cc))]> {
2748  let usesCustomInserter = 1;
2749  // Although the instructions used by these nodes do not in themselves
2750  // change CC, the insertion requires new blocks, and CC cannot be live
2751  // across them.
2752  let Defs = [CC];
2753  let Uses = [CC];
2754}
2755
2756// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
2757multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
2758                      SDPatternOperator load, AddressingMode mode> {
2759  let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
2760    def "" : Pseudo<(outs),
2761                    (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2762                    [(store (z_select_ccmask cls:$new, (load mode:$addr),
2763                                             imm32zx4:$valid, imm32zx4:$cc),
2764                            mode:$addr)]>;
2765    def Inv : Pseudo<(outs),
2766                     (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
2767                     [(store (z_select_ccmask (load mode:$addr), cls:$new,
2768                                              imm32zx4:$valid, imm32zx4:$cc),
2769                              mode:$addr)]>;
2770  }
2771}
2772
2773// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation.  PAT and OPERAND
2774// describe the second (non-memory) operand.
2775class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
2776                       dag pat, DAGOperand operand>
2777  : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
2778           [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
2779  let Defs = [CC];
2780  let Has20BitOffset = 1;
2781  let mayLoad = 1;
2782  let mayStore = 1;
2783  let usesCustomInserter = 1;
2784}
2785
2786// Specializations of AtomicLoadWBinary.
2787class AtomicLoadBinaryReg32<SDPatternOperator operator>
2788  : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
2789class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm>
2790  : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
2791class AtomicLoadBinaryReg64<SDPatternOperator operator>
2792  : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
2793class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm>
2794  : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
2795
2796// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation.  PAT and OPERAND
2797// describe the second (non-memory) operand.
2798class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
2799                        DAGOperand operand>
2800  : Pseudo<(outs GR32:$dst),
2801           (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
2802                ADDR32:$negbitshift, uimm32:$bitsize),
2803           [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
2804                                      ADDR32:$negbitshift, uimm32:$bitsize))]> {
2805  let Defs = [CC];
2806  let Has20BitOffset = 1;
2807  let mayLoad = 1;
2808  let mayStore = 1;
2809  let usesCustomInserter = 1;
2810}
2811
2812// Specializations of AtomicLoadWBinary.
2813class AtomicLoadWBinaryReg<SDPatternOperator operator>
2814  : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
2815class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm>
2816  : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
2817
2818// Define an instruction that operates on two fixed-length blocks of memory,
2819// and associated pseudo instructions for operating on blocks of any size.
2820// The Sequence form uses a straight-line sequence of instructions and
2821// the Loop form uses a loop of length-256 instructions followed by
2822// another instruction to handle the excess.
2823multiclass MemorySS<string mnemonic, bits<8> opcode,
2824                    SDPatternOperator sequence, SDPatternOperator loop> {
2825  def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
2826                                       bdaddr12only:$BD2),
2827                  mnemonic##"\t$BDL1, $BD2", []>;
2828  let usesCustomInserter = 1 in {
2829    def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2830                                       imm64:$length),
2831                           [(sequence bdaddr12only:$dest, bdaddr12only:$src,
2832                                      imm64:$length)]>;
2833    def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
2834                                   imm64:$length, GR64:$count256),
2835                      [(loop bdaddr12only:$dest, bdaddr12only:$src,
2836                             imm64:$length, GR64:$count256)]>;
2837  }
2838}
2839
2840// Define an instruction that operates on two strings, both terminated
2841// by the character in R0.  The instruction processes a CPU-determinated
2842// number of bytes at a time and sets CC to 3 if the instruction needs
2843// to be repeated.  Also define a pseudo instruction that represents
2844// the full loop (the main instruction plus the branch on CC==3).
2845multiclass StringRRE<string mnemonic, bits<16> opcode,
2846                     SDPatternOperator operator> {
2847  def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
2848                   (ins GR64:$R1src, GR64:$R2src),
2849                   mnemonic#"\t$R1, $R2", []> {
2850    let Uses = [R0L];
2851    let Constraints = "$R1 = $R1src, $R2 = $R2src";
2852    let DisableEncoding = "$R1src, $R2src";
2853  }
2854  let usesCustomInserter = 1 in
2855    def Loop : Pseudo<(outs GR64:$end),
2856                      (ins GR64:$start1, GR64:$start2, GR32:$char),
2857                      [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
2858                                                 GR32:$char))]>;
2859}
2860
2861// A pseudo instruction that is a direct alias of a real instruction.
2862// These aliases are used in cases where a particular register operand is
2863// fixed or where the same instruction is used with different register sizes.
2864// The size parameter is the size in bytes of the associated real instruction.
2865class Alias<int size, dag outs, dag ins, list<dag> pattern>
2866  : InstSystemZ<size, outs, ins, "", pattern> {
2867  let isPseudo = 1;
2868  let isCodeGenOnly = 1;
2869}
2870
2871class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
2872 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
2873
2874// An alias of a UnaryVRR*, but with different register sizes.
2875class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
2876  : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
2877          [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;
2878
2879// An alias of a UnaryVRX, but with different register sizes.
2880class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
2881                    AddressingMode mode = bdxaddr12only>
2882  : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
2883          [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>;
2884
2885// An alias of a StoreVRX, but with different register sizes.
2886class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
2887                    AddressingMode mode = bdxaddr12only>
2888  : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
2889          [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
2890
2891// An alias of a BinaryRI, but with different register sizes.
2892class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
2893                    Immediate imm>
2894  : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2895          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2896  let Constraints = "$R1 = $R1src";
2897}
2898
2899// An alias of a BinaryRIL, but with different register sizes.
2900class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
2901                     Immediate imm>
2902  : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2903          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2904  let Constraints = "$R1 = $R1src";
2905}
2906
2907// An alias of a BinaryVRRf, but with different register sizes.
2908class BinaryAliasVRRf<RegisterOperand cls>
2909  : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
2910
2911// An alias of a CompareRI, but with different register sizes.
2912class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
2913                     Immediate imm>
2914  : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {
2915  let isCompare = 1;
2916}
2917
2918// An alias of a RotateSelectRIEf, but with different register sizes.
2919class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
2920  : Alias<6, (outs cls1:$R1),
2921          (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
2922               imm32zx6:$I5), []> {
2923  let Constraints = "$R1 = $R1src";
2924}
2925