1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// TODO: Most floating-point instructions (except for simple moves and the 11// like) can raise exceptions -- should they have hasSideEffects=1 ? 12 13//===----------------------------------------------------------------------===// 14// Select instructions 15//===----------------------------------------------------------------------===// 16 17// C's ?: operator for floating-point operands. 18def SelectF32 : SelectWrapper<f32, FP32>; 19def SelectF64 : SelectWrapper<f64, FP64>; 20let Predicates = [FeatureNoVectorEnhancements1] in 21 def SelectF128 : SelectWrapper<f128, FP128>; 22let Predicates = [FeatureVectorEnhancements1] in 23 def SelectVR128 : SelectWrapper<f128, VR128>; 24 25defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 26 nonvolatile_load, bdxaddr20only>; 27defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 28 nonvolatile_load, bdxaddr20only>; 29 30//===----------------------------------------------------------------------===// 31// Move instructions 32//===----------------------------------------------------------------------===// 33 34// Load zero. 35let isAsCheapAsAMove = 1, isMoveImm = 1 in { 36 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>; 37 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>; 38 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>; 39} 40 41// Moves between two floating-point registers. 42def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>; 43def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>; 44def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>; 45 46// For z13 we prefer LDR over LER to avoid partial register dependencies. 47let isCodeGenOnly = 1 in 48 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>; 49 50// Moves between two floating-point registers that also set the condition 51// codes. 52let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 53 defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>; 54 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>; 55 defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>; 56} 57// Note that LTxBRCompare is not available if we have vector support, 58// since load-and-test instructions will partially clobber the target 59// (vector) register. 60let Predicates = [FeatureNoVector] in { 61 defm : CompareZeroFP<LTEBRCompare, FP32>; 62 defm : CompareZeroFP<LTDBRCompare, FP64>; 63 defm : CompareZeroFP<LTXBRCompare, FP128>; 64} 65 66// Use a normal load-and-test for compare against zero in case of 67// vector support (via a pseudo to simplify instruction selection). 68let Defs = [CC], usesCustomInserter = 1 in { 69 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; 70 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; 71 def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; 72} 73let Predicates = [FeatureVector] in { 74 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>; 75 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>; 76} 77let Predicates = [FeatureVector, FeatureNoVectorEnhancements1] in 78 defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>; 79 80// Moves between 64-bit integer and floating-point registers. 81def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; 82def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; 83 84// fcopysign with an FP32 result. 85let isCodeGenOnly = 1 in { 86 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>; 87 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>; 88} 89 90// The sign of an FP128 is in the high register. 91let Predicates = [FeatureNoVectorEnhancements1] in 92 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))), 93 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 94let Predicates = [FeatureVectorEnhancements1] in 95 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))), 96 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_r64))>; 97 98// fcopysign with an FP64 result. 99let isCodeGenOnly = 1 in 100 def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>; 101def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>; 102 103// The sign of an FP128 is in the high register. 104let Predicates = [FeatureNoVectorEnhancements1] in 105 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))), 106 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 107let Predicates = [FeatureVectorEnhancements1] in 108 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))), 109 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_r64))>; 110 111// fcopysign with an FP128 result. Use "upper" as the high half and leave 112// the low half as-is. 113class CopySign128<RegisterOperand cls, dag upper> 114 : Pat<(fcopysign FP128:$src1, cls:$src2), 115 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 116 117let Predicates = [FeatureNoVectorEnhancements1] in { 118 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 119 FP32:$src2)>; 120 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 121 FP64:$src2)>; 122 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 123 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 124} 125 126defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 127defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 128defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 129 130//===----------------------------------------------------------------------===// 131// Load instructions 132//===----------------------------------------------------------------------===// 133 134let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 135 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 136 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 137 138 // For z13 we prefer LDE over LE to avoid partial register dependencies. 139 let isCodeGenOnly = 1 in 140 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>; 141 142 // These instructions are split after register allocation, so we don't 143 // want a custom inserter. 144 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 145 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 146 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 147 } 148} 149 150//===----------------------------------------------------------------------===// 151// Store instructions 152//===----------------------------------------------------------------------===// 153 154let SimpleBDXStore = 1, mayStore = 1 in { 155 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 156 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 157 158 // These instructions are split after register allocation, so we don't 159 // want a custom inserter. 160 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 161 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 162 [(store FP128:$src, bdxaddr20only128:$dst)]>; 163 } 164} 165 166//===----------------------------------------------------------------------===// 167// Conversion instructions 168//===----------------------------------------------------------------------===// 169 170// Convert floating-point values to narrower representations, rounding 171// according to the current mode. The destination of LEXBR and LDXBR 172// is a 128-bit value, but only the first register of the pair is used. 173def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround, FP32, FP64>; 174def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>; 175def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>; 176 177def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>, 178 Requires<[FeatureFPExtension]>; 179def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>, 180 Requires<[FeatureFPExtension]>; 181def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>, 182 Requires<[FeatureFPExtension]>; 183 184let Predicates = [FeatureNoVectorEnhancements1] in { 185 def : Pat<(f32 (fpround FP128:$src)), 186 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>; 187 def : Pat<(f64 (fpround FP128:$src)), 188 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 189} 190 191// Extend register floating-point values to wider representations. 192def LDEBR : UnaryRRE<"ldebr", 0xB304, fpextend, FP64, FP32>; 193def LXEBR : UnaryRRE<"lxebr", 0xB306, null_frag, FP128, FP32>; 194def LXDBR : UnaryRRE<"lxdbr", 0xB305, null_frag, FP128, FP64>; 195let Predicates = [FeatureNoVectorEnhancements1] in { 196 def : Pat<(f128 (fpextend (f32 FP32:$src))), (LXEBR FP32:$src)>; 197 def : Pat<(f128 (fpextend (f64 FP64:$src))), (LXDBR FP64:$src)>; 198} 199 200// Extend memory floating-point values to wider representations. 201def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 202def LXEB : UnaryRXE<"lxeb", 0xED06, null_frag, FP128, 4>; 203def LXDB : UnaryRXE<"lxdb", 0xED05, null_frag, FP128, 8>; 204let Predicates = [FeatureNoVectorEnhancements1] in { 205 def : Pat<(f128 (extloadf32 bdxaddr12only:$src)), 206 (LXEB bdxaddr12only:$src)>; 207 def : Pat<(f128 (extloadf64 bdxaddr12only:$src)), 208 (LXDB bdxaddr12only:$src)>; 209} 210 211// Convert a signed integer register value to a floating-point one. 212def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>; 213def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>; 214def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>; 215 216def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>; 217def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>; 218def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>; 219 220// The FP extension feature provides versions of the above that allow 221// specifying rounding mode and inexact-exception suppression flags. 222let Predicates = [FeatureFPExtension] in { 223 def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>; 224 def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>; 225 def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>; 226 227 def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>; 228 def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>; 229 def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>; 230} 231 232// Convert am unsigned integer register value to a floating-point one. 233let Predicates = [FeatureFPExtension] in { 234 def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>; 235 def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>; 236 def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>; 237 238 def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>; 239 def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>; 240 def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>; 241 242 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 243 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 244 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 245 246 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 247 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 248 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 249} 250 251// Convert a floating-point register value to a signed integer value, 252// with the second operand (modifier M3) specifying the rounding mode. 253let Defs = [CC] in { 254 def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>; 255 def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>; 256 def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>; 257 258 def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>; 259 def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>; 260 def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>; 261} 262 263// fp_to_sint always rounds towards zero, which is modifier value 5. 264def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 265def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 266def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 267 268def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 269def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 270def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 271 272// The FP extension feature provides versions of the above that allow 273// also specifying the inexact-exception suppression flag. 274let Predicates = [FeatureFPExtension], Defs = [CC] in { 275 def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>; 276 def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>; 277 def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>; 278 279 def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>; 280 def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>; 281 def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>; 282} 283 284// Convert a floating-point register value to an unsigned integer value. 285let Predicates = [FeatureFPExtension] in { 286 let Defs = [CC] in { 287 def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>; 288 def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>; 289 def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>; 290 291 def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>; 292 def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>; 293 def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>; 294 } 295 296 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 297 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 298 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 299 300 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 301 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 302 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 303} 304 305 306//===----------------------------------------------------------------------===// 307// Unary arithmetic 308//===----------------------------------------------------------------------===// 309 310// We prefer generic instructions during isel, because they do not 311// clobber CC and therefore give the scheduler more freedom. In cases 312// the CC is actually useful, the SystemZElimCompare pass will try to 313// convert generic instructions into opcodes that also set CC. Note 314// that lcdf / lpdf / lndf only affect the sign bit, and can therefore 315// be used with fp32 as well. This could be done for fp128, in which 316// case the operands would have to be tied. 317 318// Negation (Load Complement). 319let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 320 def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>; 321 def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>; 322 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>; 323} 324// Generic form, which does not set CC. 325def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>; 326let isCodeGenOnly = 1 in 327 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>; 328 329// Absolute value (Load Positive). 330let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 331 def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>; 332 def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>; 333 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>; 334} 335// Generic form, which does not set CC. 336def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>; 337let isCodeGenOnly = 1 in 338 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>; 339 340// Negative absolute value (Load Negative). 341let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 342 def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>; 343 def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>; 344 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>; 345} 346// Generic form, which does not set CC. 347def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>; 348let isCodeGenOnly = 1 in 349 def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>; 350 351// Square root. 352def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>; 353def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>; 354def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>; 355 356def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 357def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 358 359// Round to an integer, with the second operand (modifier M3) specifying 360// the rounding mode. These forms always check for inexact conditions. 361def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>; 362def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>; 363def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>; 364 365// frint rounds according to the current mode (modifier 0) and detects 366// inexact conditions. 367def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 368def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 369def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 370 371let Predicates = [FeatureFPExtension] in { 372 // Extended forms of the FIxBR instructions. M4 can be set to 4 373 // to suppress detection of inexact conditions. 374 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>; 375 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>; 376 def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>; 377 378 // fnearbyint is like frint but does not detect inexact conditions. 379 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 380 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 381 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 382 383 // floor is no longer allowed to raise an inexact condition, 384 // so restrict it to the cases where the condition can be suppressed. 385 // Mode 7 is round towards -inf. 386 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 387 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 388 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 389 390 // Same idea for ceil, where mode 6 is round towards +inf. 391 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 392 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 393 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 394 395 // Same idea for trunc, where mode 5 is round towards zero. 396 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 397 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 398 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 399 400 // Same idea for round, where mode 1 is round towards nearest with 401 // ties away from zero. 402 def : Pat<(fround FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 403 def : Pat<(fround FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 404 def : Pat<(fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 405} 406 407//===----------------------------------------------------------------------===// 408// Binary arithmetic 409//===----------------------------------------------------------------------===// 410 411// Addition. 412let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 413 let isCommutable = 1 in { 414 def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>; 415 def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>; 416 def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>; 417 } 418 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 419 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 420} 421 422// Subtraction. 423let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 424 def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>; 425 def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>; 426 def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>; 427 428 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 429 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 430} 431 432// Multiplication. 433let isCommutable = 1 in { 434 def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>; 435 def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>; 436 def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>; 437} 438def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 439def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 440 441// f64 multiplication of two FP32 registers. 442def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; 443def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (fpextend FP32:$src2))), 444 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 445 FP32:$src1, subreg_r32), FP32:$src2)>; 446 447// f64 multiplication of an FP32 register and an f32 memory. 448def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 449def : Pat<(fmul (f64 (fpextend FP32:$src1)), 450 (f64 (extloadf32 bdxaddr12only:$addr))), 451 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32), 452 bdxaddr12only:$addr)>; 453 454// f128 multiplication of two FP64 registers. 455def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>; 456let Predicates = [FeatureNoVectorEnhancements1] in 457 def : Pat<(fmul (f128 (fpextend FP64:$src1)), (f128 (fpextend FP64:$src2))), 458 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 459 FP64:$src1, subreg_h64), FP64:$src2)>; 460 461// f128 multiplication of an FP64 register and an f64 memory. 462def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 463let Predicates = [FeatureNoVectorEnhancements1] in 464 def : Pat<(fmul (f128 (fpextend FP64:$src1)), 465 (f128 (extloadf64 bdxaddr12only:$addr))), 466 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 467 bdxaddr12only:$addr)>; 468 469// Fused multiply-add. 470def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32, FP32>; 471def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64, FP64>; 472 473def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, FP32, load, 4>; 474def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, FP64, load, 8>; 475 476// Fused multiply-subtract. 477def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32, FP32>; 478def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64, FP64>; 479 480def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, FP32, load, 4>; 481def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, FP64, load, 8>; 482 483// Division. 484def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>; 485def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>; 486def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>; 487 488def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 489def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 490 491// Divide to integer. 492let Defs = [CC] in { 493 def DIEBR : TernaryRRFb<"diebr", 0xB353, FP32, FP32, FP32>; 494 def DIDBR : TernaryRRFb<"didbr", 0xB35B, FP64, FP64, FP64>; 495} 496 497//===----------------------------------------------------------------------===// 498// Comparisons 499//===----------------------------------------------------------------------===// 500 501let Defs = [CC], CCValues = 0xF in { 502 def CEBR : CompareRRE<"cebr", 0xB309, z_fcmp, FP32, FP32>; 503 def CDBR : CompareRRE<"cdbr", 0xB319, z_fcmp, FP64, FP64>; 504 def CXBR : CompareRRE<"cxbr", 0xB349, z_fcmp, FP128, FP128>; 505 506 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 507 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 508 509 def KEBR : CompareRRE<"kebr", 0xB308, null_frag, FP32, FP32>; 510 def KDBR : CompareRRE<"kdbr", 0xB318, null_frag, FP64, FP64>; 511 def KXBR : CompareRRE<"kxbr", 0xB348, null_frag, FP128, FP128>; 512 513 def KEB : CompareRXE<"keb", 0xED08, null_frag, FP32, load, 4>; 514 def KDB : CompareRXE<"kdb", 0xED18, null_frag, FP64, load, 8>; 515} 516 517// Test Data Class. 518let Defs = [CC], CCValues = 0xC in { 519 def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>; 520 def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>; 521 def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>; 522} 523 524//===----------------------------------------------------------------------===// 525// Floating-point control register instructions 526//===----------------------------------------------------------------------===// 527 528let hasSideEffects = 1 in { 529 let mayLoad = 1, mayStore = 1 in { 530 // TODO: EFPC and SFPC do not touch memory at all 531 def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>; 532 def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>; 533 534 def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>; 535 def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>; 536 } 537 538 def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>; 539 def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>; 540 541 def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>, 542 Requires<[FeatureFPExtension]>; 543 def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>; 544 def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>; 545} 546 547//===----------------------------------------------------------------------===// 548// Peepholes 549//===----------------------------------------------------------------------===// 550 551def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>; 552def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>; 553def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 554