1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Select instructions
12//===----------------------------------------------------------------------===//
13
14// C's ?: operator for floating-point operands.
15def SelectF32  : SelectWrapper<FP32>;
16def SelectF64  : SelectWrapper<FP64>;
17def SelectF128 : SelectWrapper<FP128>;
18
19defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
20                               nonvolatile_load, bdxaddr20only>;
21defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
22                               nonvolatile_load, bdxaddr20only>;
23
24//===----------------------------------------------------------------------===//
25// Move instructions
26//===----------------------------------------------------------------------===//
27
28// Load zero.
29let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in {
30  def LZER : InherentRRE<"lzer", 0xB374, FP32,  (fpimm0)>;
31  def LZDR : InherentRRE<"lzdr", 0xB375, FP64,  (fpimm0)>;
32  def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
33}
34
35// Moves between two floating-point registers.
36let hasSideEffects = 0 in {
37  def LER : UnaryRR <"le", 0x38,   null_frag, FP32,  FP32>;
38  def LDR : UnaryRR <"ld", 0x28,   null_frag, FP64,  FP64>;
39  def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
40}
41
42// Moves between two floating-point registers that also set the condition
43// codes.
44let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
45  defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
46  defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
47  defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
48}
49// Note that the comparison against zero operation is not available if we
50// have vector support, since load-and-test instructions will partially
51// clobber the target (vector) register.
52let Predicates = [FeatureNoVector] in {
53  defm : CompareZeroFP<LTEBRCompare, FP32>;
54  defm : CompareZeroFP<LTDBRCompare, FP64>;
55  defm : CompareZeroFP<LTXBRCompare, FP128>;
56}
57
58// Moves between 64-bit integer and floating-point registers.
59def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
60def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
61
62// fcopysign with an FP32 result.
63let isCodeGenOnly = 1 in {
64  def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
65  def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
66}
67
68// The sign of an FP128 is in the high register.
69def : Pat<(fcopysign FP32:$src1, FP128:$src2),
70          (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
71
72// fcopysign with an FP64 result.
73let isCodeGenOnly = 1 in
74  def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
75def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
76
77// The sign of an FP128 is in the high register.
78def : Pat<(fcopysign FP64:$src1, FP128:$src2),
79          (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
80
81// fcopysign with an FP128 result.  Use "upper" as the high half and leave
82// the low half as-is.
83class CopySign128<RegisterOperand cls, dag upper>
84  : Pat<(fcopysign FP128:$src1, cls:$src2),
85        (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
86
87def : CopySign128<FP32,  (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
88                                  FP32:$src2)>;
89def : CopySign128<FP64,  (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
90                                  FP64:$src2)>;
91def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
92                                  (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
93
94defm LoadStoreF32  : MVCLoadStore<load, f32,  MVCSequence, 4>;
95defm LoadStoreF64  : MVCLoadStore<load, f64,  MVCSequence, 8>;
96defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
97
98//===----------------------------------------------------------------------===//
99// Load instructions
100//===----------------------------------------------------------------------===//
101
102let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
103  defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
104  defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
105
106  // For z13 we prefer LDE over LE to avoid partial register dependencies.
107  def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;
108
109  // These instructions are split after register allocation, so we don't
110  // want a custom inserter.
111  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
112    def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
113                     [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
114  }
115}
116
117//===----------------------------------------------------------------------===//
118// Store instructions
119//===----------------------------------------------------------------------===//
120
121let SimpleBDXStore = 1 in {
122  defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
123  defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
124
125  // These instructions are split after register allocation, so we don't
126  // want a custom inserter.
127  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
128    def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
129                     [(store FP128:$src, bdxaddr20only128:$dst)]>;
130  }
131}
132
133//===----------------------------------------------------------------------===//
134// Conversion instructions
135//===----------------------------------------------------------------------===//
136
137// Convert floating-point values to narrower representations, rounding
138// according to the current mode.  The destination of LEXBR and LDXBR
139// is a 128-bit value, but only the first register of the pair is used.
140def LEDBR : UnaryRRE<"ledb", 0xB344, fround,    FP32,  FP64>;
141def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
142def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
143
144def LEDBRA : UnaryRRF4<"ledbra", 0xB344, FP32,  FP64>,
145             Requires<[FeatureFPExtension]>;
146def LEXBRA : UnaryRRF4<"lexbra", 0xB346, FP128, FP128>,
147             Requires<[FeatureFPExtension]>;
148def LDXBRA : UnaryRRF4<"ldxbra", 0xB345, FP128, FP128>,
149             Requires<[FeatureFPExtension]>;
150
151def : Pat<(f32 (fround FP128:$src)),
152          (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>;
153def : Pat<(f64 (fround FP128:$src)),
154          (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
155
156// Extend register floating-point values to wider representations.
157def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64,  FP32>;
158def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
159def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
160
161// Extend memory floating-point values to wider representations.
162def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64,  4>;
163def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
164def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
165
166// Convert a signed integer register value to a floating-point one.
167def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32,  GR32>;
168def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64,  GR32>;
169def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
170
171def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32,  GR64>;
172def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64,  GR64>;
173def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
174
175// Convert am unsigned integer register value to a floating-point one.
176let Predicates = [FeatureFPExtension] in {
177  def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32,  GR32>;
178  def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64,  GR32>;
179  def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>;
180
181  def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32,  GR64>;
182  def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64,  GR64>;
183  def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>;
184
185  def : Pat<(f32  (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
186  def : Pat<(f64  (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
187  def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
188
189  def : Pat<(f32  (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
190  def : Pat<(f64  (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
191  def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
192}
193
194// Convert a floating-point register value to a signed integer value,
195// with the second operand (modifier M3) specifying the rounding mode.
196let Defs = [CC] in {
197  def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
198  def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
199  def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
200
201  def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
202  def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
203  def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
204}
205
206// fp_to_sint always rounds towards zero, which is modifier value 5.
207def : Pat<(i32 (fp_to_sint FP32:$src)),  (CFEBR 5, FP32:$src)>;
208def : Pat<(i32 (fp_to_sint FP64:$src)),  (CFDBR 5, FP64:$src)>;
209def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
210
211def : Pat<(i64 (fp_to_sint FP32:$src)),  (CGEBR 5, FP32:$src)>;
212def : Pat<(i64 (fp_to_sint FP64:$src)),  (CGDBR 5, FP64:$src)>;
213def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
214
215// Convert a floating-point register value to an unsigned integer value.
216let Predicates = [FeatureFPExtension] in {
217  let Defs = [CC] in {
218    def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>;
219    def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>;
220    def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>;
221
222    def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>;
223    def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>;
224    def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>;
225  }
226
227  def : Pat<(i32 (fp_to_uint FP32:$src)),  (CLFEBR 5, FP32:$src,  0)>;
228  def : Pat<(i32 (fp_to_uint FP64:$src)),  (CLFDBR 5, FP64:$src,  0)>;
229  def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;
230
231  def : Pat<(i64 (fp_to_uint FP32:$src)),  (CLGEBR 5, FP32:$src,  0)>;
232  def : Pat<(i64 (fp_to_uint FP64:$src)),  (CLGDBR 5, FP64:$src,  0)>;
233  def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;
234}
235
236
237//===----------------------------------------------------------------------===//
238// Unary arithmetic
239//===----------------------------------------------------------------------===//
240
241// We prefer generic instructions during isel, because they do not
242// clobber CC and therefore give the scheduler more freedom. In cases
243// the CC is actually useful, the SystemZElimCompare pass will try to
244// convert generic instructions into opcodes that also set CC. Note
245// that lcdf / lpdf / lndf only affect the sign bit, and can therefore
246// be used with fp32 as well. This could be done for fp128, in which
247// case the operands would have to be tied.
248
249// Negation (Load Complement).
250let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
251  def LCEBR : UnaryRRE<"lceb", 0xB303, null_frag, FP32,  FP32>;
252  def LCDBR : UnaryRRE<"lcdb", 0xB313, null_frag, FP64,  FP64>;
253  def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
254}
255// Generic form, which does not set CC.
256def LCDFR : UnaryRRE<"lcdf", 0xB373, fneg, FP64,  FP64>;
257let isCodeGenOnly = 1 in
258  def LCDFR_32 : UnaryRRE<"lcdf", 0xB373, fneg, FP32,  FP32>;
259
260// Absolute value (Load Positive).
261let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
262  def LPEBR : UnaryRRE<"lpeb", 0xB300, null_frag, FP32,  FP32>;
263  def LPDBR : UnaryRRE<"lpdb", 0xB310, null_frag, FP64,  FP64>;
264  def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
265}
266// Generic form, which does not set CC.
267def LPDFR : UnaryRRE<"lpdf", 0xB370, fabs, FP64,  FP64>;
268let isCodeGenOnly = 1 in
269  def LPDFR_32 : UnaryRRE<"lpdf", 0xB370, fabs, FP32,  FP32>;
270
271// Negative absolute value (Load Negative).
272let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
273  def LNEBR : UnaryRRE<"lneb", 0xB301, null_frag, FP32,  FP32>;
274  def LNDBR : UnaryRRE<"lndb", 0xB311, null_frag, FP64,  FP64>;
275  def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
276}
277// Generic form, which does not set CC.
278def LNDFR : UnaryRRE<"lndf", 0xB371, fnabs, FP64,  FP64>;
279let isCodeGenOnly = 1 in
280  def LNDFR_32 : UnaryRRE<"lndf", 0xB371, fnabs, FP32,  FP32>;
281
282// Square root.
283def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32,  FP32>;
284def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64,  FP64>;
285def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
286
287def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
288def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
289
290// Round to an integer, with the second operand (modifier M3) specifying
291// the rounding mode.  These forms always check for inexact conditions.
292def FIEBR : UnaryRRF<"fieb", 0xB357, FP32,  FP32>;
293def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64,  FP64>;
294def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
295
296// frint rounds according to the current mode (modifier 0) and detects
297// inexact conditions.
298def : Pat<(frint FP32:$src),  (FIEBR 0, FP32:$src)>;
299def : Pat<(frint FP64:$src),  (FIDBR 0, FP64:$src)>;
300def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
301
302let Predicates = [FeatureFPExtension] in {
303  // Extended forms of the FIxBR instructions.  M4 can be set to 4
304  // to suppress detection of inexact conditions.
305  def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32,  FP32>;
306  def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64,  FP64>;
307  def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
308
309  // fnearbyint is like frint but does not detect inexact conditions.
310  def : Pat<(fnearbyint FP32:$src),  (FIEBRA 0, FP32:$src,  4)>;
311  def : Pat<(fnearbyint FP64:$src),  (FIDBRA 0, FP64:$src,  4)>;
312  def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
313
314  // floor is no longer allowed to raise an inexact condition,
315  // so restrict it to the cases where the condition can be suppressed.
316  // Mode 7 is round towards -inf.
317  def : Pat<(ffloor FP32:$src),  (FIEBRA 7, FP32:$src,  4)>;
318  def : Pat<(ffloor FP64:$src),  (FIDBRA 7, FP64:$src,  4)>;
319  def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
320
321  // Same idea for ceil, where mode 6 is round towards +inf.
322  def : Pat<(fceil FP32:$src),  (FIEBRA 6, FP32:$src,  4)>;
323  def : Pat<(fceil FP64:$src),  (FIDBRA 6, FP64:$src,  4)>;
324  def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
325
326  // Same idea for trunc, where mode 5 is round towards zero.
327  def : Pat<(ftrunc FP32:$src),  (FIEBRA 5, FP32:$src,  4)>;
328  def : Pat<(ftrunc FP64:$src),  (FIDBRA 5, FP64:$src,  4)>;
329  def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
330
331  // Same idea for round, where mode 1 is round towards nearest with
332  // ties away from zero.
333  def : Pat<(frnd FP32:$src),  (FIEBRA 1, FP32:$src,  4)>;
334  def : Pat<(frnd FP64:$src),  (FIDBRA 1, FP64:$src,  4)>;
335  def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
336}
337
338//===----------------------------------------------------------------------===//
339// Binary arithmetic
340//===----------------------------------------------------------------------===//
341
342// Addition.
343let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
344  let isCommutable = 1 in {
345    def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32,  FP32>;
346    def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64,  FP64>;
347    def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
348  }
349  def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
350  def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
351}
352
353// Subtraction.
354let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
355  def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32,  FP32>;
356  def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64,  FP64>;
357  def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
358
359  def SEB : BinaryRXE<"seb",  0xED0B, fsub, FP32, load, 4>;
360  def SDB : BinaryRXE<"sdb",  0xED1B, fsub, FP64, load, 8>;
361}
362
363// Multiplication.
364let isCommutable = 1 in {
365  def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32,  FP32>;
366  def MDBR  : BinaryRRE<"mdb",  0xB31C, fmul, FP64,  FP64>;
367  def MXBR  : BinaryRRE<"mxb",  0xB34C, fmul, FP128, FP128>;
368}
369def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
370def MDB  : BinaryRXE<"mdb",  0xED1C, fmul, FP64, load, 8>;
371
372// f64 multiplication of two FP32 registers.
373def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
374def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
375          (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
376                                FP32:$src1, subreg_r32), FP32:$src2)>;
377
378// f64 multiplication of an FP32 register and an f32 memory.
379def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
380def : Pat<(fmul (f64 (fextend FP32:$src1)),
381                (f64 (extloadf32 bdxaddr12only:$addr))),
382          (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32),
383                bdxaddr12only:$addr)>;
384
385// f128 multiplication of two FP64 registers.
386def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
387def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
388          (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
389                                FP64:$src1, subreg_h64), FP64:$src2)>;
390
391// f128 multiplication of an FP64 register and an f64 memory.
392def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
393def : Pat<(fmul (f128 (fextend FP64:$src1)),
394                (f128 (extloadf64 bdxaddr12only:$addr))),
395          (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
396                bdxaddr12only:$addr)>;
397
398// Fused multiply-add.
399def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
400def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
401
402def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
403def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
404
405// Fused multiply-subtract.
406def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
407def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
408
409def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
410def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
411
412// Division.
413def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32,  FP32>;
414def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64,  FP64>;
415def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
416
417def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
418def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
419
420//===----------------------------------------------------------------------===//
421// Comparisons
422//===----------------------------------------------------------------------===//
423
424let Defs = [CC], CCValues = 0xF in {
425  def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32,  FP32>;
426  def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64,  FP64>;
427  def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
428
429  def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
430  def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
431}
432
433//===----------------------------------------------------------------------===//
434// Peepholes
435//===----------------------------------------------------------------------===//
436
437def : Pat<(f32  fpimmneg0), (LCDFR_32 (LZER))>;
438def : Pat<(f64  fpimmneg0), (LCDFR (LZDR))>;
439def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
440