1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Select instructions 12//===----------------------------------------------------------------------===// 13 14// C's ?: operator for floating-point operands. 15def SelectF32 : SelectWrapper<FP32>; 16def SelectF64 : SelectWrapper<FP64>; 17def SelectF128 : SelectWrapper<FP128>; 18 19defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 20 nonvolatile_load, bdxaddr20only>; 21defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 22 nonvolatile_load, bdxaddr20only>; 23 24//===----------------------------------------------------------------------===// 25// Move instructions 26//===----------------------------------------------------------------------===// 27 28// Load zero. 29let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in { 30 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>; 31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>; 32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>; 33} 34 35// Moves between two floating-point registers. 36let hasSideEffects = 0 in { 37 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>; 38 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>; 39 def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>; 40 41 // For z13 we prefer LDR over LER to avoid partial register dependencies. 42 let isCodeGenOnly = 1 in 43 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>; 44} 45 46// Moves between two floating-point registers that also set the condition 47// codes. 48let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 49 defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>; 50 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>; 51 defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>; 52} 53// Note that LTxBRCompare is not available if we have vector support, 54// since load-and-test instructions will partially clobber the target 55// (vector) register. 56let Predicates = [FeatureNoVector] in { 57 defm : CompareZeroFP<LTEBRCompare, FP32>; 58 defm : CompareZeroFP<LTDBRCompare, FP64>; 59 defm : CompareZeroFP<LTXBRCompare, FP128>; 60} 61 62// Use a normal load-and-test for compare against zero in case of 63// vector support (via a pseudo to simplify instruction selection). 64let Defs = [CC], usesCustomInserter = 1 in { 65 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; 66 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; 67 def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; 68} 69let Predicates = [FeatureVector] in { 70 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>; 71 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>; 72 defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>; 73} 74 75// Moves between 64-bit integer and floating-point registers. 76def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; 77def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; 78 79// fcopysign with an FP32 result. 80let isCodeGenOnly = 1 in { 81 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>; 82 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>; 83} 84 85// The sign of an FP128 is in the high register. 86def : Pat<(fcopysign FP32:$src1, FP128:$src2), 87 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 88 89// fcopysign with an FP64 result. 90let isCodeGenOnly = 1 in 91 def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>; 92def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>; 93 94// The sign of an FP128 is in the high register. 95def : Pat<(fcopysign FP64:$src1, FP128:$src2), 96 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 97 98// fcopysign with an FP128 result. Use "upper" as the high half and leave 99// the low half as-is. 100class CopySign128<RegisterOperand cls, dag upper> 101 : Pat<(fcopysign FP128:$src1, cls:$src2), 102 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 103 104def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 105 FP32:$src2)>; 106def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 107 FP64:$src2)>; 108def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 109 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 110 111defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 112defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 113defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 114 115//===----------------------------------------------------------------------===// 116// Load instructions 117//===----------------------------------------------------------------------===// 118 119let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 120 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 121 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 122 123 // For z13 we prefer LDE over LE to avoid partial register dependencies. 124 let isCodeGenOnly = 1 in 125 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>; 126 127 // These instructions are split after register allocation, so we don't 128 // want a custom inserter. 129 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 130 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 131 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 132 } 133} 134 135//===----------------------------------------------------------------------===// 136// Store instructions 137//===----------------------------------------------------------------------===// 138 139let SimpleBDXStore = 1 in { 140 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 141 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 142 143 // These instructions are split after register allocation, so we don't 144 // want a custom inserter. 145 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 146 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 147 [(store FP128:$src, bdxaddr20only128:$dst)]>; 148 } 149} 150 151//===----------------------------------------------------------------------===// 152// Conversion instructions 153//===----------------------------------------------------------------------===// 154 155// Convert floating-point values to narrower representations, rounding 156// according to the current mode. The destination of LEXBR and LDXBR 157// is a 128-bit value, but only the first register of the pair is used. 158def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround, FP32, FP64>; 159def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>; 160def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>; 161 162def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>, 163 Requires<[FeatureFPExtension]>; 164def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>, 165 Requires<[FeatureFPExtension]>; 166def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>, 167 Requires<[FeatureFPExtension]>; 168 169def : Pat<(f32 (fpround FP128:$src)), 170 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>; 171def : Pat<(f64 (fpround FP128:$src)), 172 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 173 174// Extend register floating-point values to wider representations. 175def LDEBR : UnaryRRE<"ldebr", 0xB304, fpextend, FP64, FP32>; 176def LXEBR : UnaryRRE<"lxebr", 0xB306, fpextend, FP128, FP32>; 177def LXDBR : UnaryRRE<"lxdbr", 0xB305, fpextend, FP128, FP64>; 178 179// Extend memory floating-point values to wider representations. 180def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 181def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>; 182def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>; 183 184// Convert a signed integer register value to a floating-point one. 185def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>; 186def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>; 187def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>; 188 189def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>; 190def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>; 191def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>; 192 193// The FP extension feature provides versions of the above that allow 194// specifying rounding mode and inexact-exception suppression flags. 195let Predicates = [FeatureFPExtension] in { 196 def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>; 197 def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>; 198 def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>; 199 200 def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>; 201 def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>; 202 def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>; 203} 204 205// Convert am unsigned integer register value to a floating-point one. 206let Predicates = [FeatureFPExtension] in { 207 def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>; 208 def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>; 209 def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>; 210 211 def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>; 212 def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>; 213 def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>; 214 215 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 216 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 217 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 218 219 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 220 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 221 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 222} 223 224// Convert a floating-point register value to a signed integer value, 225// with the second operand (modifier M3) specifying the rounding mode. 226let Defs = [CC] in { 227 def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>; 228 def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>; 229 def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>; 230 231 def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>; 232 def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>; 233 def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>; 234} 235 236// fp_to_sint always rounds towards zero, which is modifier value 5. 237def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 238def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 239def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 240 241def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 242def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 243def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 244 245// The FP extension feature provides versions of the above that allow 246// also specifying the inexact-exception suppression flag. 247let Predicates = [FeatureFPExtension], Defs = [CC] in { 248 def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>; 249 def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>; 250 def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>; 251 252 def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>; 253 def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>; 254 def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>; 255} 256 257// Convert a floating-point register value to an unsigned integer value. 258let Predicates = [FeatureFPExtension] in { 259 let Defs = [CC] in { 260 def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>; 261 def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>; 262 def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>; 263 264 def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>; 265 def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>; 266 def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>; 267 } 268 269 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 270 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 271 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 272 273 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 274 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 275 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 276} 277 278 279//===----------------------------------------------------------------------===// 280// Unary arithmetic 281//===----------------------------------------------------------------------===// 282 283// We prefer generic instructions during isel, because they do not 284// clobber CC and therefore give the scheduler more freedom. In cases 285// the CC is actually useful, the SystemZElimCompare pass will try to 286// convert generic instructions into opcodes that also set CC. Note 287// that lcdf / lpdf / lndf only affect the sign bit, and can therefore 288// be used with fp32 as well. This could be done for fp128, in which 289// case the operands would have to be tied. 290 291// Negation (Load Complement). 292let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 293 def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>; 294 def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>; 295 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>; 296} 297// Generic form, which does not set CC. 298def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>; 299let isCodeGenOnly = 1 in 300 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>; 301 302// Absolute value (Load Positive). 303let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 304 def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>; 305 def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>; 306 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>; 307} 308// Generic form, which does not set CC. 309def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>; 310let isCodeGenOnly = 1 in 311 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>; 312 313// Negative absolute value (Load Negative). 314let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 315 def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>; 316 def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>; 317 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>; 318} 319// Generic form, which does not set CC. 320def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>; 321let isCodeGenOnly = 1 in 322 def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>; 323 324// Square root. 325def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>; 326def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>; 327def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>; 328 329def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 330def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 331 332// Round to an integer, with the second operand (modifier M3) specifying 333// the rounding mode. These forms always check for inexact conditions. 334def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>; 335def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>; 336def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>; 337 338// frint rounds according to the current mode (modifier 0) and detects 339// inexact conditions. 340def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 341def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 342def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 343 344let Predicates = [FeatureFPExtension] in { 345 // Extended forms of the FIxBR instructions. M4 can be set to 4 346 // to suppress detection of inexact conditions. 347 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>; 348 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>; 349 def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>; 350 351 // fnearbyint is like frint but does not detect inexact conditions. 352 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 353 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 354 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 355 356 // floor is no longer allowed to raise an inexact condition, 357 // so restrict it to the cases where the condition can be suppressed. 358 // Mode 7 is round towards -inf. 359 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 360 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 361 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 362 363 // Same idea for ceil, where mode 6 is round towards +inf. 364 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 365 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 366 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 367 368 // Same idea for trunc, where mode 5 is round towards zero. 369 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 370 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 371 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 372 373 // Same idea for round, where mode 1 is round towards nearest with 374 // ties away from zero. 375 def : Pat<(fround FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 376 def : Pat<(fround FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 377 def : Pat<(fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 378} 379 380//===----------------------------------------------------------------------===// 381// Binary arithmetic 382//===----------------------------------------------------------------------===// 383 384// Addition. 385let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 386 let isCommutable = 1 in { 387 def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>; 388 def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>; 389 def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>; 390 } 391 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 392 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 393} 394 395// Subtraction. 396let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 397 def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>; 398 def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>; 399 def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>; 400 401 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 402 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 403} 404 405// Multiplication. 406let isCommutable = 1 in { 407 def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>; 408 def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>; 409 def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>; 410} 411def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 412def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 413 414// f64 multiplication of two FP32 registers. 415def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; 416def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (fpextend FP32:$src2))), 417 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 418 FP32:$src1, subreg_r32), FP32:$src2)>; 419 420// f64 multiplication of an FP32 register and an f32 memory. 421def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 422def : Pat<(fmul (f64 (fpextend FP32:$src1)), 423 (f64 (extloadf32 bdxaddr12only:$addr))), 424 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32), 425 bdxaddr12only:$addr)>; 426 427// f128 multiplication of two FP64 registers. 428def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>; 429def : Pat<(fmul (f128 (fpextend FP64:$src1)), (f128 (fpextend FP64:$src2))), 430 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 431 FP64:$src1, subreg_h64), FP64:$src2)>; 432 433// f128 multiplication of an FP64 register and an f64 memory. 434def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 435def : Pat<(fmul (f128 (fpextend FP64:$src1)), 436 (f128 (extloadf64 bdxaddr12only:$addr))), 437 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 438 bdxaddr12only:$addr)>; 439 440// Fused multiply-add. 441def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32, FP32>; 442def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64, FP64>; 443 444def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, FP32, load, 4>; 445def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, FP64, load, 8>; 446 447// Fused multiply-subtract. 448def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32, FP32>; 449def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64, FP64>; 450 451def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, FP32, load, 4>; 452def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, FP64, load, 8>; 453 454// Division. 455def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>; 456def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>; 457def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>; 458 459def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 460def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 461 462// Divide to integer. 463let Defs = [CC] in { 464 def DIEBR : TernaryRRFb<"diebr", 0xB353, FP32, FP32, FP32>; 465 def DIDBR : TernaryRRFb<"didbr", 0xB35B, FP64, FP64, FP64>; 466} 467 468//===----------------------------------------------------------------------===// 469// Comparisons 470//===----------------------------------------------------------------------===// 471 472let Defs = [CC], CCValues = 0xF in { 473 def CEBR : CompareRRE<"cebr", 0xB309, z_fcmp, FP32, FP32>; 474 def CDBR : CompareRRE<"cdbr", 0xB319, z_fcmp, FP64, FP64>; 475 def CXBR : CompareRRE<"cxbr", 0xB349, z_fcmp, FP128, FP128>; 476 477 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 478 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 479 480 def KEBR : CompareRRE<"kebr", 0xB308, null_frag, FP32, FP32>; 481 def KDBR : CompareRRE<"kdbr", 0xB318, null_frag, FP64, FP64>; 482 def KXBR : CompareRRE<"kxbr", 0xB348, null_frag, FP128, FP128>; 483 484 def KEB : CompareRXE<"keb", 0xED08, null_frag, FP32, load, 4>; 485 def KDB : CompareRXE<"kdb", 0xED18, null_frag, FP64, load, 8>; 486} 487 488// Test Data Class. 489let Defs = [CC], CCValues = 0xC in { 490 def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>; 491 def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>; 492 def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>; 493} 494 495//===----------------------------------------------------------------------===// 496// Floating-point control register instructions 497//===----------------------------------------------------------------------===// 498 499let hasSideEffects = 1 in { 500 def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>; 501 def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>; 502 503 def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>; 504 def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>; 505 506 def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>; 507 def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>; 508 509 def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>, 510 Requires<[FeatureFPExtension]>; 511 def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>; 512 def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>; 513} 514 515//===----------------------------------------------------------------------===// 516// Peepholes 517//===----------------------------------------------------------------------===// 518 519def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>; 520def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>; 521def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 522