1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// Control-flow instructions
12//===----------------------------------------------------------------------===//
13
14// C's ?: operator for floating-point operands.
15def SelectF32  : SelectWrapper<FP32>;
16def SelectF64  : SelectWrapper<FP64>;
17def SelectF128 : SelectWrapper<FP128>;
18
19//===----------------------------------------------------------------------===//
20// Move instructions
21//===----------------------------------------------------------------------===//
22
23// Load zero.
24let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
25  def LZER : InherentRRE<"lzer", 0xB374, FP32,  (fpimm0)>;
26  def LZDR : InherentRRE<"lzdr", 0xB375, FP64,  (fpimm0)>;
27  def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
28}
29
30// Moves between two floating-point registers.
31let neverHasSideEffects = 1 in {
32  def LER : UnaryRR <"ler", 0x38,   null_frag, FP32,  FP32>;
33  def LDR : UnaryRR <"ldr", 0x28,   null_frag, FP64,  FP64>;
34  def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
35}
36
37// Moves between 64-bit integer and floating-point registers.
38def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
39def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
40
41// fcopysign with an FP32 result.
42let isCodeGenOnly = 1 in {
43  def CPSDRss : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP32, FP32>;
44  def CPSDRsd : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP32, FP64>;
45}
46
47// The sign of an FP128 is in the high register.  Give the CPSDRsd
48// operands in R1, R2, R3 order.
49def : Pat<(fcopysign FP32:$src1, FP128:$src2),
50          (CPSDRsd (EXTRACT_SUBREG FP128:$src2, subreg_high), FP32:$src1)>;
51
52// fcopysign with an FP64 result.
53let isCodeGenOnly = 1 in
54  def CPSDRds : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP64, FP32>;
55def CPSDRdd : BinaryRevRRF<"cpsdr", 0xB372, fcopysign, FP64, FP64>;
56
57// The sign of an FP128 is in the high register.  Give the CPSDRdd
58// operands in R1, R2, R3 order.
59def : Pat<(fcopysign FP64:$src1, FP128:$src2),
60          (CPSDRdd (EXTRACT_SUBREG FP128:$src2, subreg_high), FP64:$src1)>;
61
62// fcopysign with an FP128 result.  Use "upper" as the high half and leave
63// the low half as-is.
64class CopySign128<RegisterOperand cls, dag upper>
65  : Pat<(fcopysign FP128:$src1, cls:$src2),
66        (INSERT_SUBREG FP128:$src1, upper, subreg_high)>;
67
68// Give the CPSDR* operands in R1, R2, R3 order.
69def : CopySign128<FP32,  (CPSDRds FP32:$src2,
70                                  (EXTRACT_SUBREG FP128:$src1, subreg_high))>;
71def : CopySign128<FP64,  (CPSDRdd FP64:$src2,
72                                  (EXTRACT_SUBREG FP128:$src1, subreg_high))>;
73def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src2, subreg_high),
74                                  (EXTRACT_SUBREG FP128:$src1, subreg_high))>;
75
76//===----------------------------------------------------------------------===//
77// Load instructions
78//===----------------------------------------------------------------------===//
79
80let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
81  defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32>;
82  defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64>;
83
84  // These instructions are split after register allocation, so we don't
85  // want a custom inserter.
86  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
87    def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
88                     [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
89  }
90}
91
92//===----------------------------------------------------------------------===//
93// Store instructions
94//===----------------------------------------------------------------------===//
95
96let SimpleBDXStore = 1 in {
97  defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32>;
98  defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64>;
99
100  // These instructions are split after register allocation, so we don't
101  // want a custom inserter.
102  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
103    def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
104                     [(store FP128:$src, bdxaddr20only128:$dst)]>;
105  }
106}
107
108//===----------------------------------------------------------------------===//
109// Conversion instructions
110//===----------------------------------------------------------------------===//
111
112// Convert floating-point values to narrower representations, rounding
113// according to the current mode.  The destination of LEXBR and LDXBR
114// is a 128-bit value, but only the first register of the pair is used.
115def LEDBR : UnaryRRE<"ledbr", 0xB344, fround,    FP32,  FP64>;
116def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>;
117def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>;
118
119def : Pat<(f32 (fround FP128:$src)),
120          (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_32bit)>;
121def : Pat<(f64 (fround FP128:$src)),
122          (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_high)>;
123
124// Extend register floating-point values to wider representations.
125def LDEBR : UnaryRRE<"ldebr", 0xB304, fextend, FP64,  FP32>;
126def LXEBR : UnaryRRE<"lxebr", 0xB306, fextend, FP128, FP32>;
127def LXDBR : UnaryRRE<"lxdbr", 0xB305, fextend, FP128, FP64>;
128
129// Extend memory floating-point values to wider representations.
130def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64>;
131def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128>;
132def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128>;
133
134// Convert a signed integer register value to a floating-point one.
135let Defs = [PSW] in {
136  def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32,  GR32>;
137  def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64,  GR32>;
138  def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>;
139
140  def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32,  GR64>;
141  def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64,  GR64>;
142  def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>;
143}
144
145// Convert a floating-point register value to a signed integer value,
146// with the second operand (modifier M3) specifying the rounding mode.
147let Defs = [PSW] in {
148  def CFEBR : UnaryRRF<"cfebr", 0xB398, GR32, FP32>;
149  def CFDBR : UnaryRRF<"cfdbr", 0xB399, GR32, FP64>;
150  def CFXBR : UnaryRRF<"cfxbr", 0xB39A, GR32, FP128>;
151
152  def CGEBR : UnaryRRF<"cgebr", 0xB3A8, GR64, FP32>;
153  def CGDBR : UnaryRRF<"cgdbr", 0xB3A9, GR64, FP64>;
154  def CGXBR : UnaryRRF<"cgxbr", 0xB3AA, GR64, FP128>;
155}
156
157// fp_to_sint always rounds towards zero, which is modifier value 5.
158def : Pat<(i32 (fp_to_sint FP32:$src)),  (CFEBR FP32:$src,  5)>;
159def : Pat<(i32 (fp_to_sint FP64:$src)),  (CFDBR FP64:$src,  5)>;
160def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR FP128:$src, 5)>;
161
162def : Pat<(i64 (fp_to_sint FP32:$src)),  (CGEBR FP32:$src,  5)>;
163def : Pat<(i64 (fp_to_sint FP64:$src)),  (CGDBR FP64:$src,  5)>;
164def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR FP128:$src, 5)>;
165
166//===----------------------------------------------------------------------===//
167// Unary arithmetic
168//===----------------------------------------------------------------------===//
169
170// Negation (Load Complement).
171let Defs = [PSW] in {
172  def LCEBR : UnaryRRE<"lcebr", 0xB303, fneg, FP32,  FP32>;
173  def LCDBR : UnaryRRE<"lcdbr", 0xB313, fneg, FP64,  FP64>;
174  def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>;
175}
176
177// Absolute value (Load Positive).
178let Defs = [PSW] in {
179  def LPEBR : UnaryRRE<"lpebr", 0xB300, fabs, FP32,  FP32>;
180  def LPDBR : UnaryRRE<"lpdbr", 0xB310, fabs, FP64,  FP64>;
181  def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>;
182}
183
184// Negative absolute value (Load Negative).
185let Defs = [PSW] in {
186  def LNEBR : UnaryRRE<"lnebr", 0xB301, fnabs, FP32,  FP32>;
187  def LNDBR : UnaryRRE<"lndbr", 0xB311, fnabs, FP64,  FP64>;
188  def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>;
189}
190
191// Square root.
192def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32,  FP32>;
193def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64,  FP64>;
194def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>;
195
196def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32>;
197def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64>;
198
199// Round to an integer, with the second operand (modifier M3) specifying
200// the rounding mode.
201//
202// These forms always check for inexact conditions.  z196 added versions
203// that allow this to suppressed (as for fnearbyint), but we don't yet
204// support -march=z196.
205let Defs = [PSW] in {
206  def FIEBR : UnaryRRF<"fiebr", 0xB357, FP32,  FP32>;
207  def FIDBR : UnaryRRF<"fidbr", 0xB35F, FP64,  FP64>;
208  def FIXBR : UnaryRRF<"fixbr", 0xB347, FP128, FP128>;
209}
210
211// frint rounds according to the current mode (modifier 0) and detects
212// inexact conditions.
213def : Pat<(frint FP32:$src),  (FIEBR FP32:$src,  0)>;
214def : Pat<(frint FP64:$src),  (FIDBR FP64:$src,  0)>;
215def : Pat<(frint FP128:$src), (FIXBR FP128:$src, 0)>;
216
217//===----------------------------------------------------------------------===//
218// Binary arithmetic
219//===----------------------------------------------------------------------===//
220
221// Addition.
222let Defs = [PSW] in {
223  let isCommutable = 1 in {
224    def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32,  FP32>;
225    def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64,  FP64>;
226    def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>;
227  }
228  def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load>;
229  def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load>;
230}
231
232// Subtraction.
233let Defs = [PSW] in {
234  def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32,  FP32>;
235  def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64,  FP64>;
236  def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>;
237
238  def SEB : BinaryRXE<"seb",  0xED0B, fsub, FP32, load>;
239  def SDB : BinaryRXE<"sdb",  0xED1B, fsub, FP64, load>;
240}
241
242// Multiplication.
243let isCommutable = 1 in {
244  def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32,  FP32>;
245  def MDBR  : BinaryRRE<"mdbr",  0xB31C, fmul, FP64,  FP64>;
246  def MXBR  : BinaryRRE<"mxbr",  0xB34C, fmul, FP128, FP128>;
247}
248def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load>;
249def MDB  : BinaryRXE<"mdb",  0xED1C, fmul, FP64, load>;
250
251// f64 multiplication of two FP32 registers.
252def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>;
253def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
254          (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
255                                FP32:$src1, subreg_32bit), FP32:$src2)>;
256
257// f64 multiplication of an FP32 register and an f32 memory.
258def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load>;
259def : Pat<(fmul (f64 (fextend FP32:$src1)),
260                (f64 (extloadf32 bdxaddr12only:$addr))),
261          (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_32bit),
262                bdxaddr12only:$addr)>;
263
264// f128 multiplication of two FP64 registers.
265def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>;
266def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
267          (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
268                                FP64:$src1, subreg_high), FP64:$src2)>;
269
270// f128 multiplication of an FP64 register and an f64 memory.
271def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load>;
272def : Pat<(fmul (f128 (fextend FP64:$src1)),
273                (f128 (extloadf64 bdxaddr12only:$addr))),
274          (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_high),
275                bdxaddr12only:$addr)>;
276
277// Fused multiply-add.
278def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32>;
279def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64>;
280
281def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load>;
282def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load>;
283
284// Fused multiply-subtract.
285def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32>;
286def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64>;
287
288def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load>;
289def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load>;
290
291// Division.
292def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32,  FP32>;
293def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64,  FP64>;
294def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>;
295
296def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load>;
297def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load>;
298
299//===----------------------------------------------------------------------===//
300// Comparisons
301//===----------------------------------------------------------------------===//
302
303let Defs = [PSW] in {
304  def CEBR : CompareRRE<"cebr", 0xB309, z_cmp, FP32,  FP32>;
305  def CDBR : CompareRRE<"cdbr", 0xB319, z_cmp, FP64,  FP64>;
306  def CXBR : CompareRRE<"cxbr", 0xB349, z_cmp, FP128, FP128>;
307
308  def CEB : CompareRXE<"ceb", 0xED09, z_cmp, FP32, load>;
309  def CDB : CompareRXE<"cdb", 0xED19, z_cmp, FP64, load>;
310}
311
312//===----------------------------------------------------------------------===//
313// Peepholes
314//===----------------------------------------------------------------------===//
315
316def : Pat<(f32  fpimmneg0), (LCEBR (LZER))>;
317def : Pat<(f64  fpimmneg0), (LCDBR (LZDR))>;
318def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
319