1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Select instructions 12//===----------------------------------------------------------------------===// 13 14// C's ?: operator for floating-point operands. 15def SelectF32 : SelectWrapper<FP32>; 16def SelectF64 : SelectWrapper<FP64>; 17def SelectF128 : SelectWrapper<FP128>; 18 19defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 20 nonvolatile_load, bdxaddr20only>; 21defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 22 nonvolatile_load, bdxaddr20only>; 23 24//===----------------------------------------------------------------------===// 25// Move instructions 26//===----------------------------------------------------------------------===// 27 28// Load zero. 29let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in { 30 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>; 31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>; 32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>; 33} 34 35// Moves between two floating-point registers. 36let hasSideEffects = 0 in { 37 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>; 38 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>; 39 def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>; 40 41 // For z13 we prefer LDR over LER to avoid partial register dependencies. 42 let isCodeGenOnly = 1 in 43 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>; 44} 45 46// Moves between two floating-point registers that also set the condition 47// codes. 48let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 49 defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>; 50 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>; 51 defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>; 52} 53// Note that LTxBRCompare is not available if we have vector support, 54// since load-and-test instructions will partially clobber the target 55// (vector) register. 56let Predicates = [FeatureNoVector] in { 57 defm : CompareZeroFP<LTEBRCompare, FP32>; 58 defm : CompareZeroFP<LTDBRCompare, FP64>; 59 defm : CompareZeroFP<LTXBRCompare, FP128>; 60} 61 62// Use a normal load-and-test for compare against zero in case of 63// vector support (via a pseudo to simplify instruction selection). 64let Defs = [CC], usesCustomInserter = 1 in { 65 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; 66 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; 67 def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; 68} 69let Predicates = [FeatureVector] in { 70 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>; 71 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>; 72 defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>; 73} 74 75// Moves between 64-bit integer and floating-point registers. 76def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; 77def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; 78 79// fcopysign with an FP32 result. 80let isCodeGenOnly = 1 in { 81 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>; 82 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>; 83} 84 85// The sign of an FP128 is in the high register. 86def : Pat<(fcopysign FP32:$src1, FP128:$src2), 87 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 88 89// fcopysign with an FP64 result. 90let isCodeGenOnly = 1 in 91 def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>; 92def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>; 93 94// The sign of an FP128 is in the high register. 95def : Pat<(fcopysign FP64:$src1, FP128:$src2), 96 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 97 98// fcopysign with an FP128 result. Use "upper" as the high half and leave 99// the low half as-is. 100class CopySign128<RegisterOperand cls, dag upper> 101 : Pat<(fcopysign FP128:$src1, cls:$src2), 102 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 103 104def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 105 FP32:$src2)>; 106def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 107 FP64:$src2)>; 108def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 109 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 110 111defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 112defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 113defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 114 115//===----------------------------------------------------------------------===// 116// Load instructions 117//===----------------------------------------------------------------------===// 118 119let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 120 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 121 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 122 123 // For z13 we prefer LDE over LE to avoid partial register dependencies. 124 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>; 125 126 // These instructions are split after register allocation, so we don't 127 // want a custom inserter. 128 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 129 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 130 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 131 } 132} 133 134//===----------------------------------------------------------------------===// 135// Store instructions 136//===----------------------------------------------------------------------===// 137 138let SimpleBDXStore = 1 in { 139 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 140 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 141 142 // These instructions are split after register allocation, so we don't 143 // want a custom inserter. 144 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 145 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 146 [(store FP128:$src, bdxaddr20only128:$dst)]>; 147 } 148} 149 150//===----------------------------------------------------------------------===// 151// Conversion instructions 152//===----------------------------------------------------------------------===// 153 154// Convert floating-point values to narrower representations, rounding 155// according to the current mode. The destination of LEXBR and LDXBR 156// is a 128-bit value, but only the first register of the pair is used. 157def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround, FP32, FP64>; 158def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>; 159def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>; 160 161def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>, 162 Requires<[FeatureFPExtension]>; 163def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>, 164 Requires<[FeatureFPExtension]>; 165def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>, 166 Requires<[FeatureFPExtension]>; 167 168def : Pat<(f32 (fpround FP128:$src)), 169 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>; 170def : Pat<(f64 (fpround FP128:$src)), 171 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 172 173// Extend register floating-point values to wider representations. 174def LDEBR : UnaryRRE<"ldebr", 0xB304, fpextend, FP64, FP32>; 175def LXEBR : UnaryRRE<"lxebr", 0xB306, fpextend, FP128, FP32>; 176def LXDBR : UnaryRRE<"lxdbr", 0xB305, fpextend, FP128, FP64>; 177 178// Extend memory floating-point values to wider representations. 179def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 180def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>; 181def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>; 182 183// Convert a signed integer register value to a floating-point one. 184def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>; 185def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>; 186def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>; 187 188def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>; 189def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>; 190def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>; 191 192// The FP extension feature provides versions of the above that allow 193// specifying rounding mode and inexact-exception suppression flags. 194let Predicates = [FeatureFPExtension] in { 195 def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>; 196 def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>; 197 def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>; 198 199 def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>; 200 def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>; 201 def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>; 202} 203 204// Convert am unsigned integer register value to a floating-point one. 205let Predicates = [FeatureFPExtension] in { 206 def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>; 207 def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>; 208 def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>; 209 210 def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>; 211 def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>; 212 def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>; 213 214 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 215 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 216 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 217 218 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 219 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 220 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 221} 222 223// Convert a floating-point register value to a signed integer value, 224// with the second operand (modifier M3) specifying the rounding mode. 225let Defs = [CC] in { 226 def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>; 227 def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>; 228 def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>; 229 230 def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>; 231 def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>; 232 def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>; 233} 234 235// fp_to_sint always rounds towards zero, which is modifier value 5. 236def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 237def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 238def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 239 240def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 241def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 242def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 243 244// The FP extension feature provides versions of the above that allow 245// also specifying the inexact-exception suppression flag. 246let Predicates = [FeatureFPExtension], Defs = [CC] in { 247 def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>; 248 def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>; 249 def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>; 250 251 def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>; 252 def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>; 253 def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>; 254} 255 256// Convert a floating-point register value to an unsigned integer value. 257let Predicates = [FeatureFPExtension] in { 258 let Defs = [CC] in { 259 def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>; 260 def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>; 261 def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>; 262 263 def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>; 264 def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>; 265 def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>; 266 } 267 268 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 269 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 270 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 271 272 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 273 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 274 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 275} 276 277 278//===----------------------------------------------------------------------===// 279// Unary arithmetic 280//===----------------------------------------------------------------------===// 281 282// We prefer generic instructions during isel, because they do not 283// clobber CC and therefore give the scheduler more freedom. In cases 284// the CC is actually useful, the SystemZElimCompare pass will try to 285// convert generic instructions into opcodes that also set CC. Note 286// that lcdf / lpdf / lndf only affect the sign bit, and can therefore 287// be used with fp32 as well. This could be done for fp128, in which 288// case the operands would have to be tied. 289 290// Negation (Load Complement). 291let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 292 def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>; 293 def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>; 294 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>; 295} 296// Generic form, which does not set CC. 297def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>; 298let isCodeGenOnly = 1 in 299 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>; 300 301// Absolute value (Load Positive). 302let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 303 def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>; 304 def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>; 305 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>; 306} 307// Generic form, which does not set CC. 308def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>; 309let isCodeGenOnly = 1 in 310 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>; 311 312// Negative absolute value (Load Negative). 313let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 314 def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>; 315 def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>; 316 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>; 317} 318// Generic form, which does not set CC. 319def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>; 320let isCodeGenOnly = 1 in 321 def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>; 322 323// Square root. 324def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>; 325def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>; 326def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>; 327 328def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 329def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 330 331// Round to an integer, with the second operand (modifier M3) specifying 332// the rounding mode. These forms always check for inexact conditions. 333def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>; 334def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>; 335def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>; 336 337// frint rounds according to the current mode (modifier 0) and detects 338// inexact conditions. 339def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 340def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 341def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 342 343let Predicates = [FeatureFPExtension] in { 344 // Extended forms of the FIxBR instructions. M4 can be set to 4 345 // to suppress detection of inexact conditions. 346 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>; 347 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>; 348 def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>; 349 350 // fnearbyint is like frint but does not detect inexact conditions. 351 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 352 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 353 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 354 355 // floor is no longer allowed to raise an inexact condition, 356 // so restrict it to the cases where the condition can be suppressed. 357 // Mode 7 is round towards -inf. 358 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 359 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 360 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 361 362 // Same idea for ceil, where mode 6 is round towards +inf. 363 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 364 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 365 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 366 367 // Same idea for trunc, where mode 5 is round towards zero. 368 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 369 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 370 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 371 372 // Same idea for round, where mode 1 is round towards nearest with 373 // ties away from zero. 374 def : Pat<(fround FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 375 def : Pat<(fround FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 376 def : Pat<(fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 377} 378 379//===----------------------------------------------------------------------===// 380// Binary arithmetic 381//===----------------------------------------------------------------------===// 382 383// Addition. 384let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 385 let isCommutable = 1 in { 386 def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>; 387 def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>; 388 def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>; 389 } 390 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 391 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 392} 393 394// Subtraction. 395let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 396 def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>; 397 def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>; 398 def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>; 399 400 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 401 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 402} 403 404// Multiplication. 405let isCommutable = 1 in { 406 def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>; 407 def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>; 408 def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>; 409} 410def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 411def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 412 413// f64 multiplication of two FP32 registers. 414def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; 415def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (fpextend FP32:$src2))), 416 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 417 FP32:$src1, subreg_r32), FP32:$src2)>; 418 419// f64 multiplication of an FP32 register and an f32 memory. 420def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 421def : Pat<(fmul (f64 (fpextend FP32:$src1)), 422 (f64 (extloadf32 bdxaddr12only:$addr))), 423 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32), 424 bdxaddr12only:$addr)>; 425 426// f128 multiplication of two FP64 registers. 427def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>; 428def : Pat<(fmul (f128 (fpextend FP64:$src1)), (f128 (fpextend FP64:$src2))), 429 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 430 FP64:$src1, subreg_h64), FP64:$src2)>; 431 432// f128 multiplication of an FP64 register and an f64 memory. 433def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 434def : Pat<(fmul (f128 (fpextend FP64:$src1)), 435 (f128 (extloadf64 bdxaddr12only:$addr))), 436 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 437 bdxaddr12only:$addr)>; 438 439// Fused multiply-add. 440def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32>; 441def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64>; 442 443def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>; 444def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>; 445 446// Fused multiply-subtract. 447def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32>; 448def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64>; 449 450def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>; 451def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>; 452 453// Division. 454def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>; 455def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>; 456def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>; 457 458def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 459def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 460 461//===----------------------------------------------------------------------===// 462// Comparisons 463//===----------------------------------------------------------------------===// 464 465let Defs = [CC], CCValues = 0xF in { 466 def CEBR : CompareRRE<"cebr", 0xB309, z_fcmp, FP32, FP32>; 467 def CDBR : CompareRRE<"cdbr", 0xB319, z_fcmp, FP64, FP64>; 468 def CXBR : CompareRRE<"cxbr", 0xB349, z_fcmp, FP128, FP128>; 469 470 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 471 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 472} 473 474// Test Data Class. 475let Defs = [CC], CCValues = 0xC in { 476 def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>; 477 def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>; 478 def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>; 479} 480 481//===----------------------------------------------------------------------===// 482// Floating-point control register instructions 483//===----------------------------------------------------------------------===// 484 485let hasSideEffects = 1 in { 486 def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>; 487 def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>; 488 489 def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>; 490 def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>; 491 492 def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>; 493 def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>; 494 495 def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>, 496 Requires<[FeatureFPExtension]>; 497 def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>; 498 def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>; 499} 500 501//===----------------------------------------------------------------------===// 502// Peepholes 503//===----------------------------------------------------------------------===// 504 505def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>; 506def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>; 507def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 508