1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "systemz-lower" 15 16 #include "SystemZISelLowering.h" 17 #include "SystemZ.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZSubtarget.h" 20 #include "llvm/DerivedTypes.h" 21 #include "llvm/Function.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/GlobalVariable.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/CodeGen/CallingConvLower.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/PseudoSourceValue.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/ValueTypes.h" 34 #include "llvm/Target/TargetOptions.h" 35 #include "llvm/Target/TargetLoweringObjectFile.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/ADT/VectorExtras.h" 40 using namespace llvm; 41 42 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : 43 TargetLowering(tm, new TargetLoweringObjectFileELF()), 44 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 45 46 RegInfo = TM.getRegisterInfo(); 47 48 // Set up the register classes. 49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); 50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); 51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); 52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); 53 54 if (!UseSoftFloat) { 55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); 56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); 57 } 58 59 // Compute derived properties from the register classes 60 computeRegisterProperties(); 61 62 // Set shifts properties 63 setShiftAmountType(MVT::i64); 64 65 // Provide all sorts of operation actions 66 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 67 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 68 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 69 70 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); 71 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); 72 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 73 74 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); 75 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); 76 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 77 78 setStackPointerRegisterToSaveRestore(SystemZ::R15D); 79 80 // TODO: It may be better to default to latency-oriented scheduling, however 81 // LLVM's current latency-oriented scheduler can't handle physreg definitions 82 // such as SystemZ has with PSW, so set this to the register-pressure 83 // scheduler, because it can. 84 setSchedulingPreference(SchedulingForRegPressure); 85 86 setBooleanContents(ZeroOrOneBooleanContent); 87 88 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 89 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 90 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 91 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 92 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 93 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 94 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 95 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 96 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 97 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 99 100 setOperationAction(ISD::SDIV, MVT::i32, Expand); 101 setOperationAction(ISD::UDIV, MVT::i32, Expand); 102 setOperationAction(ISD::SDIV, MVT::i64, Expand); 103 setOperationAction(ISD::UDIV, MVT::i64, Expand); 104 setOperationAction(ISD::SREM, MVT::i32, Expand); 105 setOperationAction(ISD::UREM, MVT::i32, Expand); 106 setOperationAction(ISD::SREM, MVT::i64, Expand); 107 setOperationAction(ISD::UREM, MVT::i64, Expand); 108 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 110 111 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 112 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 113 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 114 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 115 setOperationAction(ISD::CTLZ, MVT::i32, Promote); 116 setOperationAction(ISD::CTLZ, MVT::i64, Legal); 117 118 // FIXME: Can we lower these 2 efficiently? 119 setOperationAction(ISD::SETCC, MVT::i32, Expand); 120 setOperationAction(ISD::SETCC, MVT::i64, Expand); 121 setOperationAction(ISD::SETCC, MVT::f32, Expand); 122 setOperationAction(ISD::SETCC, MVT::f64, Expand); 123 setOperationAction(ISD::SELECT, MVT::i32, Expand); 124 setOperationAction(ISD::SELECT, MVT::i64, Expand); 125 setOperationAction(ISD::SELECT, MVT::f32, Expand); 126 setOperationAction(ISD::SELECT, MVT::f64, Expand); 127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 131 132 setOperationAction(ISD::MULHS, MVT::i64, Expand); 133 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 134 135 // FIXME: Can we support these natively? 136 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 137 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 138 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 139 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 140 141 // Lower some FP stuff 142 setOperationAction(ISD::FSIN, MVT::f32, Expand); 143 setOperationAction(ISD::FSIN, MVT::f64, Expand); 144 setOperationAction(ISD::FCOS, MVT::f32, Expand); 145 setOperationAction(ISD::FCOS, MVT::f64, Expand); 146 setOperationAction(ISD::FREM, MVT::f32, Expand); 147 setOperationAction(ISD::FREM, MVT::f64, Expand); 148 149 // We have only 64-bit bitconverts 150 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 151 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 152 153 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 154 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 155 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 156 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 157 158 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 159 } 160 161 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 162 switch (Op.getOpcode()) { 163 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 164 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 165 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 166 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 167 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 168 default: 169 llvm_unreachable("Should not custom lower this!"); 170 return SDValue(); 171 } 172 } 173 174 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 175 if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64)) 176 return false; 177 178 // +0.0 lzer 179 // +0.0f lzdr 180 // -0.0 lzer + lner 181 // -0.0f lzdr + lndr 182 return Imm.isZero() || Imm.isNegZero(); 183 } 184 185 //===----------------------------------------------------------------------===// 186 // SystemZ Inline Assembly Support 187 //===----------------------------------------------------------------------===// 188 189 /// getConstraintType - Given a constraint letter, return the type of 190 /// constraint it is for this target. 191 TargetLowering::ConstraintType 192 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const { 193 if (Constraint.size() == 1) { 194 switch (Constraint[0]) { 195 case 'r': 196 return C_RegisterClass; 197 default: 198 break; 199 } 200 } 201 return TargetLowering::getConstraintType(Constraint); 202 } 203 204 std::pair<unsigned, const TargetRegisterClass*> 205 SystemZTargetLowering:: 206 getRegForInlineAsmConstraint(const std::string &Constraint, 207 EVT VT) const { 208 if (Constraint.size() == 1) { 209 // GCC Constraint Letters 210 switch (Constraint[0]) { 211 default: break; 212 case 'r': // GENERAL_REGS 213 if (VT == MVT::i32) 214 return std::make_pair(0U, SystemZ::GR32RegisterClass); 215 else if (VT == MVT::i128) 216 return std::make_pair(0U, SystemZ::GR128RegisterClass); 217 218 return std::make_pair(0U, SystemZ::GR64RegisterClass); 219 } 220 } 221 222 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 223 } 224 225 //===----------------------------------------------------------------------===// 226 // Calling Convention Implementation 227 //===----------------------------------------------------------------------===// 228 229 #include "SystemZGenCallingConv.inc" 230 231 SDValue 232 SystemZTargetLowering::LowerFormalArguments(SDValue Chain, 233 CallingConv::ID CallConv, 234 bool isVarArg, 235 const SmallVectorImpl<ISD::InputArg> 236 &Ins, 237 DebugLoc dl, 238 SelectionDAG &DAG, 239 SmallVectorImpl<SDValue> &InVals) { 240 241 switch (CallConv) { 242 default: 243 llvm_unreachable("Unsupported calling convention"); 244 case CallingConv::C: 245 case CallingConv::Fast: 246 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 247 } 248 } 249 250 SDValue 251 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 252 CallingConv::ID CallConv, bool isVarArg, 253 bool isTailCall, 254 const SmallVectorImpl<ISD::OutputArg> &Outs, 255 const SmallVectorImpl<ISD::InputArg> &Ins, 256 DebugLoc dl, SelectionDAG &DAG, 257 SmallVectorImpl<SDValue> &InVals) { 258 259 switch (CallConv) { 260 default: 261 llvm_unreachable("Unsupported calling convention"); 262 case CallingConv::Fast: 263 case CallingConv::C: 264 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 265 Outs, Ins, dl, DAG, InVals); 266 } 267 } 268 269 /// LowerCCCArguments - transform physical registers into virtual registers and 270 /// generate load operations for arguments places on the stack. 271 // FIXME: struct return stuff 272 // FIXME: varargs 273 SDValue 274 SystemZTargetLowering::LowerCCCArguments(SDValue Chain, 275 CallingConv::ID CallConv, 276 bool isVarArg, 277 const SmallVectorImpl<ISD::InputArg> 278 &Ins, 279 DebugLoc dl, 280 SelectionDAG &DAG, 281 SmallVectorImpl<SDValue> &InVals) { 282 283 MachineFunction &MF = DAG.getMachineFunction(); 284 MachineFrameInfo *MFI = MF.getFrameInfo(); 285 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 286 287 // Assign locations to all of the incoming arguments. 288 SmallVector<CCValAssign, 16> ArgLocs; 289 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 290 ArgLocs, *DAG.getContext()); 291 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); 292 293 if (isVarArg) 294 llvm_report_error("Varargs not supported yet"); 295 296 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 297 SDValue ArgValue; 298 CCValAssign &VA = ArgLocs[i]; 299 EVT LocVT = VA.getLocVT(); 300 if (VA.isRegLoc()) { 301 // Arguments passed in registers 302 TargetRegisterClass *RC; 303 switch (LocVT.getSimpleVT().SimpleTy) { 304 default: 305 #ifndef NDEBUG 306 errs() << "LowerFormalArguments Unhandled argument type: " 307 << LocVT.getSimpleVT().SimpleTy 308 << "\n"; 309 #endif 310 llvm_unreachable(0); 311 case MVT::i64: 312 RC = SystemZ::GR64RegisterClass; 313 break; 314 case MVT::f32: 315 RC = SystemZ::FP32RegisterClass; 316 break; 317 case MVT::f64: 318 RC = SystemZ::FP64RegisterClass; 319 break; 320 } 321 322 unsigned VReg = RegInfo.createVirtualRegister(RC); 323 RegInfo.addLiveIn(VA.getLocReg(), VReg); 324 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT); 325 } else { 326 // Sanity check 327 assert(VA.isMemLoc()); 328 329 // Create the nodes corresponding to a load from this parameter slot. 330 // Create the frame index object for this incoming parameter... 331 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, 332 VA.getLocMemOffset(), true, false); 333 334 // Create the SelectionDAG nodes corresponding to a load 335 // from this parameter 336 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 337 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN, 338 PseudoSourceValue::getFixedStack(FI), 0); 339 } 340 341 // If this is an 8/16/32-bit value, it is really passed promoted to 64 342 // bits. Insert an assert[sz]ext to capture this, then truncate to the 343 // right size. 344 if (VA.getLocInfo() == CCValAssign::SExt) 345 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 346 DAG.getValueType(VA.getValVT())); 347 else if (VA.getLocInfo() == CCValAssign::ZExt) 348 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, 349 DAG.getValueType(VA.getValVT())); 350 351 if (VA.getLocInfo() != CCValAssign::Full) 352 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 353 354 InVals.push_back(ArgValue); 355 } 356 357 return Chain; 358 } 359 360 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 361 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 362 /// TODO: sret. 363 SDValue 364 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 365 CallingConv::ID CallConv, bool isVarArg, 366 bool isTailCall, 367 const SmallVectorImpl<ISD::OutputArg> 368 &Outs, 369 const SmallVectorImpl<ISD::InputArg> &Ins, 370 DebugLoc dl, SelectionDAG &DAG, 371 SmallVectorImpl<SDValue> &InVals) { 372 373 MachineFunction &MF = DAG.getMachineFunction(); 374 375 // Offset to first argument stack slot. 376 const unsigned FirstArgOffset = 160; 377 378 // Analyze operands of the call, assigning locations to each operand. 379 SmallVector<CCValAssign, 16> ArgLocs; 380 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 381 ArgLocs, *DAG.getContext()); 382 383 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); 384 385 // Get a count of how many bytes are to be pushed on the stack. 386 unsigned NumBytes = CCInfo.getNextStackOffset(); 387 388 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 389 getPointerTy(), true)); 390 391 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 392 SmallVector<SDValue, 12> MemOpChains; 393 SDValue StackPtr; 394 395 // Walk the register/memloc assignments, inserting copies/loads. 396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 397 CCValAssign &VA = ArgLocs[i]; 398 399 SDValue Arg = Outs[i].Val; 400 401 // Promote the value if needed. 402 switch (VA.getLocInfo()) { 403 default: assert(0 && "Unknown loc info!"); 404 case CCValAssign::Full: break; 405 case CCValAssign::SExt: 406 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 407 break; 408 case CCValAssign::ZExt: 409 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 410 break; 411 case CCValAssign::AExt: 412 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 413 break; 414 } 415 416 // Arguments that can be passed on register must be kept at RegsToPass 417 // vector 418 if (VA.isRegLoc()) { 419 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 420 } else { 421 assert(VA.isMemLoc()); 422 423 if (StackPtr.getNode() == 0) 424 StackPtr = 425 DAG.getCopyFromReg(Chain, dl, 426 (RegInfo->hasFP(MF) ? 427 SystemZ::R11D : SystemZ::R15D), 428 getPointerTy()); 429 430 unsigned Offset = FirstArgOffset + VA.getLocMemOffset(); 431 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 432 StackPtr, 433 DAG.getIntPtrConstant(Offset)); 434 435 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 436 PseudoSourceValue::getStack(), Offset)); 437 } 438 } 439 440 // Transform all store nodes into one single node because all store nodes are 441 // independent of each other. 442 if (!MemOpChains.empty()) 443 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 444 &MemOpChains[0], MemOpChains.size()); 445 446 // Build a sequence of copy-to-reg nodes chained together with token chain and 447 // flag operands which copy the outgoing args into registers. The InFlag in 448 // necessary since all emited instructions must be stuck together. 449 SDValue InFlag; 450 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 451 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 452 RegsToPass[i].second, InFlag); 453 InFlag = Chain.getValue(1); 454 } 455 456 // If the callee is a GlobalAddress node (quite common, every direct call is) 457 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 458 // Likewise ExternalSymbol -> TargetExternalSymbol. 459 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 460 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 461 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 462 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 463 464 // Returns a chain & a flag for retval copy to use. 465 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 466 SmallVector<SDValue, 8> Ops; 467 Ops.push_back(Chain); 468 Ops.push_back(Callee); 469 470 // Add argument registers to the end of the list so that they are 471 // known live into the call. 472 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 473 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 474 RegsToPass[i].second.getValueType())); 475 476 if (InFlag.getNode()) 477 Ops.push_back(InFlag); 478 479 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 480 InFlag = Chain.getValue(1); 481 482 // Create the CALLSEQ_END node. 483 Chain = DAG.getCALLSEQ_END(Chain, 484 DAG.getConstant(NumBytes, getPointerTy(), true), 485 DAG.getConstant(0, getPointerTy(), true), 486 InFlag); 487 InFlag = Chain.getValue(1); 488 489 // Handle result values, copying them out of physregs into vregs that we 490 // return. 491 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 492 DAG, InVals); 493 } 494 495 /// LowerCallResult - Lower the result values of a call into the 496 /// appropriate copies out of appropriate physical registers. 497 /// 498 SDValue 499 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 500 CallingConv::ID CallConv, bool isVarArg, 501 const SmallVectorImpl<ISD::InputArg> 502 &Ins, 503 DebugLoc dl, SelectionDAG &DAG, 504 SmallVectorImpl<SDValue> &InVals) { 505 506 // Assign locations to each value returned by this call. 507 SmallVector<CCValAssign, 16> RVLocs; 508 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 509 *DAG.getContext()); 510 511 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); 512 513 // Copy all of the result registers out of their specified physreg. 514 for (unsigned i = 0; i != RVLocs.size(); ++i) { 515 CCValAssign &VA = RVLocs[i]; 516 517 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 518 VA.getLocVT(), InFlag).getValue(1); 519 SDValue RetValue = Chain.getValue(0); 520 InFlag = Chain.getValue(2); 521 522 // If this is an 8/16/32-bit value, it is really passed promoted to 64 523 // bits. Insert an assert[sz]ext to capture this, then truncate to the 524 // right size. 525 if (VA.getLocInfo() == CCValAssign::SExt) 526 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, 527 DAG.getValueType(VA.getValVT())); 528 else if (VA.getLocInfo() == CCValAssign::ZExt) 529 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, 530 DAG.getValueType(VA.getValVT())); 531 532 if (VA.getLocInfo() != CCValAssign::Full) 533 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue); 534 535 InVals.push_back(RetValue); 536 } 537 538 return Chain; 539 } 540 541 542 SDValue 543 SystemZTargetLowering::LowerReturn(SDValue Chain, 544 CallingConv::ID CallConv, bool isVarArg, 545 const SmallVectorImpl<ISD::OutputArg> &Outs, 546 DebugLoc dl, SelectionDAG &DAG) { 547 548 // CCValAssign - represent the assignment of the return value to a location 549 SmallVector<CCValAssign, 16> RVLocs; 550 551 // CCState - Info about the registers and stack slot. 552 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 553 RVLocs, *DAG.getContext()); 554 555 // Analize return values. 556 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); 557 558 // If this is the first return lowered for this function, add the regs to the 559 // liveout set for the function. 560 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 561 for (unsigned i = 0; i != RVLocs.size(); ++i) 562 if (RVLocs[i].isRegLoc()) 563 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 564 } 565 566 SDValue Flag; 567 568 // Copy the result values into the output registers. 569 for (unsigned i = 0; i != RVLocs.size(); ++i) { 570 CCValAssign &VA = RVLocs[i]; 571 SDValue ResValue = Outs[i].Val; 572 assert(VA.isRegLoc() && "Can only return in registers!"); 573 574 // If this is an 8/16/32-bit value, it is really should be passed promoted 575 // to 64 bits. 576 if (VA.getLocInfo() == CCValAssign::SExt) 577 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); 578 else if (VA.getLocInfo() == CCValAssign::ZExt) 579 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); 580 else if (VA.getLocInfo() == CCValAssign::AExt) 581 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); 582 583 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); 584 585 // Guarantee that all emitted copies are stuck together, 586 // avoiding something bad. 587 Flag = Chain.getValue(1); 588 } 589 590 if (Flag.getNode()) 591 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 592 593 // Return Void 594 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); 595 } 596 597 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, 598 ISD::CondCode CC, SDValue &SystemZCC, 599 SelectionDAG &DAG) { 600 // FIXME: Emit a test if RHS is zero 601 602 bool isUnsigned = false; 603 SystemZCC::CondCodes TCC; 604 switch (CC) { 605 default: 606 llvm_unreachable("Invalid integer condition!"); 607 case ISD::SETEQ: 608 case ISD::SETOEQ: 609 TCC = SystemZCC::E; 610 break; 611 case ISD::SETUEQ: 612 TCC = SystemZCC::NLH; 613 break; 614 case ISD::SETNE: 615 case ISD::SETONE: 616 TCC = SystemZCC::NE; 617 break; 618 case ISD::SETUNE: 619 TCC = SystemZCC::LH; 620 break; 621 case ISD::SETO: 622 TCC = SystemZCC::O; 623 break; 624 case ISD::SETUO: 625 TCC = SystemZCC::NO; 626 break; 627 case ISD::SETULE: 628 if (LHS.getValueType().isFloatingPoint()) { 629 TCC = SystemZCC::NH; 630 break; 631 } 632 isUnsigned = true; // FALLTHROUGH 633 case ISD::SETLE: 634 case ISD::SETOLE: 635 TCC = SystemZCC::LE; 636 break; 637 case ISD::SETUGE: 638 if (LHS.getValueType().isFloatingPoint()) { 639 TCC = SystemZCC::NL; 640 break; 641 } 642 isUnsigned = true; // FALLTHROUGH 643 case ISD::SETGE: 644 case ISD::SETOGE: 645 TCC = SystemZCC::HE; 646 break; 647 case ISD::SETUGT: 648 if (LHS.getValueType().isFloatingPoint()) { 649 TCC = SystemZCC::NLE; 650 break; 651 } 652 isUnsigned = true; // FALLTHROUGH 653 case ISD::SETGT: 654 case ISD::SETOGT: 655 TCC = SystemZCC::H; 656 break; 657 case ISD::SETULT: 658 if (LHS.getValueType().isFloatingPoint()) { 659 TCC = SystemZCC::NHE; 660 break; 661 } 662 isUnsigned = true; // FALLTHROUGH 663 case ISD::SETLT: 664 case ISD::SETOLT: 665 TCC = SystemZCC::L; 666 break; 667 } 668 669 SystemZCC = DAG.getConstant(TCC, MVT::i32); 670 671 DebugLoc dl = LHS.getDebugLoc(); 672 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), 673 dl, MVT::i64, LHS, RHS); 674 } 675 676 677 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 678 SDValue Chain = Op.getOperand(0); 679 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 680 SDValue LHS = Op.getOperand(2); 681 SDValue RHS = Op.getOperand(3); 682 SDValue Dest = Op.getOperand(4); 683 DebugLoc dl = Op.getDebugLoc(); 684 685 SDValue SystemZCC; 686 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 687 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(), 688 Chain, Dest, SystemZCC, Flag); 689 } 690 691 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 692 SDValue LHS = Op.getOperand(0); 693 SDValue RHS = Op.getOperand(1); 694 SDValue TrueV = Op.getOperand(2); 695 SDValue FalseV = Op.getOperand(3); 696 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 697 DebugLoc dl = Op.getDebugLoc(); 698 699 SDValue SystemZCC; 700 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 701 702 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 703 SmallVector<SDValue, 4> Ops; 704 Ops.push_back(TrueV); 705 Ops.push_back(FalseV); 706 Ops.push_back(SystemZCC); 707 Ops.push_back(Flag); 708 709 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size()); 710 } 711 712 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, 713 SelectionDAG &DAG) { 714 DebugLoc dl = Op.getDebugLoc(); 715 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 716 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 717 718 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 719 bool ExtraLoadRequired = 720 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false); 721 722 SDValue Result; 723 if (!IsPic && !ExtraLoadRequired) { 724 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 725 Offset = 0; 726 } else { 727 unsigned char OpFlags = 0; 728 if (ExtraLoadRequired) 729 OpFlags = SystemZII::MO_GOTENT; 730 731 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 732 } 733 734 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl, 735 getPointerTy(), Result); 736 737 if (ExtraLoadRequired) 738 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 739 PseudoSourceValue::getGOT(), 0); 740 741 // If there was a non-zero offset that we didn't fold, create an explicit 742 // addition for it. 743 if (Offset != 0) 744 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 745 DAG.getConstant(Offset, getPointerTy())); 746 747 return Result; 748 } 749 750 // FIXME: PIC here 751 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, 752 SelectionDAG &DAG) { 753 DebugLoc dl = Op.getDebugLoc(); 754 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 755 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 756 757 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 758 } 759 760 761 // FIXME: PIC here 762 // FIXME: This is just dirty hack. We need to lower cpool properly 763 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, 764 SelectionDAG &DAG) { 765 DebugLoc dl = Op.getDebugLoc(); 766 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 767 768 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 769 CP->getAlignment(), 770 CP->getOffset()); 771 772 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 773 } 774 775 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { 776 switch (Opcode) { 777 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG"; 778 case SystemZISD::CALL: return "SystemZISD::CALL"; 779 case SystemZISD::BRCOND: return "SystemZISD::BRCOND"; 780 case SystemZISD::CMP: return "SystemZISD::CMP"; 781 case SystemZISD::UCMP: return "SystemZISD::UCMP"; 782 case SystemZISD::SELECT: return "SystemZISD::SELECT"; 783 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper"; 784 default: return NULL; 785 } 786 } 787 788 //===----------------------------------------------------------------------===// 789 // Other Lowering Code 790 //===----------------------------------------------------------------------===// 791 792 MachineBasicBlock* 793 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 794 MachineBasicBlock *BB, 795 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 796 const SystemZInstrInfo &TII = *TM.getInstrInfo(); 797 DebugLoc dl = MI->getDebugLoc(); 798 assert((MI->getOpcode() == SystemZ::Select32 || 799 MI->getOpcode() == SystemZ::SelectF32 || 800 MI->getOpcode() == SystemZ::Select64 || 801 MI->getOpcode() == SystemZ::SelectF64) && 802 "Unexpected instr type to insert"); 803 804 // To "insert" a SELECT instruction, we actually have to insert the diamond 805 // control-flow pattern. The incoming instruction knows the destination vreg 806 // to set, the condition code register to branch on, the true/false values to 807 // select between, and a branch opcode to use. 808 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 809 MachineFunction::iterator I = BB; 810 ++I; 811 812 // thisMBB: 813 // ... 814 // TrueVal = ... 815 // cmpTY ccX, r1, r2 816 // jCC copy1MBB 817 // fallthrough --> copy0MBB 818 MachineBasicBlock *thisMBB = BB; 819 MachineFunction *F = BB->getParent(); 820 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 821 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 822 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); 823 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); 824 F->insert(I, copy0MBB); 825 F->insert(I, copy1MBB); 826 // Inform sdisel of the edge changes. 827 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 828 SE = BB->succ_end(); SI != SE; ++SI) 829 EM->insert(std::make_pair(*SI, copy1MBB)); 830 // Update machine-CFG edges by transferring all successors of the current 831 // block to the new block which will contain the Phi node for the select. 832 copy1MBB->transferSuccessors(BB); 833 // Next, add the true and fallthrough blocks as its successors. 834 BB->addSuccessor(copy0MBB); 835 BB->addSuccessor(copy1MBB); 836 837 // copy0MBB: 838 // %FalseValue = ... 839 // # fallthrough to copy1MBB 840 BB = copy0MBB; 841 842 // Update machine-CFG edges 843 BB->addSuccessor(copy1MBB); 844 845 // copy1MBB: 846 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 847 // ... 848 BB = copy1MBB; 849 BuildMI(BB, dl, TII.get(SystemZ::PHI), 850 MI->getOperand(0).getReg()) 851 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 852 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 853 854 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 855 return BB; 856 } 857