1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "systemz-lower" 15 16 #include "SystemZISelLowering.h" 17 #include "SystemZ.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZSubtarget.h" 20 #include "llvm/DerivedTypes.h" 21 #include "llvm/Function.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/GlobalVariable.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/CodeGen/CallingConvLower.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/PseudoSourceValue.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 34 #include "llvm/CodeGen/ValueTypes.h" 35 #include "llvm/Target/TargetOptions.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/ADT/VectorExtras.h" 40 using namespace llvm; 41 42 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : 43 TargetLowering(tm, new TargetLoweringObjectFileELF()), 44 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 45 46 RegInfo = TM.getRegisterInfo(); 47 48 // Set up the register classes. 49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); 50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); 51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); 52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); 53 54 if (!UseSoftFloat) { 55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); 56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); 57 } 58 59 // Compute derived properties from the register classes 60 computeRegisterProperties(); 61 62 // Provide all sorts of operation actions 63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 66 67 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); 68 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); 69 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 70 71 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); 72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); 73 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 74 75 setStackPointerRegisterToSaveRestore(SystemZ::R15D); 76 77 // TODO: It may be better to default to latency-oriented scheduling, however 78 // LLVM's current latency-oriented scheduler can't handle physreg definitions 79 // such as SystemZ has with PSW, so set this to the register-pressure 80 // scheduler, because it can. 81 setSchedulingPreference(Sched::RegPressure); 82 83 setBooleanContents(ZeroOrOneBooleanContent); 84 85 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 86 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 87 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 88 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 89 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 90 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 93 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 94 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 96 97 setOperationAction(ISD::SDIV, MVT::i32, Expand); 98 setOperationAction(ISD::UDIV, MVT::i32, Expand); 99 setOperationAction(ISD::SDIV, MVT::i64, Expand); 100 setOperationAction(ISD::UDIV, MVT::i64, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i64, Expand); 104 setOperationAction(ISD::UREM, MVT::i64, Expand); 105 106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 107 108 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 109 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 110 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 111 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 112 setOperationAction(ISD::CTLZ, MVT::i32, Promote); 113 setOperationAction(ISD::CTLZ, MVT::i64, Legal); 114 115 // FIXME: Can we lower these 2 efficiently? 116 setOperationAction(ISD::SETCC, MVT::i32, Expand); 117 setOperationAction(ISD::SETCC, MVT::i64, Expand); 118 setOperationAction(ISD::SETCC, MVT::f32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f64, Expand); 120 setOperationAction(ISD::SELECT, MVT::i32, Expand); 121 setOperationAction(ISD::SELECT, MVT::i64, Expand); 122 setOperationAction(ISD::SELECT, MVT::f32, Expand); 123 setOperationAction(ISD::SELECT, MVT::f64, Expand); 124 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 125 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 128 129 setOperationAction(ISD::MULHS, MVT::i64, Expand); 130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 131 132 // FIXME: Can we support these natively? 133 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 134 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 135 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 136 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 137 138 // Lower some FP stuff 139 setOperationAction(ISD::FSIN, MVT::f32, Expand); 140 setOperationAction(ISD::FSIN, MVT::f64, Expand); 141 setOperationAction(ISD::FCOS, MVT::f32, Expand); 142 setOperationAction(ISD::FCOS, MVT::f64, Expand); 143 setOperationAction(ISD::FREM, MVT::f32, Expand); 144 setOperationAction(ISD::FREM, MVT::f64, Expand); 145 setOperationAction(ISD::FMA, MVT::f32, Expand); 146 setOperationAction(ISD::FMA, MVT::f64, Expand); 147 148 // We have only 64-bit bitconverts 149 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 150 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 151 152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 153 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 154 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 155 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 156 157 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 158 159 setMinFunctionAlignment(1); 160 } 161 162 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, 163 SelectionDAG &DAG) const { 164 switch (Op.getOpcode()) { 165 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 166 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 167 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 168 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 169 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 170 default: 171 llvm_unreachable("Should not custom lower this!"); 172 return SDValue(); 173 } 174 } 175 176 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 177 if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64)) 178 return false; 179 180 // +0.0 lzer 181 // +0.0f lzdr 182 // -0.0 lzer + lner 183 // -0.0f lzdr + lndr 184 return Imm.isZero() || Imm.isNegZero(); 185 } 186 187 //===----------------------------------------------------------------------===// 188 // SystemZ Inline Assembly Support 189 //===----------------------------------------------------------------------===// 190 191 /// getConstraintType - Given a constraint letter, return the type of 192 /// constraint it is for this target. 193 TargetLowering::ConstraintType 194 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const { 195 if (Constraint.size() == 1) { 196 switch (Constraint[0]) { 197 case 'r': 198 return C_RegisterClass; 199 default: 200 break; 201 } 202 } 203 return TargetLowering::getConstraintType(Constraint); 204 } 205 206 std::pair<unsigned, const TargetRegisterClass*> 207 SystemZTargetLowering:: 208 getRegForInlineAsmConstraint(const std::string &Constraint, 209 EVT VT) const { 210 if (Constraint.size() == 1) { 211 // GCC Constraint Letters 212 switch (Constraint[0]) { 213 default: break; 214 case 'r': // GENERAL_REGS 215 if (VT == MVT::i32) 216 return std::make_pair(0U, SystemZ::GR32RegisterClass); 217 else if (VT == MVT::i128) 218 return std::make_pair(0U, SystemZ::GR128RegisterClass); 219 220 return std::make_pair(0U, SystemZ::GR64RegisterClass); 221 } 222 } 223 224 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 225 } 226 227 //===----------------------------------------------------------------------===// 228 // Calling Convention Implementation 229 //===----------------------------------------------------------------------===// 230 231 #include "SystemZGenCallingConv.inc" 232 233 SDValue 234 SystemZTargetLowering::LowerFormalArguments(SDValue Chain, 235 CallingConv::ID CallConv, 236 bool isVarArg, 237 const SmallVectorImpl<ISD::InputArg> 238 &Ins, 239 DebugLoc dl, 240 SelectionDAG &DAG, 241 SmallVectorImpl<SDValue> &InVals) 242 const { 243 244 switch (CallConv) { 245 default: 246 llvm_unreachable("Unsupported calling convention"); 247 case CallingConv::C: 248 case CallingConv::Fast: 249 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 250 } 251 } 252 253 SDValue 254 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 255 CallingConv::ID CallConv, bool isVarArg, 256 bool &isTailCall, 257 const SmallVectorImpl<ISD::OutputArg> &Outs, 258 const SmallVectorImpl<SDValue> &OutVals, 259 const SmallVectorImpl<ISD::InputArg> &Ins, 260 DebugLoc dl, SelectionDAG &DAG, 261 SmallVectorImpl<SDValue> &InVals) const { 262 // SystemZ target does not yet support tail call optimization. 263 isTailCall = false; 264 265 switch (CallConv) { 266 default: 267 llvm_unreachable("Unsupported calling convention"); 268 case CallingConv::Fast: 269 case CallingConv::C: 270 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 271 Outs, OutVals, Ins, dl, DAG, InVals); 272 } 273 } 274 275 /// LowerCCCArguments - transform physical registers into virtual registers and 276 /// generate load operations for arguments places on the stack. 277 // FIXME: struct return stuff 278 // FIXME: varargs 279 SDValue 280 SystemZTargetLowering::LowerCCCArguments(SDValue Chain, 281 CallingConv::ID CallConv, 282 bool isVarArg, 283 const SmallVectorImpl<ISD::InputArg> 284 &Ins, 285 DebugLoc dl, 286 SelectionDAG &DAG, 287 SmallVectorImpl<SDValue> &InVals) 288 const { 289 290 MachineFunction &MF = DAG.getMachineFunction(); 291 MachineFrameInfo *MFI = MF.getFrameInfo(); 292 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 293 294 // Assign locations to all of the incoming arguments. 295 SmallVector<CCValAssign, 16> ArgLocs; 296 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 297 getTargetMachine(), ArgLocs, *DAG.getContext()); 298 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); 299 300 if (isVarArg) 301 report_fatal_error("Varargs not supported yet"); 302 303 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 304 SDValue ArgValue; 305 CCValAssign &VA = ArgLocs[i]; 306 EVT LocVT = VA.getLocVT(); 307 if (VA.isRegLoc()) { 308 // Arguments passed in registers 309 TargetRegisterClass *RC; 310 switch (LocVT.getSimpleVT().SimpleTy) { 311 default: 312 #ifndef NDEBUG 313 errs() << "LowerFormalArguments Unhandled argument type: " 314 << LocVT.getSimpleVT().SimpleTy 315 << "\n"; 316 #endif 317 llvm_unreachable(0); 318 case MVT::i64: 319 RC = SystemZ::GR64RegisterClass; 320 break; 321 case MVT::f32: 322 RC = SystemZ::FP32RegisterClass; 323 break; 324 case MVT::f64: 325 RC = SystemZ::FP64RegisterClass; 326 break; 327 } 328 329 unsigned VReg = RegInfo.createVirtualRegister(RC); 330 RegInfo.addLiveIn(VA.getLocReg(), VReg); 331 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT); 332 } else { 333 // Sanity check 334 assert(VA.isMemLoc()); 335 336 // Create the nodes corresponding to a load from this parameter slot. 337 // Create the frame index object for this incoming parameter... 338 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, 339 VA.getLocMemOffset(), true); 340 341 // Create the SelectionDAG nodes corresponding to a load 342 // from this parameter 343 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 344 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN, 345 MachinePointerInfo::getFixedStack(FI), 346 false, false, 0); 347 } 348 349 // If this is an 8/16/32-bit value, it is really passed promoted to 64 350 // bits. Insert an assert[sz]ext to capture this, then truncate to the 351 // right size. 352 if (VA.getLocInfo() == CCValAssign::SExt) 353 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 354 DAG.getValueType(VA.getValVT())); 355 else if (VA.getLocInfo() == CCValAssign::ZExt) 356 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, 357 DAG.getValueType(VA.getValVT())); 358 359 if (VA.getLocInfo() != CCValAssign::Full) 360 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 361 362 InVals.push_back(ArgValue); 363 } 364 365 return Chain; 366 } 367 368 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 369 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 370 /// TODO: sret. 371 SDValue 372 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 373 CallingConv::ID CallConv, bool isVarArg, 374 bool isTailCall, 375 const SmallVectorImpl<ISD::OutputArg> 376 &Outs, 377 const SmallVectorImpl<SDValue> &OutVals, 378 const SmallVectorImpl<ISD::InputArg> &Ins, 379 DebugLoc dl, SelectionDAG &DAG, 380 SmallVectorImpl<SDValue> &InVals) const { 381 MachineFunction &MF = DAG.getMachineFunction(); 382 const TargetFrameLowering *TFI = TM.getFrameLowering(); 383 384 // Offset to first argument stack slot. 385 const unsigned FirstArgOffset = 160; 386 387 // Analyze operands of the call, assigning locations to each operand. 388 SmallVector<CCValAssign, 16> ArgLocs; 389 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 390 getTargetMachine(), ArgLocs, *DAG.getContext()); 391 392 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); 393 394 // Get a count of how many bytes are to be pushed on the stack. 395 unsigned NumBytes = CCInfo.getNextStackOffset(); 396 397 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 398 getPointerTy(), true)); 399 400 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 401 SmallVector<SDValue, 12> MemOpChains; 402 SDValue StackPtr; 403 404 // Walk the register/memloc assignments, inserting copies/loads. 405 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 406 CCValAssign &VA = ArgLocs[i]; 407 408 SDValue Arg = OutVals[i]; 409 410 // Promote the value if needed. 411 switch (VA.getLocInfo()) { 412 default: assert(0 && "Unknown loc info!"); 413 case CCValAssign::Full: break; 414 case CCValAssign::SExt: 415 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 416 break; 417 case CCValAssign::ZExt: 418 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 419 break; 420 case CCValAssign::AExt: 421 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 422 break; 423 } 424 425 // Arguments that can be passed on register must be kept at RegsToPass 426 // vector 427 if (VA.isRegLoc()) { 428 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 429 } else { 430 assert(VA.isMemLoc()); 431 432 if (StackPtr.getNode() == 0) 433 StackPtr = 434 DAG.getCopyFromReg(Chain, dl, 435 (TFI->hasFP(MF) ? 436 SystemZ::R11D : SystemZ::R15D), 437 getPointerTy()); 438 439 unsigned Offset = FirstArgOffset + VA.getLocMemOffset(); 440 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 441 StackPtr, 442 DAG.getIntPtrConstant(Offset)); 443 444 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 445 MachinePointerInfo(), 446 false, false, 0)); 447 } 448 } 449 450 // Transform all store nodes into one single node because all store nodes are 451 // independent of each other. 452 if (!MemOpChains.empty()) 453 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 454 &MemOpChains[0], MemOpChains.size()); 455 456 // Build a sequence of copy-to-reg nodes chained together with token chain and 457 // flag operands which copy the outgoing args into registers. The InFlag in 458 // necessary since all emitted instructions must be stuck together. 459 SDValue InFlag; 460 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 461 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 462 RegsToPass[i].second, InFlag); 463 InFlag = Chain.getValue(1); 464 } 465 466 // If the callee is a GlobalAddress node (quite common, every direct call is) 467 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 468 // Likewise ExternalSymbol -> TargetExternalSymbol. 469 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 470 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 471 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 472 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 473 474 // Returns a chain & a flag for retval copy to use. 475 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 476 SmallVector<SDValue, 8> Ops; 477 Ops.push_back(Chain); 478 Ops.push_back(Callee); 479 480 // Add argument registers to the end of the list so that they are 481 // known live into the call. 482 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 483 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 484 RegsToPass[i].second.getValueType())); 485 486 if (InFlag.getNode()) 487 Ops.push_back(InFlag); 488 489 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 490 InFlag = Chain.getValue(1); 491 492 // Create the CALLSEQ_END node. 493 Chain = DAG.getCALLSEQ_END(Chain, 494 DAG.getConstant(NumBytes, getPointerTy(), true), 495 DAG.getConstant(0, getPointerTy(), true), 496 InFlag); 497 InFlag = Chain.getValue(1); 498 499 // Handle result values, copying them out of physregs into vregs that we 500 // return. 501 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 502 DAG, InVals); 503 } 504 505 /// LowerCallResult - Lower the result values of a call into the 506 /// appropriate copies out of appropriate physical registers. 507 /// 508 SDValue 509 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 510 CallingConv::ID CallConv, bool isVarArg, 511 const SmallVectorImpl<ISD::InputArg> 512 &Ins, 513 DebugLoc dl, SelectionDAG &DAG, 514 SmallVectorImpl<SDValue> &InVals) const { 515 516 // Assign locations to each value returned by this call. 517 SmallVector<CCValAssign, 16> RVLocs; 518 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 519 getTargetMachine(), RVLocs, *DAG.getContext()); 520 521 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); 522 523 // Copy all of the result registers out of their specified physreg. 524 for (unsigned i = 0; i != RVLocs.size(); ++i) { 525 CCValAssign &VA = RVLocs[i]; 526 527 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 528 VA.getLocVT(), InFlag).getValue(1); 529 SDValue RetValue = Chain.getValue(0); 530 InFlag = Chain.getValue(2); 531 532 // If this is an 8/16/32-bit value, it is really passed promoted to 64 533 // bits. Insert an assert[sz]ext to capture this, then truncate to the 534 // right size. 535 if (VA.getLocInfo() == CCValAssign::SExt) 536 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, 537 DAG.getValueType(VA.getValVT())); 538 else if (VA.getLocInfo() == CCValAssign::ZExt) 539 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, 540 DAG.getValueType(VA.getValVT())); 541 542 if (VA.getLocInfo() != CCValAssign::Full) 543 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue); 544 545 InVals.push_back(RetValue); 546 } 547 548 return Chain; 549 } 550 551 552 SDValue 553 SystemZTargetLowering::LowerReturn(SDValue Chain, 554 CallingConv::ID CallConv, bool isVarArg, 555 const SmallVectorImpl<ISD::OutputArg> &Outs, 556 const SmallVectorImpl<SDValue> &OutVals, 557 DebugLoc dl, SelectionDAG &DAG) const { 558 559 // CCValAssign - represent the assignment of the return value to a location 560 SmallVector<CCValAssign, 16> RVLocs; 561 562 // CCState - Info about the registers and stack slot. 563 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 564 getTargetMachine(), RVLocs, *DAG.getContext()); 565 566 // Analize return values. 567 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); 568 569 // If this is the first return lowered for this function, add the regs to the 570 // liveout set for the function. 571 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 572 for (unsigned i = 0; i != RVLocs.size(); ++i) 573 if (RVLocs[i].isRegLoc()) 574 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 575 } 576 577 SDValue Flag; 578 579 // Copy the result values into the output registers. 580 for (unsigned i = 0; i != RVLocs.size(); ++i) { 581 CCValAssign &VA = RVLocs[i]; 582 SDValue ResValue = OutVals[i]; 583 assert(VA.isRegLoc() && "Can only return in registers!"); 584 585 // If this is an 8/16/32-bit value, it is really should be passed promoted 586 // to 64 bits. 587 if (VA.getLocInfo() == CCValAssign::SExt) 588 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); 589 else if (VA.getLocInfo() == CCValAssign::ZExt) 590 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); 591 else if (VA.getLocInfo() == CCValAssign::AExt) 592 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); 593 594 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); 595 596 // Guarantee that all emitted copies are stuck together, 597 // avoiding something bad. 598 Flag = Chain.getValue(1); 599 } 600 601 if (Flag.getNode()) 602 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 603 604 // Return Void 605 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); 606 } 607 608 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, 609 ISD::CondCode CC, SDValue &SystemZCC, 610 SelectionDAG &DAG) const { 611 // FIXME: Emit a test if RHS is zero 612 613 bool isUnsigned = false; 614 SystemZCC::CondCodes TCC; 615 switch (CC) { 616 default: 617 llvm_unreachable("Invalid integer condition!"); 618 case ISD::SETEQ: 619 case ISD::SETOEQ: 620 TCC = SystemZCC::E; 621 break; 622 case ISD::SETUEQ: 623 TCC = SystemZCC::NLH; 624 break; 625 case ISD::SETNE: 626 case ISD::SETONE: 627 TCC = SystemZCC::NE; 628 break; 629 case ISD::SETUNE: 630 TCC = SystemZCC::LH; 631 break; 632 case ISD::SETO: 633 TCC = SystemZCC::O; 634 break; 635 case ISD::SETUO: 636 TCC = SystemZCC::NO; 637 break; 638 case ISD::SETULE: 639 if (LHS.getValueType().isFloatingPoint()) { 640 TCC = SystemZCC::NH; 641 break; 642 } 643 isUnsigned = true; // FALLTHROUGH 644 case ISD::SETLE: 645 case ISD::SETOLE: 646 TCC = SystemZCC::LE; 647 break; 648 case ISD::SETUGE: 649 if (LHS.getValueType().isFloatingPoint()) { 650 TCC = SystemZCC::NL; 651 break; 652 } 653 isUnsigned = true; // FALLTHROUGH 654 case ISD::SETGE: 655 case ISD::SETOGE: 656 TCC = SystemZCC::HE; 657 break; 658 case ISD::SETUGT: 659 if (LHS.getValueType().isFloatingPoint()) { 660 TCC = SystemZCC::NLE; 661 break; 662 } 663 isUnsigned = true; // FALLTHROUGH 664 case ISD::SETGT: 665 case ISD::SETOGT: 666 TCC = SystemZCC::H; 667 break; 668 case ISD::SETULT: 669 if (LHS.getValueType().isFloatingPoint()) { 670 TCC = SystemZCC::NHE; 671 break; 672 } 673 isUnsigned = true; // FALLTHROUGH 674 case ISD::SETLT: 675 case ISD::SETOLT: 676 TCC = SystemZCC::L; 677 break; 678 } 679 680 SystemZCC = DAG.getConstant(TCC, MVT::i32); 681 682 DebugLoc dl = LHS.getDebugLoc(); 683 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), 684 dl, MVT::i64, LHS, RHS); 685 } 686 687 688 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 689 SDValue Chain = Op.getOperand(0); 690 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 691 SDValue LHS = Op.getOperand(2); 692 SDValue RHS = Op.getOperand(3); 693 SDValue Dest = Op.getOperand(4); 694 DebugLoc dl = Op.getDebugLoc(); 695 696 SDValue SystemZCC; 697 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 698 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(), 699 Chain, Dest, SystemZCC, Flag); 700 } 701 702 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, 703 SelectionDAG &DAG) const { 704 SDValue LHS = Op.getOperand(0); 705 SDValue RHS = Op.getOperand(1); 706 SDValue TrueV = Op.getOperand(2); 707 SDValue FalseV = Op.getOperand(3); 708 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 709 DebugLoc dl = Op.getDebugLoc(); 710 711 SDValue SystemZCC; 712 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 713 714 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 715 SmallVector<SDValue, 4> Ops; 716 Ops.push_back(TrueV); 717 Ops.push_back(FalseV); 718 Ops.push_back(SystemZCC); 719 Ops.push_back(Flag); 720 721 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size()); 722 } 723 724 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, 725 SelectionDAG &DAG) const { 726 DebugLoc dl = Op.getDebugLoc(); 727 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 728 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 729 730 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 731 bool ExtraLoadRequired = 732 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false); 733 734 SDValue Result; 735 if (!IsPic && !ExtraLoadRequired) { 736 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 737 Offset = 0; 738 } else { 739 unsigned char OpFlags = 0; 740 if (ExtraLoadRequired) 741 OpFlags = SystemZII::MO_GOTENT; 742 743 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 744 } 745 746 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl, 747 getPointerTy(), Result); 748 749 if (ExtraLoadRequired) 750 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 751 MachinePointerInfo::getGOT(), false, false, 0); 752 753 // If there was a non-zero offset that we didn't fold, create an explicit 754 // addition for it. 755 if (Offset != 0) 756 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 757 DAG.getConstant(Offset, getPointerTy())); 758 759 return Result; 760 } 761 762 // FIXME: PIC here 763 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, 764 SelectionDAG &DAG) const { 765 DebugLoc dl = Op.getDebugLoc(); 766 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 767 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 768 769 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 770 } 771 772 773 // FIXME: PIC here 774 // FIXME: This is just dirty hack. We need to lower cpool properly 775 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, 776 SelectionDAG &DAG) const { 777 DebugLoc dl = Op.getDebugLoc(); 778 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 779 780 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 781 CP->getAlignment(), 782 CP->getOffset()); 783 784 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 785 } 786 787 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { 788 switch (Opcode) { 789 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG"; 790 case SystemZISD::CALL: return "SystemZISD::CALL"; 791 case SystemZISD::BRCOND: return "SystemZISD::BRCOND"; 792 case SystemZISD::CMP: return "SystemZISD::CMP"; 793 case SystemZISD::UCMP: return "SystemZISD::UCMP"; 794 case SystemZISD::SELECT: return "SystemZISD::SELECT"; 795 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper"; 796 default: return NULL; 797 } 798 } 799 800 //===----------------------------------------------------------------------===// 801 // Other Lowering Code 802 //===----------------------------------------------------------------------===// 803 804 MachineBasicBlock* 805 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 806 MachineBasicBlock *BB) const { 807 const SystemZInstrInfo &TII = *TM.getInstrInfo(); 808 DebugLoc dl = MI->getDebugLoc(); 809 assert((MI->getOpcode() == SystemZ::Select32 || 810 MI->getOpcode() == SystemZ::SelectF32 || 811 MI->getOpcode() == SystemZ::Select64 || 812 MI->getOpcode() == SystemZ::SelectF64) && 813 "Unexpected instr type to insert"); 814 815 // To "insert" a SELECT instruction, we actually have to insert the diamond 816 // control-flow pattern. The incoming instruction knows the destination vreg 817 // to set, the condition code register to branch on, the true/false values to 818 // select between, and a branch opcode to use. 819 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 820 MachineFunction::iterator I = BB; 821 ++I; 822 823 // thisMBB: 824 // ... 825 // TrueVal = ... 826 // cmpTY ccX, r1, r2 827 // jCC copy1MBB 828 // fallthrough --> copy0MBB 829 MachineBasicBlock *thisMBB = BB; 830 MachineFunction *F = BB->getParent(); 831 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 832 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 833 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); 834 F->insert(I, copy0MBB); 835 F->insert(I, copy1MBB); 836 // Update machine-CFG edges by transferring all successors of the current 837 // block to the new block which will contain the Phi node for the select. 838 copy1MBB->splice(copy1MBB->begin(), BB, 839 llvm::next(MachineBasicBlock::iterator(MI)), 840 BB->end()); 841 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 842 // Next, add the true and fallthrough blocks as its successors. 843 BB->addSuccessor(copy0MBB); 844 BB->addSuccessor(copy1MBB); 845 846 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); 847 848 // copy0MBB: 849 // %FalseValue = ... 850 // # fallthrough to copy1MBB 851 BB = copy0MBB; 852 853 // Update machine-CFG edges 854 BB->addSuccessor(copy1MBB); 855 856 // copy1MBB: 857 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 858 // ... 859 BB = copy1MBB; 860 BuildMI(*BB, BB->begin(), dl, TII.get(SystemZ::PHI), 861 MI->getOperand(0).getReg()) 862 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 863 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 864 865 MI->eraseFromParent(); // The pseudo instruction is gone now. 866 return BB; 867 } 868