1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "systemz-lower" 15 16 #include "SystemZISelLowering.h" 17 #include "SystemZ.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZSubtarget.h" 20 #include "llvm/DerivedTypes.h" 21 #include "llvm/Function.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/GlobalVariable.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/CodeGen/CallingConvLower.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/PseudoSourceValue.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 34 #include "llvm/CodeGen/ValueTypes.h" 35 #include "llvm/Target/TargetOptions.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/ADT/VectorExtras.h" 40 using namespace llvm; 41 42 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : 43 TargetLowering(tm, new TargetLoweringObjectFileELF()), 44 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 45 46 RegInfo = TM.getRegisterInfo(); 47 48 // Set up the register classes. 49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); 50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); 51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); 52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); 53 54 if (!UseSoftFloat) { 55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); 56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); 57 } 58 59 // Compute derived properties from the register classes 60 computeRegisterProperties(); 61 62 // Provide all sorts of operation actions 63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 66 67 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); 68 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); 69 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 70 71 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); 72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); 73 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 74 75 setStackPointerRegisterToSaveRestore(SystemZ::R15D); 76 77 // TODO: It may be better to default to latency-oriented scheduling, however 78 // LLVM's current latency-oriented scheduler can't handle physreg definitions 79 // such as SystemZ has with PSW, so set this to the register-pressure 80 // scheduler, because it can. 81 setSchedulingPreference(Sched::RegPressure); 82 83 setBooleanContents(ZeroOrOneBooleanContent); 84 85 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 86 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 87 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 88 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 89 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 90 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 93 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 94 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 96 97 setOperationAction(ISD::SDIV, MVT::i32, Expand); 98 setOperationAction(ISD::UDIV, MVT::i32, Expand); 99 setOperationAction(ISD::SDIV, MVT::i64, Expand); 100 setOperationAction(ISD::UDIV, MVT::i64, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i64, Expand); 104 setOperationAction(ISD::UREM, MVT::i64, Expand); 105 106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 107 108 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 109 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 110 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 111 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 112 setOperationAction(ISD::CTLZ, MVT::i32, Promote); 113 setOperationAction(ISD::CTLZ, MVT::i64, Legal); 114 115 // FIXME: Can we lower these 2 efficiently? 116 setOperationAction(ISD::SETCC, MVT::i32, Expand); 117 setOperationAction(ISD::SETCC, MVT::i64, Expand); 118 setOperationAction(ISD::SETCC, MVT::f32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f64, Expand); 120 setOperationAction(ISD::SELECT, MVT::i32, Expand); 121 setOperationAction(ISD::SELECT, MVT::i64, Expand); 122 setOperationAction(ISD::SELECT, MVT::f32, Expand); 123 setOperationAction(ISD::SELECT, MVT::f64, Expand); 124 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 125 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 128 129 setOperationAction(ISD::MULHS, MVT::i64, Expand); 130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 131 132 // FIXME: Can we support these natively? 133 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 134 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 135 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 136 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 137 138 // Lower some FP stuff 139 setOperationAction(ISD::FSIN, MVT::f32, Expand); 140 setOperationAction(ISD::FSIN, MVT::f64, Expand); 141 setOperationAction(ISD::FCOS, MVT::f32, Expand); 142 setOperationAction(ISD::FCOS, MVT::f64, Expand); 143 setOperationAction(ISD::FREM, MVT::f32, Expand); 144 setOperationAction(ISD::FREM, MVT::f64, Expand); 145 146 // We have only 64-bit bitconverts 147 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 148 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 149 150 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 151 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 152 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 153 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 154 155 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 156 } 157 158 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, 159 SelectionDAG &DAG) const { 160 switch (Op.getOpcode()) { 161 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 162 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 163 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 164 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 165 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 166 default: 167 llvm_unreachable("Should not custom lower this!"); 168 return SDValue(); 169 } 170 } 171 172 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 173 if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64)) 174 return false; 175 176 // +0.0 lzer 177 // +0.0f lzdr 178 // -0.0 lzer + lner 179 // -0.0f lzdr + lndr 180 return Imm.isZero() || Imm.isNegZero(); 181 } 182 183 //===----------------------------------------------------------------------===// 184 // SystemZ Inline Assembly Support 185 //===----------------------------------------------------------------------===// 186 187 /// getConstraintType - Given a constraint letter, return the type of 188 /// constraint it is for this target. 189 TargetLowering::ConstraintType 190 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const { 191 if (Constraint.size() == 1) { 192 switch (Constraint[0]) { 193 case 'r': 194 return C_RegisterClass; 195 default: 196 break; 197 } 198 } 199 return TargetLowering::getConstraintType(Constraint); 200 } 201 202 std::pair<unsigned, const TargetRegisterClass*> 203 SystemZTargetLowering:: 204 getRegForInlineAsmConstraint(const std::string &Constraint, 205 EVT VT) const { 206 if (Constraint.size() == 1) { 207 // GCC Constraint Letters 208 switch (Constraint[0]) { 209 default: break; 210 case 'r': // GENERAL_REGS 211 if (VT == MVT::i32) 212 return std::make_pair(0U, SystemZ::GR32RegisterClass); 213 else if (VT == MVT::i128) 214 return std::make_pair(0U, SystemZ::GR128RegisterClass); 215 216 return std::make_pair(0U, SystemZ::GR64RegisterClass); 217 } 218 } 219 220 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 221 } 222 223 //===----------------------------------------------------------------------===// 224 // Calling Convention Implementation 225 //===----------------------------------------------------------------------===// 226 227 #include "SystemZGenCallingConv.inc" 228 229 SDValue 230 SystemZTargetLowering::LowerFormalArguments(SDValue Chain, 231 CallingConv::ID CallConv, 232 bool isVarArg, 233 const SmallVectorImpl<ISD::InputArg> 234 &Ins, 235 DebugLoc dl, 236 SelectionDAG &DAG, 237 SmallVectorImpl<SDValue> &InVals) 238 const { 239 240 switch (CallConv) { 241 default: 242 llvm_unreachable("Unsupported calling convention"); 243 case CallingConv::C: 244 case CallingConv::Fast: 245 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 246 } 247 } 248 249 SDValue 250 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 251 CallingConv::ID CallConv, bool isVarArg, 252 bool &isTailCall, 253 const SmallVectorImpl<ISD::OutputArg> &Outs, 254 const SmallVectorImpl<SDValue> &OutVals, 255 const SmallVectorImpl<ISD::InputArg> &Ins, 256 DebugLoc dl, SelectionDAG &DAG, 257 SmallVectorImpl<SDValue> &InVals) const { 258 // SystemZ target does not yet support tail call optimization. 259 isTailCall = false; 260 261 switch (CallConv) { 262 default: 263 llvm_unreachable("Unsupported calling convention"); 264 case CallingConv::Fast: 265 case CallingConv::C: 266 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 267 Outs, OutVals, Ins, dl, DAG, InVals); 268 } 269 } 270 271 /// LowerCCCArguments - transform physical registers into virtual registers and 272 /// generate load operations for arguments places on the stack. 273 // FIXME: struct return stuff 274 // FIXME: varargs 275 SDValue 276 SystemZTargetLowering::LowerCCCArguments(SDValue Chain, 277 CallingConv::ID CallConv, 278 bool isVarArg, 279 const SmallVectorImpl<ISD::InputArg> 280 &Ins, 281 DebugLoc dl, 282 SelectionDAG &DAG, 283 SmallVectorImpl<SDValue> &InVals) 284 const { 285 286 MachineFunction &MF = DAG.getMachineFunction(); 287 MachineFrameInfo *MFI = MF.getFrameInfo(); 288 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 289 290 // Assign locations to all of the incoming arguments. 291 SmallVector<CCValAssign, 16> ArgLocs; 292 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 293 ArgLocs, *DAG.getContext()); 294 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); 295 296 if (isVarArg) 297 report_fatal_error("Varargs not supported yet"); 298 299 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 300 SDValue ArgValue; 301 CCValAssign &VA = ArgLocs[i]; 302 EVT LocVT = VA.getLocVT(); 303 if (VA.isRegLoc()) { 304 // Arguments passed in registers 305 TargetRegisterClass *RC; 306 switch (LocVT.getSimpleVT().SimpleTy) { 307 default: 308 #ifndef NDEBUG 309 errs() << "LowerFormalArguments Unhandled argument type: " 310 << LocVT.getSimpleVT().SimpleTy 311 << "\n"; 312 #endif 313 llvm_unreachable(0); 314 case MVT::i64: 315 RC = SystemZ::GR64RegisterClass; 316 break; 317 case MVT::f32: 318 RC = SystemZ::FP32RegisterClass; 319 break; 320 case MVT::f64: 321 RC = SystemZ::FP64RegisterClass; 322 break; 323 } 324 325 unsigned VReg = RegInfo.createVirtualRegister(RC); 326 RegInfo.addLiveIn(VA.getLocReg(), VReg); 327 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT); 328 } else { 329 // Sanity check 330 assert(VA.isMemLoc()); 331 332 // Create the nodes corresponding to a load from this parameter slot. 333 // Create the frame index object for this incoming parameter... 334 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, 335 VA.getLocMemOffset(), true); 336 337 // Create the SelectionDAG nodes corresponding to a load 338 // from this parameter 339 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 340 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN, 341 MachinePointerInfo::getFixedStack(FI), 342 false, false, 0); 343 } 344 345 // If this is an 8/16/32-bit value, it is really passed promoted to 64 346 // bits. Insert an assert[sz]ext to capture this, then truncate to the 347 // right size. 348 if (VA.getLocInfo() == CCValAssign::SExt) 349 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 350 DAG.getValueType(VA.getValVT())); 351 else if (VA.getLocInfo() == CCValAssign::ZExt) 352 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, 353 DAG.getValueType(VA.getValVT())); 354 355 if (VA.getLocInfo() != CCValAssign::Full) 356 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 357 358 InVals.push_back(ArgValue); 359 } 360 361 return Chain; 362 } 363 364 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 365 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 366 /// TODO: sret. 367 SDValue 368 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 369 CallingConv::ID CallConv, bool isVarArg, 370 bool isTailCall, 371 const SmallVectorImpl<ISD::OutputArg> 372 &Outs, 373 const SmallVectorImpl<SDValue> &OutVals, 374 const SmallVectorImpl<ISD::InputArg> &Ins, 375 DebugLoc dl, SelectionDAG &DAG, 376 SmallVectorImpl<SDValue> &InVals) const { 377 MachineFunction &MF = DAG.getMachineFunction(); 378 const TargetFrameLowering *TFI = TM.getFrameLowering(); 379 380 // Offset to first argument stack slot. 381 const unsigned FirstArgOffset = 160; 382 383 // Analyze operands of the call, assigning locations to each operand. 384 SmallVector<CCValAssign, 16> ArgLocs; 385 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 386 ArgLocs, *DAG.getContext()); 387 388 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); 389 390 // Get a count of how many bytes are to be pushed on the stack. 391 unsigned NumBytes = CCInfo.getNextStackOffset(); 392 393 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 394 getPointerTy(), true)); 395 396 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 397 SmallVector<SDValue, 12> MemOpChains; 398 SDValue StackPtr; 399 400 // Walk the register/memloc assignments, inserting copies/loads. 401 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 402 CCValAssign &VA = ArgLocs[i]; 403 404 SDValue Arg = OutVals[i]; 405 406 // Promote the value if needed. 407 switch (VA.getLocInfo()) { 408 default: assert(0 && "Unknown loc info!"); 409 case CCValAssign::Full: break; 410 case CCValAssign::SExt: 411 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 412 break; 413 case CCValAssign::ZExt: 414 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 415 break; 416 case CCValAssign::AExt: 417 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 418 break; 419 } 420 421 // Arguments that can be passed on register must be kept at RegsToPass 422 // vector 423 if (VA.isRegLoc()) { 424 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 425 } else { 426 assert(VA.isMemLoc()); 427 428 if (StackPtr.getNode() == 0) 429 StackPtr = 430 DAG.getCopyFromReg(Chain, dl, 431 (TFI->hasFP(MF) ? 432 SystemZ::R11D : SystemZ::R15D), 433 getPointerTy()); 434 435 unsigned Offset = FirstArgOffset + VA.getLocMemOffset(); 436 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 437 StackPtr, 438 DAG.getIntPtrConstant(Offset)); 439 440 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 441 MachinePointerInfo(), 442 false, false, 0)); 443 } 444 } 445 446 // Transform all store nodes into one single node because all store nodes are 447 // independent of each other. 448 if (!MemOpChains.empty()) 449 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 450 &MemOpChains[0], MemOpChains.size()); 451 452 // Build a sequence of copy-to-reg nodes chained together with token chain and 453 // flag operands which copy the outgoing args into registers. The InFlag in 454 // necessary since all emitted instructions must be stuck together. 455 SDValue InFlag; 456 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 457 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 458 RegsToPass[i].second, InFlag); 459 InFlag = Chain.getValue(1); 460 } 461 462 // If the callee is a GlobalAddress node (quite common, every direct call is) 463 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 464 // Likewise ExternalSymbol -> TargetExternalSymbol. 465 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 466 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 467 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 468 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 469 470 // Returns a chain & a flag for retval copy to use. 471 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 472 SmallVector<SDValue, 8> Ops; 473 Ops.push_back(Chain); 474 Ops.push_back(Callee); 475 476 // Add argument registers to the end of the list so that they are 477 // known live into the call. 478 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 479 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 480 RegsToPass[i].second.getValueType())); 481 482 if (InFlag.getNode()) 483 Ops.push_back(InFlag); 484 485 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 486 InFlag = Chain.getValue(1); 487 488 // Create the CALLSEQ_END node. 489 Chain = DAG.getCALLSEQ_END(Chain, 490 DAG.getConstant(NumBytes, getPointerTy(), true), 491 DAG.getConstant(0, getPointerTy(), true), 492 InFlag); 493 InFlag = Chain.getValue(1); 494 495 // Handle result values, copying them out of physregs into vregs that we 496 // return. 497 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 498 DAG, InVals); 499 } 500 501 /// LowerCallResult - Lower the result values of a call into the 502 /// appropriate copies out of appropriate physical registers. 503 /// 504 SDValue 505 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 506 CallingConv::ID CallConv, bool isVarArg, 507 const SmallVectorImpl<ISD::InputArg> 508 &Ins, 509 DebugLoc dl, SelectionDAG &DAG, 510 SmallVectorImpl<SDValue> &InVals) const { 511 512 // Assign locations to each value returned by this call. 513 SmallVector<CCValAssign, 16> RVLocs; 514 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 515 *DAG.getContext()); 516 517 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); 518 519 // Copy all of the result registers out of their specified physreg. 520 for (unsigned i = 0; i != RVLocs.size(); ++i) { 521 CCValAssign &VA = RVLocs[i]; 522 523 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 524 VA.getLocVT(), InFlag).getValue(1); 525 SDValue RetValue = Chain.getValue(0); 526 InFlag = Chain.getValue(2); 527 528 // If this is an 8/16/32-bit value, it is really passed promoted to 64 529 // bits. Insert an assert[sz]ext to capture this, then truncate to the 530 // right size. 531 if (VA.getLocInfo() == CCValAssign::SExt) 532 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, 533 DAG.getValueType(VA.getValVT())); 534 else if (VA.getLocInfo() == CCValAssign::ZExt) 535 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, 536 DAG.getValueType(VA.getValVT())); 537 538 if (VA.getLocInfo() != CCValAssign::Full) 539 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue); 540 541 InVals.push_back(RetValue); 542 } 543 544 return Chain; 545 } 546 547 548 SDValue 549 SystemZTargetLowering::LowerReturn(SDValue Chain, 550 CallingConv::ID CallConv, bool isVarArg, 551 const SmallVectorImpl<ISD::OutputArg> &Outs, 552 const SmallVectorImpl<SDValue> &OutVals, 553 DebugLoc dl, SelectionDAG &DAG) const { 554 555 // CCValAssign - represent the assignment of the return value to a location 556 SmallVector<CCValAssign, 16> RVLocs; 557 558 // CCState - Info about the registers and stack slot. 559 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 560 RVLocs, *DAG.getContext()); 561 562 // Analize return values. 563 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); 564 565 // If this is the first return lowered for this function, add the regs to the 566 // liveout set for the function. 567 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 568 for (unsigned i = 0; i != RVLocs.size(); ++i) 569 if (RVLocs[i].isRegLoc()) 570 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 571 } 572 573 SDValue Flag; 574 575 // Copy the result values into the output registers. 576 for (unsigned i = 0; i != RVLocs.size(); ++i) { 577 CCValAssign &VA = RVLocs[i]; 578 SDValue ResValue = OutVals[i]; 579 assert(VA.isRegLoc() && "Can only return in registers!"); 580 581 // If this is an 8/16/32-bit value, it is really should be passed promoted 582 // to 64 bits. 583 if (VA.getLocInfo() == CCValAssign::SExt) 584 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); 585 else if (VA.getLocInfo() == CCValAssign::ZExt) 586 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); 587 else if (VA.getLocInfo() == CCValAssign::AExt) 588 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); 589 590 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); 591 592 // Guarantee that all emitted copies are stuck together, 593 // avoiding something bad. 594 Flag = Chain.getValue(1); 595 } 596 597 if (Flag.getNode()) 598 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 599 600 // Return Void 601 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); 602 } 603 604 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, 605 ISD::CondCode CC, SDValue &SystemZCC, 606 SelectionDAG &DAG) const { 607 // FIXME: Emit a test if RHS is zero 608 609 bool isUnsigned = false; 610 SystemZCC::CondCodes TCC; 611 switch (CC) { 612 default: 613 llvm_unreachable("Invalid integer condition!"); 614 case ISD::SETEQ: 615 case ISD::SETOEQ: 616 TCC = SystemZCC::E; 617 break; 618 case ISD::SETUEQ: 619 TCC = SystemZCC::NLH; 620 break; 621 case ISD::SETNE: 622 case ISD::SETONE: 623 TCC = SystemZCC::NE; 624 break; 625 case ISD::SETUNE: 626 TCC = SystemZCC::LH; 627 break; 628 case ISD::SETO: 629 TCC = SystemZCC::O; 630 break; 631 case ISD::SETUO: 632 TCC = SystemZCC::NO; 633 break; 634 case ISD::SETULE: 635 if (LHS.getValueType().isFloatingPoint()) { 636 TCC = SystemZCC::NH; 637 break; 638 } 639 isUnsigned = true; // FALLTHROUGH 640 case ISD::SETLE: 641 case ISD::SETOLE: 642 TCC = SystemZCC::LE; 643 break; 644 case ISD::SETUGE: 645 if (LHS.getValueType().isFloatingPoint()) { 646 TCC = SystemZCC::NL; 647 break; 648 } 649 isUnsigned = true; // FALLTHROUGH 650 case ISD::SETGE: 651 case ISD::SETOGE: 652 TCC = SystemZCC::HE; 653 break; 654 case ISD::SETUGT: 655 if (LHS.getValueType().isFloatingPoint()) { 656 TCC = SystemZCC::NLE; 657 break; 658 } 659 isUnsigned = true; // FALLTHROUGH 660 case ISD::SETGT: 661 case ISD::SETOGT: 662 TCC = SystemZCC::H; 663 break; 664 case ISD::SETULT: 665 if (LHS.getValueType().isFloatingPoint()) { 666 TCC = SystemZCC::NHE; 667 break; 668 } 669 isUnsigned = true; // FALLTHROUGH 670 case ISD::SETLT: 671 case ISD::SETOLT: 672 TCC = SystemZCC::L; 673 break; 674 } 675 676 SystemZCC = DAG.getConstant(TCC, MVT::i32); 677 678 DebugLoc dl = LHS.getDebugLoc(); 679 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), 680 dl, MVT::i64, LHS, RHS); 681 } 682 683 684 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 685 SDValue Chain = Op.getOperand(0); 686 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 687 SDValue LHS = Op.getOperand(2); 688 SDValue RHS = Op.getOperand(3); 689 SDValue Dest = Op.getOperand(4); 690 DebugLoc dl = Op.getDebugLoc(); 691 692 SDValue SystemZCC; 693 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 694 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(), 695 Chain, Dest, SystemZCC, Flag); 696 } 697 698 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, 699 SelectionDAG &DAG) const { 700 SDValue LHS = Op.getOperand(0); 701 SDValue RHS = Op.getOperand(1); 702 SDValue TrueV = Op.getOperand(2); 703 SDValue FalseV = Op.getOperand(3); 704 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 705 DebugLoc dl = Op.getDebugLoc(); 706 707 SDValue SystemZCC; 708 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 709 710 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 711 SmallVector<SDValue, 4> Ops; 712 Ops.push_back(TrueV); 713 Ops.push_back(FalseV); 714 Ops.push_back(SystemZCC); 715 Ops.push_back(Flag); 716 717 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size()); 718 } 719 720 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, 721 SelectionDAG &DAG) const { 722 DebugLoc dl = Op.getDebugLoc(); 723 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 724 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 725 726 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 727 bool ExtraLoadRequired = 728 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false); 729 730 SDValue Result; 731 if (!IsPic && !ExtraLoadRequired) { 732 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 733 Offset = 0; 734 } else { 735 unsigned char OpFlags = 0; 736 if (ExtraLoadRequired) 737 OpFlags = SystemZII::MO_GOTENT; 738 739 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 740 } 741 742 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl, 743 getPointerTy(), Result); 744 745 if (ExtraLoadRequired) 746 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 747 MachinePointerInfo::getGOT(), false, false, 0); 748 749 // If there was a non-zero offset that we didn't fold, create an explicit 750 // addition for it. 751 if (Offset != 0) 752 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 753 DAG.getConstant(Offset, getPointerTy())); 754 755 return Result; 756 } 757 758 // FIXME: PIC here 759 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, 760 SelectionDAG &DAG) const { 761 DebugLoc dl = Op.getDebugLoc(); 762 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 763 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 764 765 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 766 } 767 768 769 // FIXME: PIC here 770 // FIXME: This is just dirty hack. We need to lower cpool properly 771 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, 772 SelectionDAG &DAG) const { 773 DebugLoc dl = Op.getDebugLoc(); 774 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 775 776 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 777 CP->getAlignment(), 778 CP->getOffset()); 779 780 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 781 } 782 783 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { 784 switch (Opcode) { 785 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG"; 786 case SystemZISD::CALL: return "SystemZISD::CALL"; 787 case SystemZISD::BRCOND: return "SystemZISD::BRCOND"; 788 case SystemZISD::CMP: return "SystemZISD::CMP"; 789 case SystemZISD::UCMP: return "SystemZISD::UCMP"; 790 case SystemZISD::SELECT: return "SystemZISD::SELECT"; 791 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper"; 792 default: return NULL; 793 } 794 } 795 796 //===----------------------------------------------------------------------===// 797 // Other Lowering Code 798 //===----------------------------------------------------------------------===// 799 800 MachineBasicBlock* 801 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 802 MachineBasicBlock *BB) const { 803 const SystemZInstrInfo &TII = *TM.getInstrInfo(); 804 DebugLoc dl = MI->getDebugLoc(); 805 assert((MI->getOpcode() == SystemZ::Select32 || 806 MI->getOpcode() == SystemZ::SelectF32 || 807 MI->getOpcode() == SystemZ::Select64 || 808 MI->getOpcode() == SystemZ::SelectF64) && 809 "Unexpected instr type to insert"); 810 811 // To "insert" a SELECT instruction, we actually have to insert the diamond 812 // control-flow pattern. The incoming instruction knows the destination vreg 813 // to set, the condition code register to branch on, the true/false values to 814 // select between, and a branch opcode to use. 815 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 816 MachineFunction::iterator I = BB; 817 ++I; 818 819 // thisMBB: 820 // ... 821 // TrueVal = ... 822 // cmpTY ccX, r1, r2 823 // jCC copy1MBB 824 // fallthrough --> copy0MBB 825 MachineBasicBlock *thisMBB = BB; 826 MachineFunction *F = BB->getParent(); 827 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 828 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 829 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); 830 F->insert(I, copy0MBB); 831 F->insert(I, copy1MBB); 832 // Update machine-CFG edges by transferring all successors of the current 833 // block to the new block which will contain the Phi node for the select. 834 copy1MBB->splice(copy1MBB->begin(), BB, 835 llvm::next(MachineBasicBlock::iterator(MI)), 836 BB->end()); 837 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 838 // Next, add the true and fallthrough blocks as its successors. 839 BB->addSuccessor(copy0MBB); 840 BB->addSuccessor(copy1MBB); 841 842 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); 843 844 // copy0MBB: 845 // %FalseValue = ... 846 // # fallthrough to copy1MBB 847 BB = copy0MBB; 848 849 // Update machine-CFG edges 850 BB->addSuccessor(copy1MBB); 851 852 // copy1MBB: 853 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 854 // ... 855 BB = copy1MBB; 856 BuildMI(*BB, BB->begin(), dl, TII.get(SystemZ::PHI), 857 MI->getOperand(0).getReg()) 858 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 859 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 860 861 MI->eraseFromParent(); // The pseudo instruction is gone now. 862 return BB; 863 } 864