1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "systemz-lower" 15 16 #include "SystemZISelLowering.h" 17 #include "SystemZ.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZSubtarget.h" 20 #include "llvm/DerivedTypes.h" 21 #include "llvm/Function.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/GlobalVariable.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/CodeGen/CallingConvLower.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/PseudoSourceValue.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/ValueTypes.h" 34 #include "llvm/Target/TargetOptions.h" 35 #include "llvm/Target/TargetLoweringObjectFile.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/ADT/VectorExtras.h" 38 using namespace llvm; 39 40 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : 41 TargetLowering(tm, new TargetLoweringObjectFileELF()), 42 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 43 44 RegInfo = TM.getRegisterInfo(); 45 46 // Set up the register classes. 47 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); 48 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); 49 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); 50 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); 51 52 if (!UseSoftFloat) { 53 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); 54 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); 55 56 addLegalFPImmediate(APFloat(+0.0)); // lzer 57 addLegalFPImmediate(APFloat(+0.0f)); // lzdr 58 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner 59 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr 60 } 61 62 // Compute derived properties from the register classes 63 computeRegisterProperties(); 64 65 // Set shifts properties 66 setShiftAmountType(MVT::i64); 67 68 // Provide all sorts of operation actions 69 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 70 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 71 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 72 73 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); 74 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); 75 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 76 77 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); 78 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); 79 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 80 81 setStackPointerRegisterToSaveRestore(SystemZ::R15D); 82 setSchedulingPreference(SchedulingForLatency); 83 setBooleanContents(ZeroOrOneBooleanContent); 84 85 setOperationAction(ISD::RET, MVT::Other, Custom); 86 87 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 88 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 89 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 90 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 91 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 92 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 93 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 94 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 95 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 96 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 97 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 98 99 setOperationAction(ISD::SDIV, MVT::i32, Expand); 100 setOperationAction(ISD::UDIV, MVT::i32, Expand); 101 setOperationAction(ISD::SDIV, MVT::i64, Expand); 102 setOperationAction(ISD::UDIV, MVT::i64, Expand); 103 setOperationAction(ISD::SREM, MVT::i32, Expand); 104 setOperationAction(ISD::UREM, MVT::i32, Expand); 105 setOperationAction(ISD::SREM, MVT::i64, Expand); 106 setOperationAction(ISD::UREM, MVT::i64, Expand); 107 108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 109 110 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 111 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 112 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 113 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 114 setOperationAction(ISD::CTLZ, MVT::i32, Promote); 115 setOperationAction(ISD::CTLZ, MVT::i64, Legal); 116 117 // FIXME: Can we lower these 2 efficiently? 118 setOperationAction(ISD::SETCC, MVT::i32, Expand); 119 setOperationAction(ISD::SETCC, MVT::i64, Expand); 120 setOperationAction(ISD::SETCC, MVT::f32, Expand); 121 setOperationAction(ISD::SETCC, MVT::f64, Expand); 122 setOperationAction(ISD::SELECT, MVT::i32, Expand); 123 setOperationAction(ISD::SELECT, MVT::i64, Expand); 124 setOperationAction(ISD::SELECT, MVT::f32, Expand); 125 setOperationAction(ISD::SELECT, MVT::f64, Expand); 126 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 127 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 128 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 129 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 130 131 // Funny enough: we don't have 64-bit signed versions of these stuff, but have 132 // unsigned. 133 setOperationAction(ISD::MULHS, MVT::i64, Expand); 134 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 135 136 // Lower some FP stuff 137 setOperationAction(ISD::FSIN, MVT::f32, Expand); 138 setOperationAction(ISD::FSIN, MVT::f64, Expand); 139 setOperationAction(ISD::FCOS, MVT::f32, Expand); 140 setOperationAction(ISD::FCOS, MVT::f64, Expand); 141 setOperationAction(ISD::FREM, MVT::f32, Expand); 142 setOperationAction(ISD::FREM, MVT::f64, Expand); 143 144 // We have only 64-bit bitconverts 145 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 146 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 147 148 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 149 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 150 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 151 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 152 153 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 154 } 155 156 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 157 switch (Op.getOpcode()) { 158 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 159 case ISD::RET: return LowerRET(Op, DAG); 160 case ISD::CALL: return LowerCALL(Op, DAG); 161 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 162 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 163 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 164 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 165 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 166 default: 167 llvm_unreachable("Should not custom lower this!"); 168 return SDValue(); 169 } 170 } 171 172 //===----------------------------------------------------------------------===// 173 // Calling Convention Implementation 174 //===----------------------------------------------------------------------===// 175 176 #include "SystemZGenCallingConv.inc" 177 178 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, 179 SelectionDAG &DAG) { 180 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 181 switch (CC) { 182 default: 183 llvm_unreachable("Unsupported calling convention"); 184 case CallingConv::C: 185 case CallingConv::Fast: 186 return LowerCCCArguments(Op, DAG); 187 } 188 } 189 190 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 191 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 192 unsigned CallingConv = TheCall->getCallingConv(); 193 switch (CallingConv) { 194 default: 195 llvm_unreachable("Unsupported calling convention"); 196 case CallingConv::Fast: 197 case CallingConv::C: 198 return LowerCCCCallTo(Op, DAG, CallingConv); 199 } 200 } 201 202 /// LowerCCCArguments - transform physical registers into virtual registers and 203 /// generate load operations for arguments places on the stack. 204 // FIXME: struct return stuff 205 // FIXME: varargs 206 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op, 207 SelectionDAG &DAG) { 208 MachineFunction &MF = DAG.getMachineFunction(); 209 MachineFrameInfo *MFI = MF.getFrameInfo(); 210 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 211 SDValue Root = Op.getOperand(0); 212 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 213 unsigned CC = MF.getFunction()->getCallingConv(); 214 DebugLoc dl = Op.getDebugLoc(); 215 216 // Assign locations to all of the incoming arguments. 217 SmallVector<CCValAssign, 16> ArgLocs; 218 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); 219 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ); 220 221 if (isVarArg) 222 llvm_report_error("Varargs not supported yet"); 223 224 SmallVector<SDValue, 16> ArgValues; 225 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 226 SDValue ArgValue; 227 CCValAssign &VA = ArgLocs[i]; 228 MVT LocVT = VA.getLocVT(); 229 if (VA.isRegLoc()) { 230 // Arguments passed in registers 231 TargetRegisterClass *RC; 232 switch (LocVT.getSimpleVT()) { 233 default: 234 #ifndef NDEBUG 235 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " 236 << LocVT.getSimpleVT() 237 << "\n"; 238 #endif 239 llvm_unreachable(0); 240 case MVT::i64: 241 RC = SystemZ::GR64RegisterClass; 242 break; 243 case MVT::f32: 244 RC = SystemZ::FP32RegisterClass; 245 break; 246 case MVT::f64: 247 RC = SystemZ::FP64RegisterClass; 248 break; 249 } 250 251 unsigned VReg = RegInfo.createVirtualRegister(RC); 252 RegInfo.addLiveIn(VA.getLocReg(), VReg); 253 ArgValue = DAG.getCopyFromReg(Root, dl, VReg, LocVT); 254 } else { 255 // Sanity check 256 assert(VA.isMemLoc()); 257 258 // Create the nodes corresponding to a load from this parameter slot. 259 // Create the frame index object for this incoming parameter... 260 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, 261 VA.getLocMemOffset()); 262 263 // Create the SelectionDAG nodes corresponding to a load 264 // from this parameter 265 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 266 ArgValue = DAG.getLoad(LocVT, dl, Root, FIN, 267 PseudoSourceValue::getFixedStack(FI), 0); 268 } 269 270 // If this is an 8/16/32-bit value, it is really passed promoted to 64 271 // bits. Insert an assert[sz]ext to capture this, then truncate to the 272 // right size. 273 if (VA.getLocInfo() == CCValAssign::SExt) 274 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 275 DAG.getValueType(VA.getValVT())); 276 else if (VA.getLocInfo() == CCValAssign::ZExt) 277 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, 278 DAG.getValueType(VA.getValVT())); 279 280 if (VA.getLocInfo() != CCValAssign::Full) 281 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 282 283 ArgValues.push_back(ArgValue); 284 } 285 286 ArgValues.push_back(Root); 287 288 // Return the new list of results. 289 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 290 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 291 } 292 293 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 294 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 295 /// TODO: sret. 296 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, 297 unsigned CC) { 298 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 299 SDValue Chain = TheCall->getChain(); 300 SDValue Callee = TheCall->getCallee(); 301 bool isVarArg = TheCall->isVarArg(); 302 DebugLoc dl = Op.getDebugLoc(); 303 MachineFunction &MF = DAG.getMachineFunction(); 304 305 // Offset to first argument stack slot. 306 const unsigned FirstArgOffset = 160; 307 308 // Analyze operands of the call, assigning locations to each operand. 309 SmallVector<CCValAssign, 16> ArgLocs; 310 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); 311 312 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ); 313 314 // Get a count of how many bytes are to be pushed on the stack. 315 unsigned NumBytes = CCInfo.getNextStackOffset(); 316 317 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 318 getPointerTy(), true)); 319 320 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 321 SmallVector<SDValue, 12> MemOpChains; 322 SDValue StackPtr; 323 324 // Walk the register/memloc assignments, inserting copies/loads. 325 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 326 CCValAssign &VA = ArgLocs[i]; 327 328 // Arguments start after the 5 first operands of ISD::CALL 329 SDValue Arg = TheCall->getArg(i); 330 331 // Promote the value if needed. 332 switch (VA.getLocInfo()) { 333 default: assert(0 && "Unknown loc info!"); 334 case CCValAssign::Full: break; 335 case CCValAssign::SExt: 336 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 337 break; 338 case CCValAssign::ZExt: 339 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 340 break; 341 case CCValAssign::AExt: 342 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 343 break; 344 } 345 346 // Arguments that can be passed on register must be kept at RegsToPass 347 // vector 348 if (VA.isRegLoc()) { 349 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 350 } else { 351 assert(VA.isMemLoc()); 352 353 if (StackPtr.getNode() == 0) 354 StackPtr = 355 DAG.getCopyFromReg(Chain, dl, 356 (RegInfo->hasFP(MF) ? 357 SystemZ::R11D : SystemZ::R15D), 358 getPointerTy()); 359 360 unsigned Offset = FirstArgOffset + VA.getLocMemOffset(); 361 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 362 StackPtr, 363 DAG.getIntPtrConstant(Offset)); 364 365 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 366 PseudoSourceValue::getStack(), Offset)); 367 } 368 } 369 370 // Transform all store nodes into one single node because all store nodes are 371 // independent of each other. 372 if (!MemOpChains.empty()) 373 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 374 &MemOpChains[0], MemOpChains.size()); 375 376 // Build a sequence of copy-to-reg nodes chained together with token chain and 377 // flag operands which copy the outgoing args into registers. The InFlag in 378 // necessary since all emited instructions must be stuck together. 379 SDValue InFlag; 380 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 381 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 382 RegsToPass[i].second, InFlag); 383 InFlag = Chain.getValue(1); 384 } 385 386 // If the callee is a GlobalAddress node (quite common, every direct call is) 387 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 388 // Likewise ExternalSymbol -> TargetExternalSymbol. 389 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 390 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 391 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 392 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 393 394 // Returns a chain & a flag for retval copy to use. 395 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 396 SmallVector<SDValue, 8> Ops; 397 Ops.push_back(Chain); 398 Ops.push_back(Callee); 399 400 // Add argument registers to the end of the list so that they are 401 // known live into the call. 402 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 403 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 404 RegsToPass[i].second.getValueType())); 405 406 if (InFlag.getNode()) 407 Ops.push_back(InFlag); 408 409 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 410 InFlag = Chain.getValue(1); 411 412 // Create the CALLSEQ_END node. 413 Chain = DAG.getCALLSEQ_END(Chain, 414 DAG.getConstant(NumBytes, getPointerTy(), true), 415 DAG.getConstant(0, getPointerTy(), true), 416 InFlag); 417 InFlag = Chain.getValue(1); 418 419 // Handle result values, copying them out of physregs into vregs that we 420 // return. 421 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), 422 Op.getResNo()); 423 } 424 425 /// LowerCallResult - Lower the result values of an ISD::CALL into the 426 /// appropriate copies out of appropriate physical registers. This assumes that 427 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 428 /// being lowered. Returns a SDNode with the same number of values as the 429 /// ISD::CALL. 430 SDNode* 431 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 432 CallSDNode *TheCall, 433 unsigned CallingConv, 434 SelectionDAG &DAG) { 435 bool isVarArg = TheCall->isVarArg(); 436 DebugLoc dl = TheCall->getDebugLoc(); 437 438 // Assign locations to each value returned by this call. 439 SmallVector<CCValAssign, 16> RVLocs; 440 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs, 441 *DAG.getContext()); 442 443 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ); 444 SmallVector<SDValue, 8> ResultVals; 445 446 // Copy all of the result registers out of their specified physreg. 447 for (unsigned i = 0; i != RVLocs.size(); ++i) { 448 CCValAssign &VA = RVLocs[i]; 449 450 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 451 VA.getLocVT(), InFlag).getValue(1); 452 SDValue RetValue = Chain.getValue(0); 453 InFlag = Chain.getValue(2); 454 455 // If this is an 8/16/32-bit value, it is really passed promoted to 64 456 // bits. Insert an assert[sz]ext to capture this, then truncate to the 457 // right size. 458 if (VA.getLocInfo() == CCValAssign::SExt) 459 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, 460 DAG.getValueType(VA.getValVT())); 461 else if (VA.getLocInfo() == CCValAssign::ZExt) 462 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, 463 DAG.getValueType(VA.getValVT())); 464 465 if (VA.getLocInfo() != CCValAssign::Full) 466 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue); 467 468 ResultVals.push_back(RetValue); 469 } 470 471 ResultVals.push_back(Chain); 472 473 // Merge everything together with a MERGE_VALUES node. 474 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), 475 &ResultVals[0], ResultVals.size()).getNode(); 476 } 477 478 479 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 480 // CCValAssign - represent the assignment of the return value to a location 481 SmallVector<CCValAssign, 16> RVLocs; 482 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 483 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 484 DebugLoc dl = Op.getDebugLoc(); 485 486 // CCState - Info about the registers and stack slot. 487 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, *DAG.getContext()); 488 489 // Analize return values of ISD::RET 490 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ); 491 492 // If this is the first return lowered for this function, add the regs to the 493 // liveout set for the function. 494 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 495 for (unsigned i = 0; i != RVLocs.size(); ++i) 496 if (RVLocs[i].isRegLoc()) 497 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 498 } 499 500 // The chain is always operand #0 501 SDValue Chain = Op.getOperand(0); 502 SDValue Flag; 503 504 // Copy the result values into the output registers. 505 for (unsigned i = 0; i != RVLocs.size(); ++i) { 506 CCValAssign &VA = RVLocs[i]; 507 SDValue ResValue = Op.getOperand(i*2+1); 508 assert(VA.isRegLoc() && "Can only return in registers!"); 509 510 // If this is an 8/16/32-bit value, it is really should be passed promoted 511 // to 64 bits. 512 if (VA.getLocInfo() == CCValAssign::SExt) 513 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); 514 else if (VA.getLocInfo() == CCValAssign::ZExt) 515 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); 516 else if (VA.getLocInfo() == CCValAssign::AExt) 517 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); 518 519 // ISD::RET => ret chain, (regnum1,val1), ... 520 // So i*2+1 index only the regnums 521 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); 522 523 // Guarantee that all emitted copies are stuck together, 524 // avoiding something bad. 525 Flag = Chain.getValue(1); 526 } 527 528 if (Flag.getNode()) 529 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 530 531 // Return Void 532 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); 533 } 534 535 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, 536 ISD::CondCode CC, SDValue &SystemZCC, 537 SelectionDAG &DAG) { 538 // FIXME: Emit a test if RHS is zero 539 540 bool isUnsigned = false; 541 SystemZCC::CondCodes TCC; 542 switch (CC) { 543 default: 544 llvm_unreachable("Invalid integer condition!"); 545 case ISD::SETEQ: 546 case ISD::SETOEQ: 547 TCC = SystemZCC::E; 548 break; 549 case ISD::SETUEQ: 550 TCC = SystemZCC::NLH; 551 break; 552 case ISD::SETNE: 553 case ISD::SETONE: 554 TCC = SystemZCC::NE; 555 break; 556 case ISD::SETUNE: 557 TCC = SystemZCC::LH; 558 break; 559 case ISD::SETO: 560 TCC = SystemZCC::O; 561 break; 562 case ISD::SETUO: 563 TCC = SystemZCC::NO; 564 break; 565 case ISD::SETULE: 566 if (LHS.getValueType().isFloatingPoint()) { 567 TCC = SystemZCC::NH; 568 break; 569 } 570 isUnsigned = true; // FALLTHROUGH 571 case ISD::SETLE: 572 case ISD::SETOLE: 573 TCC = SystemZCC::LE; 574 break; 575 case ISD::SETUGE: 576 if (LHS.getValueType().isFloatingPoint()) { 577 TCC = SystemZCC::NL; 578 break; 579 } 580 isUnsigned = true; // FALLTHROUGH 581 case ISD::SETGE: 582 case ISD::SETOGE: 583 TCC = SystemZCC::HE; 584 break; 585 case ISD::SETUGT: 586 if (LHS.getValueType().isFloatingPoint()) { 587 TCC = SystemZCC::NLE; 588 break; 589 } 590 isUnsigned = true; // FALLTHROUGH 591 case ISD::SETGT: 592 case ISD::SETOGT: 593 TCC = SystemZCC::H; 594 break; 595 case ISD::SETULT: 596 if (LHS.getValueType().isFloatingPoint()) { 597 TCC = SystemZCC::NHE; 598 break; 599 } 600 isUnsigned = true; // FALLTHROUGH 601 case ISD::SETLT: 602 case ISD::SETOLT: 603 TCC = SystemZCC::L; 604 break; 605 } 606 607 SystemZCC = DAG.getConstant(TCC, MVT::i32); 608 609 DebugLoc dl = LHS.getDebugLoc(); 610 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), 611 dl, MVT::Flag, LHS, RHS); 612 } 613 614 615 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 616 SDValue Chain = Op.getOperand(0); 617 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 618 SDValue LHS = Op.getOperand(2); 619 SDValue RHS = Op.getOperand(3); 620 SDValue Dest = Op.getOperand(4); 621 DebugLoc dl = Op.getDebugLoc(); 622 623 SDValue SystemZCC; 624 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 625 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(), 626 Chain, Dest, SystemZCC, Flag); 627 } 628 629 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 630 SDValue LHS = Op.getOperand(0); 631 SDValue RHS = Op.getOperand(1); 632 SDValue TrueV = Op.getOperand(2); 633 SDValue FalseV = Op.getOperand(3); 634 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 635 DebugLoc dl = Op.getDebugLoc(); 636 637 SDValue SystemZCC; 638 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 639 640 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 641 SmallVector<SDValue, 4> Ops; 642 Ops.push_back(TrueV); 643 Ops.push_back(FalseV); 644 Ops.push_back(SystemZCC); 645 Ops.push_back(Flag); 646 647 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size()); 648 } 649 650 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, 651 SelectionDAG &DAG) { 652 DebugLoc dl = Op.getDebugLoc(); 653 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 654 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 655 656 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 657 bool ExtraLoadRequired = 658 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false); 659 660 SDValue Result; 661 if (!IsPic && !ExtraLoadRequired) { 662 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 663 Offset = 0; 664 } else { 665 unsigned char OpFlags = 0; 666 if (ExtraLoadRequired) 667 OpFlags = SystemZII::MO_GOTENT; 668 669 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 670 } 671 672 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl, 673 getPointerTy(), Result); 674 675 if (ExtraLoadRequired) 676 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 677 PseudoSourceValue::getGOT(), 0); 678 679 // If there was a non-zero offset that we didn't fold, create an explicit 680 // addition for it. 681 if (Offset != 0) 682 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 683 DAG.getConstant(Offset, getPointerTy())); 684 685 return Result; 686 } 687 688 // FIXME: PIC here 689 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, 690 SelectionDAG &DAG) { 691 DebugLoc dl = Op.getDebugLoc(); 692 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 693 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 694 695 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 696 } 697 698 699 // FIXME: PIC here 700 // FIXME: This is just dirty hack. We need to lower cpool properly 701 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, 702 SelectionDAG &DAG) { 703 DebugLoc dl = Op.getDebugLoc(); 704 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 705 706 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 707 CP->getAlignment(), 708 CP->getOffset()); 709 710 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 711 } 712 713 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { 714 switch (Opcode) { 715 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG"; 716 case SystemZISD::CALL: return "SystemZISD::CALL"; 717 case SystemZISD::BRCOND: return "SystemZISD::BRCOND"; 718 case SystemZISD::CMP: return "SystemZISD::CMP"; 719 case SystemZISD::UCMP: return "SystemZISD::UCMP"; 720 case SystemZISD::SELECT: return "SystemZISD::SELECT"; 721 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper"; 722 default: return NULL; 723 } 724 } 725 726 //===----------------------------------------------------------------------===// 727 // Other Lowering Code 728 //===----------------------------------------------------------------------===// 729 730 MachineBasicBlock* 731 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 732 MachineBasicBlock *BB) const { 733 const SystemZInstrInfo &TII = *TM.getInstrInfo(); 734 DebugLoc dl = MI->getDebugLoc(); 735 assert((MI->getOpcode() == SystemZ::Select32 || 736 MI->getOpcode() == SystemZ::SelectF32 || 737 MI->getOpcode() == SystemZ::Select64 || 738 MI->getOpcode() == SystemZ::SelectF64) && 739 "Unexpected instr type to insert"); 740 741 // To "insert" a SELECT instruction, we actually have to insert the diamond 742 // control-flow pattern. The incoming instruction knows the destination vreg 743 // to set, the condition code register to branch on, the true/false values to 744 // select between, and a branch opcode to use. 745 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 746 MachineFunction::iterator I = BB; 747 ++I; 748 749 // thisMBB: 750 // ... 751 // TrueVal = ... 752 // cmpTY ccX, r1, r2 753 // jCC copy1MBB 754 // fallthrough --> copy0MBB 755 MachineBasicBlock *thisMBB = BB; 756 MachineFunction *F = BB->getParent(); 757 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 758 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 759 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); 760 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); 761 F->insert(I, copy0MBB); 762 F->insert(I, copy1MBB); 763 // Update machine-CFG edges by transferring all successors of the current 764 // block to the new block which will contain the Phi node for the select. 765 copy1MBB->transferSuccessors(BB); 766 // Next, add the true and fallthrough blocks as its successors. 767 BB->addSuccessor(copy0MBB); 768 BB->addSuccessor(copy1MBB); 769 770 // copy0MBB: 771 // %FalseValue = ... 772 // # fallthrough to copy1MBB 773 BB = copy0MBB; 774 775 // Update machine-CFG edges 776 BB->addSuccessor(copy1MBB); 777 778 // copy1MBB: 779 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 780 // ... 781 BB = copy1MBB; 782 BuildMI(BB, dl, TII.get(SystemZ::PHI), 783 MI->getOperand(0).getReg()) 784 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 785 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 786 787 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 788 return BB; 789 } 790