1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "systemz-lower" 15 16 #include "SystemZISelLowering.h" 17 #include "SystemZ.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZSubtarget.h" 20 #include "llvm/DerivedTypes.h" 21 #include "llvm/Function.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/GlobalVariable.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/CodeGen/CallingConvLower.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/PseudoSourceValue.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/ValueTypes.h" 34 #include "llvm/Target/TargetOptions.h" 35 #include "llvm/Target/TargetLoweringObjectFile.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/ADT/VectorExtras.h" 40 using namespace llvm; 41 42 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : 43 TargetLowering(tm, new TargetLoweringObjectFileELF()), 44 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 45 46 RegInfo = TM.getRegisterInfo(); 47 48 // Set up the register classes. 49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); 50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); 51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); 52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); 53 54 if (!UseSoftFloat) { 55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); 56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); 57 } 58 59 // Compute derived properties from the register classes 60 computeRegisterProperties(); 61 62 // Set shifts properties 63 setShiftAmountType(MVT::i64); 64 65 // Provide all sorts of operation actions 66 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 67 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 68 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 69 70 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); 71 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); 72 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 73 74 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); 75 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); 76 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 77 78 setStackPointerRegisterToSaveRestore(SystemZ::R15D); 79 80 // TODO: It may be better to default to latency-oriented scheduling, however 81 // LLVM's current latency-oriented scheduler can't handle physreg definitions 82 // such as SystemZ has with PSW, so set this to the register-pressure 83 // scheduler, because it can. 84 setSchedulingPreference(SchedulingForRegPressure); 85 86 setBooleanContents(ZeroOrOneBooleanContent); 87 88 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 89 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 90 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 91 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 92 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 93 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 94 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 95 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 96 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 97 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 99 100 setOperationAction(ISD::SDIV, MVT::i32, Expand); 101 setOperationAction(ISD::UDIV, MVT::i32, Expand); 102 setOperationAction(ISD::SDIV, MVT::i64, Expand); 103 setOperationAction(ISD::UDIV, MVT::i64, Expand); 104 setOperationAction(ISD::SREM, MVT::i32, Expand); 105 setOperationAction(ISD::UREM, MVT::i32, Expand); 106 setOperationAction(ISD::SREM, MVT::i64, Expand); 107 setOperationAction(ISD::UREM, MVT::i64, Expand); 108 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 110 111 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 112 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 113 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 114 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 115 setOperationAction(ISD::CTLZ, MVT::i32, Promote); 116 setOperationAction(ISD::CTLZ, MVT::i64, Legal); 117 118 // FIXME: Can we lower these 2 efficiently? 119 setOperationAction(ISD::SETCC, MVT::i32, Expand); 120 setOperationAction(ISD::SETCC, MVT::i64, Expand); 121 setOperationAction(ISD::SETCC, MVT::f32, Expand); 122 setOperationAction(ISD::SETCC, MVT::f64, Expand); 123 setOperationAction(ISD::SELECT, MVT::i32, Expand); 124 setOperationAction(ISD::SELECT, MVT::i64, Expand); 125 setOperationAction(ISD::SELECT, MVT::f32, Expand); 126 setOperationAction(ISD::SELECT, MVT::f64, Expand); 127 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 128 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 129 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 130 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 131 132 setOperationAction(ISD::MULHS, MVT::i64, Expand); 133 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 134 135 // FIXME: Can we support these natively? 136 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 137 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 138 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 139 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 140 141 // Lower some FP stuff 142 setOperationAction(ISD::FSIN, MVT::f32, Expand); 143 setOperationAction(ISD::FSIN, MVT::f64, Expand); 144 setOperationAction(ISD::FCOS, MVT::f32, Expand); 145 setOperationAction(ISD::FCOS, MVT::f64, Expand); 146 setOperationAction(ISD::FREM, MVT::f32, Expand); 147 setOperationAction(ISD::FREM, MVT::f64, Expand); 148 149 // We have only 64-bit bitconverts 150 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 151 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 152 153 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 154 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 155 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 156 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 157 158 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 159 } 160 161 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 162 switch (Op.getOpcode()) { 163 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 164 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 165 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 166 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 167 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 168 default: 169 llvm_unreachable("Should not custom lower this!"); 170 return SDValue(); 171 } 172 } 173 174 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 175 if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64)) 176 return false; 177 178 // +0.0 lzer 179 // +0.0f lzdr 180 // -0.0 lzer + lner 181 // -0.0f lzdr + lndr 182 return Imm.isZero() || Imm.isNegZero(); 183 } 184 185 //===----------------------------------------------------------------------===// 186 // SystemZ Inline Assembly Support 187 //===----------------------------------------------------------------------===// 188 189 /// getConstraintType - Given a constraint letter, return the type of 190 /// constraint it is for this target. 191 TargetLowering::ConstraintType 192 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const { 193 if (Constraint.size() == 1) { 194 switch (Constraint[0]) { 195 case 'r': 196 return C_RegisterClass; 197 default: 198 break; 199 } 200 } 201 return TargetLowering::getConstraintType(Constraint); 202 } 203 204 std::pair<unsigned, const TargetRegisterClass*> 205 SystemZTargetLowering:: 206 getRegForInlineAsmConstraint(const std::string &Constraint, 207 EVT VT) const { 208 if (Constraint.size() == 1) { 209 // GCC Constraint Letters 210 switch (Constraint[0]) { 211 default: break; 212 case 'r': // GENERAL_REGS 213 if (VT == MVT::i32) 214 return std::make_pair(0U, SystemZ::GR32RegisterClass); 215 else if (VT == MVT::i128) 216 return std::make_pair(0U, SystemZ::GR128RegisterClass); 217 218 return std::make_pair(0U, SystemZ::GR64RegisterClass); 219 } 220 } 221 222 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 223 } 224 225 //===----------------------------------------------------------------------===// 226 // Calling Convention Implementation 227 //===----------------------------------------------------------------------===// 228 229 #include "SystemZGenCallingConv.inc" 230 231 SDValue 232 SystemZTargetLowering::LowerFormalArguments(SDValue Chain, 233 CallingConv::ID CallConv, 234 bool isVarArg, 235 const SmallVectorImpl<ISD::InputArg> 236 &Ins, 237 DebugLoc dl, 238 SelectionDAG &DAG, 239 SmallVectorImpl<SDValue> &InVals) { 240 241 switch (CallConv) { 242 default: 243 llvm_unreachable("Unsupported calling convention"); 244 case CallingConv::C: 245 case CallingConv::Fast: 246 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 247 } 248 } 249 250 SDValue 251 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 252 CallingConv::ID CallConv, bool isVarArg, 253 bool &isTailCall, 254 const SmallVectorImpl<ISD::OutputArg> &Outs, 255 const SmallVectorImpl<ISD::InputArg> &Ins, 256 DebugLoc dl, SelectionDAG &DAG, 257 SmallVectorImpl<SDValue> &InVals) { 258 // SystemZ target does not yet support tail call optimization. 259 isTailCall = false; 260 261 switch (CallConv) { 262 default: 263 llvm_unreachable("Unsupported calling convention"); 264 case CallingConv::Fast: 265 case CallingConv::C: 266 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 267 Outs, Ins, dl, DAG, InVals); 268 } 269 } 270 271 /// LowerCCCArguments - transform physical registers into virtual registers and 272 /// generate load operations for arguments places on the stack. 273 // FIXME: struct return stuff 274 // FIXME: varargs 275 SDValue 276 SystemZTargetLowering::LowerCCCArguments(SDValue Chain, 277 CallingConv::ID CallConv, 278 bool isVarArg, 279 const SmallVectorImpl<ISD::InputArg> 280 &Ins, 281 DebugLoc dl, 282 SelectionDAG &DAG, 283 SmallVectorImpl<SDValue> &InVals) { 284 285 MachineFunction &MF = DAG.getMachineFunction(); 286 MachineFrameInfo *MFI = MF.getFrameInfo(); 287 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 288 289 // Assign locations to all of the incoming arguments. 290 SmallVector<CCValAssign, 16> ArgLocs; 291 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 292 ArgLocs, *DAG.getContext()); 293 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); 294 295 if (isVarArg) 296 llvm_report_error("Varargs not supported yet"); 297 298 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 299 SDValue ArgValue; 300 CCValAssign &VA = ArgLocs[i]; 301 EVT LocVT = VA.getLocVT(); 302 if (VA.isRegLoc()) { 303 // Arguments passed in registers 304 TargetRegisterClass *RC; 305 switch (LocVT.getSimpleVT().SimpleTy) { 306 default: 307 #ifndef NDEBUG 308 errs() << "LowerFormalArguments Unhandled argument type: " 309 << LocVT.getSimpleVT().SimpleTy 310 << "\n"; 311 #endif 312 llvm_unreachable(0); 313 case MVT::i64: 314 RC = SystemZ::GR64RegisterClass; 315 break; 316 case MVT::f32: 317 RC = SystemZ::FP32RegisterClass; 318 break; 319 case MVT::f64: 320 RC = SystemZ::FP64RegisterClass; 321 break; 322 } 323 324 unsigned VReg = RegInfo.createVirtualRegister(RC); 325 RegInfo.addLiveIn(VA.getLocReg(), VReg); 326 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT); 327 } else { 328 // Sanity check 329 assert(VA.isMemLoc()); 330 331 // Create the nodes corresponding to a load from this parameter slot. 332 // Create the frame index object for this incoming parameter... 333 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, 334 VA.getLocMemOffset(), true, false); 335 336 // Create the SelectionDAG nodes corresponding to a load 337 // from this parameter 338 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 339 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN, 340 PseudoSourceValue::getFixedStack(FI), 0); 341 } 342 343 // If this is an 8/16/32-bit value, it is really passed promoted to 64 344 // bits. Insert an assert[sz]ext to capture this, then truncate to the 345 // right size. 346 if (VA.getLocInfo() == CCValAssign::SExt) 347 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 348 DAG.getValueType(VA.getValVT())); 349 else if (VA.getLocInfo() == CCValAssign::ZExt) 350 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, 351 DAG.getValueType(VA.getValVT())); 352 353 if (VA.getLocInfo() != CCValAssign::Full) 354 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 355 356 InVals.push_back(ArgValue); 357 } 358 359 return Chain; 360 } 361 362 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 363 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 364 /// TODO: sret. 365 SDValue 366 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 367 CallingConv::ID CallConv, bool isVarArg, 368 bool isTailCall, 369 const SmallVectorImpl<ISD::OutputArg> 370 &Outs, 371 const SmallVectorImpl<ISD::InputArg> &Ins, 372 DebugLoc dl, SelectionDAG &DAG, 373 SmallVectorImpl<SDValue> &InVals) { 374 375 MachineFunction &MF = DAG.getMachineFunction(); 376 377 // Offset to first argument stack slot. 378 const unsigned FirstArgOffset = 160; 379 380 // Analyze operands of the call, assigning locations to each operand. 381 SmallVector<CCValAssign, 16> ArgLocs; 382 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 383 ArgLocs, *DAG.getContext()); 384 385 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); 386 387 // Get a count of how many bytes are to be pushed on the stack. 388 unsigned NumBytes = CCInfo.getNextStackOffset(); 389 390 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 391 getPointerTy(), true)); 392 393 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 394 SmallVector<SDValue, 12> MemOpChains; 395 SDValue StackPtr; 396 397 // Walk the register/memloc assignments, inserting copies/loads. 398 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 399 CCValAssign &VA = ArgLocs[i]; 400 401 SDValue Arg = Outs[i].Val; 402 403 // Promote the value if needed. 404 switch (VA.getLocInfo()) { 405 default: assert(0 && "Unknown loc info!"); 406 case CCValAssign::Full: break; 407 case CCValAssign::SExt: 408 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 409 break; 410 case CCValAssign::ZExt: 411 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 412 break; 413 case CCValAssign::AExt: 414 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 415 break; 416 } 417 418 // Arguments that can be passed on register must be kept at RegsToPass 419 // vector 420 if (VA.isRegLoc()) { 421 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 422 } else { 423 assert(VA.isMemLoc()); 424 425 if (StackPtr.getNode() == 0) 426 StackPtr = 427 DAG.getCopyFromReg(Chain, dl, 428 (RegInfo->hasFP(MF) ? 429 SystemZ::R11D : SystemZ::R15D), 430 getPointerTy()); 431 432 unsigned Offset = FirstArgOffset + VA.getLocMemOffset(); 433 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 434 StackPtr, 435 DAG.getIntPtrConstant(Offset)); 436 437 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 438 PseudoSourceValue::getStack(), Offset)); 439 } 440 } 441 442 // Transform all store nodes into one single node because all store nodes are 443 // independent of each other. 444 if (!MemOpChains.empty()) 445 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 446 &MemOpChains[0], MemOpChains.size()); 447 448 // Build a sequence of copy-to-reg nodes chained together with token chain and 449 // flag operands which copy the outgoing args into registers. The InFlag in 450 // necessary since all emited instructions must be stuck together. 451 SDValue InFlag; 452 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 453 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 454 RegsToPass[i].second, InFlag); 455 InFlag = Chain.getValue(1); 456 } 457 458 // If the callee is a GlobalAddress node (quite common, every direct call is) 459 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 460 // Likewise ExternalSymbol -> TargetExternalSymbol. 461 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 462 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy()); 463 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 464 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 465 466 // Returns a chain & a flag for retval copy to use. 467 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 468 SmallVector<SDValue, 8> Ops; 469 Ops.push_back(Chain); 470 Ops.push_back(Callee); 471 472 // Add argument registers to the end of the list so that they are 473 // known live into the call. 474 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 475 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 476 RegsToPass[i].second.getValueType())); 477 478 if (InFlag.getNode()) 479 Ops.push_back(InFlag); 480 481 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 482 InFlag = Chain.getValue(1); 483 484 // Create the CALLSEQ_END node. 485 Chain = DAG.getCALLSEQ_END(Chain, 486 DAG.getConstant(NumBytes, getPointerTy(), true), 487 DAG.getConstant(0, getPointerTy(), true), 488 InFlag); 489 InFlag = Chain.getValue(1); 490 491 // Handle result values, copying them out of physregs into vregs that we 492 // return. 493 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 494 DAG, InVals); 495 } 496 497 /// LowerCallResult - Lower the result values of a call into the 498 /// appropriate copies out of appropriate physical registers. 499 /// 500 SDValue 501 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 502 CallingConv::ID CallConv, bool isVarArg, 503 const SmallVectorImpl<ISD::InputArg> 504 &Ins, 505 DebugLoc dl, SelectionDAG &DAG, 506 SmallVectorImpl<SDValue> &InVals) { 507 508 // Assign locations to each value returned by this call. 509 SmallVector<CCValAssign, 16> RVLocs; 510 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 511 *DAG.getContext()); 512 513 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); 514 515 // Copy all of the result registers out of their specified physreg. 516 for (unsigned i = 0; i != RVLocs.size(); ++i) { 517 CCValAssign &VA = RVLocs[i]; 518 519 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 520 VA.getLocVT(), InFlag).getValue(1); 521 SDValue RetValue = Chain.getValue(0); 522 InFlag = Chain.getValue(2); 523 524 // If this is an 8/16/32-bit value, it is really passed promoted to 64 525 // bits. Insert an assert[sz]ext to capture this, then truncate to the 526 // right size. 527 if (VA.getLocInfo() == CCValAssign::SExt) 528 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, 529 DAG.getValueType(VA.getValVT())); 530 else if (VA.getLocInfo() == CCValAssign::ZExt) 531 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, 532 DAG.getValueType(VA.getValVT())); 533 534 if (VA.getLocInfo() != CCValAssign::Full) 535 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue); 536 537 InVals.push_back(RetValue); 538 } 539 540 return Chain; 541 } 542 543 544 SDValue 545 SystemZTargetLowering::LowerReturn(SDValue Chain, 546 CallingConv::ID CallConv, bool isVarArg, 547 const SmallVectorImpl<ISD::OutputArg> &Outs, 548 DebugLoc dl, SelectionDAG &DAG) { 549 550 // CCValAssign - represent the assignment of the return value to a location 551 SmallVector<CCValAssign, 16> RVLocs; 552 553 // CCState - Info about the registers and stack slot. 554 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 555 RVLocs, *DAG.getContext()); 556 557 // Analize return values. 558 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); 559 560 // If this is the first return lowered for this function, add the regs to the 561 // liveout set for the function. 562 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 563 for (unsigned i = 0; i != RVLocs.size(); ++i) 564 if (RVLocs[i].isRegLoc()) 565 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 566 } 567 568 SDValue Flag; 569 570 // Copy the result values into the output registers. 571 for (unsigned i = 0; i != RVLocs.size(); ++i) { 572 CCValAssign &VA = RVLocs[i]; 573 SDValue ResValue = Outs[i].Val; 574 assert(VA.isRegLoc() && "Can only return in registers!"); 575 576 // If this is an 8/16/32-bit value, it is really should be passed promoted 577 // to 64 bits. 578 if (VA.getLocInfo() == CCValAssign::SExt) 579 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); 580 else if (VA.getLocInfo() == CCValAssign::ZExt) 581 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); 582 else if (VA.getLocInfo() == CCValAssign::AExt) 583 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); 584 585 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); 586 587 // Guarantee that all emitted copies are stuck together, 588 // avoiding something bad. 589 Flag = Chain.getValue(1); 590 } 591 592 if (Flag.getNode()) 593 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 594 595 // Return Void 596 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); 597 } 598 599 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, 600 ISD::CondCode CC, SDValue &SystemZCC, 601 SelectionDAG &DAG) { 602 // FIXME: Emit a test if RHS is zero 603 604 bool isUnsigned = false; 605 SystemZCC::CondCodes TCC; 606 switch (CC) { 607 default: 608 llvm_unreachable("Invalid integer condition!"); 609 case ISD::SETEQ: 610 case ISD::SETOEQ: 611 TCC = SystemZCC::E; 612 break; 613 case ISD::SETUEQ: 614 TCC = SystemZCC::NLH; 615 break; 616 case ISD::SETNE: 617 case ISD::SETONE: 618 TCC = SystemZCC::NE; 619 break; 620 case ISD::SETUNE: 621 TCC = SystemZCC::LH; 622 break; 623 case ISD::SETO: 624 TCC = SystemZCC::O; 625 break; 626 case ISD::SETUO: 627 TCC = SystemZCC::NO; 628 break; 629 case ISD::SETULE: 630 if (LHS.getValueType().isFloatingPoint()) { 631 TCC = SystemZCC::NH; 632 break; 633 } 634 isUnsigned = true; // FALLTHROUGH 635 case ISD::SETLE: 636 case ISD::SETOLE: 637 TCC = SystemZCC::LE; 638 break; 639 case ISD::SETUGE: 640 if (LHS.getValueType().isFloatingPoint()) { 641 TCC = SystemZCC::NL; 642 break; 643 } 644 isUnsigned = true; // FALLTHROUGH 645 case ISD::SETGE: 646 case ISD::SETOGE: 647 TCC = SystemZCC::HE; 648 break; 649 case ISD::SETUGT: 650 if (LHS.getValueType().isFloatingPoint()) { 651 TCC = SystemZCC::NLE; 652 break; 653 } 654 isUnsigned = true; // FALLTHROUGH 655 case ISD::SETGT: 656 case ISD::SETOGT: 657 TCC = SystemZCC::H; 658 break; 659 case ISD::SETULT: 660 if (LHS.getValueType().isFloatingPoint()) { 661 TCC = SystemZCC::NHE; 662 break; 663 } 664 isUnsigned = true; // FALLTHROUGH 665 case ISD::SETLT: 666 case ISD::SETOLT: 667 TCC = SystemZCC::L; 668 break; 669 } 670 671 SystemZCC = DAG.getConstant(TCC, MVT::i32); 672 673 DebugLoc dl = LHS.getDebugLoc(); 674 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), 675 dl, MVT::i64, LHS, RHS); 676 } 677 678 679 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 680 SDValue Chain = Op.getOperand(0); 681 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 682 SDValue LHS = Op.getOperand(2); 683 SDValue RHS = Op.getOperand(3); 684 SDValue Dest = Op.getOperand(4); 685 DebugLoc dl = Op.getDebugLoc(); 686 687 SDValue SystemZCC; 688 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 689 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(), 690 Chain, Dest, SystemZCC, Flag); 691 } 692 693 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 694 SDValue LHS = Op.getOperand(0); 695 SDValue RHS = Op.getOperand(1); 696 SDValue TrueV = Op.getOperand(2); 697 SDValue FalseV = Op.getOperand(3); 698 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 699 DebugLoc dl = Op.getDebugLoc(); 700 701 SDValue SystemZCC; 702 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 703 704 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 705 SmallVector<SDValue, 4> Ops; 706 Ops.push_back(TrueV); 707 Ops.push_back(FalseV); 708 Ops.push_back(SystemZCC); 709 Ops.push_back(Flag); 710 711 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size()); 712 } 713 714 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, 715 SelectionDAG &DAG) { 716 DebugLoc dl = Op.getDebugLoc(); 717 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 718 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 719 720 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 721 bool ExtraLoadRequired = 722 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false); 723 724 SDValue Result; 725 if (!IsPic && !ExtraLoadRequired) { 726 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 727 Offset = 0; 728 } else { 729 unsigned char OpFlags = 0; 730 if (ExtraLoadRequired) 731 OpFlags = SystemZII::MO_GOTENT; 732 733 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags); 734 } 735 736 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl, 737 getPointerTy(), Result); 738 739 if (ExtraLoadRequired) 740 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 741 PseudoSourceValue::getGOT(), 0); 742 743 // If there was a non-zero offset that we didn't fold, create an explicit 744 // addition for it. 745 if (Offset != 0) 746 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 747 DAG.getConstant(Offset, getPointerTy())); 748 749 return Result; 750 } 751 752 // FIXME: PIC here 753 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, 754 SelectionDAG &DAG) { 755 DebugLoc dl = Op.getDebugLoc(); 756 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 757 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 758 759 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 760 } 761 762 763 // FIXME: PIC here 764 // FIXME: This is just dirty hack. We need to lower cpool properly 765 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, 766 SelectionDAG &DAG) { 767 DebugLoc dl = Op.getDebugLoc(); 768 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 769 770 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 771 CP->getAlignment(), 772 CP->getOffset()); 773 774 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 775 } 776 777 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { 778 switch (Opcode) { 779 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG"; 780 case SystemZISD::CALL: return "SystemZISD::CALL"; 781 case SystemZISD::BRCOND: return "SystemZISD::BRCOND"; 782 case SystemZISD::CMP: return "SystemZISD::CMP"; 783 case SystemZISD::UCMP: return "SystemZISD::UCMP"; 784 case SystemZISD::SELECT: return "SystemZISD::SELECT"; 785 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper"; 786 default: return NULL; 787 } 788 } 789 790 //===----------------------------------------------------------------------===// 791 // Other Lowering Code 792 //===----------------------------------------------------------------------===// 793 794 MachineBasicBlock* 795 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 796 MachineBasicBlock *BB, 797 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const { 798 const SystemZInstrInfo &TII = *TM.getInstrInfo(); 799 DebugLoc dl = MI->getDebugLoc(); 800 assert((MI->getOpcode() == SystemZ::Select32 || 801 MI->getOpcode() == SystemZ::SelectF32 || 802 MI->getOpcode() == SystemZ::Select64 || 803 MI->getOpcode() == SystemZ::SelectF64) && 804 "Unexpected instr type to insert"); 805 806 // To "insert" a SELECT instruction, we actually have to insert the diamond 807 // control-flow pattern. The incoming instruction knows the destination vreg 808 // to set, the condition code register to branch on, the true/false values to 809 // select between, and a branch opcode to use. 810 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 811 MachineFunction::iterator I = BB; 812 ++I; 813 814 // thisMBB: 815 // ... 816 // TrueVal = ... 817 // cmpTY ccX, r1, r2 818 // jCC copy1MBB 819 // fallthrough --> copy0MBB 820 MachineBasicBlock *thisMBB = BB; 821 MachineFunction *F = BB->getParent(); 822 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 823 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 824 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); 825 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); 826 F->insert(I, copy0MBB); 827 F->insert(I, copy1MBB); 828 // Inform sdisel of the edge changes. 829 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 830 SE = BB->succ_end(); SI != SE; ++SI) 831 EM->insert(std::make_pair(*SI, copy1MBB)); 832 // Update machine-CFG edges by transferring all successors of the current 833 // block to the new block which will contain the Phi node for the select. 834 copy1MBB->transferSuccessors(BB); 835 // Next, add the true and fallthrough blocks as its successors. 836 BB->addSuccessor(copy0MBB); 837 BB->addSuccessor(copy1MBB); 838 839 // copy0MBB: 840 // %FalseValue = ... 841 // # fallthrough to copy1MBB 842 BB = copy0MBB; 843 844 // Update machine-CFG edges 845 BB->addSuccessor(copy1MBB); 846 847 // copy1MBB: 848 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 849 // ... 850 BB = copy1MBB; 851 BuildMI(BB, dl, TII.get(SystemZ::PHI), 852 MI->getOperand(0).getReg()) 853 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 854 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 855 856 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 857 return BB; 858 } 859